woody/Gen4_R-Car_Trace32
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
27bce98882c2bc04593a1c1b54504631662dad37
Gen4_R-Car_Trace32/2_Trunk/perm0518.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

4391 lines
559 KiB
Plaintext
Raw Blame History

; --------------------------------------------------------------------------------
; @Title: M0518 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2022-03-02 NEJ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: SVD generated, based on: M0518AE_v1.svd (Ver. 1.0)
; @Core: Cortex-M0
; @Chip: M0518LC2AE, M0518LD2AE, M0518SC2AE, M0518SD2AE
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perm0518.per 14430 2022-03-02 16:42:03Z kwisniewski $
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ADC"
base ad:0x400E0000
rgroup.long 0x00++0x03
line.long 0x00 "ADDR0,ADC Data Register 0"
bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
bitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x04++0x03
line.long 0x00 "ADDR1,ADC Data Register 1"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x08++0x03
line.long 0x00 "ADDR2,ADC Data Register 2"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x0C++0x03
line.long 0x00 "ADDR3,ADC Data Register 3"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x10++0x03
line.long 0x00 "ADDR4,ADC Data Register 4"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x14++0x03
line.long 0x00 "ADDR5,ADC Data Register 5"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x18++0x03
line.long 0x00 "ADDR6,ADC Data Register 6"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x1C++0x03
line.long 0x00 "ADDR7,ADC Data Register 7"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\n"
group.long 0x20++0x03
line.long 0x00 "ADCR,ADC Control Register"
bitfld.long 0x00 31. "DMOF,A/D Differential Input Mode Output Format\n" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.."
bitfld.long 0x00 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from three sources: software PWM Center-aligned trigger and external pin STADC" "0: Conversion stops and A/D converter enter idle..,1: Conversion starts"
newline
bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control\n" "0: Single-end analog input mode,1: Differential analog input mode"
bitfld.long 0x00 8. "TRGEN,Hardware Trigger Enable Bit\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode the.." "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge"
bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nSoftware should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS" "0: A/D conversion is started by external STADC pin,?,?,3: A/D conversion is started by PWM.."
newline
bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode\nWhen changing the operation mode software should disable ADST bit (ADCR[11]) firstly" "0: Single conversion,1: Reserved,2: Single-cycle scan,3: Continuous scan"
bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
newline
bitfld.long 0x00 0. "ADEN,A/D Converter Enable Bit\nBefore starting A/D conversion function this bit should be set to 1" "0: Disabled,1: Enabled"
group.long 0x24++0x03
line.long 0x00 "ADCHER,ADC Channel Enable Register"
bitfld.long 0x00 8.--9. "PRESEL,Analog Input Channel 7 Selection\n" "0: External analog input,1: Internal band-gap voltage,2: Reserved,3: Reserved"
hexmask.long.byte 0x00 0.--7. 1. "CHEN,Analog Input Channel Enable Bit\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0"
group.long 0x28++0x03
line.long 0x00 "ADCMPR0,ADC Compare Register 0"
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format"
bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]) the internal match counter will increase 1 The comparing data must successively matched with the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be.."
bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) + 1) the CMPF0/1 bit (ADSR[1]/[2]) will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
newline
bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]) CMPF0/1 bit (ADSR[1]/[2]) will be asserted in the meanwhile if CMPIE.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled"
group.long 0x2C++0x03
line.long 0x00 "ADCMPR1,ADC Compare Register 1"
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format"
bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]) the internal match counter will increase 1 The comparing data must successively matched with the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be.."
bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) + 1) the CMPF0/1 bit (ADSR[1]/[2]) will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
newline
bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]) CMPF0/1 bit (ADSR[1]/[2]) will be asserted in the meanwhile if CMPIE.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled"
group.long 0x30++0x03
line.long 0x00 "ADSR,ADC Status Register"
hexmask.long.byte 0x00 16.--23. 1. "OVERRUN,Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR0~7[16]).\nIt is read only"
hexmask.long.byte 0x00 8.--15. 1. "VALID,Data Valid Flag\nIt is a mirror of VALID bit (ADDR0~7[17]).\nIt is read only"
newline
bitfld.long 0x00 4.--6. "CHANNEL,Current Conversion Channel\nIt is read only" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit (ADCR[11]).\nIt is read only" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
newline
bitfld.long 0x00 2. "CMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting"
bitfld.long 0x00 1. "CMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting"
newline
bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1" "0,1"
tree.end
tree "BPWM"
repeat 2. (list 0. 1.) (list ad:0x40044000 ad:0x40144000)
tree "BPWM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
newline
bitfld.long 0x00 16.--21. "IMMLDENn,Immediately Load Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF..,?..."
bitfld.long 0x00 0.--5. "CTRLDn,Center Re-Load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.\n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
group.long 0x10++0x03
line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select\n" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
group.long 0x14++0x03
line.long 0x00 "BPWM_CLKPSC,BPWM Clock Pre-scale Register"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Pre-Scale \nThe clock of BPWM counter is decided by clock prescaler"
group.long 0x20++0x03
line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
bitfld.long 0x00 0. "CNTEN0,BPWM Counter Enable 0\n" "0: BPWM Counter and clock prescaler Stop Running,1: BPWM Counter and clock prescaler Start Running"
group.long 0x24++0x03
line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
group.long 0x30++0x03
line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD.\n"
group.long 0x50++0x03
line.long 0x00 "BPWM_CMPDAT0,BPWM Comparator Register 0"
hexmask.long.word 0x00 0.--15. 1. "CMP,BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode BPWM_CMPDAT0 2 4 denote as first.."
group.long 0x54++0x03
line.long 0x00 "BPWM_CMPDAT1,BPWM Comparator Register 1"
hexmask.long.word 0x00 0.--15. 1. "CMP,BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode BPWM_CMPDAT0 2 4 denote as first.."
group.long 0x58++0x03
line.long 0x00 "BPWM_CMPDAT2,BPWM Comparator Register 2"
hexmask.long.word 0x00 0.--15. 1. "CMP,BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode BPWM_CMPDAT0 2 4 denote as first.."
group.long 0x5C++0x03
line.long 0x00 "BPWM_CMPDAT3,BPWM Comparator Register 3"
hexmask.long.word 0x00 0.--15. 1. "CMP,BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode BPWM_CMPDAT0 2 4 denote as first.."
group.long 0x60++0x03
line.long 0x00 "BPWM_CMPDAT4,BPWM Comparator Register 4"
hexmask.long.word 0x00 0.--15. 1. "CMP,BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode BPWM_CMPDAT0 2 4 denote as first.."
group.long 0x64++0x03
line.long 0x00 "BPWM_CMPDAT5,BPWM Comparator Register 5"
hexmask.long.word 0x00 0.--15. 1. "CMP,BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode BPWM_CMPDAT0 2 4 denote as first.."
rgroup.long 0x90++0x03
line.long 0x00 "BPWM_CNT0,BPWM Counter Register 0"
bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)\n" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
group.long 0xB0++0x03
line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
hexmask.long.word 0x00 16.--27. 1. "PRDPCTLn,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIODn+1).\nNote: This bit is center point control when BPWM counter operating in up-down.."
hexmask.long.word 0x00 0.--11. 1. "ZPCTLn,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero"
group.long 0xB4++0x03
line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
hexmask.long.word 0x00 16.--27. 1. "CMPDCTLn,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4"
hexmask.long.word 0x00 0.--11. 1. "CMPUCTLn,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4"
group.long 0xB8++0x03
line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
bitfld.long 0x00 0.--5. "MSKENn,BPWM Mask Enable Control\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output..,?..."
group.long 0xBC++0x03
line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
bitfld.long 0x00 0.--5. "MSKDATn,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn,?..."
group.long 0xD4++0x03
line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
bitfld.long 0x00 0.--5. "PINVn,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled,?..."
group.long 0xD8++0x03
line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
bitfld.long 0x00 0.--5. "POENn,BPWM Pin Output Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: BPWM pin at tri-state,1: BPWM pin in output mode,?..."
group.long 0xE0++0x03
line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
bitfld.long 0x00 24.--29. "CMPDIENn,BPWM Compare Down Count Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled,?..."
bitfld.long 0x00 16.--21. "CMPUIENn,BPWM Compare Up Count Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled,?..."
newline
bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
group.long 0xE8++0x03
line.long 0x00 "BPWM_INTSTS0,BPWM Interrupt Flag Register"
bitfld.long 0x00 24.--29. "CMPDIFn,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "CMPUIFn,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches zero software can write 1 to clear this bit to zero" "0,1"
group.long 0xF8++0x03
line.long 0x00 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select\n" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select\n" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select\n" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
group.long 0xFC++0x03
line.long 0x00 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select\n" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select\n" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
group.long 0x110++0x03
line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select\n" "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
wgroup.long 0x114++0x03
line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected BPWM channels (include BPWM0_CHx and BPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
group.long 0x120++0x03
line.long 0x00 "BPWM_STATUS,BPWM Status Register"
bitfld.long 0x00 16.--21. "ADCTRGn,ADC Start Of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger..,?..."
bitfld.long 0x00 0. "CNTMAX0,Time-Base Counter 0 Equal To 0xFFFF Latched Status\n" "0: Indicates the time-base counter never reached..,1: Indicates the time-base counter reached its.."
group.long 0x200++0x03
line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
bitfld.long 0x00 0.--5. "CAPINENn,Capture Input Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled,?..."
group.long 0x204++0x03
line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
bitfld.long 0x00 24.--29. "FCRLDENn,Falling Capture Reload Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled,?..."
bitfld.long 0x00 16.--21. "RCRLDENn,Rising Capture Reload Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled,?..."
newline
bitfld.long 0x00 8.--13. "CAPINVn,Capture Inverter Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled,?..."
bitfld.long 0x00 0.--5. "CAPENn,Capture Function Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: Capture function Disabled,1: Capture function Enabled,?..."
rgroup.long 0x208++0x03
line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
bitfld.long 0x00 8.--13. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x20C++0x03
line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
rgroup.long 0x210++0x03
line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x214++0x03
line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x218++0x03
line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x21C++0x03
line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x220++0x03
line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x224++0x03
line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x228++0x03
line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x22C++0x03
line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x230++0x03
line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x234++0x03
line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x238++0x03
line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x250++0x03
line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
group.long 0x254++0x03
line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
bitfld.long 0x00 8.--13. "CFLIFn,BPWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this..,?..."
bitfld.long 0x00 0.--5. "CRLIFn,BPWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this..,?..."
rgroup.long 0x304++0x03
line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
rgroup.long 0x31C++0x03
line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT0 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x320++0x03
line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT1 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x324++0x03
line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT2 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x328++0x03
line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT3 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x32C++0x03
line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT4 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x330++0x03
line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT5 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
tree.end
repeat.end
tree.end
tree "CLK"
base ad:0x50000200
group.long 0x00++0x03
line.long 0x00 "PWRCON,System Power-down Control Register"
bitfld.long 0x00 8. "PD_WAIT_CPU,Power-Down Entry Condition Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: Chip enters Power-down mode when the..,1: Chip enters Power- down mode when the both.."
bitfld.long 0x00 7. "PWR_DOWN_EN,System Power-Down Enable Bit (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0 the chip enters Power-down mode immediately.." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or.."
newline
bitfld.long 0x00 6. "PD_WU_STS,Power-Down Mode Wake-Up Interrupt Status\nSet by Power-down wake-up event it indicates that resume from Power-down mode .\nThe flag is set if the GPIO UART WDT I2C TIMER or BOD wake-up occurred.\nWrite 1 to clear the bit to 0.\nNote: This bit.." "0,1"
bitfld.long 0x00 5. "PD_WU_INT_EN,Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address.." "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
newline
bitfld.long 0x00 4. "PD_WU_DLY,Wake-Up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
bitfld.long 0x00 3. "OSC10K_EN,10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
newline
bitfld.long 0x00 2. "OSC22M_EN,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
bitfld.long 0x00 0. "XTL12M_EN,4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CONFIG0 [26:24]" "0: 4 ~ 24 MHz external high speed crystal..,1: 4 ~ 24 MHz external high speed crystal.."
group.long 0x04++0x03
line.long 0x00 "AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x00 2. "ISP_EN,Flash ISP Controller Clock Enable Bit\n" "0: Flash ISP peripherial clock Disabled,1: Flash ISP peripherial clock Enabled"
group.long 0x08++0x03
line.long 0x00 "APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x00 28. "ADC_EN,Analog-Digital-Converter (ADC) Clock Enable Bit\n" "0: ADC clock Disabled,1: ADC clock Enabled"
bitfld.long 0x00 18. "UART2_EN,UART2 Clock Enable Bit\n" "0: UART2 clock Disabled,1: UART2 clock Enabled"
newline
bitfld.long 0x00 17. "UART1_EN,UART1 Clock Enable Bit\n" "0: UART1 clock Disabled,1: UART1 clock Enabled"
bitfld.long 0x00 16. "UART0_EN,UART0 Clock Enable Bit\n" "0: UART0 clock Disabled,1: UART0 clock Enabled"
newline
bitfld.long 0x00 12. "SPI0_EN,SPI0 Clock Enable Bit\n" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
bitfld.long 0x00 9. "I2C1_EN,I2C1 Clock Enable Bit\n" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
newline
bitfld.long 0x00 8. "I2C0_EN,I2C0 Clock Enable Bit\n" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
bitfld.long 0x00 6. "FDIV_EN,Frequency Divider Output Clock Enable Bit\n" "0: FDIV clock Disabled,1: FDIV clock Enabled"
newline
bitfld.long 0x00 5. "TMR3_EN,Timer3 Clock Enable Bit\n" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
bitfld.long 0x00 4. "TMR2_EN,Timer2 Clock Enable Bit\n" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
newline
bitfld.long 0x00 3. "TMR1_EN,Timer1 Clock Enable Bit\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
bitfld.long 0x00 2. "TMR0_EN,Timer0 Clock Enable Bit\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
newline
bitfld.long 0x00 0. "WDT_EN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
group.long 0x0C++0x03
line.long 0x00 "CLKSTATUS,Clock Status Monitor Register"
rbitfld.long 0x00 7. "CLK_SW_FAIL,Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0])" "0: Clock switching success,1: Clock switching failure"
rbitfld.long 0x00 4. "OSC22M_STB,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Clock Source Stable Flag (Read Only)\n" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
newline
rbitfld.long 0x00 3. "OSC10K_STB,Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)\n" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
rbitfld.long 0x00 2. "PLL_STB,Internal PLL Clock Source Stable Flag (Read Only)\n" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable in normal mode"
newline
rbitfld.long 0x00 0. "XTL12M_STB,4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)\n" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
group.long 0x10++0x03
line.long 0x00 "CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x00 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Select (Write Protect)\n" "0: Clock source from 4~24 MHz external high..,1: Reserved,2: Clock source from 4~24 MHz external high..,3: Clock source from HCLK/2,?,?,?,7: Clock source from 22.1184 MHz internal high.."
bitfld.long 0x00 0.--2. "HCLK_S,HCLK Clock Source Select (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be enabled\nThe 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration.." "0: Clock source from 4~24 MHz external high..,1: Reserved,2: Clock source from PLL,3: Clock source from 10 kHz internal low speed..,?,?,?,7: Clock source from 22.1184 MHz internalhigh.."
group.long 0x14++0x03
line.long 0x00 "CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x00 24.--25. "UART_S,UART Clock Source Selection\n" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,?,3: Clock source from 22.1184 MHz internal high.."
bitfld.long 0x00 20.--22. "TMR3_S,TIMER3 Clock Source Selection\n" "0: Clock source from 4~24 MHz external high..,1: Reserved,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
newline
bitfld.long 0x00 16.--18. "TMR2_S,TIMER2 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high..,1: Reserved,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
bitfld.long 0x00 12.--14. "TMR1_S,TIMER1 Clock Source Selection\n" "0: Clock source from 4~24 MHz external high..,1: Reserved,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
newline
bitfld.long 0x00 8.--10. "TMR0_S,TIMER0 Clock Source Selection\n" "0: Clock source from 4~24 MHz external high..,1: Reserved,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
bitfld.long 0x00 4. "SPI0_S,SPI0 Clock Source Selection\n" "0: Clock source from PLL,1: Clock source from HCLK"
newline
bitfld.long 0x00 2.--3. "ADC_S,ADC Clock Source Select\n" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from HCLK,3: Clock source from 22.1184 MHz internal high.."
bitfld.long 0x00 0.--1. "WDT_S,Watchdog Timer Clock Source Select (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: Reserved,1: Reserved,2: Clock source from HCLK/2048,3: Clock source from 10 kHz internal low speed.."
group.long 0x18++0x03
line.long 0x00 "CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x00 16.--23. 1. "ADC_N,ADC Clock Divide Number From ADC Clock Source\n"
bitfld.long 0x00 8.--11. "UART_N,UART Clock Divide Number From UART Clock Source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HCLK_N,HCLK Clock Divide Number From HCLK Clock Source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x00 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection\n" "?,?,2: Clock source from HCLK/2048 clock,3: Clock source from 10 kHz internal low speed.."
bitfld.long 0x00 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\n" "0: Clock source from 4~24 MHz external high..,1: Reserved,2: Clock source from HCLK,3: Clock source from 22.1184 MHz internal high.."
group.long 0x20++0x03
line.long 0x00 "PLLCON,PLL Control Register"
bitfld.long 0x00 19. "PLL_SRC,PLL Source Clock Selection\n" "0: PLL source clock from 4~24 MHz external high..,1: PLL source clock from 22.1184 MHz internal.."
bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Pin Control\n" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
newline
bitfld.long 0x00 17. "BP,PLL Bypass Control\n" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock.."
bitfld.long 0x00 16. "PD,Power-Down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too.\n" "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)"
newline
bitfld.long 0x00 14.--15. "OUT_DV,PLL Output Divider Control Bits\nRefer to the formulas below the table" "0,1,2,3"
bitfld.long 0x00 9.--13. "IN_DV,PLL Input Divider Control Bits\nRefer to the formulas below the table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--8. 1. "FB_DV,PLL Feedback Divider Control Bits\nRefer to the formulas below the table"
group.long 0x24++0x03
line.long 0x00 "FRQDIV,Frequency Divider Control Register"
bitfld.long 0x00 5. "DIVIDER1,Frequency Divider One Enable Bit\n" "0: Frequency divider will output clock with..,1: Frequency divider will output clock with.."
bitfld.long 0x00 4. "DIVIDER_EN,Frequency Divider Enable Bit\n" "0: Frequency divider function Disabled,1: Frequency divider function Enabled"
newline
bitfld.long 0x00 0.--3. "FSEL,Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "APBCLK1,APB Devices Clock Enable Control Register 1"
bitfld.long 0x00 19. "BPWM1_EN,BPWM1 Clock Enable Bit\n" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled"
bitfld.long 0x00 18. "BPWM0_EN,BPWM0 Clock Enable Bit\n" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
newline
bitfld.long 0x00 17. "PWM1_EN,PWM1 Clock Enable Bit\n" "0: PWM1 clock Disabled,1: PWM1 clock Enabled"
bitfld.long 0x00 16. "PWM0_EN,PWM0 Clock Enable Bit\n" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
newline
bitfld.long 0x00 10. "UART5_EN,UART5 Clock Enable Bit\n" "0: UART5 clock Disabled,1: UART5 clock Enabled"
bitfld.long 0x00 9. "UART4_EN,UART4 Clock Enable Bit\n" "0: UART4 clock Disabled,1: UART4 clock Enabled"
newline
bitfld.long 0x00 8. "UART3_EN,UART3 Clock Enable Bit\n" "0: UART3 clock Disabled,1: UART3 clock Enabled"
group.long 0x34++0x03
line.long 0x00 "CLKSEL3,Clock Source Select Control Register 3"
bitfld.long 0x00 19. "BPWM1_S,BPWM1 Clock Source Selection\nThe Engine clock source of BPWM1 is defined by BPWM1_S.\n" "0: Clock source from PLL,1: Clock source from PCLK"
bitfld.long 0x00 18. "BPWM0_S,BPWM0 Clock Source Selection\nThe Engine clock source of BPWM0 is defined by BPWM0_S.\n" "0: Clock source from PLL,1: Clock source from PCLK"
newline
bitfld.long 0x00 17. "PWM1_S,PWM1 Clock Source Selection\nThe Engine clock source of PWM1 is defined by PWM1_S.\n" "0: Clock source from PLL,1: Clock source from PCLK"
bitfld.long 0x00 16. "PWM0_S,PWM0 Clock Source Selection\nThe Engine clock source of PWM0 is defined by PWM0_S.\n" "0: Clock source from PLL,1: Clock source from PCLK"
group.long 0x70++0x03
line.long 0x00 "CLKDCTL,Clock Fail Detector Control Register"
bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit\n" "0: HXT clock frequency monitor fail interrupt..,1: HXT clock frequency monitor fail interrupt.."
bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit\n" "0: HXT clock frequency monitor Disabled,1: HXT clock frequency monitor Enabled"
newline
bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit\n" "0: HXT clock Fail interrupt Disabled,1: HXT clock Fail interrupt Enabled"
bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit\n" "0: HXT clock Fail detector Disabled,1: HXT clock Fail detector Enabled"
group.long 0x74++0x03
line.long 0x00 "CLKDSTS,Clock Fail Detector Status Register"
bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag\n" "0: HXT clock normal,1: HXT clock frequency abnormal (write 1 to clear)"
bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag\n" "0: HXT clock normal,1: HXT clock stop (write 1 to clear)"
group.long 0x78++0x03
line.long 0x00 "CDUPB,Clock Frequency Detector Upper Boundary Register"
hexmask.long.word 0x00 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1"
group.long 0x7C++0x03
line.long 0x00 "CDLOWB,Clock Frequency Detector Lower Boundary Register"
hexmask.long.word 0x00 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor values lower than this register the HXT frequency detect fail interrupt flag will set to 1"
tree.end
tree "FMC"
base ad:0x5000C000
group.long 0x00++0x03
line.long 0x00 "ISPCON,ISP Control Register"
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is.." "0,1"
bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\n" "0: LDROM cannot be updated,1: LDROM can be updated when chip runs in APROM"
newline
bitfld.long 0x00 4. "CFGUEN,Enable Config Update By ISP (Write Protect)\n" "0: ISP update config-bit Disabled,1: ISP update config-bit Enabled"
bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\n" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
newline
bitfld.long 0x00 1. "BS,Boot Select (Write Protect )\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM,1: Boot from LDROM"
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect )\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
group.long 0x04++0x03
line.long 0x00 "ISPADR,ISP Address Register"
hexmask.long 0x00 0.--31. 1. "ISPADR,ISP Address\nThe NuMicro( M0518 series has a maximum of 17Kx32 (68 KB) embedded Flash which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation"
group.long 0x08++0x03
line.long 0x00 "ISPDAT,ISP Data Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
group.long 0x0C++0x03
line.long 0x00 "ISPCMD,ISP Command Register"
bitfld.long 0x00 0.--5. "ISPCMD,ISP Command\nISP command table is shown below:\n" "0: ,?,?,?,4: Read Unique ID,?,?,?,?,?,?,11: Read Company ID (0xDA),?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,33: Program,34: Page Erase,?,?,?,?,?,?,?,?,?,?,?,46: Set Vector Page Re-Map,?..."
group.long 0x10++0x03
line.long 0x00 "ISPTRG,ISP Trigger Control Register"
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit It means programming this bit needs to write 59h 16h 88h.." "0: ISP operation finished,1: ISP is in progress"
rgroup.long 0x14++0x03
line.long 0x00 "DFBADR,Data Flash Base Address"
hexmask.long 0x00 0.--31. 1. "DFBADR,Data Flash Base Address\nThis register indicates Data Flash start address"
group.long 0x18++0x03
line.long 0x00 "FATCON,Flash Access Time Control Register"
bitfld.long 0x00 6. "FOMSEL1,Chip Frequency Optimization Mode Select1 (Write-protection Bit)" "0,1"
bitfld.long 0x00 4. "FOMSEL0,Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)\nWhen CPU frequency is lower than 25 MHz user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance.\n" "0,1"
group.long 0x40++0x03
line.long 0x00 "ISPSTA,ISP Status Register"
hexmask.long.word 0x00 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}"
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4).." "0,1"
newline
rbitfld.long 0x00 1.--2. "CBS,Chip Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0" "0,1,2,3"
rbitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0" "0: ISP operation finished,1: ISP operation progressed"
tree.end
tree "GCR"
base ad:0x50000000
rgroup.long 0x00++0x03
line.long 0x00 "PDID,Part Device Identification Number Register"
hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects device part number code"
group.long 0x04++0x03
line.long 0x00 "RSTSRC,System Reset Source Register"
bitfld.long 0x00 7. "RSTS_CPU,CPU Reset Flag\nThe RSTS_CPU flag Is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 To reset Cortex-M0 core and flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: Cortex-M0 CPU core and FMC are reset by.."
bitfld.long 0x00 5. "RSTS_SYS,SYS Reset Flag\nThe RSTS_SYS flag Is set by the Reset Signal from the Cortex-M0 core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
newline
bitfld.long 0x00 4. "RSTS_BOD,Brown-Out Detector Reset Flag\nThe RSTS_BOD flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
bitfld.long 0x00 3. "RSTS_LVR,Low Voltage Reset Flag\nThe RSTS_LVR flag is set by the Reset Signal from the Low-Voltage-Reset controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: The LVR controller had issued the reset.."
newline
bitfld.long 0x00 2. "RSTS_WDT,Watchdog Timer Reset Flag\nThe RSTS_WDT flag is set by the Reset Signal from the watchdog timer or window watchdog timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register WTRF.." "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
bitfld.long 0x00 1. "RSTS_RESET,Reset Pin Reset Flag\nThe RSTS_RESET flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: The Pin nRESET had issued the reset signal to.."
newline
bitfld.long 0x00 0. "RSTS_POR,Power-On Reset Flag\nThe RSTS_POR Flag is set by the Reset Signal from the Power-On Reset (POR) vontroller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIP_RST (IPRSTC1[0]),1: Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]).."
group.long 0x08++0x03
line.long 0x00 "IPRSTC1,Peripheral Reset Control Register 1"
bitfld.long 0x00 1. "CPU_RST,CPU Core One-Shot Reset (Write Protect)\nSetting this bit will only reset the CPU core and Flash Memory Controller(FMC) and this bit will automatically return 0 after the two clock cycles.\nNote: This bit is the protected bit and programming it.." "0: CPU normal operation,1: CPU one-shot reset"
bitfld.long 0x00 0. "CHIP_RST,CHIP One-Shot Reset (Write Protect)\nSetting this bit will reset the whole chip including CPU core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset all the chip.." "0: CHIP normal operation,1: CHIP one-shot reset"
group.long 0x0C++0x03
line.long 0x00 "IPRSTC2,Peripheral Reset Control Register 2"
bitfld.long 0x00 28. "ADC_RST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset"
bitfld.long 0x00 18. "UART2_RST,UART2 Controller Reset \n" "0: UART2 controller normal operation,1: UART2 controller reset"
newline
bitfld.long 0x00 17. "UART1_RST,UART1 Controller Reset\n" "0: UART1 controller normal operation,1: UART1 controller reset"
bitfld.long 0x00 16. "UART0_RST,UART0 Controller Reset\n" "0: UART0 controller normal operation,1: UART0 controller reset"
newline
bitfld.long 0x00 12. "SPI0_RST,SPI0 Controller Reset\n" "0: SPI0 controller normal operation,1: SPI0 controller reset"
bitfld.long 0x00 9. "I2C1_RST,I2C1 Controller Reset\n" "0: I2C1 controller normal operation,1: I2C1 controller reset"
newline
bitfld.long 0x00 8. "I2C0_RST,I2C0 Controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset"
bitfld.long 0x00 5. "TMR3_RST,Timer3 Controller Reset\n" "0: Timer3 controller normal operation,1: Timer3 controller reset"
newline
bitfld.long 0x00 4. "TMR2_RST,Timer2 Controller Reset\n" "0: Timer2 controller normal operation,1: Timer2 controller reset"
bitfld.long 0x00 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
newline
bitfld.long 0x00 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
bitfld.long 0x00 1. "GPIO_RST,GPIO Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
group.long 0x10++0x03
line.long 0x00 "IPRSTC3,Peripheral Reset Control Register 3"
bitfld.long 0x00 19. "BPWM1_RST,BPWM1 Controller Reset\n" "0: BPWM1 controller normal operation,1: BPWM1 controller reset"
bitfld.long 0x00 18. "BPWM0_RST,BPWM0 Controller Reset\n" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
newline
bitfld.long 0x00 17. "PWM1_RST,PWM1 Controller Reset\n" "0: PWM1 controller normal operation,1: PWM1 controller reset"
bitfld.long 0x00 16. "PWM0_RST,PWM0 Controller Reset\n" "0: PWM0 controller normal operation,1: PWM0 controller reset"
newline
bitfld.long 0x00 10. "UART5_RST,UART5 Controller Reset\n" "0: UART5 controller normal operation,1: UART5 controller reset"
bitfld.long 0x00 9. "UART4_RST,UART4 Controller Reset\n" "0: UART4 controller normal operation,1: UART4 controller reset"
newline
bitfld.long 0x00 8. "UART3_RST,UART3 Controller Reset\n" "0: UART3 controller normal operation,1: UART3 controller reset"
group.long 0x18++0x03
line.long 0x00 "BODCR,Brown-out Detector Control Register"
bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-Glitch Time Select (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: Without de-glitch function,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
bitfld.long 0x00 8.--10. "BODDGSEL,Brown-Out Detector Output De-Glitch Time Select (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
newline
bitfld.long 0x00 7. "LVR_EN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.."
bitfld.long 0x00 6. "BOD_OUT,Brown-Out Detector Output Status\n" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
newline
bitfld.long 0x00 5. "BOD_LPM,Brown-Out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is the protected bit and programming.." "0: BOD operated in Normal mode (default),1: BOD Low Power mode Enabled"
bitfld.long 0x00 4. "BOD_INTF,Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
newline
bitfld.long 0x00 3. "BOD_RSTEN,Brown-Out Reset Enable Bit (Write Protect)\nWhile the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high) BOD will assert a signal to reset chip when the detected voltage is lower than the.." "0: Brown-out INTERRUPT function Enabled,1: Brown-out RESET function Enabled"
bitfld.long 0x00 1.--2. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash memory controller user configuration register CBOV (CONFIG0[22:21]) bit.\nNote: This bit is the protected bit" "0: Brown-out voltage is 2.2V,1: Brown-out voltage is 2.7V,2: Brown-out voltage is 3.7V,3: Brown-out voltage is 4.4V"
newline
bitfld.long 0x00 0. "BOD_EN,Brown-Out Detector Enable Bit (Write Protect)\nThe default value is set by flash memory controller user configuration register CBODEN (CONFIG0[23]) bit.\nNote: This bit is the protected bit" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
group.long 0x24++0x03
line.long 0x00 "PORCR,Power-on-reset Controller Register"
hexmask.long.word 0x00 0.--15. 1. "POR_DIS_CODE,Power-On-Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
group.long 0x28++0x03
line.long 0x00 "VREFCR,VREF Controller Register"
bitfld.long 0x00 4. "ADC_VREFSEL,ADC VREF Path Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: ADC VREF is from VREF pin,1: ADC VREF is from AVDD"
group.long 0x30++0x03
line.long 0x00 "GPA_MFP,GPIOA Multiple Function and Input Type Control Register"
hexmask.long.word 0x00 16.--31. 1. "GPA_TYPEn,Trigger Function Selection\n"
bitfld.long 0x00 15. "GPA_MFP15,PA.15 Pin Function Selection\nBit GPA_MFP15 determines the PA.15 function.\n" "0: GPIO function is selected,1: PWM0_CH3 function is selected"
newline
bitfld.long 0x00 14. "GPA_MFP14,PA.14 Pin Function Selection\nBit GPA_MFP14 determines the PA.14 function.\n" "0: GPIO function is selected,1: PWM0_CH2 function is selected"
bitfld.long 0x00 13. "GPA_MFP13,PA.13 Pin Function Selection\nBits PA13_UR5TXD (ALT_MFP4[9]) and GPA_MFP13 determine the PA.13 function.\n(PA13_UR5TXD GPA_MFP13) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 12. "GPA_MFP12,PA.12 Pin Function Selection\nBits PA12_UR5RXD (ALT_MFP4[8]) and GPA_MFP12 determine the PA.12 function.\n(PA12_UR5RXD GPA_MFP12) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 11. "GPA_MFP11,PA.11 Pin Function Selection\nBits PA11_PWM13 (ALT_MFP3[9]) and GPA_MFP11 determine the PA.11 function.\n(PA11_PWM13 GPA_MFP11) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 10. "GPA_MFP10,PA.10 Pin Function Selection\nBits PA10_PWM12 (ALT_MFP3[8]) and GPA_MFP10 determine the PA.10 function.\n(PA10_PWM12 GPA_MFP10) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 9. "GPA_MFP9,PA.9 Pin Function Selection\nBits PA9_UR1CTS (ALT_MFP4[1]) and GPA_MFP9 determine the PA.9 function.\n(PA9_UR1CTS GPA_MFP9) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 8. "GPA_MFP8,PA.8 Pin Function Selection\nBits PA8_UR1RTS (ALT_MFP4[0]) and GPA_MFP8 determine the PA.8 function.\n(PA8_UR1RTS GPA_MFP8) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 7. "GPA_MFP7,PA.7 Pin Function Selection\nBits PA7_VREF (ALT_MFP4[14]) and GPA_MFP7 determine the PA.7 function.\n(PA7_VREF GPA_MFP7) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 6. "GPA_MFP6,PA.6 Pin Function Selection\nBits PA6_UR3TXD (ALT_MFP4[5]) and GPA_MFP6 determine the PA.6 function.\n(PA6_UR3TXD GPA_MFP6) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 5. "GPA_MFP5,PA.5 Pin Function Selection\nBits PA5_UR3RXD (ALT_MFP4[4]) and GPA_MFP5 determine the PA.5 function.\n(PA5_UR3RXD GPA_MFP5) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 4. "GPA_MFP4,PA.4 Pin Function Selection\nBit GPA_MFP4 determines the PA.4 function.\n" "0: GPIO function is selected,1: ADC4 function is selected"
bitfld.long 0x00 3. "GPA_MFP3,PA.3 Pin Function Selection\nBits PA3_PWM11 (ALT_MFP3[7]) PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function.\n(PA3_PWM11 PA3_UR3RXD GPA_MFP3) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 2. "GPA_MFP2,PA.2 Pin Function Selection\nBits PA2_PWM10 (ALT_MFP3[6]) PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function.\n(PA2_PWM10 PA2_UR3TXD GPA_MFP2) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 1. "GPA_MFP1,PA.1 Pin Function Selection\nBits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function.\n(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is as following.." "0,1"
newline
bitfld.long 0x00 0. "GPA_MFP0,PA.0 Pin Function Selection\nBits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function.\n(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is as following.." "0,1"
group.long 0x34++0x03
line.long 0x00 "GPB_MFP,GPIOB Multiple Function and Input Type Control Register"
hexmask.long.word 0x00 16.--31. 1. "GPB_TYPEn,Trigger Function Selection\n"
bitfld.long 0x00 15. "GPB_MFP15,PB.15 Pin Function Selection\nBits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function.\n(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as following.." "0,1"
newline
bitfld.long 0x00 14. "GPB_MFP14,PB.14 Pin Function Selection\nBit GPB_MFP14 determines the PB.14 function.\n" "0: GPIO function is selected,1: INT0 function is selected"
bitfld.long 0x00 12. "GPB_MFP12,PB.12 Pin Function Selection\nBits PB12_BPWM13 (ALT_MFP3[21]) and GPB_MFP12 determine the PB.12 function.\n(PB12_BPWM13 GPB_MFP12) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 11. "GPB_MFP11,PB.11 Pin Function Selection\nBits PB11_PWM04 (ALT_MFP3[24]) and GPB_MFP11 determine the PB.11 function.\n(PB11_PWM04 GPB_MFP11) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 10. "GPB_MFP10,PB.10 Pin Function Selection\nBit GPB_MFP10 determines the PB.10 function.\n" "0: GPIO function is selected,1: TM2 function is selected"
newline
bitfld.long 0x00 9. "GPB_MFP9,PB.9 Pin Function Selection\nBit GPB_MFP9 determines the PB.9 function.\n" "0: GPIO function is selected,1: TM1 function is selected"
bitfld.long 0x00 8. "GPB_MFP8,PB.8 Pin Function Selection\nBits PB8_BPWM12 (ALT_MFP3[20]) PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function.\n(PB8_BPWM12 PB8_CLKO GPB_MFP8) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 7. "GPB_MFP7,PB.7 Pin Function Selection\nBit GPB_MFP7 determines the PB.7 function.\n" "0: GPIO function is selected,1: UART1_nCTS function is selected"
bitfld.long 0x00 6. "GPB_MFP6,PB.6 Pin Function Selection\nBit GPB_MFP6 determines the PB.6 function.\n" "0: GPIO function is selected,1: UART1_nRTS function is selected"
newline
bitfld.long 0x00 5. "GPB_MFP5,PB 5 Pin Function Selection\nBit GPB_MFP5 determines the PB.5 function.\n" "0: GPIO function is selected,1: UART1_TXD function is selected"
bitfld.long 0x00 4. "GPB_MFP4,PB.4 Pin Function Selection\nBit GPB_MFP4 determines the PB.4 function.\n" "0: GPIO function is selected,1: UART1_RXD function is selected"
newline
bitfld.long 0x00 3. "GPB_MFP3,PB.3 Pin Function Selection\nBits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function.\n(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 2. "GPB_MFP2,PB.2 Pin Function Selection\nBits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function.\n(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 1. "GPB_MFP1,PB.1 Pin Function Selection\nBit GPB_MFP1 determines the PB.1 function.\n" "0: GPIO function is selected,1: UART0_TXD function is selected"
bitfld.long 0x00 0. "GPB_MFP0,PB.0 Pin Function Selection\nBit GPB_MFP0 determines the PB.0 function.\n" "0: GPIO function is selected,1: UART0_RXD function is selected"
group.long 0x38++0x03
line.long 0x00 "GPC_MFP,GPIOC Multiple Function and Input Type Control Register"
hexmask.long.word 0x00 16.--31. 1. "GPC_TYPEn,Trigger Function Selection\n"
bitfld.long 0x00 11. "GPC_MFP11,PC.11 Pin Function Selection\nBit GPC_MFP11 determines the PC.11 function.\n" "0: GPIO function is selected,1: PWM1_BRAKE1 function is selected"
newline
bitfld.long 0x00 10. "GPC_MFP10,PC.10 Pin Function Selection\nBit GPC_MFP10 determines the PC.10 function.\n" "0: GPIO function is selected,1: PWM1_BRAKE0 function is selected"
bitfld.long 0x00 9. "GPC_MFP9,PC.9 Pin Function Selection\nBit GPC_MFP9 determines the PC.9 function.\n" "0: GPIO function is selected,1: PWM0_BRAKE1 function is selected"
newline
bitfld.long 0x00 8. "GPC_MFP8,PC.8 Pin Function Selection\nBit GPC_MFP8 determines the PC.8 function.\n" "0: GPIO function is selected,1: PWM0_BRAKE0 function is selected"
bitfld.long 0x00 7. "GPC_MFP7,PC.7 Pin Function Selection\nBits PC7_PWM0BK1 (ALT_MFP3[29]) PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function.\n(PC7_PWM0BK1 PC7_I2C0SCL GPC_MFP7) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 6. "GPC_MFP6,PC.6 Pin Function Selection\nBits PC6_PWM0BK0 (ALT_MFP3[28]) PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function.\n(PC6_PWM0BK0 PC6_I2C0SDA GPC_MFP6) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 3. "GPC_MFP3,PC.3 Pin Function Selection\nBits PC3_BPWM03 (ALT_MFP3[15]) and GPC_MFP3 determine the PC.3 function.\n(PC3_BPWM03 GPC_MFP3) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 2. "GPC_MFP2,PC.2 Pin Function Selection\nBits PC2_BPWM02 (ALT_MFP3[14]) and GPC_MFP2 determine the PC.2 function.\n(PC2_BPWM02 GPC_MFP2) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 1. "GPC_MFP1,PC.1 Pin Function Selection\nBits PC1_BPWM01 (ALT_MFP3[13]) and GPC_MFP1 determine the PC.1 function.\n(PC1_BPWM01 GPC_MFP1) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 0. "GPC_MFP0,PC.0 Pin Function Selection\nBits PC0_BPWM00 (ALT_MFP3[12]) and GPC_MFP0 determine the PC.0 function.\n(PC0_BPWM00 GPC_MFP0) value and function mapping is as following list.\n" "0,1"
group.long 0x3C++0x03
line.long 0x00 "GPD_MFP,GPIOD Multiple Function and Input Type Control Register"
hexmask.long.word 0x00 16.--31. 1. "GPD_TYPEn,Trigger Function Selection\n"
bitfld.long 0x00 15. "GPD_MFP15,PD.15 Pin Function Selection \nBits PD15_BPWM04 (ALT_MFP3[16]) and GPD_MFP15 determine the PD.15 function.\n(PD15_BPWM04 GPD_MFP15) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 14. "GPD_MFP14,PD.14 Pin Function Selection \nBits PD14_BPWM05 (ALT_MFP3[17]) and GPD_MFP14 determine the PD.14 function.\n(PD14_BPWM05 GPD_MFP14) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 7. "GPD_MFP7,PD.7 Pin Function Selection \nBits PD7_BPWM10 (ALT_MFP3[18]) and GPD_MFP7 determine the PD.7 function.\n(PD7_BPWM10 GPD_MFP7) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 6. "GPD_MFP6,PD.6 Pin Function Selection\nBits PD6_BPWM11 (ALT_MFP3[19]) and GPD_MFP6 determine the PD.6 function.\n(PD6_BPWM11 GPD_MFP6) value and function mapping is as following list.\n" "0,1"
group.long 0x40++0x03
line.long 0x00 "GPE_MFP,GPIOE Multiple Function and Input Type Control Register"
bitfld.long 0x00 21. "GPE_TYPE5,Trigger Function Selection\n" "0: GPIOE[5] I/O input Schmitt Trigger function..,1: GPIOE[5] I/O input Schmitt Trigger function.."
bitfld.long 0x00 5. "GPE_MFP5,PE.5 Pin Function Selection\nBits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list.\n" "0,1"
group.long 0x44++0x03
line.long 0x00 "GPF_MFP,GPIOF Multiple Function and Input Type Control Register"
hexmask.long.word 0x00 16.--24. 1. "GPF_TYPEn,Trigger Function Selection\n"
bitfld.long 0x00 8. "GPF_MFP8,PF.8 Pin Function Selection\nBit PF8_BPWM14 (ALT_MFP3[22]) GPF_MFP8 determines the PF.8 function.\n(PF8_BPWM14 GPF_MFP8) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 7. "GPF_MFP7,PF.7 Pin Function Selection\nBit GPF_MFP7 determines the PF.7 function.\n" "0: GPIO function is selected,1: ICE_DAT function is selected"
bitfld.long 0x00 6. "GPF_MFP6,PF.6 Pin Function Selection\nBit GPF_MFP6 determines the PF.6 function.\n" "0: GPIO function is selected,1: ICE_CLK function is selected"
newline
bitfld.long 0x00 5. "GPF_MFP5,PF.5 Pin Function Selection\nBits PF5_PWM15 (ALT_MFP3[11]) and GPF_MFP5 determine the PF.5 function.\n(PF5_PWM15 GPF_MFP5) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 4. "GPF_MFP4,PF.4 Pin Function Selection \nBits PF4_PWM14 (ALT_MFP3[10]) and GPF_MFP4 determine the PF.4 function.\n(PF4_PWM14 GPF_MFP4) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 1. "GPF_MFP1,PF.1 Pin Function Selection \nBit GPF_MFP1 determine the PF.1 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])" "0: GPIO function is selected,1: XT1_IN function is selected"
bitfld.long 0x00 0. "GPF_MFP0,PF.0 Pin Function Selection\nBit GPF_MFP0 determines the PF.0 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])" "0: GPIO function is selected,1: XT1_OUT function is selected"
group.long 0x50++0x03
line.long 0x00 "ALT_MFP,Alternative Multiple Function Pin Control Register"
bitfld.long 0x00 29. "PB8_CLKO,PB.8 Pin Alternative Function Selection\nBits PB8_BPWM12 (ALT_MFP3[20]) PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function.\n(PB8_BPWM12 PB8_CLKO GPB_MFP8) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 27. "PB3_T3EX,PB.3 Pin Alternative Function Selection\nBits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function.\n(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as following.." "0,1"
newline
bitfld.long 0x00 26. "PB2_T2EX,PB.2 Pin Alternative Function Selection\nBits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function.\n(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as following.." "0,1"
bitfld.long 0x00 25. "PE5_T1EX,PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 24. "PB15_T0EX,PB.15 Pin Alternative Function Selection\nBits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function.\n(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as.." "0,1"
group.long 0x5C++0x03
line.long 0x00 "ALT_MFP2,Alternative Multiple Function Pin Control Register 2"
bitfld.long 0x00 5. "PB3_TM3,PB.3 Pin Alternative Function Selection\nBits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function.\n(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as following.." "0,1"
bitfld.long 0x00 4. "PB2_TM2,PB.2 Pin Alternative Function Selection\nBits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function.\n(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as following.." "0,1"
newline
bitfld.long 0x00 3. "PE5_TM1,PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 2. "PB15_TM0,PB.15 Pin Alternative Function Selection\nBits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function.\n(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as.." "0,1"
group.long 0x60++0x03
line.long 0x00 "ALT_MFP3,Alternative Multiple Function Pin Control Register 3"
bitfld.long 0x00 31. "PB2_PWM1BK1,PB.2 Pin Alternative Function Selection\nBits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function.\n(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as.." "0,1"
bitfld.long 0x00 30. "PB3_PWM1BK0,PB.3 Pin Alternative Function Selection\nBits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function.\n(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as.." "0,1"
newline
bitfld.long 0x00 29. "PC7_PWM0BK1,PC.7 Pin Alternative Function Selection\nBits PC7_PWM0BK1 (ALT_MFP3[29]) PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function.\n(PC7_PWM0BK1 PC7_I2C0SCL GPC_MFP7) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 28. "PC6_PWM0BK0,PC.6 Pin Alternative Function Selection\nBits PC6_PWM0BK0 (ALT_MFP3[28]) PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function.\n(PC6_PWM0BK0 PC6_I2C0SDA GPB_MFP6) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 24. "PB11_PWM04,PB.11 Pin Alternative Function Selection\nBits PB11_PWM04 (ALT_MFP3[24]) and GPB_MFP11 determine the PB.11 function.\n(PB11_PWM04 GPB_MFP11) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 23. "PB15_BPWM15,PB.15 Pin Function Selection\nBits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function.\n(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as following.." "0,1"
newline
bitfld.long 0x00 22. "PF8_BPWM14,PF.8 Pin Function Selection\nBit PF8_BPWM14 (ALT_MFP3[22]) GPF_MFP8 determines the PF.8 function.\n(PF8_BPWM14 GPF_MFP8) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 21. "PB12_BPWM13,PB.12 Pin Alternative Function Selection\nBits PB12_BPWM13 (ALT_MFP3[21]) and GPB_MFP12 determine the PB.12 function.\n(PB12_BPWM13 GPB_MFP12) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 20. "PB8_BPWM12,PB.8 Pin Alternative Function Selection\nBits PB8_BPWM12 (ALT_MFP3[20]) PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function.\n(PB8_BPWM12 PB8_CLKO GPB_MFP8) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 19. "PD6_BPWM11,PD.6 Pin Alternative Function Selection\nBits PD6_BPWM11 (ALT_MFP3[19]) and GPD_MFP6 determine the PD.6 function.\n(PD6_BPWM11 GPD_MFP6) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 18. "PD7_BPWM10,PD.7 Pin Alternative Function Selection \nBits PD7_BPWM10 (ALT_MFP3[18]) and GPD_MFP7 determine the PD.7 function.\n(PD7_BPWM10 GPD_MFP7) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 17. "PD14_BPWM05,PD.14 Pin Alternative Function Selection \nBits PD14_BPWM05 (ALT_MFP3[17]) and GPD_MFP14 determine the PD.14 function.\n(PD14_BPWM05 GPD_MFP14) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 16. "PD15_BPWM04,PD.15 Pin Alternative Function Selection \nBits PD15_BPWM04 (ALT_MFP3[16]) and GPD_MFP15 determine the PD.15 function.\n(PD15_BPWM04 GPD_MFP15) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 15. "PC3_BPWM03,PC.3 Pin Alternative Function Selection\nBits PC3_BPWM03 (ALT_MFP3[15]) and GPC_MFP3 determine the PC.3 function.\n(PC3_BPWM03 GPC_MFP3) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 14. "PC2_BPWM02,PC.2 Pin Alternative Function Selection\nBits PC2_BPWM02 (ALT_MFP3[14]) and GPC_MFP2 determine the PC.2 function.\n(PC2_BPWM02 GPC_MFP2) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 13. "PC1_BPWM01,PC.1 Pin Alternative Function Selection\nBits PC1_BPWM01 (ALT_MFP3[13]) and GPC_MFP1 determine the PC.1 function.\n(PC1_BPWM01 GPC_MFP1) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 12. "PC0_BPWM00,PC.0 Pin Alternative Function Selection\nBits PC0_BPWM00 (ALT_MFP3[12]) and GPC_MFP0 determine the PC.0 function.\n(PC0_BPWM00 GPC_MFP0) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 11. "PF5_PWM15,PF.5 Pin Alternative Function Selection\nBits PF5_PWM15 (ALT_MFP3[11]) and GPF_MFP5 determine the PF.5 function.\n(PF5_PWM15 GPF_MFP5) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 10. "PF4_PWM14,PF.4 Pin Alternative Function Selection \nBits PF4_PWM14 (ALT_MFP3[10]) and GPF_MFP4 determine the PF.4 function.\n(PF4_PWM14 GPF_MFP4) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 9. "PA11_PWM13,PA.11 Pin Alternative Function Selection\nBits PA11_PWM13 (ALT_MFP3[9]) and GPA_MFP11 determine the PA.11 function.\n(PA11_PWM13 GPA_MFP11) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 8. "PA10_PWM12,PA.10 Pin Alternative Function Selection\nBits PA10_PWM12 (ALT_MFP3[8]) and GPA_MFP10 determine the PA.10 function.\n(PA10_PWM12 GPA_MFP10) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 7. "PA3_PWM11,PA.3 Pin Alternative Function Selection\nBits PA3_PWM11 (ALT_MFP3[7]) PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function.\n(PA3_PWM11 PA3_UR3RXD GPA_MFP3) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 6. "PA2_PWM10,PA.2 Pin Alternative Function Selection\nBits PA2_PWM10 (ALT_MFP3[6]) PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function.\n(PA2_PWM10 PA2_UR3TXD GPA_MFP2) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 5. "PA1_PWM05,PA.1 Pin Alternative Function Selection\nBits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function.\n(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is as.." "0,1"
newline
bitfld.long 0x00 4. "PA0_PWM04,PA.0 Pin Alternative Function Selection\nBits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function.\n(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is as.." "0,1"
group.long 0x64++0x03
line.long 0x00 "ALT_MFP4,Alternative Multiple Function Pin Control Register 4"
bitfld.long 0x00 14. "PA7_VREF,PA.7 Pin Alternative Function Selection\nBits PA7_VREF (ALT_MFP4[14]) and GPA_MFP7 determine the PA.7 function.\n(PA7_VREF GPA_MFP7) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 13. "PA1_I2C1SDA,PA.1 Pin Alternative Function Selection\nBits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function.\n(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is as.." "0,1"
newline
bitfld.long 0x00 12. "PA0_I2C1SCL,PA.0 Pin Alternative Function Selection\nBits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function.\n(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is as.." "0,1"
bitfld.long 0x00 11. "PC7_I2C0SCL,PC.7 Pin Alternative Function Selection\nBits PC7_PWM0BK1 (ALT_MFP3[29]) PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function.\n(PC7_PWM0BK1 PC7_I2C0SCL GPC_MFP7) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 10. "PC6_I2C0SDA,PC.6 Pin Alternative Function Selection\nBits PC6_PWM0BK0 (ALT_MFP3[28]) PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function.\n(PC6_PWM0BK0 PC6_I2C0SDA GPC_MFP6) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 9. "PA13_UR5TXD,PA.13 Pin Alternative Function Selection\nBits PA13_UR5TXD (ALT_MFP4[9]) and GPA_MFP13 determine the PA.13 function.\n(PA13_UR5TXD GPA_MFP13) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 8. "PA12_UR5RXD,PA.12 Pin Alternative Function Selection\nBits PA12_UR5RXD (ALT_MFP4[8]) and GPA_MFP12 determine the PA.12 function.\n(PA12_UR5RXD GPA_MFP12) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 7. "PA0_UR5TXD,PA.0 Pin Alternative Function Selection\nBits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function.\n(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is as.." "0,1"
newline
bitfld.long 0x00 6. "PA1_UR5RXD,PA.1 Pin Alternative Function Selection\nBits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function.\n(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is as.." "0,1"
bitfld.long 0x00 5. "PA6_UR3TXD,PA.6 Pin Alternative Function Selection\nBits PA6_UR3TXD (ALT_MFP4[5]) and GPA_MFP6 determine the PA.6 function.\n(PA6_UR3TXD GPA_MFP6) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 4. "PA5_UR3RXD,PA.5 Pin Alternative Function Selection\nBits PA5_UR3RXD (ALT_MFP4[4]) and GPA_MFP5 determine the PA.5 function.\n(PA5_UR3RXD GPA_MFP5) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 3. "PA2_UR3TXD,PA.2 Pin Alternative Function Selection\nBits PA2_PWM10 (ALT_MFP3[6]) PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function.\n(PA2_PWM10 PA2_UR3TXD GPA_MFP2) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 2. "PA3_UR3RXD,PA.3 Pin Alternative Function Selection\nBits PA3_PWM11 (ALT_MFP3[7]) PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function.\n(PA3_PWM11 PA3_UR3RXD GPA_MFP3) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 1. "PA9_UR1CTS,PA.9 Pin Alternative Function Selection\nBits PA9_UR1CTS (ALT_MFP4[1]) and GPA_MFP9 determine the PA.9 function.\n(PA9_UR1CTS GPA_MFP9) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 0. "PA8_UR1RTS,PA.8 Pin Alternative Function Selection\nBits PA8_UR1RTS (ALT_MFP4[0]) and GPA_MFP8 determine the PA.8 function.\n(PA8_UR1RTS GPA_MFP8) value and function mapping is as following list.\n" "0,1"
group.long 0x100++0x03
line.long 0x00 "REGWRPROT,Register Write Protection Register"
hexmask.long.byte 0x00 1.--7. 1. "REGWRPROT,Register Write-Protection Code (Write Only)\nSome registers have write-protection function"
rbitfld.long 0x00 0. "REGPROTDIS,Register Write-Protection Disable Index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nVREFCR: address 0x5000_0028\nPWRCON: address 0x5000_0200 (bit[6] is not.." "0: Write-protection is enabled for writing..,1: Write-protection is disabled for writing.."
tree.end
tree "GPIO"
base ad:0x50004000
group.long 0x00++0x03
line.long 0x00 "GPIOA_PMD,GPIO Port A Pin I/O Mode Control"
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x04++0x03
line.long 0x00 "GPIOA_OFFD,GPIO Port A Pin Digital Input Path Disable Control"
bitfld.long 0x00 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
group.long 0x08++0x03
line.long 0x00 "GPIOA_DOUT,GPIO Port A Data Output Value"
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
group.long 0x0C++0x03
line.long 0x00 "GPIOA_DMASK,GPIO Port A Data Output Write Mask"
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
rgroup.long 0x10++0x03
line.long 0x00 "GPIOA_PIN,GPIO Port A Pin Value"
bitfld.long 0x00 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
bitfld.long 0x00 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
bitfld.long 0x00 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
group.long 0x14++0x03
line.long 0x00 "GPIOA_DBEN,GPIO Port A De-bounce Enable"
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
group.long 0x18++0x03
line.long 0x00 "GPIOA_IMD,GPIO Port A Interrupt Mode Control"
bitfld.long 0x00 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x1C++0x03
line.long 0x00 "GPIOA_IEN,GPIO Port A Interrupt Enable"
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
group.long 0x20++0x03
line.long 0x00 "GPIOA_ISRC,GPIO Port A Interrupt Source Flag"
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
group.long 0x40++0x03
line.long 0x00 "GPIOB_PMD,GPIO Port B Pin I/O Mode Control"
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x44++0x03
line.long 0x00 "GPIOB_OFFD,GPIO Port B Pin Digital Input Path Disable Control"
bitfld.long 0x00 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
group.long 0x48++0x03
line.long 0x00 "GPIOB_DOUT,GPIO Port B Data Output Value"
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
group.long 0x4C++0x03
line.long 0x00 "GPIOB_DMASK,GPIO Port B Data Output Write Mask"
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
group.long 0x50++0x03
line.long 0x00 "GPIOB_PIN,GPIO Port B Pin Value"
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
group.long 0x54++0x03
line.long 0x00 "GPIOB_DBEN,GPIO Port B De-bounce Enable"
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
group.long 0x58++0x03
line.long 0x00 "GPIOB_IMD,GPIO Port B Interrupt Mode Control"
bitfld.long 0x00 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x5C++0x03
line.long 0x00 "GPIOB_IEN,GPIO Port B Interrupt Enable"
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
group.long 0x60++0x03
line.long 0x00 "GPIOB_ISRC,GPIO Port B Interrupt Source Flag"
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
group.long 0x80++0x03
line.long 0x00 "GPIOC_PMD,GPIO Port C Pin I/O Mode Control"
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x84++0x03
line.long 0x00 "GPIOC_OFFD,GPIO Port C Pin Digital Input Path Disable Control"
bitfld.long 0x00 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
group.long 0x88++0x03
line.long 0x00 "GPIOC_DOUT,GPIO Port C Data Output Value"
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
group.long 0x8C++0x03
line.long 0x00 "GPIOC_DMASK,GPIO Port C Data Output Write Mask"
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
group.long 0x90++0x03
line.long 0x00 "GPIOC_PIN,GPIO Port C Pin Value"
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
group.long 0x94++0x03
line.long 0x00 "GPIOC_DBEN,GPIO Port C De-bounce Enable"
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
group.long 0x98++0x03
line.long 0x00 "GPIOC_IMD,GPIO Port C Interrupt Mode Control"
bitfld.long 0x00 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x9C++0x03
line.long 0x00 "GPIOC_IEN,GPIO Port C Interrupt Enable"
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
group.long 0xA0++0x03
line.long 0x00 "GPIOC_ISRC,GPIO Port C Interrupt Source Flag"
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
group.long 0xC0++0x03
line.long 0x00 "GPIOD_PMD,GPIO Port D Pin I/O Mode Control"
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0xC4++0x03
line.long 0x00 "GPIOD_OFFD,GPIO Port D Pin Digital Input Path Disable Control"
bitfld.long 0x00 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
group.long 0xC8++0x03
line.long 0x00 "GPIOD_DOUT,GPIO Port D Data Output Value"
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
group.long 0xCC++0x03
line.long 0x00 "GPIOD_DMASK,GPIO Port D Data Output Write Mask"
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
group.long 0xD0++0x03
line.long 0x00 "GPIOD_PIN,GPIO Port D Pin Value"
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
group.long 0xD4++0x03
line.long 0x00 "GPIOD_DBEN,GPIO Port D De-bounce Enable"
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
group.long 0xD8++0x03
line.long 0x00 "GPIOD_IMD,GPIO Port D Interrupt Mode Control"
bitfld.long 0x00 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0xDC++0x03
line.long 0x00 "GPIOD_IEN,GPIO Port D Interrupt Enable"
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
group.long 0xE0++0x03
line.long 0x00 "GPIOD_ISRC,GPIO Port D Interrupt Source Flag"
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
group.long 0x100++0x03
line.long 0x00 "GPIOE_PMD,GPIO Port E Pin I/O Mode Control"
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x104++0x03
line.long 0x00 "GPIOE_OFFD,GPIO Port E Pin Digital Input Path Disable Control"
bitfld.long 0x00 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
group.long 0x108++0x03
line.long 0x00 "GPIOE_DOUT,GPIO Port E Data Output Value"
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
group.long 0x10C++0x03
line.long 0x00 "GPIOE_DMASK,GPIO Port E Data Output Write Mask"
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
group.long 0x110++0x03
line.long 0x00 "GPIOE_PIN,GPIO Port E Pin Value"
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
group.long 0x114++0x03
line.long 0x00 "GPIOE_DBEN,GPIO Port E De-bounce Enable"
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
group.long 0x118++0x03
line.long 0x00 "GPIOE_IMD,GPIO Port E Interrupt Mode Control"
bitfld.long 0x00 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x11C++0x03
line.long 0x00 "GPIOE_IEN,GPIO Port E Interrupt Enable"
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
group.long 0x120++0x03
line.long 0x00 "GPIOE_ISRC,GPIO Port E Interrupt Source Flag"
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
group.long 0x140++0x03
line.long 0x00 "GPIOF_PMD,GPIO Port F Pin I/O Mode Control"
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10])" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x144++0x03
line.long 0x00 "GPIOF_OFFD,GPIO Port F Pin Digital Input Path Disable Control"
bitfld.long 0x00 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
newline
bitfld.long 0x00 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
bitfld.long 0x00 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled" "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital.."
group.long 0x148++0x03
line.long 0x00 "GPIOF_DOUT,GPIO Port F Data Output Value"
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
newline
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive.."
group.long 0x14C++0x03
line.long 0x00 "GPIOF_DMASK,GPIO Port F Data Output Write Mask"
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
newline
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
group.long 0x150++0x03
line.long 0x00 "GPIOF_PIN,GPIO Port F Pin Value"
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
group.long 0x154++0x03
line.long 0x00 "GPIOF_DBEN,GPIO Port F De-bounce Enable"
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
newline
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
group.long 0x158++0x03
line.long 0x00 "GPIOF_IMD,GPIO Port F Interrupt Mode Control"
bitfld.long 0x00 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x00 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x15C++0x03
line.long 0x00 "GPIOF_IEN,GPIO Port F Interrupt Enable"
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
newline
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
newline
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
group.long 0x160++0x03
line.long 0x00 "GPIOF_ISRC,GPIO Port F Interrupt Source Flag"
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
newline
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
group.long 0x180++0x03
line.long 0x00 "DBNCECON,External Interrupt De-bounce Control"
bitfld.long 0x00 5. "ICLK_ON,Interrupt Clock On Mode\nIt is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
bitfld.long 0x00 4. "DBCLKSRC,De-Bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
newline
bitfld.long 0x00 0.--3. "DBCLKSEL,De-Bounce Sampling Cycle Selection\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x200++0x03
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x204++0x03
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x208++0x03
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x20C++0x03
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x210++0x03
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x214++0x03
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x218++0x03
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x21C++0x03
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x220++0x03
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x224++0x03
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x228++0x03
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x22C++0x03
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x230++0x03
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x234++0x03
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x238++0x03
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x23C++0x03
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x240++0x03
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x244++0x03
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x248++0x03
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x24C++0x03
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x250++0x03
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x254++0x03
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x258++0x03
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x25C++0x03
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x260++0x03
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x264++0x03
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x268++0x03
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x26C++0x03
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x270++0x03
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x274++0x03
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x278++0x03
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x27C++0x03
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output"
group.long 0x280++0x03
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x284++0x03
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x288++0x03
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x28C++0x03
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x298++0x03
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x29C++0x03
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2A0++0x03
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2A4++0x03
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2A8++0x03
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2AC++0x03
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2B8++0x03
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2BC++0x03
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output"
group.long 0x2D8++0x03
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x2DC++0x03
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output"
group.long 0x2F8++0x03
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output"
group.long 0x2FC++0x03
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output"
group.long 0x314++0x03
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x340++0x03
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x344++0x03
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output"
group.long 0x350++0x03
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output"
group.long 0x354++0x03
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output"
group.long 0x358++0x03
line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output"
group.long 0x35C++0x03
line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output"
group.long 0x360++0x03
line.long 0x00 "PF8_PDIO,GPIO PF.n Pin Data Input/Output"
tree.end
tree "I2C"
repeat 2. (list 0. 1.) (list ad:0x40020000 ad:0x40120000)
tree "I2C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "I2CON,I2C Control Register"
bitfld.long 0x00 7. "EI,Interrupt Enable Coontrol\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x00 6. "ENS1,I2C Controller Enable Coontrol\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1"
newline
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested" "0,1"
bitfld.long 0x00 2. "AA,Assert Acknowledge Control\n" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2CADDR0,I2C Slave Address Register0"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x08++0x03
line.long 0x00 "I2CDAT,I2C Data Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CDAT,I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port"
rgroup.long 0x0C++0x03
line.long 0x00 "I2CSTATUS,I2C Status Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CSTATUS,I2C Status Register\nThere are 26 possible status codes"
group.long 0x10++0x03
line.long 0x00 "I2CLK,I2C Clock Divided Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CLK,I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4"
group.long 0x14++0x03
line.long 0x00 "I2CTOC,I2C Time-out Counter Register"
bitfld.long 0x00 2. "ENTI,Time-Out Counter Enable Coontrol \nWhen Enabled the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "DIV4,Time-Out Counter Input Clock Divided By 4\nWhen Enabled The time-out period is extend 4 times" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "TIF,Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI (I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "I2CADDR1,I2C Slave Address Register1"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x1C++0x03
line.long 0x00 "I2CADDR2,I2C Slave Address Register2"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x20++0x03
line.long 0x00 "I2CADDR3,I2C Slave Address Register3"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x24++0x03
line.long 0x00 "I2CADM0,I2C Slave Address Mask Register0"
hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register"
group.long 0x28++0x03
line.long 0x00 "I2CADM1,I2C Slave Address Mask Register1"
hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register"
group.long 0x2C++0x03
line.long 0x00 "I2CADM2,I2C Slave Address Mask Register2"
hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register"
group.long 0x30++0x03
line.long 0x00 "I2CADM3,I2C Slave Address Mask Register3"
hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register"
group.long 0x3C++0x03
line.long 0x00 "I2CWKUPCON,I2C Wake-up Control Register"
bitfld.long 0x00 0. "WKUPEN,I2C Wake-Up Enable Coontrol\n" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
group.long 0x40++0x03
line.long 0x00 "I2CWKUPSTS,I2C Wake-up Status Register"
bitfld.long 0x00 0. "WKUPIF,I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit" "0: Chip is not woken-up from Power-down mode by..,1: Chip is woken-up from Power-down mode by I2C"
tree.end
repeat.end
tree.end
tree "INT"
base ad:0x50000300
rgroup.long 0x00++0x03
line.long 0x00 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
bitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "IRQ4_SRC,IRQ4 (GPA/B) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "IRQ5_SRC,IRQ5 (GPC/D/E/F) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "IRQ6_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "IRQ7_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x03
line.long 0x00 "IRQ10_SRC,IRQ10 (TMR2) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "IRQ11_SRC,IRQ11 (TMR3) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "IRQ12_SRC,IRQ12 (UART0/2) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x03
line.long 0x00 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x03
line.long 0x00 "IRQ15_SRC,IRQ15 (UART3) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "IRQ16_SRC,IRQ16 (UART4) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x03
line.long 0x00 "IRQ17_SRC,IRQ17 (UART5) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x48++0x03
line.long 0x00 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x03
line.long 0x00 "IRQ19_SRC,IRQ19 (I2C1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x03
line.long 0x00 "IRQ20_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x03
line.long 0x00 "IRQ21_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "IRQ22_SRC,IRQ22 (PWM0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "IRQ23_SRC,IRQ23 (PWM1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x03
line.long 0x00 "IRQ24_SRC,IRQ24 (BPWM0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x64++0x03
line.long 0x00 "IRQ25_SRC,IRQ25 (BPWM1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x68++0x03
line.long 0x00 "IRQ26_SRC,IRQ26 (BRAKE0) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6C++0x03
line.long 0x00 "IRQ27_SRC,IRQ27 (BRAKE1) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x74++0x03
line.long 0x00 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x78++0x03
line.long 0x00 "IRQ30_SRC,IRQ30 (CKD) Interrupt Source Identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7C++0x03
line.long 0x00 "IRQ31_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "NMI_SEL,NMI Source Interrupt Select Control Register"
bitfld.long 0x00 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
bitfld.long 0x00 0.--4. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x84++0x03
line.long 0x00 "MCU_IRQ,MCU Interrupt Request Source Register"
hexmask.long 0x00 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0"
group.long 0x88++0x03
line.long 0x00 "MCU_IRQCR,MCU Interrupt Request Control Register"
bitfld.long 0x00 0. "FAST_IRQ,Fast IRQ Latency Enable Bit\n" "0: MCU IRQ latency is fixed at 13 clock cycles..,1: MCU IRQ latency will not fixed MCU will enter.."
tree.end
tree "PWM"
repeat 2. (list 0. 1.) (list ad:0x40040000 ad:0x40140000)
tree "PWM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "PWM_CTL0,PWM Control Register 0"
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
newline
bitfld.long 0x00 16.--21. "IMMLDENn,Immediately Load Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF..,?..."
bitfld.long 0x00 0.--5. "CTRLDn,Center Re-Load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "PWM_CTL1,PWM Control Register 1"
bitfld.long 0x00 24.--26. "PWMMODEn,PWM Mode\nEach bit n controls the corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: PWM independent mode,1: PWM complementary mode,?..."
bitfld.long 0x00 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nEach bit n controls corresponding PWM channel n.\n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
newline
bitfld.long 0x00 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nEach bit n controls corresponding PWM channel n.\n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
bitfld.long 0x00 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nEach bit n controls corresponding PWM channel n.\n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
group.long 0x10++0x03
line.long 0x00 "PWM_CLKSRC,PWM Clock Source Register"
bitfld.long 0x00 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select\n" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
bitfld.long 0x00 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select\n" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
newline
bitfld.long 0x00 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select\n" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
group.long 0x14++0x03
line.long 0x00 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0_1"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale \nThe clock of PWM counter is decided by clock prescaler"
group.long 0x18++0x03
line.long 0x00 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2_3"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale \nThe clock of PWM counter is decided by clock prescaler"
group.long 0x1C++0x03
line.long 0x00 "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4_5"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale \nThe clock of PWM counter is decided by clock prescaler"
group.long 0x20++0x03
line.long 0x00 "PWM_CNTEN,PWM Counter Enable Register"
bitfld.long 0x00 4. "CNTEN4,PWM Counter Enable 4\n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
bitfld.long 0x00 2. "CNTEN2,PWM Counter Enable 2\n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
newline
bitfld.long 0x00 0. "CNTEN0,PWM Counter Enable 0\n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
group.long 0x24++0x03
line.long 0x00 "PWM_CNTCLR,PWM Clear Counter Register"
bitfld.long 0x00 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.\n" "0: No effect,1: Clear 16-bit PWM counter to 0000H"
bitfld.long 0x00 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.\n" "0: No effect,1: Clear 16-bit PWM counter to 0000H"
newline
bitfld.long 0x00 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n" "0: No effect,1: Clear 16-bit PWM counter to 0000H"
group.long 0x30++0x03
line.long 0x00 "PWM_PERIOD0,PWM Period Register 0"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.\n"
group.long 0x38++0x03
line.long 0x00 "PWM_PERIOD2,PWM Period Register 2"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.\n"
group.long 0x40++0x03
line.long 0x00 "PWM_PERIOD4,PWM Period Register 4"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.\n"
group.long 0x50++0x03
line.long 0x00 "PWM_CMPDAT0,PWM Comparator Register 0"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
group.long 0x54++0x03
line.long 0x00 "PWM_CMPDAT1,PWM Comparator Register 1"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
group.long 0x58++0x03
line.long 0x00 "PWM_CMPDAT2,PWM Comparator Register 2"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
group.long 0x5C++0x03
line.long 0x00 "PWM_CMPDAT3,PWM Comparator Register 3"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
group.long 0x60++0x03
line.long 0x00 "PWM_CMPDAT4,PWM Comparator Register 4"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
group.long 0x64++0x03
line.long 0x00 "PWM_CMPDAT5,PWM Comparator Register 5"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
group.long 0x70++0x03
line.long 0x00 "PWM_DTCTL0_1,PWM Dead-time Control Register 0_1"
bitfld.long 0x00 24. "DTCKSEL,Dead-Time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x00 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
newline
hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected"
group.long 0x74++0x03
line.long 0x00 "PWM_DTCTL2_3,PWM Dead-time Control Register 2_3"
bitfld.long 0x00 24. "DTCKSEL,Dead-Time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x00 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
newline
hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected"
group.long 0x78++0x03
line.long 0x00 "PWM_DTCTL4_5,PWM Dead-time Control Register 4_5"
bitfld.long 0x00 24. "DTCKSEL,Dead-Time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x00 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
newline
hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected"
rgroup.long 0x90++0x03
line.long 0x00 "PWM_CNT0,PWM Counter Register 0"
bitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)\n" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
group.long 0x98++0x03
line.long 0x00 "PWM_CNT2,PWM Counter Register 2"
rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)\n" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
group.long 0xA0++0x03
line.long 0x00 "PWM_CNT4,PWM Counter Register 4"
rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)\n" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
group.long 0xB0++0x03
line.long 0x00 "PWM_WGCTL0,PWM Generation Register 0"
hexmask.long.word 0x00 16.--27. 1. "PRDPCTLn,PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter.."
hexmask.long.word 0x00 0.--11. 1. "ZPCTLn,PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero"
group.long 0xB4++0x03
line.long 0x00 "PWM_WGCTL1,PWM Generation Register 1"
hexmask.long.word 0x00 16.--27. 1. "CMPDCTLn,PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4"
hexmask.long.word 0x00 0.--11. 1. "CMPUCTLn,PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4"
group.long 0xB8++0x03
line.long 0x00 "PWM_MSKEN,PWM Mask Enable Register"
bitfld.long 0x00 0.--5. "MSKENn,PWM Mask Enable Control\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output..,?..."
group.long 0xBC++0x03
line.long 0x00 "PWM_MSK,PWM Mask Data Register"
bitfld.long 0x00 0.--5. "MSKDATn,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWMn,1: Output logic high to PWMn,?..."
group.long 0xC0++0x03
line.long 0x00 "PWM_BNF,PWM Brake Noise Filter Register"
bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting:\n" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting:\n" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
newline
bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse\n" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is.."
bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "BRK1FCS,Brake 1 Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
bitfld.long 0x00 8. "BRK1FEN,PWM Brake 1 Noise Filter Enable Control\n" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
newline
bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse\n" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is.."
bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 1.--3. "BRK0FCS,Brake 0 Edge Detector Filter Clock Selection\n" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,2: Filter clock is HCLK/4,3: Filter clock is HCLK/8,4: Filter clock is HCLK/16,5: Filter clock is HCLK/32,6: Filter clock is HCLK/64,7: Filter clock is HCLK/128"
bitfld.long 0x00 0. "BRK0FEN,PWM Brake 0 Noise Filter Enable Control\n" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
group.long 0xC4++0x03
line.long 0x00 "PWM_FAILBRK,PWM System Fail Brake Control Register"
bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Control\n" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
bitfld.long 0x00 1. "BODBRKEN,Brown-Out Detection Trigger PWM Brake Function 0 Enable\n" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
newline
bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Control\n" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
group.long 0xC8++0x03
line.long 0x00 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0_1"
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect)\nNote: This register is write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.."
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect)\nNote: This register is write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.."
newline
bitfld.long 0x00 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
newline
bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x00 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
newline
bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
group.long 0xCC++0x03
line.long 0x00 "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2_3"
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect)\nNote: This register is write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.."
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect)\nNote: This register is write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.."
newline
bitfld.long 0x00 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
newline
bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x00 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
newline
bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
group.long 0xD0++0x03
line.long 0x00 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4_5"
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect)\nNote: This register is write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.."
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect)\nNote: This register is write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.."
newline
bitfld.long 0x00 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
newline
bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x00 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
newline
bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
group.long 0xD4++0x03
line.long 0x00 "PWM_POLCTL,PWM Pin Polar Inverse Register"
bitfld.long 0x00 0.--5. "PINVn,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled,?..."
group.long 0xD8++0x03
line.long 0x00 "PWM_POEN,PWM Output Enable Register"
bitfld.long 0x00 0.--5. "POENn,PWM Pin Output Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: PWM pin at tri-state,1: PWM pin in output mode,?..."
wgroup.long 0xDC++0x03
line.long 0x00 "PWM_SWBRK,PWM Software Brake Control Register"
bitfld.long 0x00 8.--10. "BRKLTRGn,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "BRKETRGn,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1,2,3,4,5,6,7"
group.long 0xE0++0x03
line.long 0x00 "PWM_INTEN0,PWM Interrupt Enable Register 0"
bitfld.long 0x00 24.--29. "CMPDIENn,PWM Compare Down Count Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled,?..."
bitfld.long 0x00 16.--21. "CMPUIENn,PWM Compare Up Count Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled,?..."
newline
bitfld.long 0x00 12. "PIEN4,PWM Period Point Interrupt Enable 4\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x00 10. "PIEN2,PWM Period Point Interrupt Enable 2\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
newline
bitfld.long 0x00 8. "PIEN0,PWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x00 4. "ZIEN4,PWM Zero Point Interrupt Enable 4\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
newline
bitfld.long 0x00 2. "ZIEN2,PWM Zero Point Interrupt Enable 2\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x00 0. "ZIEN0,PWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
group.long 0xE4++0x03
line.long 0x00 "PWM_INTEN1,PWM Interrupt Enable Register 1"
bitfld.long 0x00 10. "BRKLIEN4_5,PWM Level-Detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
bitfld.long 0x00 9. "BRKLIEN2_3,PWM Level-Detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
newline
bitfld.long 0x00 8. "BRKLIEN0_1,PWM Level-Detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
bitfld.long 0x00 2. "BRKEIEN4_5,PWM Edge-Detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
newline
bitfld.long 0x00 1. "BRKEIEN2_3,PWM Edge-Detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
bitfld.long 0x00 0. "BRKEIEN0_1,PWM Edge-Detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
group.long 0xE8++0x03
line.long 0x00 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
bitfld.long 0x00 24.--29. "CMPDIFn,PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "CMPUIFn,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4 software can write 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2 software can write 1 to clear this bit to zero" "0,1"
newline
bitfld.long 0x00 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0 software can write 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches zero software can write 1 to clear this bit to zero" "0,1"
newline
bitfld.long 0x00 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches zero software can write 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches zero software can write 1 to clear this bit to zero" "0,1"
group.long 0xEC++0x03
line.long 0x00 "PWM_INTSTS1,PWM Interrupt Flag Register 1"
rbitfld.long 0x00 29. "BRKLSTS5,PWM Channel5 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel5 level-detect brake state is..,1: When PWM channel5 level-detect brake detects.."
rbitfld.long 0x00 28. "BRKLSTS4,PWM Channel4 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel4 level-detect brake state is..,1: When PWM channel4 level-detect brake detects.."
newline
rbitfld.long 0x00 27. "BRKLSTS3,PWM Channel3 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel3 level-detect brake state is..,1: When PWM channel3 level-detect brake detects.."
rbitfld.long 0x00 26. "BRKLSTS2,PWM Channel2 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel2 level-detect brake state is..,1: When PWM channel2 level-detect brake detects.."
newline
rbitfld.long 0x00 25. "BRKLSTS1,PWM Channel1 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel1 level-detect brake state is..,1: When PWM channel1 level-detect brake detects.."
rbitfld.long 0x00 24. "BRKLSTS0,PWM Channel0 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel0 level-detect brake state is..,1: When PWM channel0 level-detect brake detects.."
newline
bitfld.long 0x00 21. "BRKESTS5,PWM Channel5 Edge-Detect Brake Status\n" "0: PWM channel5 edge-detect brake state is..,1: When PWM channel5 edge-detect brake detects a.."
bitfld.long 0x00 20. "BRKESTS4,PWM Channel4 Edge-Detect Brake Status\n" "0: PWM channel4 edge-detect brake state is..,1: When PWM channel4 edge-detect brake detects a.."
newline
bitfld.long 0x00 19. "BRKESTS3,PWM Channel3 Edge-Detect Brake Status\n" "0: PWM channel3 edge-detect brake state is..,1: When PWM channel3 edge-detect brake detects a.."
bitfld.long 0x00 18. "BRKESTS2,PWM Channel2 Edge-Detect Brake Status\n" "0: PWM channel2 edge-detect brake state is..,1: When PWM channel2 edge-detect brake detects a.."
newline
bitfld.long 0x00 17. "BRKESTS1,PWM Channel1 Edge-Detect Brake Status\n" "0: PWM channel1 edge-detect brake state is..,1: When PWM channel1 edge-detect brake detects a.."
bitfld.long 0x00 16. "BRKESTS0,PWM Channel0 Edge-Detect Brake Status\n" "0: PWM channel0 edge-detect brake state is..,1: When PWM channel0 edge-detect brake detects a.."
newline
bitfld.long 0x00 13. "BRKLIF5,PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel5 level-detect brake event do not..,1: When PWM channel5 level-detect brake event.."
bitfld.long 0x00 12. "BRKLIF4,PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel4 level-detect brake event do not..,1: When PWM channel4 level-detect brake event.."
newline
bitfld.long 0x00 11. "BRKLIF3,PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel3 level-detect brake event do not..,1: When PWM channel3 level-detect brake event.."
bitfld.long 0x00 10. "BRKLIF2,PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel2 level-detect brake event do not..,1: When PWM channel2 level-detect brake event.."
newline
bitfld.long 0x00 9. "BRKLIF1,PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel1 level-detect brake event do not..,1: When PWM channel1 level-detect brake event.."
bitfld.long 0x00 8. "BRKLIF0,PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel0 level-detect brake event do not..,1: When PWM channel0 level-detect brake event.."
newline
bitfld.long 0x00 5. "BRKEIF5,PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel5 edge-detect brake event do not..,1: When PWM channel5 edge-detect brake event.."
bitfld.long 0x00 4. "BRKEIF4,PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel4 edge-detect brake event do not..,1: When PWM channel4 edge-detect brake event.."
newline
bitfld.long 0x00 3. "BRKEIF3,PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel3 edge-detect brake event do not..,1: When PWM channel3 edge-detect brake event.."
bitfld.long 0x00 2. "BRKEIF2,PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel2 edge-detect brake event do not..,1: When PWM channel2 edge-detect brake event.."
newline
bitfld.long 0x00 1. "BRKEIF1,PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel1 edge-detect brake event do not..,1: When PWM channel1 edge-detect brake event.."
bitfld.long 0x00 0. "BRKEIF0,PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected" "0: PWM channel0 edge-detect brake event do not..,1: When PWM channel0 edge-detect brake event.."
group.long 0xF8++0x03
line.long 0x00 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0"
bitfld.long 0x00 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 24.--27. "TRGSEL3,PWM_CH3 Trigger ADC Source Select\n" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count CMPDAT point,4: PWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH3 up-count CMPDAT point,9: PWM_CH3 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 16.--19. "TRGSEL2,PWM_CH2 Trigger ADC Source Select\n" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count CMPDAT point,4: PWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH3 up-count CMPDAT point,9: PWM_CH3 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 8.--11. "TRGSEL1,PWM_CH1 Trigger ADC Source Select\n" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count CMPDAT point,4: PWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH1 up-count CMPDAT point,9: PWM_CH1 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 0.--3. "TRGSEL0,PWM_CH0 Trigger ADC Source Select\n" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count CMPDAT point,4: PWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH1 up-count CMPDAT point,9: PWM_CH1 down-count CMPDAT point,?..."
group.long 0xFC++0x03
line.long 0x00 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1"
bitfld.long 0x00 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 8.--11. "TRGSEL5,PWM_CH5 Trigger ADC Source Select\n" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count CMPDAT point,4: PWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH5 up-count CMPDAT point,9: PWM_CH5 down-count CMPDAT point,?..."
newline
bitfld.long 0x00 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 0.--3. "TRGSEL4,PWM_CH4 Trigger ADC Source Select\n" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count CMPDAT point,4: PWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH5 up-count CMPDAT point,9: PWM_CH5 down-count CMPDAT point,?..."
group.long 0x110++0x03
line.long 0x00 "PWM_SSCTL,PWM Synchronous Start Control Register"
bitfld.long 0x00 8.--9. "SSRC,PWM Synchronous Start Source Select\n" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
bitfld.long 0x00 4. "SSEN4,PWM Synchronous Start Function Enable 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
newline
bitfld.long 0x00 2. "SSEN2,PWM Synchronous Start Function Enable 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
bitfld.long 0x00 0. "SSEN0,PWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
wgroup.long 0x114++0x03
line.long 0x00 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
bitfld.long 0x00 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
group.long 0x120++0x03
line.long 0x00 "PWM_STATUS,PWM Status Register"
bitfld.long 0x00 16.--21. "ADCTRGn,ADC Start Of Conversion Status\nEach bit n controls the corresponding PWM channel n.\n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger..,?..."
bitfld.long 0x00 4. "CNTMAX4,Time-Base Counter 4 Equal To 0xFFFF Latched Status\n" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
newline
bitfld.long 0x00 2. "CNTMAX2,Time-Base Counter 2 Equal To 0xFFFF Latched Status\n" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
bitfld.long 0x00 0. "CNTMAX0,Time-Base Counter 0 Equal To 0xFFFF Latched Status\n" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
group.long 0x200++0x03
line.long 0x00 "PWM_CAPINEN,PWM Capture Input Enable Register"
bitfld.long 0x00 0.--5. "CAPINENn,Capture Input Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled,?..."
group.long 0x204++0x03
line.long 0x00 "PWM_CAPCTL,PWM Capture Control Register"
bitfld.long 0x00 24.--29. "FCRLDENn,Falling Capture Reload Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled,?..."
bitfld.long 0x00 16.--21. "RCRLDENn,Rising Capture Reload Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled,?..."
newline
bitfld.long 0x00 8.--13. "CAPINVn,Capture Inverter Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled,?..."
bitfld.long 0x00 0.--5. "CAPENn,Capture Function Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: Capture function Disabled,1: Capture function Enabled,?..."
rgroup.long 0x208++0x03
line.long 0x00 "PWM_CAPSTS,PWM Capture Status Register"
bitfld.long 0x00 8.--13. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x20C++0x03
line.long 0x00 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
rgroup.long 0x210++0x03
line.long 0x00 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x214++0x03
line.long 0x00 "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x218++0x03
line.long 0x00 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x21C++0x03
line.long 0x00 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x220++0x03
line.long 0x00 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x224++0x03
line.long 0x00 "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x228++0x03
line.long 0x00 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x22C++0x03
line.long 0x00 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x230++0x03
line.long 0x00 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x234++0x03
line.long 0x00 "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x238++0x03
line.long 0x00 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x250++0x03
line.long 0x00 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
bitfld.long 0x00 8.--13. "CAPFIENn,PWM Capture Falling Latch Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
bitfld.long 0x00 0.--5. "CAPRIENn,PWM Capture Rising Latch Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
group.long 0x254++0x03
line.long 0x00 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
bitfld.long 0x00 8.--13. "CFLIFn,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this..,?..."
bitfld.long 0x00 0.--5. "CRLIFn,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this..,?..."
rgroup.long 0x304++0x03
line.long 0x00 "PWM_PBUF0,PWM PERIOD0 Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
group.long 0x30C++0x03
line.long 0x00 "PWM_PBUF2,PWM PERIOD2 Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
group.long 0x314++0x03
line.long 0x00 "PWM_PBUF4,PWM PERIOD4 Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
rgroup.long 0x31C++0x03
line.long 0x00 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x320++0x03
line.long 0x00 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x324++0x03
line.long 0x00 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x328++0x03
line.long 0x00 "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x32C++0x03
line.long 0x00 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x330++0x03
line.long 0x00 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
tree.end
repeat.end
tree.end
tree "SPI"
base ad:0x40030000
group.long 0x00++0x03
line.long 0x00 "SPI_CNTRL,Control and Status Register"
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
newline
rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
newline
bitfld.long 0x00 23. "VARCLK_EN,Variable Clock Enable Coontrol (Master Only)\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)" "0: SPI clock output frequency is fixed and..,1: SPI clock output frequency is variable"
bitfld.long 0x00 21. "FIFO,FIFO Mode Enable Bit\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
newline
bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nIn Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
bitfld.long 0x00 18. "SLAVE,Slave Mode Enable Bit\n" "0: Master mode,1: Slave mode"
newline
bitfld.long 0x00 17. "IE,Unit Transfer Interrupt Enable Bit\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
bitfld.long 0x00 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
newline
bitfld.long 0x00 12.--15. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "CLKP,Clock Polarity\n" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
newline
bitfld.long 0x00 10. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX0/1 register is.."
bitfld.long 0x00 3.--7. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted/received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 2. "TX_NEG,Transmit On Negative Edge\n" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
bitfld.long 0x00 1. "RX_NEG,Receive On Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
newline
bitfld.long 0x00 0. "GO_BUSY,SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1" "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
group.long 0x04++0x03
line.long 0x00 "SPI_DIVIDER,Clock Divider Register"
hexmask.long.byte 0x00 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function"
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI bus clock of SPI master"
group.long 0x08++0x03
line.long 0x00 "SPI_SSR,Slave Select Register"
bitfld.long 0x00 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done" "0: Transferred bit length of one transaction..,1: Transferred bit length meets the specified.."
bitfld.long 0x00 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)\n" "0: Slave select signal is edge-trigger,1: Slave select signal is level-trigger"
newline
bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master Only)\n" "0: If this bit is cleared slave select signal..,1: If this bit is set SPI0_SPISS0 signal will be.."
bitfld.long 0x00 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI0_SPISS0).\n" "0: The slave select signal SPI0_SPISS0 is active..,1: The slave select signal SPI0_SPISS0 is active.."
newline
bitfld.long 0x00 0. "SSR,Slave Select Control Bit (Master Only)\nIf AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPI0_SPISS0 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set writing 0 to any.." "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "SPI_RX0,Data Receive Register 0"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin"
group.long 0x14++0x03
line.long 0x00 "SPI_RX1,Data Receive Register 1"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin"
wgroup.long 0x20++0x03
line.long 0x00 "SPI_TX0,Data Transmit Register 0"
abitfld.long 0x00 0.--31. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer" "0x00000001=1: When the SPI controller is..,0x00000002=2: In Master mode SPI controller will.."
group.long 0x24++0x03
line.long 0x00 "SPI_TX1,Data Transmit Register 1"
abitfld.long 0x00 0.--31. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer" "0x00000001=1: When the SPI controller is..,0x00000002=2: In Master mode SPI controller will.."
group.long 0x34++0x03
line.long 0x00 "SPI_VARCLK,Variable Clock Pattern Register"
hexmask.long 0x00 0.--31. 1. "VARCLK,Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer"
group.long 0x3C++0x03
line.long 0x00 "SPI_CNTRL2,Control and Status Register 2"
bitfld.long 0x00 31. "BCn,SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details" "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible"
bitfld.long 0x00 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
newline
bitfld.long 0x00 13. "DUAL_IO_EN,Dual I/O Mode Enable Bit\n" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
bitfld.long 0x00 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control\n" "0: Dual Input mode,1: Dual Output mode"
newline
bitfld.long 0x00 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode" "0: Slave has not detected any SPI clock..,1: A transaction has started in Slave 3-wire mode"
bitfld.long 0x00 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable Bit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode" "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled"
newline
bitfld.long 0x00 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0,1"
bitfld.long 0x00 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
group.long 0x40++0x03
line.long 0x00 "SPI_FIFO_CTL,SPI FIFO Control Register"
bitfld.long 0x00 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "TIMEOUT_INTEN,Receive FIFO Time-Out Interrupt Enable Bit\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
bitfld.long 0x00 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Bit\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
newline
bitfld.long 0x00 3. "TX_INTEN,Transmit Threshold Interrupt Enable Bit\n" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
bitfld.long 0x00 2. "RX_INTEN,Receive Threshold Interrupt Enable Bit\n" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
newline
bitfld.long 0x00 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer"
bitfld.long 0x00 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer"
group.long 0x44++0x03
line.long 0x00 "SPI_STATUS,SPI Status Register"
rbitfld.long 0x00 28.--31. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
newline
rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
newline
rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x00 20. "TIMEOUT,Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
newline
bitfld.long 0x00 16. "IF,SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x00 12.--15. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode" "0: Slave has not detected any SPI clock..,1: A transaction has started in Slave 3-wire mode"
rbitfld.long 0x00 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
newline
bitfld.long 0x00 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself" "0,1"
rbitfld.long 0x00 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO..,1: The valid data count within the receive FIFO.."
tree.end
tree "SYST_NVIC_SCS"
base ad:0xE000E000
group.long 0x10++0x03
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. "COUNTFLAG,Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection\n" "0: Clock source is (optional) external reference..,1: Core clock used for SysTick"
newline
bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled\n" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled\n" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
group.long 0x14++0x03
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Value to load into the Current Value register when the counter reaches 0"
group.long 0x18++0x03
line.long 0x00 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
group.long 0x100++0x03
line.long 0x00 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Enable Register\nEnable one or more interrupts"
group.long 0x180++0x03
line.long 0x00 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Disable Bits\nDisable one or more interrupts"
group.long 0x200++0x03
line.long 0x00 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Set Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status"
group.long 0x280++0x03
line.long 0x00 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status"
group.long 0x400++0x03
line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_3,Priority Of IRQ3\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_2,Priority Of IRQ2\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_1,Priority Of IRQ1\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_0,Priority Of IRQ0\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x404++0x03
line.long 0x00 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_7,Priority Of IRQ7\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_6,Priority Of IRQ6\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_5,Priority Of IRQ5\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_4,Priority Of IRQ4\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x408++0x03
line.long 0x00 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_11,Priority Of IRQ11\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_10,Priority Of IRQ10\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_9,Priority Of IRQ9\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_8,Priority Of IRQ8\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x40C++0x03
line.long 0x00 "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_15,Priority Of IRQ15\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority Of IRQ14\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_13,Priority Of IRQ13\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_12,Priority Of IRQ12\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x410++0x03
line.long 0x00 "NVIC_IPR4,IRQ16 ~ IRQ19 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_19,Priority Of IRQ19\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_18,Priority Of IRQ18\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_17,Priority Of IRQ17\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_16,Priority Of IRQ16\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x414++0x03
line.long 0x00 "NVIC_IPR5,IRQ20 ~ IRQ23 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_23,Priority Of IRQ23\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_22,Priority Of IRQ22\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_21,Priority Of IRQ21\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_20,Priority Of IRQ20\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x418++0x03
line.long 0x00 "NVIC_IPR6,IRQ24 ~ IRQ27 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_27,Priority Of IRQ27\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_26,Priority Of IRQ26\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_25,Priority Of IRQ25\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_24,Priority Of IRQ24\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x41C++0x03
line.long 0x00 "NVIC_IPR7,IRQ28 ~ IRQ31 Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_31,Priority Of IRQ31\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_30,Priority Of IRQ30\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_29,Priority Of IRQ29\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_28,Priority Of IRQ28\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer Code Assigned By ARM\n"
bitfld.long 0x00 16.--19. "PART,Architecture Of The Processor\nRead as 0xC for ARMv6-M parts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Part Number Of The Processor\nRead as 0xC20"
bitfld.long 0x00 0.--3. "REVISION,Revision Number\nRead as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x03
line.long 0x00 "ICSR,Interrupt Control and State Register"
bitfld.long 0x00 31. "NMIPENDSET,NMI Set-Pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.."
bitfld.long 0x00 28. "PENDSVSET,PendSV Set-Pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
newline
bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-Pending Bit\nWrite Operation:\nThis is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-Pending Bit\nWrite Operation:\n" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
newline
bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-Pending Bit\nWrite Operation:\nThis is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
bitfld.long 0x00 23. "ISRPREEMPT,If Set A Pending Exception Will Be Serviced On Exit From The Debug Halt State\nThis bit is read only" "0,1"
newline
bitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI And Faults:\nThis bit is read only" "0: Interrupt not pending,1: Interrupt pending"
bitfld.long 0x00 12.--17. "VECTPENDING,Indicates The Exception Number Of The Highest Priority Pending Enabled Exception:\n" "0: No pending exceptions,?..."
newline
bitfld.long 0x00 0.--5. "VECTACTIVE,Contains The Active Exception Number\n" "0: Thread mode,?..."
group.long 0xD0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWrite Operation:\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored"
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence" "0,1"
newline
bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nReserved for debug use" "0,1"
group.long 0xD10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Send Event On Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: Sleep mode,1: Deep Sleep mode"
newline
bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-On-Exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.."
group.long 0xD1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority Of System Handler" "0,1,2,3"
group.long 0xD20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority Of System Handler" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority Of System Handler" "0,1,2,3"
tree.end
tree "TIMER"
tree "TMR01"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "TCSR0,Timer0 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
newline
bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x00 19. "TRG_PWM_EN,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.\n" "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out.."
bitfld.long 0x00 18. "TRG_SRC_SEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.\n" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM"
newline
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x04++0x03
line.long 0x00 "TCMPR0,Timer0 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x08++0x03
line.long 0x00 "TISR0,Timer0 Interrupt Status Register"
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
rgroup.long 0x0C++0x03
line.long 0x00 "TDR0,Timer0 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
rgroup.long 0x10++0x03
line.long 0x00 "TCAP0,Timer0 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
group.long 0x14++0x03
line.long 0x00 "TEXCON0,Timer0 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
newline
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
group.long 0x18++0x03
line.long 0x00 "TEXISR0,Timer0 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TCSR1,Timer1 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
newline
bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x00 19. "TRG_PWM_EN,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.\n" "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out.."
bitfld.long 0x00 18. "TRG_SRC_SEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.\n" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM"
newline
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x24++0x03
line.long 0x00 "TCMPR1,Timer1 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x28++0x03
line.long 0x00 "TISR1,Timer1 Interrupt Status Register"
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
group.long 0x2C++0x03
line.long 0x00 "TDR1,Timer1 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
group.long 0x30++0x03
line.long 0x00 "TCAP1,Timer1 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
group.long 0x34++0x03
line.long 0x00 "TEXCON1,Timer1 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
newline
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
group.long 0x38++0x03
line.long 0x00 "TEXISR1,Timer1 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
tree.end
tree "TMR23"
base ad:0x40110000
group.long 0x00++0x03
line.long 0x00 "TCSR2,Timer2 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
newline
bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x00 19. "TRG_PWM_EN,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.\n" "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out.."
bitfld.long 0x00 18. "TRG_SRC_SEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.\n" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM"
newline
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x04++0x03
line.long 0x00 "TCMPR2,Timer2 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x08++0x03
line.long 0x00 "TISR2,Timer2 Interrupt Status Register"
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
rgroup.long 0x0C++0x03
line.long 0x00 "TDR2,Timer2 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
rgroup.long 0x10++0x03
line.long 0x00 "TCAP2,Timer2 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
group.long 0x14++0x03
line.long 0x00 "TEXCON2,Timer2 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
newline
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
group.long 0x18++0x03
line.long 0x00 "TEXISR2,Timer2 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TCSR3,Timer3 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
newline
bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
newline
bitfld.long 0x00 19. "TRG_PWM_EN,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.\n" "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out.."
bitfld.long 0x00 18. "TRG_SRC_SEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.\n" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM"
newline
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x24++0x03
line.long 0x00 "TCMPR3,Timer3 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x28++0x03
line.long 0x00 "TISR3,Timer3 Interrupt Status Register"
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
group.long 0x2C++0x03
line.long 0x00 "TDR3,Timer3 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
group.long 0x30++0x03
line.long 0x00 "TCAP3,Timer3 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
group.long 0x34++0x03
line.long 0x00 "TEXCON3,Timer3 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
newline
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
group.long 0x38++0x03
line.long 0x00 "TEXISR3,Timer3 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
tree.end
tree.end
tree "UART"
repeat 2. (list 0. 1.) (list ad:0x40050000 ad:0x40150000)
tree "UART$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return the 8-bit data received from RX pin (LSB first)"
wgroup.long 0x00++0x03
line.long 0x00 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
bitfld.long 0x00 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
newline
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
bitfld.long 0x00 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
newline
bitfld.long 0x00 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
newline
bitfld.long 0x00 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control\n" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the.."
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol\n" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled"
newline
bitfld.long 0x00 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol\n" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)\n" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
newline
bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol\n" "0: RLS_INT Masked off,1: RLS_INT Enabled"
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol\n" "0: THRE_INT Masked off,1: THRE_INT Enabled"
newline
bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol\n" "0: RDA_INT Masked off,1: RDA_INT Enabled"
group.long 0x08++0x03
line.long 0x00 "UA_FCR,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
newline
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).\n" "0: RX FIFO Interrupt Trigger Level is 1..,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
newline
bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UA_LCR,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
bitfld.long 0x00 5. "SPE,Stick Parity Enable Coontrol\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.."
newline
bitfld.long 0x00 4. "EPE,Even Parity Enable Coontrol\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable Coontrol\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
newline
bitfld.long 0x00 2. "NSB,Number Of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.."
bitfld.long 0x00 0.--1. "WLS,Word Length Selection\n" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit"
group.long 0x10++0x03
line.long 0x00 "UA_MCR,UART Modem Control Register"
rbitfld.long 0x00 13. "RTS_ST,RTS Pin State (Read Only) ( Available In UART0/UART1 Channel)\nThis bit mirror from RTS pin output of voltage logic status.\n" "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "LEV_RTS,RTS Pin Active Level ( Available In UART0/UART1 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 692 and Figure 693 for UART function mode.\nNote2: Refer to Figure 6103 and Figure 6104 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active"
newline
bitfld.long 0x00 1. "RTS,RTS (Request-To-Send) Signal Control (Available In UART0/UART1 Channel)\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UA_MSR,UART Modem Status Register"
bitfld.long 0x00 8. "LEV_CTS,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 691 for more information" "0: CTS pin input is high level active,1: CTS pin input is low level active"
rbitfld.long 0x00 4. "CTS_ST,CTS Pin Status (Read Only) \nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
newline
rbitfld.long 0x00 0. "DCTSF,Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only but can be cleared by writing 1 to it" "0: CTS input has not change state,1: CTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UA_FSR,UART FIFO Status Register"
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted" "0: TX FIFO is not empty.\nTX Buffer is not empty,1: TX FIFO is empty.\nTX Buffer is empty"
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1" "0: TX FIFO is not overflow.\nTX Buffer is not..,1: TX FIFO is overflow.\nTX Buffer is overflow"
newline
rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not" "0: TX FIFO is not full.\nTX Buffer is not full,1: TX FIFO is full.\nTX Buffer is full"
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not" "0: TX FIFO is not empty.\nTX Buffer is not empty,1: TX FIFO is empty.\nTX Buffer is empty"
newline
rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2)" "0: RX FIFO is not full.\nRX buffer is not full,1: RX FIFO is full.\nRX bufferis full"
newline
rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not" "0: RX FIFO is not empty.\nRX Buffer is not empty,1: RX FIFO is empty.\nRX Buffer is empty"
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes 1.." "0: No framing error is generated,1: Framing error is generated"
newline
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing 1 to it" "0: No parity error is generated,1: Parity error is generated"
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only.." "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
newline
rbitfld.long 0x00 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing 1 to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
rbitfld.long 0x00 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic 1 when auto-baud rate detect function is finished" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
newline
rbitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow" "0: RX FIFO is not overflow.\nRX Buffer is not..,1: RX FIFO is overflow.\nRX Buffer is overflow"
group.long 0x1C++0x03
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
rbitfld.long 0x00 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data.."
rbitfld.long 0x00 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
newline
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
newline
rbitfld.long 0x00 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
newline
rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
newline
rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
newline
rbitfld.long 0x00 6. "WKIF,UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only" "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
newline
rbitfld.long 0x00 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
newline
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
newline
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UA_TOR,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Coontrol\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal Control\n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control\n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
newline
bitfld.long 0x00 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
newline
bitfld.long 0x00 18. "ABRDEN,Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated" "0,1"
newline
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
newline
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
newline
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
newline
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Coontrol\n" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
group.long 0x34++0x03
line.long 0x00 "UA_LIN_CTL,UART LIN Control Register"
hexmask.long.byte 0x00 24.--31. 1. "LIN_PID,LIN PID Register\nIf the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any.."
bitfld.long 0x00 22.--23. "LIN_HEAD_SEL,LIN Header Select\n" "0: The LIN header includes break field,1: The LIN header includes break field and sync..,2: The LIN header includes break field sync..,3: Reserved"
newline
bitfld.long 0x00 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1 bit..,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
bitfld.long 0x00 16.--19. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "BIT_ERR_EN,Bit Error Detect Enable Coontrol\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
bitfld.long 0x00 11. "LIN_RX_DIS,LIN Receiver Disable Bit\n" "0: LIN receiver Enabled,1: LIN receiver Disabled"
newline
bitfld.long 0x00 10. "LIN_BKDET_EN,LIN Break Detection Enable Coontrol\n" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x00 9. "LIN_IDPEN,LIN ID Parity Enable Coontrol\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
newline
bitfld.long 0x00 8. "LIN_SHD,LIN TX Send Header Enable Coontrol\nThe LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
bitfld.long 0x00 4. "LIN_MUTE_EN,LIN Mute Mode Enable Coontrol\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
newline
bitfld.long 0x00 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Coontrol\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.."
bitfld.long 0x00 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Coontrol\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
newline
bitfld.long 0x00 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Coontrol\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x00 0. "LINS_EN,LIN Slave Mode Enable Coontrol\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
group.long 0x38++0x03
line.long 0x00 "UA_LIN_SR,UART LIN Status Register"
rbitfld.long 0x00 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set.\n" "0,1"
rbitfld.long 0x00 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n" "0: LIN break not detected,1: LIN break detected"
newline
bitfld.long 0x00 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
rbitfld.long 0x00 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
newline
rbitfld.long 0x00 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
rbitfld.long 0x00 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
tree.end
repeat.end
tree "UART2"
base ad:0x40154000
rgroup.long 0x00++0x03
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return the 8-bit data received from RX pin (LSB first)"
wgroup.long 0x00++0x03
line.long 0x00 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
bitfld.long 0x00 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
newline
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
bitfld.long 0x00 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
newline
bitfld.long 0x00 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
newline
bitfld.long 0x00 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control\n" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the.."
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol\n" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled"
newline
bitfld.long 0x00 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol\n" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)\n" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
newline
bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol\n" "0: RLS_INT Masked off,1: RLS_INT Enabled"
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol\n" "0: THRE_INT Masked off,1: THRE_INT Enabled"
newline
bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol\n" "0: RDA_INT Masked off,1: RDA_INT Enabled"
group.long 0x08++0x03
line.long 0x00 "UA_FCR,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
newline
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).\n" "0: RX FIFO Interrupt Trigger Level is 1..,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
newline
bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UA_LCR,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
bitfld.long 0x00 5. "SPE,Stick Parity Enable Coontrol\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.."
newline
bitfld.long 0x00 4. "EPE,Even Parity Enable Coontrol\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable Coontrol\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
newline
bitfld.long 0x00 2. "NSB,Number Of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.."
bitfld.long 0x00 0.--1. "WLS,Word Length Selection\n" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit"
group.long 0x18++0x03
line.long 0x00 "UA_FSR,UART FIFO Status Register"
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted" "0: TX FIFO is not empty.\nTX Buffer is not empty,1: TX FIFO is empty.\nTX Buffer is empty"
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1" "0: TX FIFO is not overflow.\nTX Buffer is not..,1: TX FIFO is overflow.\nTX Buffer is overflow"
newline
rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not" "0: TX FIFO is not full.\nTX Buffer is not full,1: TX FIFO is full.\nTX Buffer is full"
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not" "0: TX FIFO is not empty.\nTX Buffer is not empty,1: TX FIFO is empty.\nTX Buffer is empty"
newline
rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2)" "0: RX FIFO is not full.\nRX buffer is not full,1: RX FIFO is full.\nRX bufferis full"
newline
rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not" "0: RX FIFO is not empty.\nRX Buffer is not empty,1: RX FIFO is empty.\nRX Buffer is empty"
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes 1.." "0: No framing error is generated,1: Framing error is generated"
newline
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing 1 to it" "0: No parity error is generated,1: Parity error is generated"
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only.." "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
newline
rbitfld.long 0x00 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing 1 to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
rbitfld.long 0x00 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic 1 when auto-baud rate detect function is finished" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
newline
rbitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow" "0: RX FIFO is not overflow.\nRX Buffer is not..,1: RX FIFO is overflow.\nRX Buffer is overflow"
group.long 0x1C++0x03
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
rbitfld.long 0x00 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data.."
rbitfld.long 0x00 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
newline
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
newline
rbitfld.long 0x00 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
newline
rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
newline
rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
newline
rbitfld.long 0x00 6. "WKIF,UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only" "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
newline
rbitfld.long 0x00 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
newline
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
newline
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UA_TOR,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Coontrol\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal Control\n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control\n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
newline
bitfld.long 0x00 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
newline
bitfld.long 0x00 18. "ABRDEN,Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated" "0,1"
newline
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
newline
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
newline
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
newline
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Coontrol\n" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
group.long 0x34++0x03
line.long 0x00 "UA_LIN_CTL,UART LIN Control Register"
hexmask.long.byte 0x00 24.--31. 1. "LIN_PID,LIN PID Register\nIf the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any.."
bitfld.long 0x00 22.--23. "LIN_HEAD_SEL,LIN Header Select\n" "0: The LIN header includes break field,1: The LIN header includes break field and sync..,2: The LIN header includes break field sync..,3: Reserved"
newline
bitfld.long 0x00 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1 bit..,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
bitfld.long 0x00 16.--19. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "BIT_ERR_EN,Bit Error Detect Enable Coontrol\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
bitfld.long 0x00 11. "LIN_RX_DIS,LIN Receiver Disable Bit\n" "0: LIN receiver Enabled,1: LIN receiver Disabled"
newline
bitfld.long 0x00 10. "LIN_BKDET_EN,LIN Break Detection Enable Coontrol\n" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x00 9. "LIN_IDPEN,LIN ID Parity Enable Coontrol\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
newline
bitfld.long 0x00 8. "LIN_SHD,LIN TX Send Header Enable Coontrol\nThe LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
bitfld.long 0x00 4. "LIN_MUTE_EN,LIN Mute Mode Enable Coontrol\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
newline
bitfld.long 0x00 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Coontrol\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.."
bitfld.long 0x00 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Coontrol\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
newline
bitfld.long 0x00 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Coontrol\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x00 0. "LINS_EN,LIN Slave Mode Enable Coontrol\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
group.long 0x38++0x03
line.long 0x00 "UA_LIN_SR,UART LIN Status Register"
rbitfld.long 0x00 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set.\n" "0,1"
rbitfld.long 0x00 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n" "0: LIN break not detected,1: LIN break detected"
newline
bitfld.long 0x00 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
rbitfld.long 0x00 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
newline
rbitfld.long 0x00 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
rbitfld.long 0x00 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
tree.end
repeat 3. (list 3. 4. 5.) (list ad:0x40054000 ad:0x40058000 ad:0x40158000)
tree "UART$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return the 8-bit data received from RX pin (LSB first)"
wgroup.long 0x00++0x03
line.long 0x00 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
bitfld.long 0x00 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
newline
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
bitfld.long 0x00 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
newline
bitfld.long 0x00 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
newline
bitfld.long 0x00 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control\n" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the.."
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol\n" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled"
newline
bitfld.long 0x00 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol\n" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)\n" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
newline
bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol\n" "0: RLS_INT Masked off,1: RLS_INT Enabled"
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol\n" "0: THRE_INT Masked off,1: THRE_INT Enabled"
newline
bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol\n" "0: RDA_INT Masked off,1: RDA_INT Enabled"
group.long 0x08++0x03
line.long 0x00 "UA_FCR,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
newline
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).\n" "0: RX FIFO Interrupt Trigger Level is 1..,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
newline
bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UA_LCR,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
bitfld.long 0x00 5. "SPE,Stick Parity Enable Coontrol\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.."
newline
bitfld.long 0x00 4. "EPE,Even Parity Enable Coontrol\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable Coontrol\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
newline
bitfld.long 0x00 2. "NSB,Number Of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.."
bitfld.long 0x00 0.--1. "WLS,Word Length Selection\n" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit"
group.long 0x18++0x03
line.long 0x00 "UA_FSR,UART FIFO Status Register"
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted" "0: TX FIFO is not empty.\nTX Buffer is not empty,1: TX FIFO is empty.\nTX Buffer is empty"
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1" "0: TX FIFO is not overflow.\nTX Buffer is not..,1: TX FIFO is overflow.\nTX Buffer is overflow"
newline
rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not" "0: TX FIFO is not full.\nTX Buffer is not full,1: TX FIFO is full.\nTX Buffer is full"
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not" "0: TX FIFO is not empty.\nTX Buffer is not empty,1: TX FIFO is empty.\nTX Buffer is empty"
newline
rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2)" "0: RX FIFO is not full.\nRX buffer is not full,1: RX FIFO is full.\nRX bufferis full"
newline
rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not" "0: RX FIFO is not empty.\nRX Buffer is not empty,1: RX FIFO is empty.\nRX Buffer is empty"
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes 1.." "0: No framing error is generated,1: Framing error is generated"
newline
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing 1 to it" "0: No parity error is generated,1: Parity error is generated"
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only.." "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
newline
rbitfld.long 0x00 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing 1 to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
rbitfld.long 0x00 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic 1 when auto-baud rate detect function is finished" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
newline
rbitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow" "0: RX FIFO is not overflow.\nRX Buffer is not..,1: RX FIFO is overflow.\nRX Buffer is overflow"
group.long 0x1C++0x03
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
rbitfld.long 0x00 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data.."
rbitfld.long 0x00 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
newline
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
newline
rbitfld.long 0x00 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
newline
rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
newline
rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
newline
rbitfld.long 0x00 6. "WKIF,UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only" "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
newline
rbitfld.long 0x00 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
newline
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
newline
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UA_TOR,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Coontrol\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
newline
bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal Control\n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control\n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
newline
bitfld.long 0x00 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
newline
bitfld.long 0x00 18. "ABRDEN,Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated" "0,1"
newline
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
newline
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
newline
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
newline
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Coontrol\n" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
tree.end
repeat.end
tree.end
tree "WDT"
base ad:0x40004000
group.long 0x00++0x03
line.long 0x00 "WTCR,Watchdog Timer Control Register"
bitfld.long 0x00 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 8.--10. "WTIS,Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\n" "0: 24 *TWDT,1: 26 * TWDT,2: 28 * TWDT,3: 210 * TWDT,4: 212 * TWDT,5: 214 * TWDT,6: 216 * TWDT,7: 218 * TWDT"
newline
bitfld.long 0x00 7. "WTE,Watchdog Timer Enable Control (Write Protect)\nNote: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0 this bit is forced as 1 and user cannot change this bit to 0" "0: WDT Disabled,1: WDT Enabled"
bitfld.long 0x00 6. "WTIE,Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU.\n" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
newline
bitfld.long 0x00 5. "WTWKF,Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 4. "WTWKE,Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1 while WTIF is generated to 1 and WTIE enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
newline
bitfld.long 0x00 3. "WTIF,Watchdog Timer Time-Out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
bitfld.long 0x00 2. "WTRF,Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
newline
bitfld.long 0x00 1. "WTRE,Watchdog Timer Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\n" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
bitfld.long 0x00 0. "WTR,Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware" "0: No effect,1: Reset the internal 18-bit WDT up counter value"
group.long 0x04++0x03
line.long 0x00 "WTCRALT,Watchdog Timer Alternative Control Register"
bitfld.long 0x00 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened" "0: Watchdog Timer Reset Delay Period is 1026 *..,1: Watchdog Timer Reset Delay Period is 130 *..,2: Watchdog Timer Reset Delay Period is 18 *..,3: Watchdog Timer Reset Delay Period is 3 *.."
tree.end
tree "WWDT"
base ad:0x40004100
wgroup.long 0x00++0x03
line.long 0x00 "WWDTRLD,Window Watchdog Timer Reload Counter Register"
hexmask.long 0x00 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F"
group.long 0x04++0x03
line.long 0x00 "WWDTCR,Window Watchdog Timer Control Register"
bitfld.long 0x00 31. "DBGACK_WWDT,ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 16.--21. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--11. "PERIODSEL,WWDT Counter Prescale Period Selection\n" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
bitfld.long 0x00 1. "WWDTIE,WWDT Interrupt Enable Control\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU.\n" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
newline
bitfld.long 0x00 0. "WWDTEN,WWDT Enable Control\nSet this bit to enable WWDT counter counting.\n" "0: WWDT counter is stopped,1: WWDT counter is starting counting"
group.long 0x08++0x03
line.long 0x00 "WWDTSR,Window Watchdog Timer Status Register"
bitfld.long 0x00 1. "WWDTRF,WWDT Time-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches WINCMP value"
rgroup.long 0x0C++0x03
line.long 0x00 "WWDTCVR,Window Watchdog Timer Counter Value Register"
bitfld.long 0x00 0.--5. "WWDTCVAL,WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
autoindent.off
newline
Reference in New Issue View Git Blame Copy Permalink