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Gen4_R-Car_Trace32/2_Trunk/perlpc86x.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: LPC86x On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2023-11-22 NEJ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: Generated (TRACE32, build: 164847.), based on:
; LPC865.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: LPC865M201JBD64, LPC865M201JHI33, LPC865M201JHI48
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perlpc86x.per 17099 2023-11-25 09:02:15Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACOMP (Analog Comparator)"
base ad:0x40024000
group.long 0x0++0x7
line.long 0x0 "CTRL,Comparator control register"
bitfld.long 0x0 25.--26. "HYS,Controls the hysteresis of the comparator. When the comparator is outputting a certain state this is the difference between the selected signals in the opposite direction from the state being output that will switch the output." "0: None (the output will switch as the voltages..,1: 5 mv,2: 10 mv,3: 20 mv"
bitfld.long 0x0 24. "INTENA,Must be set to generate interrupts." "0,1"
newline
bitfld.long 0x0 23. "COMPEDGE,Comparator edge-detect status." "0,1"
bitfld.long 0x0 21. "COMPSTAT,Comparator status. This bit reflects the state of the comparator output." "0,1"
newline
bitfld.long 0x0 20. "EDGECLR,Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request toggle the EDGECLR bit by first writing a 1 and then a 0." "0,1"
bitfld.long 0x0 11.--13. "COMP_VM_SEL,Selects negative voltage input" "0: VOLTAGE_LADDER_OUTPUT,1: ACMP_I1,2: ACMP_I2,3: ACMP_I3,4: ACMP_I4,5: ACMP_I5,6: Band gap. Internal reference voltage.,7: None"
newline
bitfld.long 0x0 8.--10. "COMP_VP_SEL,Selects positive voltage input" "0: VOLTAGE_LADDER_OUTPUT,1: ACMP_I1,2: ACMP_I2,3: ACMP_I3,4: ACMP_I4,5: ACMP_I5,6: Band gap. Internal reference voltage.,7: None"
bitfld.long 0x0 6. "COMPSA,Comparator output control" "0: Comparator output is used directly.,1: Comparator output is synchronized to the bus.."
newline
bitfld.long 0x0 3.--4. "EDGESEL,This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):" "0: Falling edges,1: Rising edges,2: Both edges,3: Both edges"
line.long 0x4 "LAD,Voltage ladder register"
bitfld.long 0x4 6. "LADREF,Selects the reference voltage Vref for the voltage ladder." "0: Supply pin VDD,1: VDDCMP pin"
hexmask.long.byte 0x4 1.--5. 1. "LADSEL,Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref"
newline
bitfld.long 0x4 0. "LADEN,Voltage ladder enable" "0,1"
tree.end
tree "ADC (12-bit Analog-to-Digital Converter)"
base ad:0x4001C000
group.long 0x0++0x3
line.long 0x0 "CTRL,ADC Control register. Contains the clock divide value. resolution selection. sampling time selection. and mode controls."
bitfld.long 0x0 30. "CALMODE,Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit .." "0,1"
bitfld.long 0x0 10. "LPWRMODE,The low-power ADC mode" "0: The low-power ADC mode is disabled. The analog..,1: The low-power ADC mode is enabled. The analog.."
newline
bitfld.long 0x0 8. "ASYNMODE,Select clock mode." "0: Synchronous mode. The ADC clock is derived from..,1: Asynchronous mode. The ADC clock is based on the.."
hexmask.long.byte 0x0 0.--7. 1. "CLKDIV,In synchronous mode only the system clock is divided by this value plus one to produce the clock for the ADC converter which should be less than or equal to 72 MHz. Typically software should program the smallest value in this field that yields.."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x8)++0x3
line.long 0x0 "SEQ_CTRL$1,ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n."
bitfld.long 0x0 31. "SEQ_ENA,Sequence Enable. In order to avoid spuriously triggering the sequence care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met the.." "0: Disabled. Sequence n is disabled. Sequence n..,1: Enabled. Sequence n is enabled."
bitfld.long 0x0 30. "MODE,Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion or the individual channel result registers at the end of.." "0: End of conversion. The sequence A interrupt/DMA..,1: End of sequence. The sequence A interrupt/DMA.."
newline
bitfld.long 0x0 29. "LOWPRIO,Set priority for sequence A." "0: Low priority. Any B trigger which occurs while..,1: High priority. Setting this bit to a 1 will.."
bitfld.long 0x0 28. "SINGLESTEP,When this bit is set a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels.." "0,1"
newline
bitfld.long 0x0 27. "BURST,Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in.." "0,1"
bitfld.long 0x0 26. "START,Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1.." "0,1"
newline
hexmask.long.byte 0x0 20.--24. 1. "TSAMP,The default sample period (TSAMP = '00000') at the beginning of each new conversion is 6.5 ADC clock periods. Depending on avariety of factors including ADC clock rate output impedance of the analog source driver ADC resolution and the selection.."
bitfld.long 0x0 19. "SYNCBYPASS,Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or.." "0: Enable trigger synchronization. The hardware..,1: Bypass trigger synchronization. The hardware.."
newline
bitfld.long 0x0 18. "TRIGPOL,Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set.." "0: Negative edge. A negative edge launches the..,1: Positive edge. A positive edge launches the.."
bitfld.long 0x0 12.--14. "TRIGGER,Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger it is recommended writing.." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--11. 1. "CHANNELS,Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence where bit 0 corresponds to.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x10)++0x3
line.long 0x0 "SEQ_GDAT$1,ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n."
bitfld.long 0x0 31. "DATAVALID,This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE.." "0,1"
bitfld.long 0x0 30. "OVERRUN,This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared along with the DATAVALID bit whenever this register is read. This bit.." "0,1"
newline
hexmask.long.byte 0x0 26.--29. 1. "CHN,These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0 0001 channel 1 etc.)."
bitfld.long 0x0 18.--19. "THCMPCROSS,Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and if so in what direction the crossing occurred." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "THCMPRANGE,Indicates whether the result of the last conversion performed was above below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)." "0,1,2,3"
hexmask.long.word 0x0 4.--15. 1. "RESULT,This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input.."
repeat.end
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x20)++0x3
line.long 0x0 "DAT[$1],ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N."
bitfld.long 0x0 31. "DATAVALID,This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to.." "0,1"
bitfld.long 0x0 30. "OVERRUN,This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared along with the DONE bit whenever.." "0,1"
newline
hexmask.long.byte 0x0 26.--29. 1. "CHANNEL,This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register 0b0001 for the DAT1 register etc)"
bitfld.long 0x0 18.--19. "THCMPCROSS,Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold.." "0: No threshold Crossing detected: The most recent..,1: Reserved,2: Downward Threshold Crossing Detected,3: Upward Threshold Crossing Detected"
newline
bitfld.long 0x0 16.--17. "THCMPRANGE,Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the.." "0: In Range: The last completed conversion was..,1: Below Range: The last completed conversion on..,2: Above Range: The last completed conversion was..,3: Reserved"
hexmask.long.word 0x0 4.--15. 1. "RESULT,This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin as it falls within the range of VREFP to VREFN. Zero in the field.."
repeat.end
group.long 0x50++0x1F
line.long 0x0 "THR0_LOW,ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0."
hexmask.long.word 0x0 4.--15. 1. "THRLOW,Low threshold value against which ADC results will be compared"
line.long 0x4 "THR1_LOW,ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1."
hexmask.long.word 0x4 4.--15. 1. "THRLOW,Low threshold value against which ADC results will be compared"
line.long 0x8 "THR0_HIGH,ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0."
hexmask.long.word 0x8 4.--15. 1. "THRHIGH,High threshold value against which ADC results will be compared"
line.long 0xC "THR1_HIGH,ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1."
hexmask.long.word 0xC 4.--15. 1. "THRHIGH,High threshold value against which ADC results will be compared"
line.long 0x10 "CHAN_THRSEL,ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel"
bitfld.long 0x10 11. "CH11_THRSEL,Threshold select for channel 11. See description for channel 0." "0,1"
bitfld.long 0x10 10. "CH10_THRSEL,Threshold select for channel 10. See description for channel 0." "0,1"
newline
bitfld.long 0x10 9. "CH9_THRSEL,Threshold select for channel 9. See description for channel 0." "0,1"
bitfld.long 0x10 8. "CH8_THRSEL,Threshold select for channel 8. See description for channel 0." "0,1"
newline
bitfld.long 0x10 7. "CH7_THRSEL,Threshold select for channel 7. See description for channel 0." "0,1"
bitfld.long 0x10 6. "CH6_THRSEL,Threshold select for channel 6. See description for channel 0." "0,1"
newline
bitfld.long 0x10 5. "CH5_THRSEL,Threshold select for channel 5. See description for channel 0." "0,1"
bitfld.long 0x10 4. "CH4_THRSEL,Threshold select for channel 4. See description for channel 0." "0,1"
newline
bitfld.long 0x10 3. "CH3_THRSEL,Threshold select for channel 3. See description for channel 0." "0,1"
bitfld.long 0x10 2. "CH2_THRSEL,Threshold select for channel 2. See description for channel 0." "0,1"
newline
bitfld.long 0x10 1. "CH1_THRSEL,Threshold select for channel 1. See description for channel 0." "0,1"
bitfld.long 0x10 0. "CH0_THRSEL,Threshold select for channel 0." "0: Threshold 0. Results for this channel will be..,1: Threshold 1. Results for this channel will be.."
line.long 0x14 "INTEN,ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A. sequence-B. threshold compare and data overrun interrupts to be generated."
bitfld.long 0x14 25.--26. "ADCMPINTEN11,Channel 21 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 23.--24. "ADCMPINTEN10,Channel 10 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 21.--22. "ADCMPINTEN9,Channel 9 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 19.--20. "ADCMPINTEN8,Channel 8 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 17.--18. "ADCMPINTEN7,Channel 7 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 15.--16. "ADCMPINTEN6,Channel 6 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 13.--14. "ADCMPINTEN5,Channel 5 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 11.--12. "ADCMPINTEN4,Channel 4 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 9.--10. "ADCMPINTEN3,Channel 3 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 7.--8. "ADCMPINTEN2,Channel 2 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 5.--6. "ADCMPINTEN1,Channel 1 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 3.--4. "ADCMPINTEN0,Threshold comparison interrupt enable for channel 0." "0: Disabled.,1: Outside threshold.,2: Crossing threshold.,?"
newline
bitfld.long 0x14 2. "OVR_INTEN,Overrun interrupt enable." "0: Disabled. The overrun interrupt is disabled.,1: Enabled. The overrun interrupt is enabled."
bitfld.long 0x14 1. "SEQB_INTEN,Sequence B interrupt enable." "0: Disabled. The sequence B interrupt/DMA trigger..,1: Enabled. The sequence B interrupt/DMA trigger is.."
newline
bitfld.long 0x14 0. "SEQA_INTEN,Sequence A interrupt enable." "0: Disabled. The sequence A interrupt/DMA trigger..,1: Enabled. The sequence A interrupt/DMA trigger is.."
line.long 0x18 "FLAGS,ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)."
rbitfld.long 0x18 31. "OVR_INT,Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register.." "0,1"
rbitfld.long 0x18 30. "THCMP_INT,Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison.." "0,1"
newline
rbitfld.long 0x18 29. "SEQB_INT,Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0 this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT) which is set at the end of every ADC conversion performed as part of.." "0,1"
rbitfld.long 0x18 28. "SEQA_INT,Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0 this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT) which is set at the end of every ADC conversion performed as part of.." "0,1"
newline
rbitfld.long 0x18 25. "SEQB_OVR,Mirrors the global OVERRUN status flag in the SEQB_GDAT register" "0,1"
rbitfld.long 0x18 24. "SEQA_OVR,Mirrors the global OVERRUN status flag in the SEQA_GDAT register" "0,1"
newline
rbitfld.long 0x18 23. "OVERRUN11,Mirrors the OVERRRUN status flag from the result register for ADC channel 11" "0,1"
rbitfld.long 0x18 22. "OVERRUN10,Mirrors the OVERRRUN status flag from the result register for ADC channel 10" "0,1"
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rbitfld.long 0x18 21. "OVERRUN9,Mirrors the OVERRRUN status flag from the result register for ADC channel 9" "0,1"
rbitfld.long 0x18 20. "OVERRUN8,Mirrors the OVERRRUN status flag from the result register for ADC channel 8" "0,1"
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rbitfld.long 0x18 19. "OVERRUN7,Mirrors the OVERRRUN status flag from the result register for ADC channel 7" "0,1"
rbitfld.long 0x18 18. "OVERRUN6,Mirrors the OVERRRUN status flag from the result register for ADC channel 6" "0,1"
newline
rbitfld.long 0x18 17. "OVERRUN5,Mirrors the OVERRRUN status flag from the result register for ADC channel 5" "0,1"
rbitfld.long 0x18 16. "OVERRUN4,Mirrors the OVERRRUN status flag from the result register for ADC channel 4" "0,1"
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rbitfld.long 0x18 15. "OVERRUN3,Mirrors the OVERRRUN status flag from the result register for ADC channel 3" "0,1"
rbitfld.long 0x18 14. "OVERRUN2,Mirrors the OVERRRUN status flag from the result register for ADC channel 2" "0,1"
newline
rbitfld.long 0x18 13. "OVERRUN1,Mirrors the OVERRRUN status flag from the result register for ADC channel 1" "0,1"
rbitfld.long 0x18 12. "OVERRUN0,Mirrors the OVERRRUN status flag from the result register for ADC channel 0" "0,1"
newline
bitfld.long 0x18 11. "THCMP11,Threshold comparison event on Channel 11. See description for channel 0." "0,1"
bitfld.long 0x18 10. "THCMP10,Threshold comparison event on Channel 10. See description for channel 0." "0,1"
newline
bitfld.long 0x18 9. "THCMP9,Threshold comparison event on Channel 9. See description for channel 0." "0,1"
bitfld.long 0x18 8. "THCMP8,Threshold comparison event on Channel 8. See description for channel 0." "0,1"
newline
bitfld.long 0x18 7. "THCMP7,Threshold comparison event on Channel 7. See description for channel 0." "0,1"
bitfld.long 0x18 6. "THCMP6,Threshold comparison event on Channel 6. See description for channel 0." "0,1"
newline
bitfld.long 0x18 5. "THCMP5,Threshold comparison event on Channel 5. See description for channel 0." "0,1"
bitfld.long 0x18 4. "THCMP4,Threshold comparison event on Channel 4. See description for channel 0." "0,1"
newline
bitfld.long 0x18 3. "THCMP3,Threshold comparison event on Channel 3. See description for channel 0." "0,1"
bitfld.long 0x18 2. "THCMP2,Threshold comparison event on Channel 2. See description for channel 0." "0,1"
newline
bitfld.long 0x18 1. "THCMP1,Threshold comparison event on Channel 1. See description for channel 0." "0,1"
bitfld.long 0x18 0. "THCMP0,Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." "0,1"
line.long 0x1C "TRM,ADC Startup register."
bitfld.long 0x1C 5. "VRANGE,1.8V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be spec'd on parts that do not support operation below 2.7V" "0,1"
tree.end
tree "CRC (Cyclic Redundancy Check)"
base ad:0x50004000
group.long 0x0++0x7
line.long 0x0 "MODE,CRC mode register"
bitfld.long 0x0 5. "CMPL_SUM,CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM" "0: No 1's complement for CRC_SUM,?"
bitfld.long 0x0 4. "BIT_RVS_SUM,CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM" "0: No bit order reverse for CRC_SUM,1: Bit order reverse for CRC_SUM"
newline
bitfld.long 0x0 3. "CMPL_WR,Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA" "0: No 1's complement for CRC_WR_DATA,?"
bitfld.long 0x0 2. "BIT_RVS_WR,Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)" "0: No bit order reverse for CRC_WR_DATA,1: Bit order reverse for CRC_WR_DATA"
newline
bitfld.long 0x0 0.--1. "CRC_POLY,CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial" "0: CRC-CCITT polynomial,1: CRC-16 polynomial,?,?"
line.long 0x4 "SEED,CRC seed register"
hexmask.long 0x4 0.--31. 1. "CRC_SEED,A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses."
rgroup.long 0x8++0x3
line.long 0x0 "SUM,CRC checksum register"
hexmask.long 0x0 0.--31. 1. "CRC_SUM,The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes."
wgroup.long 0x8++0x3
line.long 0x0 "WR_DATA,CRC data register"
hexmask.long 0x0 0.--31. 1. "CRC_WR_DATA,Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8 16 or 32-bit are allowed and accept back-to-back transactions."
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x50005000
group.long 0x0++0x3
line.long 0x0 "CTRL,DMA control."
bitfld.long 0x0 0. "ENABLE,DMA controller master enable." "0: Disabled. The DMA controller is disabled. This..,1: Enabled. The DMA controller is enabled."
rgroup.long 0x4++0x3
line.long 0x0 "INTSTAT,Interrupt status."
bitfld.long 0x0 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending." "0: Not pending. No error interrupts are pending.,1: Pending. At least one error interrupt is pending."
bitfld.long 0x0 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending." "0: Not pending. No enabled interrupts are pending.,1: Pending. At least one enabled interrupt is.."
group.long 0x8++0x3
line.long 0x0 "SRAMBASE,SRAM address of the channel configuration table."
hexmask.long.tbyte 0x0 9.--31. 1. "OFFSET,Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels the table must begin on a 512 byte boundary."
group.long 0x20++0x3
line.long 0x0 "ENABLESET0,Channel Enable read and Set for all DMA channels."
hexmask.long 0x0 0.--24. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
wgroup.long 0x28++0x3
line.long 0x0 "ENABLECLR0,Channel Enable Clear for all DMA channels."
hexmask.long 0x0 0.--24. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
rgroup.long 0x30++0x3
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels."
hexmask.long 0x0 0.--24. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
rgroup.long 0x38++0x3
line.long 0x0 "BUSY0,Channel Busy status for all DMA channels."
hexmask.long 0x0 0.--24. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
group.long 0x40++0x3
line.long 0x0 "ERRINT0,Error Interrupt status for all DMA channels."
hexmask.long 0x0 0.--24. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
group.long 0x48++0x3
line.long 0x0 "INTENSET0,Interrupt Enable read and Set for all DMA channels."
hexmask.long 0x0 0.--24. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
wgroup.long 0x50++0x3
line.long 0x0 "INTENCLR0,Interrupt Enable Clear for all DMA channels."
hexmask.long 0x0 0.--24. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
group.long 0x58++0x3
line.long 0x0 "INTA0,Interrupt A status for all DMA channels."
hexmask.long 0x0 0.--24. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
group.long 0x60++0x3
line.long 0x0 "INTB0,Interrupt B status for all DMA channels."
hexmask.long 0x0 0.--24. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
wgroup.long 0x68++0x3
line.long 0x0 "SETVALID0,Set ValidPending control bits for all DMA channels."
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
wgroup.long 0x70++0x3
line.long 0x0 "SETTRIG0,Set Trigger control bits for all DMA channels."
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
wgroup.long 0x78++0x3
line.long 0x0 "ABORT0,Channel Abort control for all DMA channels."
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x50005400 ad:0x50005410 ad:0x50005420 ad:0x50005430 ad:0x50005440 ad:0x50005450 ad:0x50005460 ad:0x50005470 ad:0x50005480 ad:0x50005490 ad:0x500054A0 ad:0x500054B0 ad:0x500054C0 ad:0x500054D0 ad:0x500054E0 ad:0x500054F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--17. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Four priority levels are supported: 0x0 = highest priority. 0x3 = lowest priority." "0: highest priority,?,?,3: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled the destination data address for the DMA is 'wrapped' meaning that the destination address range for each burst will be the same. As an example this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled the source data address for the DMA is 'wrapped' meaning that the source address range for each burst will be the same. As an example this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1 Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
repeat 9. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18)(list ad:0x50005500 ad:0x50005510 ad:0x50005520 ad:0x50005530 ad:0x50005540 ad:0x50005550 ad:0x50005560 ad:0x50005570 ad:0x50005580)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--17. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Four priority levels are supported: 0x0 = highest priority. 0x3 = lowest priority." "0: highest priority,?,?,3: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled the destination data address for the DMA is 'wrapped' meaning that the destination address range for each burst will be the same. As an example this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled the source data address for the DMA is 'wrapped' meaning that the source address range for each burst will be the same. As an example this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1 Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
tree.end
tree "FLASH_CTRL (Flash Controller)"
base ad:0x40040000
group.long 0x10++0x3
line.long 0x0 "FLASHCFG,Flash configuration register"
bitfld.long 0x0 0.--1. "FLASHTIM,Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access." "0: 1 system clock flash access time.,1: 2 system clock flash access time.,2: 3 system clock flash access time.,?"
group.long 0x20++0x7
line.long 0x0 "FMSSTART,Flash signature start address register"
hexmask.long.tbyte 0x0 0.--16. 1. "START,Signature generation start address (corresponds to AHB byte address bits[18:2])."
line.long 0x4 "FMSSTOP,Flash signaure stop address register"
bitfld.long 0x4 31. "STRTBIST,When this bit is written to 1 signature generation starts. At the end of signature generation this bit is automatically cleared." "0,1"
hexmask.long.tbyte 0x4 0.--16. 1. "STOPA,Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words not bytes."
rgroup.long 0x2C++0x3
line.long 0x0 "FMSW0,Flash signature generation result register returns the flash signature produced by the embedded signature generator.."
hexmask.long 0x0 0.--31. 1. "SIG,32-bit signature."
rgroup.long 0xFE0++0x3
line.long 0x0 "FMSTAT,Flash signature generation status bit"
bitfld.long 0x0 1. "SIG_DONE,This status bit is set at the end of signature computation" "0,1"
wgroup.long 0xFE8++0x3
line.long 0x0 "FMSTATCLR,Clear FLASH signature generation status bit"
bitfld.long 0x0 1. "SIG_DONE_CLR,When the bit is written to 1 the SIGNATURE_DONE bit is cleared." "0,1"
tree.end
tree "FTM (FlexTimer)"
base ad:0x0
tree "FTM0"
base ad:0x50009000
group.long 0x0++0xB
line.long 0x0 "SC,Status And Control"
bitfld.long 0x0 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
bitfld.long 0x0 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
newline
bitfld.long 0x0 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
bitfld.long 0x0 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
newline
bitfld.long 0x0 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
bitfld.long 0x0 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
newline
bitfld.long 0x0 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed.,1: FTM counter has overflowed."
bitfld.long 0x0 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts. Use software polling.,1: Enable TOF interrupts. An interrupt is generated.."
newline
bitfld.long 0x0 7. "RF,Reload Flag" "0: A selected reload point did not happen.,1: A selected reload point happened."
bitfld.long 0x0 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled.,1: Reload point interrupt is enabled."
newline
bitfld.long 0x0 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode.,1: FTM counter operates in Up-Down Counting mode."
bitfld.long 0x0 3.--4. "CLKS,Clock Source Selection" "0: No clock selected. This in effect disables the..,1: FTM input clock,2: Fixed frequency clock,3: External clock"
newline
bitfld.long 0x0 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
line.long 0x4 "CNT,Counter"
hexmask.long.word 0x4 0.--15. 1. "COUNT,Counter Value"
line.long 0x8 "MOD,Modulo"
hexmask.long.word 0x8 0.--15. 1. "MOD,MOD"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x5000900C ad:0x50009014 ad:0x5000901C ad:0x50009024 ad:0x5000902C ad:0x50009034 ad:0x5000903C ad:0x50009044)
tree "CONTROLS[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "CSC,Channel (n) Status And Control"
rbitfld.long 0x0 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero.,1: The channel (n) input is one."
bitfld.long 0x0 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
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bitfld.long 0x0 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred.,1: A channel (n) event has occurred."
bitfld.long 0x0 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt. Use software..,1: Enable channel (n) interrupt."
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bitfld.long 0x0 5. "MSB,Channel (n) Mode Select" "0,1"
bitfld.long 0x0 4. "MSA,Channel (n) Mode Select" "0,1"
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bitfld.long 0x0 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
bitfld.long 0x0 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
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bitfld.long 0x0 1. "ICRST,FTM counter reset by the selected input capture event." "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected channel.."
line.long 0x4 "CV,Channel (n) Value"
hexmask.long.word 0x4 0.--15. 1. "VAL,Channel Value"
tree.end
repeat.end
base ad:0x50009000
group.long 0x4C++0x53
line.long 0x0 "CNTIN,Counter Initial Value"
hexmask.long.word 0x0 0.--15. 1. "INIT,INIT"
line.long 0x4 "STATUS,Capture And Compare Status"
bitfld.long 0x4 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
bitfld.long 0x4 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
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bitfld.long 0x4 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
bitfld.long 0x4 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
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bitfld.long 0x4 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
bitfld.long 0x4 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
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bitfld.long 0x4 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
bitfld.long 0x4 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
line.long 0x8 "MODE,Features Mode Selection"
bitfld.long 0x8 7. "FAULTIE,Fault Interrupt Enable" "0: Fault control interrupt is disabled.,1: Fault control interrupt is enabled."
bitfld.long 0x8 5.--6. "FAULTM,Fault Control Mode" "0: Fault control is disabled for all channels.,1: Fault control is enabled for even channels only..,2: Fault control is enabled for all channels and..,3: Fault control is enabled for all channels and.."
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bitfld.long 0x8 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled.,1: Capture test mode is enabled."
bitfld.long 0x8 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions. Software and hardware triggers..,1: Software trigger can only be used by MOD and CnV.."
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bitfld.long 0x8 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled.,1: Write protection is disabled."
bitfld.long 0x8 1. "INIT,Initialize The Channels Output" "0,1"
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bitfld.long 0x8 0. "FTMEN,FTM Enable" "0: TPM compatibility. Free running counter and..,1: Free running counter and synchronization are.."
line.long 0xC "SYNC,Synchronization"
bitfld.long 0xC 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected.,1: Software trigger is selected."
bitfld.long 0xC 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled.,1: Trigger is enabled."
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bitfld.long 0xC 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled.,1: Trigger is enabled."
bitfld.long 0xC 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled.,1: Trigger is enabled."
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bitfld.long 0xC 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
bitfld.long 0xC 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally.,1: FTM counter is updated with its initial value.."
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bitfld.long 0xC 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled.,1: The maximum loading point is enabled."
bitfld.long 0xC 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled.,1: The minimum loading point is enabled."
line.long 0x10 "OUTINIT,Initial State For Channels Output"
bitfld.long 0x10 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
bitfld.long 0x10 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
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bitfld.long 0x10 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
bitfld.long 0x10 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
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bitfld.long 0x10 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
bitfld.long 0x10 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
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bitfld.long 0x10 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
bitfld.long 0x10 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
line.long 0x14 "OUTMASK,Output Mask"
bitfld.long 0x14 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
bitfld.long 0x14 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
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bitfld.long 0x14 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
bitfld.long 0x14 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
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bitfld.long 0x14 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
bitfld.long 0x14 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
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bitfld.long 0x14 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
bitfld.long 0x14 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
line.long 0x18 "COMBINE,Function For Linked Channels"
bitfld.long 0x18 30. "FAULTEN3,Fault Control Enable For n = 6" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
bitfld.long 0x18 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.."
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bitfld.long 0x18 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.."
bitfld.long 0x18 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive.,1: The dual edge captures are active."
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bitfld.long 0x18 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
bitfld.long 0x18 25. "COMP3,Complement Of Channel (n) for n = 6" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x18 24. "COMBINE3,Combine Channels For n = 6" "0,1"
bitfld.long 0x18 22. "FAULTEN2,Fault Control Enable For n = 4" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x18 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.."
bitfld.long 0x18 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.."
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bitfld.long 0x18 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive.,1: The dual edge captures are active."
bitfld.long 0x18 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
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bitfld.long 0x18 17. "COMP2,Complement Of Channel (n) For n = 4" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
bitfld.long 0x18 16. "COMBINE2,Combine Channels For n = 4" "0,1"
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bitfld.long 0x18 14. "FAULTEN1,Fault Control Enable For n = 2" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
bitfld.long 0x18 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.."
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bitfld.long 0x18 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.."
bitfld.long 0x18 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive.,1: The dual edge captures are active."
newline
bitfld.long 0x18 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
bitfld.long 0x18 9. "COMP1,Complement Of Channel (n) For n = 2" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x18 8. "COMBINE1,Combine Channels For n = 2" "0,1"
bitfld.long 0x18 6. "FAULTEN0,Fault Control Enable For n = 0" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x18 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.."
bitfld.long 0x18 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.."
newline
bitfld.long 0x18 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive.,1: The dual edge captures are active."
bitfld.long 0x18 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
newline
bitfld.long 0x18 1. "COMP0,Complement Of Channel (n) For n = 0" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
bitfld.long 0x18 0. "COMBINE0,Combine Channels For n = 0" "0,1"
line.long 0x1C "DEADTIME,Deadtime Configuration"
bitfld.long 0x1C 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1.,1: Divide the FTM input clock by 1.,2: Divide the FTM input clock by 4.,3: Divide the FTM input clock by 16."
hexmask.long.byte 0x1C 0.--5. 1. "DTVAL,Deadtime Value"
line.long 0x20 "EXTTRIG,FTM External Trigger"
bitfld.long 0x20 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x20 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x20 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated.,1: A channel trigger was generated."
bitfld.long 0x20 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
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bitfld.long 0x20 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x20 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x20 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x20 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x20 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x20 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
line.long 0x24 "POL,Channels Polarity"
bitfld.long 0x24 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
bitfld.long 0x24 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
newline
bitfld.long 0x24 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
bitfld.long 0x24 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
newline
bitfld.long 0x24 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
bitfld.long 0x24 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
newline
bitfld.long 0x24 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
bitfld.long 0x24 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
line.long 0x28 "FMS,Fault Mode Status"
bitfld.long 0x28 7. "FAULTF,Fault Detection Flag" "0: No fault condition was detected.,1: A fault condition was detected."
bitfld.long 0x28 6. "WPEN,Write Protection Enable" "0: Write protection is disabled. Write protected..,1: Write protection is enabled. Write protected.."
newline
rbitfld.long 0x28 5. "FAULTIN,Fault Inputs" "0: The logic OR of the enabled fault inputs is 0.,1: The logic OR of the enabled fault inputs is 1."
bitfld.long 0x28 3. "FAULTF3,Fault Detection Flag 3" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault input."
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bitfld.long 0x28 2. "FAULTF2,Fault Detection Flag 2" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault input."
bitfld.long 0x28 1. "FAULTF1,Fault Detection Flag 1" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault input."
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bitfld.long 0x28 0. "FAULTF0,Fault Detection Flag 0" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault input."
line.long 0x2C "FILTER,Input Capture Filter Control"
hexmask.long.byte 0x2C 12.--15. 1. "CH3FVAL,Channel 3 Input Filter"
hexmask.long.byte 0x2C 8.--11. 1. "CH2FVAL,Channel 2 Input Filter"
newline
hexmask.long.byte 0x2C 4.--7. 1. "CH1FVAL,Channel 1 Input Filter"
hexmask.long.byte 0x2C 0.--3. 1. "CH0FVAL,Channel 0 Input Filter"
line.long 0x30 "FLTCTRL,Fault Control"
bitfld.long 0x30 15. "FSTATE,Fault output state" "0: FTM outputs will be placed into safe values when..,1: FTM outputs will be tri-stated when fault event.."
hexmask.long.byte 0x30 8.--11. 1. "FFVAL,Fault Input Filter"
newline
bitfld.long 0x30 7. "FFLTR3EN,Fault Input 3 Filter Enable" "0: Fault input filter is disabled.,1: Fault input filter is enabled."
bitfld.long 0x30 6. "FFLTR2EN,Fault Input 2 Filter Enable" "0: Fault input filter is disabled.,1: Fault input filter is enabled."
newline
bitfld.long 0x30 5. "FFLTR1EN,Fault Input 1 Filter Enable" "0: Fault input filter is disabled.,1: Fault input filter is enabled."
bitfld.long 0x30 4. "FFLTR0EN,Fault Input 0 Filter Enable" "0: Fault input filter is disabled.,1: Fault input filter is enabled."
newline
bitfld.long 0x30 3. "FAULT3EN,Fault Input 3 Enable" "0: Fault input is disabled.,1: Fault input is enabled."
bitfld.long 0x30 2. "FAULT2EN,Fault Input 2 Enable" "0: Fault input is disabled.,1: Fault input is enabled."
newline
bitfld.long 0x30 1. "FAULT1EN,Fault Input 1 Enable" "0: Fault input is disabled.,1: Fault input is enabled."
bitfld.long 0x30 0. "FAULT0EN,Fault Input 0 Enable" "0: Fault input is disabled.,1: Fault input is enabled."
line.long 0x34 "QDCTRL,Quadrature Decoder Control And Status"
bitfld.long 0x34 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled.,1: Phase A input filter is enabled."
bitfld.long 0x34 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled.,1: Phase B input filter is enabled."
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bitfld.long 0x34 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity. Phase A input signal is not..,1: Inverted polarity. Phase A input signal is.."
bitfld.long 0x34 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity. Phase B input signal is not..,1: Inverted polarity. Phase B input signal is.."
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bitfld.long 0x34 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode.,1: Count and direction encoding mode."
rbitfld.long 0x34 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
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rbitfld.long 0x34 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting. There..,1: TOF bit was set on the top of counting. There.."
bitfld.long 0x34 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled.,1: Quadrature Decoder mode is enabled."
line.long 0x38 "CONF,Configuration"
bitfld.long 0x38 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on counter..,1: Initialization trigger is generated when a.."
bitfld.long 0x38 10. "GTBEOUT,Global Time Base Output" "0: A global time base signal generation is disabled.,1: A global time base signal generation is enabled."
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bitfld.long 0x38 9. "GTBEEN,Global Time Base Enable" "0: Use of an external global time base is disabled.,1: Use of an external global time base is enabled."
bitfld.long 0x38 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
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hexmask.long.byte 0x38 0.--4. 1. "LDFQ,Frequency of the Reload Opportunities"
line.long 0x3C "FLTPOL,FTM Fault Input Polarity"
bitfld.long 0x3C 3. "FLT3POL,Fault Input 3 Polarity" "0: The fault input polarity is active high. A 1 at..,1: The fault input polarity is active low. A 0 at.."
bitfld.long 0x3C 2. "FLT2POL,Fault Input 2 Polarity" "0: The fault input polarity is active high. A 1 at..,1: The fault input polarity is active low. A 0 at.."
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bitfld.long 0x3C 1. "FLT1POL,Fault Input 1 Polarity" "0: The fault input polarity is active high. A 1 at..,1: The fault input polarity is active low. A 0 at.."
bitfld.long 0x3C 0. "FLT0POL,Fault Input 0 Polarity" "0: The fault input polarity is active high. A 1 at..,1: The fault input polarity is active low. A 0 at.."
line.long 0x40 "SYNCONF,Synchronization Configuration"
bitfld.long 0x40 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the SWOCTRL..,1: A hardware trigger activates the SWOCTRL.."
bitfld.long 0x40 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the INVCTRL..,1: A hardware trigger activates the INVCTRL.."
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bitfld.long 0x40 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the OUTMASK..,1: A hardware trigger activates the OUTMASK.."
bitfld.long 0x40 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN and.."
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bitfld.long 0x40 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
bitfld.long 0x40 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
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bitfld.long 0x40 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
bitfld.long 0x40 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
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bitfld.long 0x40 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD HCR..,1: The software trigger activates MOD HCR CNTIN and.."
bitfld.long 0x40 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the FTM..,1: The software trigger activates the FTM counter.."
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bitfld.long 0x40 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected.,1: Enhanced PWM synchronization is selected."
bitfld.long 0x40 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
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bitfld.long 0x40 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
bitfld.long 0x40 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer value..,1: CNTIN register is updated with its buffer value.."
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bitfld.long 0x40 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
line.long 0x44 "INVCTRL,FTM Inverting Control"
bitfld.long 0x44 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled."
bitfld.long 0x44 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled."
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bitfld.long 0x44 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled."
bitfld.long 0x44 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled."
line.long 0x48 "SWOCTRL,FTM Software Output Control"
bitfld.long 0x48 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x48 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x48 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x48 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x48 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x48 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x48 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x48 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x48 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
bitfld.long 0x48 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
newline
bitfld.long 0x48 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
bitfld.long 0x48 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
newline
bitfld.long 0x48 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
bitfld.long 0x48 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
newline
bitfld.long 0x48 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
bitfld.long 0x48 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
line.long 0x4C "PWMLOAD,FTM PWM Load"
bitfld.long 0x4C 11. "GLDOK,Global Load OK" "0: No action.,1: LDOK bit is set."
bitfld.long 0x4C 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled.,1: Global Load OK enabled. A pulse event on the.."
newline
bitfld.long 0x4C 9. "LDOK,Load Enable" "0: Loading updated values is disabled.,1: Loading updated values is enabled."
bitfld.long 0x4C 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
newline
bitfld.long 0x4C 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
bitfld.long 0x4C 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
newline
bitfld.long 0x4C 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
bitfld.long 0x4C 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
newline
bitfld.long 0x4C 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
bitfld.long 0x4C 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
newline
bitfld.long 0x4C 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
bitfld.long 0x4C 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
line.long 0x50 "HCR,Half Cycle Register"
hexmask.long.word 0x50 0.--15. 1. "HCVAL,Half Cycle Value"
group.long 0x200++0x3
line.long 0x0 "MOD_MIRROR,Mirror of Modulo Value"
hexmask.long.word 0x0 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
hexmask.long.byte 0x0 11.--15. 1. "FRACMOD,Modulo Fractional Value"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x204)++0x3
line.long 0x0 "CV_MIRROR[$1],Mirror of Channel (n) Match Value"
hexmask.long.word 0x0 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
hexmask.long.byte 0x0 11.--15. 1. "FRACVAL,Channel (n) Match Fractional Value"
repeat.end
tree.end
tree "FTM1"
base ad:0x5000A000
group.long 0x0++0xB
line.long 0x0 "SC,Status And Control"
bitfld.long 0x0 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
bitfld.long 0x0 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
newline
bitfld.long 0x0 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
bitfld.long 0x0 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
newline
bitfld.long 0x0 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
bitfld.long 0x0 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled."
newline
bitfld.long 0x0 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed.,1: FTM counter has overflowed."
bitfld.long 0x0 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts. Use software polling.,1: Enable TOF interrupts. An interrupt is generated.."
newline
bitfld.long 0x0 7. "RF,Reload Flag" "0: A selected reload point did not happen.,1: A selected reload point happened."
bitfld.long 0x0 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled.,1: Reload point interrupt is enabled."
newline
bitfld.long 0x0 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode.,1: FTM counter operates in Up-Down Counting mode."
bitfld.long 0x0 3.--4. "CLKS,Clock Source Selection" "0: No clock selected. This in effect disables the..,1: FTM input clock,2: Fixed frequency clock,3: External clock"
newline
bitfld.long 0x0 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
line.long 0x4 "CNT,Counter"
hexmask.long.word 0x4 0.--15. 1. "COUNT,Counter Value"
line.long 0x8 "MOD,Modulo"
hexmask.long.word 0x8 0.--15. 1. "MOD,MOD"
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x5000A00C ad:0x5000A014 ad:0x5000A01C ad:0x5000A024)
tree "CONTROLS[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "CSC,Channel (n) Status And Control"
rbitfld.long 0x0 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero.,1: The channel (n) input is one."
bitfld.long 0x0 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
newline
bitfld.long 0x0 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred.,1: A channel (n) event has occurred."
bitfld.long 0x0 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt. Use software..,1: Enable channel (n) interrupt."
newline
bitfld.long 0x0 5. "MSB,Channel (n) Mode Select" "0,1"
bitfld.long 0x0 4. "MSA,Channel (n) Mode Select" "0,1"
newline
bitfld.long 0x0 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
bitfld.long 0x0 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
newline
bitfld.long 0x0 1. "ICRST,FTM counter reset by the selected input capture event." "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected channel.."
line.long 0x4 "CV,Channel (n) Value"
hexmask.long.word 0x4 0.--15. 1. "VAL,Channel Value"
tree.end
repeat.end
base ad:0x5000A000
group.long 0x4C++0x2F
line.long 0x0 "CNTIN,Counter Initial Value"
hexmask.long.word 0x0 0.--15. 1. "INIT,INIT"
line.long 0x4 "STATUS,Capture And Compare Status"
bitfld.long 0x4 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
bitfld.long 0x4 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
newline
bitfld.long 0x4 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
bitfld.long 0x4 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred.,1: A channel event has occurred."
line.long 0x8 "MODE,Features Mode Selection"
bitfld.long 0x8 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled.,1: Capture test mode is enabled."
bitfld.long 0x8 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions. Software and hardware triggers..,1: Software trigger can only be used by MOD and CnV.."
newline
bitfld.long 0x8 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled.,1: Write protection is disabled."
bitfld.long 0x8 1. "INIT,Initialize The Channels Output" "0,1"
newline
bitfld.long 0x8 0. "FTMEN,FTM Enable" "0: TPM compatibility. Free running counter and..,1: Free running counter and synchronization are.."
line.long 0xC "SYNC,Synchronization"
bitfld.long 0xC 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected.,1: Software trigger is selected."
bitfld.long 0xC 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled.,1: Trigger is enabled."
newline
bitfld.long 0xC 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled.,1: Trigger is enabled."
bitfld.long 0xC 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled.,1: Trigger is enabled."
newline
bitfld.long 0xC 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
bitfld.long 0xC 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally.,1: FTM counter is updated with its initial value.."
newline
bitfld.long 0xC 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled.,1: The maximum loading point is enabled."
bitfld.long 0xC 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled.,1: The minimum loading point is enabled."
line.long 0x10 "OUTINIT,Initial State For Channels Output"
bitfld.long 0x10 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
bitfld.long 0x10 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
newline
bitfld.long 0x10 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
bitfld.long 0x10 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1."
line.long 0x14 "OUTMASK,Output Mask"
bitfld.long 0x14 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
bitfld.long 0x14 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
newline
bitfld.long 0x14 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
bitfld.long 0x14 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.."
line.long 0x18 "COMBINE,Function For Linked Channels"
bitfld.long 0x18 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.."
bitfld.long 0x18 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.."
newline
bitfld.long 0x18 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive.,1: The dual edge captures are active."
bitfld.long 0x18 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
newline
bitfld.long 0x18 9. "COMP1,Complement Of Channel (n) For n = 2" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
bitfld.long 0x18 8. "COMBINE1,Combine Channels For n = 2" "0,1"
newline
bitfld.long 0x18 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.."
bitfld.long 0x18 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.."
newline
bitfld.long 0x18 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive.,1: The dual edge captures are active."
bitfld.long 0x18 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
newline
bitfld.long 0x18 1. "COMP0,Complement Of Channel (n) For n = 0" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
bitfld.long 0x18 0. "COMBINE0,Combine Channels For n = 0" "0,1"
line.long 0x1C "DEADTIME,Deadtime Configuration"
bitfld.long 0x1C 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1.,1: Divide the FTM input clock by 1.,2: Divide the FTM input clock by 4.,3: Divide the FTM input clock by 16."
hexmask.long.byte 0x1C 0.--5. 1. "DTVAL,Deadtime Value"
line.long 0x20 "EXTTRIG,FTM External Trigger"
bitfld.long 0x20 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated.,1: A channel trigger was generated."
bitfld.long 0x20 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
newline
bitfld.long 0x20 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x20 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
newline
bitfld.long 0x20 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x20 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
line.long 0x24 "POL,Channels Polarity"
bitfld.long 0x24 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
bitfld.long 0x24 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
newline
bitfld.long 0x24 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
bitfld.long 0x24 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low."
line.long 0x28 "FMS,Fault Mode Status"
bitfld.long 0x28 6. "WPEN,Write Protection Enable" "0: Write protection is disabled. Write protected..,1: Write protection is enabled. Write protected.."
line.long 0x2C "FILTER,Input Capture Filter Control"
hexmask.long.byte 0x2C 12.--15. 1. "CH3FVAL,Channel 3 Input Filter"
hexmask.long.byte 0x2C 8.--11. 1. "CH2FVAL,Channel 2 Input Filter"
newline
hexmask.long.byte 0x2C 4.--7. 1. "CH1FVAL,Channel 1 Input Filter"
hexmask.long.byte 0x2C 0.--3. 1. "CH0FVAL,Channel 0 Input Filter"
group.long 0x80++0x7
line.long 0x0 "QDCTRL,Quadrature Decoder Control And Status"
bitfld.long 0x0 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled.,1: Phase A input filter is enabled."
bitfld.long 0x0 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled.,1: Phase B input filter is enabled."
newline
bitfld.long 0x0 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity. Phase A input signal is not..,1: Inverted polarity. Phase A input signal is.."
bitfld.long 0x0 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity. Phase B input signal is not..,1: Inverted polarity. Phase B input signal is.."
newline
bitfld.long 0x0 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode.,1: Count and direction encoding mode."
rbitfld.long 0x0 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
newline
rbitfld.long 0x0 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting. There..,1: TOF bit was set on the top of counting. There.."
bitfld.long 0x0 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled.,1: Quadrature Decoder mode is enabled."
line.long 0x4 "CONF,Configuration"
bitfld.long 0x4 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on counter..,1: Initialization trigger is generated when a.."
bitfld.long 0x4 10. "GTBEOUT,Global Time Base Output" "0: A global time base signal generation is disabled.,1: A global time base signal generation is enabled."
newline
bitfld.long 0x4 9. "GTBEEN,Global Time Base Enable" "0: Use of an external global time base is disabled.,1: Use of an external global time base is enabled."
bitfld.long 0x4 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--4. 1. "LDFQ,Frequency of the Reload Opportunities"
group.long 0x8C++0x13
line.long 0x0 "SYNCONF,Synchronization Configuration"
bitfld.long 0x0 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the SWOCTRL..,1: A hardware trigger activates the SWOCTRL.."
bitfld.long 0x0 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the INVCTRL..,1: A hardware trigger activates the INVCTRL.."
newline
bitfld.long 0x0 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the OUTMASK..,1: A hardware trigger activates the OUTMASK.."
bitfld.long 0x0 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN and.."
newline
bitfld.long 0x0 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
bitfld.long 0x0 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
newline
bitfld.long 0x0 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
bitfld.long 0x0 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
newline
bitfld.long 0x0 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD HCR..,1: The software trigger activates MOD HCR CNTIN and.."
bitfld.long 0x0 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the FTM..,1: The software trigger activates the FTM counter.."
newline
bitfld.long 0x0 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected.,1: Enhanced PWM synchronization is selected."
bitfld.long 0x0 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
newline
bitfld.long 0x0 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
bitfld.long 0x0 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer value..,1: CNTIN register is updated with its buffer value.."
newline
bitfld.long 0x0 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
line.long 0x4 "INVCTRL,FTM Inverting Control"
bitfld.long 0x4 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled."
bitfld.long 0x4 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled."
line.long 0x8 "SWOCTRL,FTM Software Output Control"
bitfld.long 0x8 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x8 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x8 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x8 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x8 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
bitfld.long 0x8 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
newline
bitfld.long 0x8 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
bitfld.long 0x8 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.."
line.long 0xC "PWMLOAD,FTM PWM Load"
bitfld.long 0xC 11. "GLDOK,Global Load OK" "0: No action.,1: LDOK bit is set."
bitfld.long 0xC 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled.,1: Global Load OK enabled. A pulse event on the.."
newline
bitfld.long 0xC 9. "LDOK,Load Enable" "0: Loading updated values is disabled.,1: Loading updated values is enabled."
bitfld.long 0xC 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
newline
bitfld.long 0xC 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
bitfld.long 0xC 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
newline
bitfld.long 0xC 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
bitfld.long 0xC 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity."
line.long 0x10 "HCR,Half Cycle Register"
hexmask.long.word 0x10 0.--15. 1. "HCVAL,Half Cycle Value"
group.long 0x200++0x3
line.long 0x0 "MOD_MIRROR,Mirror of Modulo Value"
hexmask.long.word 0x0 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
hexmask.long.byte 0x0 11.--15. 1. "FRACMOD,Modulo Fractional Value"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x204)++0x3
line.long 0x0 "CV_MIRROR[$1],Mirror of Channel (n) Match Value"
hexmask.long.word 0x0 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
hexmask.long.byte 0x0 11.--15. 1. "FRACVAL,Channel (n) Match Fractional Value"
repeat.end
tree.end
tree.end
tree "GPIO (General Purpose Input/Output)"
base ad:0xA0000000
repeat 2. (list 0x0 0x1)(list ad:0xA0000000 ad:0xA0000020)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
repeat 2. (list 0x0 0x1)(list ad:0xA0001000 ad:0xA0001080)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
base ad:0xA0000000
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
tree.end
tree "I2C (Inter Integrated Circuit)"
base ad:0x40050000
group.long 0x0++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
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bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled configurations settings for the Monitor function are not changed but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled configurations settings for the Slave function are not changed but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
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bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled configurations settings for the Master function are not changed but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start Stop and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0xC++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x10++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks as defined by the CLKDIV register. To change this value while I2C is in operation disable all time-outs write a new value to TIMEOUT then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x18++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start address Stop and address match must always be done with software typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue." "0: No effect.,1: Informs the Master function to continue to the.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Informs the Slave function to continue to the.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is assuming that it is enabled. If QUALMODE0 = 0 any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I3C (Improved Inter Integrated Circuit)"
base ad:0x40060000
group.long 0x0++0x17
line.long 0x0 "MCONFIG,Controller Configuration Register"
hexmask.long.byte 0x0 28.--31. 1. "I2CBAUD,I2C baud rate"
bitfld.long 0x0 25.--27. "SKEW,Skew" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24. "ODHPP,Open drain high push-pull" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "ODBAUD,Open drain baud rate"
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hexmask.long.byte 0x0 12.--15. 1. "PPLOW,Push-Pull low"
hexmask.long.byte 0x0 8.--11. 1. "PPBAUD,Push-pull baud rate"
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bitfld.long 0x0 6. "ODSTOP,Open drain stop" "0: Disable open-drain stop. ODSTOP must be disabled..,1: Enable open-drain stop. STOP is emitted at.."
bitfld.long 0x0 4.--5. "HKEEP,High-Keeper" "0: NONE. Use PUR (Pull-Up Resistor). No separate..,1: WIRED_IN. High Keeper controls use..,2: PASSIVE_SDA. Passive on SDA can Hi-Z (high..,3: PASSIVE_ON_SDA_SCL. Passive on SDA and SCL can.."
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bitfld.long 0x0 3. "DISTO,Disable Timeout" "0: Timeout enabled,1: Timeout disabled if timeout is configured"
bitfld.long 0x0 0.--1. "MSTENA,Controller enable" "0: CONTROLLER_OFF. Controller is disabled. The I3C..,1: CONTROLLER_ON. Controller is enabled. When used..,2: MASTER_CAPABLE: The I3C module is..,?"
line.long 0x4 "SCONFIG,Target Configuration register"
hexmask.long.byte 0x4 25.--31. 1. "SADDR,Static address"
hexmask.long.byte 0x4 16.--21. 1. "BAMATCH,Bus available match"
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bitfld.long 0x4 9. "OFFLINE,Offline" "0,1"
bitfld.long 0x4 4. "HDROK,HDR OK Deprecated. Use the SIDEXT[BCR] field instead" "0,1"
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bitfld.long 0x4 3. "S0IGNORE,Ignore TE0/TE1 Errors" "0,1"
bitfld.long 0x4 2. "MATCHSS,Match START or STOP" "0,1"
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bitfld.long 0x4 1. "NACK,Not acknowledge" "0,1"
bitfld.long 0x4 0. "SLVENA,Target enable" "0,1"
line.long 0x8 "SSTATUS,Target Status Register"
rbitfld.long 0x8 30.--31. "TIMECTRL,Time control" "0: NO_TIME_CONTROL: No time control is enabled,?,2: ASYNC_MODE: Asynchronous standard mode (0) is..,?"
rbitfld.long 0x8 28.--29. "ACTSTATE,Activity state from Common Command Codes (CCC)" "0: NO_LATENCY: normal bus operations,1: LATENCY_1MS: 1 ms of latency,2: LATENCY_100MS: 100 ms of latency,3: LATENCY_10S: 10 seconds of latency"
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rbitfld.long 0x8 27. "HJDIS,Hot-Join is disabled" "0,1"
rbitfld.long 0x8 25. "MRDIS,Controller requests are disabled" "0,1"
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rbitfld.long 0x8 24. "IBIDIS,In-Band Interrupts are disabled" "0,1"
rbitfld.long 0x8 20.--21. "EVDET,Event details" "0: NONE: no event or no pending event,1: NO_REQUEST: Request not sent yet. Either there..,2: NACKED: Not acknowledged(Request sent and..,3: ACKED: Acknowledged (Request sent and ACKed) so.."
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bitfld.long 0x8 19. "SLVRST,Target Reset" "0,1"
bitfld.long 0x8 18. "EVENT,Event" "0,1"
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bitfld.long 0x8 17. "CHANDLED,Common-Command-Code handled" "0,1"
bitfld.long 0x8 16. "HDRMATCH,High Data Rate command match" "0,1"
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rbitfld.long 0x8 15. "ERRWARN,Error warning" "0,1"
bitfld.long 0x8 14. "CCC,Common Command Code" "0,1"
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bitfld.long 0x8 13. "DACHG,DACHG" "0,1"
rbitfld.long 0x8 12. "TXNOTFULL,Transmit buffer is not full" "0,1"
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rbitfld.long 0x8 11. "RX_PEND,Received message pending" "0,1"
bitfld.long 0x8 10. "STOP,Stop" "0,1"
newline
bitfld.long 0x8 9. "MATCHED,Matched" "0,1"
bitfld.long 0x8 8. "START,Start" "0,1"
newline
rbitfld.long 0x8 6. "STHDR,Status High Data Rate" "0,1"
rbitfld.long 0x8 5. "STDAA,Status Dynamic Address Assignment" "0,1"
newline
rbitfld.long 0x8 4. "STREQWR,Status request write" "0,1"
rbitfld.long 0x8 3. "STREQRD,Status required" "0,1"
newline
rbitfld.long 0x8 2. "STCCCH,Status Common Command Code Handler" "0,1"
rbitfld.long 0x8 1. "STMSG,Status message" "0,1"
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rbitfld.long 0x8 0. "STNOTSTOP,Status Not Stop" "0,1"
line.long 0xC "SCTRL,Target Control Register"
hexmask.long.byte 0xC 24.--31. 1. "VENDINFO,Vendor information"
bitfld.long 0xC 20.--21. "ACTSTATE,Activity state (of target)" "0,1,2,3"
newline
hexmask.long.byte 0xC 16.--19. 1. "PENDINT,Pending interrupt"
hexmask.long.byte 0xC 8.--15. 1. "IBIDATA,In-Band Interrupt data"
newline
bitfld.long 0xC 4.--6. "MAPIDX,Map Index" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 3. "EXTDATA,Extended Data" "0,1"
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bitfld.long 0xC 0.--1. "EVENT,EVENT" "0: NORMAL_MODE: If EVENT is set to 0 after was a..,1: IBI: Start an In-Band Interrupt. This will try..,2: MASTER_REQUEST: Start a Master-Request.,3: HOT_JOIN_REQUEST: Start a Hot-Join request. A.."
line.long 0x10 "SINTSET,Target Interrupt Set Register"
bitfld.long 0x10 19. "SLVRST,Target Reset" "0,1"
bitfld.long 0x10 18. "EVENT,Event interrupt enable" "0,1"
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bitfld.long 0x10 17. "CHANDLED,Common Command Code (CCC) (that was handled by I3C module) interrupt enable" "0,1"
bitfld.long 0x10 16. "DDRMATCHED,Double Data Rate (DDR) interrupt enable" "0,1"
newline
bitfld.long 0x10 15. "ERRWARN,Error/warning interrupt enable" "0,1"
bitfld.long 0x10 14. "CCC,Common Command Code (CCC) (that was not handled by I3C module) interrupt enable" "0,1"
newline
bitfld.long 0x10 13. "DACHG,Dynamic address change interrupt enable" "0,1"
bitfld.long 0x10 12. "TXSEND,Transmit interrupt enable" "0,1"
newline
bitfld.long 0x10 11. "RXPEND,Receive interrupt enable" "0,1"
bitfld.long 0x10 10. "STOP,Stop interrupt enable" "0,1"
newline
bitfld.long 0x10 9. "MATCHED,Match interrupt enable" "0,1"
bitfld.long 0x10 8. "START,Start interrupt enable" "0,1"
line.long 0x14 "SINTCLR,Target Interrupt Clear Register"
eventfld.long 0x14 19. "SLVRST,SLVRST interrupt enable clear" "0,1"
eventfld.long 0x14 18. "EVENT,EVENT interrupt enable clear" "0,1"
newline
eventfld.long 0x14 17. "CHANDLED,CHANDLED interrupt enable clear" "0,1"
eventfld.long 0x14 16. "DDRMATCHED,DDRMATCHED interrupt enable clear" "0,1"
newline
eventfld.long 0x14 15. "ERRWARN,ERRWARN interrupt enable clear" "0,1"
eventfld.long 0x14 14. "CCC,CCC interrupt enable clear" "0,1"
newline
eventfld.long 0x14 13. "DACHG,DACHG interrupt enable clear" "0,1"
eventfld.long 0x14 12. "TXSEND,TXSEND interrupt enable clear" "0,1"
newline
eventfld.long 0x14 11. "RXPEND,RXPEND interrupt enable clear" "0,1"
eventfld.long 0x14 10. "STOP,STOP interrupt enable clear" "0,1"
newline
eventfld.long 0x14 9. "MATCHED,MATCHED interrupt enable clear" "0,1"
eventfld.long 0x14 8. "START,START interrupt enable clear" "0,1"
rgroup.long 0x18++0x3
line.long 0x0 "SINTMASKED,Target Interrupt Mask Register"
bitfld.long 0x0 18. "EVENT,EVENT interrupt mask" "0,1"
bitfld.long 0x0 17. "CHANDLED,CHANDLED interrupt mask" "0,1"
newline
bitfld.long 0x0 16. "DDRMATCHED,DDRMATCHED interrupt mask" "0,1"
bitfld.long 0x0 15. "ERRWARN,ERRWARN interrupt mask" "0,1"
newline
bitfld.long 0x0 14. "CCC,CCC interrupt mask" "0,1"
bitfld.long 0x0 13. "DACHG,DACHG interrupt mask" "0,1"
newline
bitfld.long 0x0 12. "TXSEND,TXSEND interrupt mask" "0,1"
bitfld.long 0x0 11. "RXPEND,RXPEND interrupt mask" "0,1"
newline
bitfld.long 0x0 10. "STOP,STOP interrupt mask" "0,1"
bitfld.long 0x0 9. "MATCHED,MATCHED interrupt mask" "0,1"
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bitfld.long 0x0 8. "START,START interrupt mask" "0,1"
group.long 0x1C++0x7
line.long 0x0 "SERRWARN,Target Errors and Warnings Register"
bitfld.long 0x0 17. "OWRITE,Over-write error" "0,1"
bitfld.long 0x0 16. "OREAD,Over-read error" "0,1"
newline
bitfld.long 0x0 11. "S0S1,S0 or S1 error" "0,1"
bitfld.long 0x0 10. "HCRC,HDR-DDR CRC error" "0,1"
newline
bitfld.long 0x0 9. "HPAR,HDR parity error" "0,1"
bitfld.long 0x0 8. "SPAR,SDR parity error" "0,1"
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bitfld.long 0x0 4. "INVSTART,Invalid start error" "0,1"
bitfld.long 0x0 3. "TERM,Terminated error" "0,1"
newline
bitfld.long 0x0 2. "URUNNACK,Underrun and Not Acknowledged (NACKed) error" "0,1"
bitfld.long 0x0 1. "URUN,Underrun error" "0,1"
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bitfld.long 0x0 0. "ORUN,Overrun error" "0,1"
line.long 0x4 "SDMACTRL,Target DMA Control Register"
bitfld.long 0x4 4.--5. "DMAWIDTH,Width of DMA operations" "0: BYTE,1: BYTE_AGAIN,2: HALF_WORD: Half word (16 bits). This will make..,?"
bitfld.long 0x4 2.--3. "DMATB,DMA Write (To-bus) trigger" "0: NOT_USED: DMA is not used,1: ENABLE_ONE_FRAME: DMA is enabled for 1 Frame..,2: ENABLE: DMA is enabled until turned off.,?"
newline
bitfld.long 0x4 0.--1. "DMAFB,DMA Read (From-bus) trigger" "0: DMA not used,1: DMA is enabled for one frame.,2: DMA enable,?"
group.long 0x2C++0x3
line.long 0x0 "SDATACTRL,Target Data Control Register"
rbitfld.long 0x0 31. "RXEMPTY,RX is empty" "0: RX is not empty,1: RX is empty"
rbitfld.long 0x0 30. "TXFULL,TX is full" "0: TX is not full,1: TX is full"
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hexmask.long.byte 0x0 24.--28. 1. "RXCOUNT,Count of bytes in RX"
hexmask.long.byte 0x0 16.--20. 1. "TXCOUNT,Count of bytes in TX"
newline
bitfld.long 0x0 6.--7. "RXTRIG,Trigger level for RX FIFO fullness" "0: Trigger on not empty,1: Trigger on or more full,2: Trigger on .5 or more full,3: Trigger on 3/4 or more full"
bitfld.long 0x0 4.--5. "TXTRIG,Trigger level for TX FIFO emptiness" "0: Trigger on empty,1: Trigger on full or less,2: Trigger on .5 full or less,3: Trigger on 1 less than full or less (Default)"
newline
bitfld.long 0x0 3. "UNLOCK,Unlock" "0,1"
bitfld.long 0x0 1. "FLUSHFB,Flushes the from-bus buffer/FIFO" "0,1"
newline
bitfld.long 0x0 0. "FLUSHTB,Flush the to-bus buffer/FIFO" "0,1"
wgroup.long 0x30++0xF
line.long 0x0 "SWDATAB,Target Write Data Byte Register"
bitfld.long 0x0 16. "END_ALSO,End also" "0,1"
bitfld.long 0x0 8. "END,End" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data byte to send to master"
line.long 0x4 "SWDATABE,Target Write Data Byte End"
hexmask.long.byte 0x4 0.--7. 1. "DATA,Data byte to send to master."
line.long 0x8 "SWDATAH,Target Write Data Half-word Register"
bitfld.long 0x8 16. "END,End of message" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "DATA1,The 2nd byte to send to the controller"
newline
hexmask.long.byte 0x8 0.--7. 1. "DATA0,The 1st byte to send to the controller"
line.long 0xC "SWDATAHE,Target Write Data Half-word End Register"
hexmask.long.byte 0xC 8.--15. 1. "DATA1,The 2nd byte to send to the controller"
hexmask.long.byte 0xC 0.--7. 1. "DATA0,The 1st byte to send to the controller"
rgroup.long 0x40++0x3
line.long 0x0 "SRDATAB,Target Read Data Byte Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA0,Byte read from the controller"
rgroup.long 0x48++0x3
line.long 0x0 "SRDATAH,Target Read Data Half-word Register"
hexmask.long.byte 0x0 8.--15. 1. "MSB,Represents the second byte read from the controller (and written by the target)."
hexmask.long.byte 0x0 0.--7. 1. "LSB,Represents the first byte read from the controller (and written by the target)."
wgroup.long 0x54++0x3
line.long 0x0 "SWDATAB1,Target Write Data Byte Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Byte rto send to controller"
rgroup.long 0x60++0x3
line.long 0x0 "SCAPABILITIES,Target Capabilities Register"
bitfld.long 0x0 31. "DMA,DMA" "0: DMA is not supported,1: DMA is supported"
bitfld.long 0x0 30. "INT,INT" "0: Interrupts are not supported,1: Interrupts are supported"
newline
bitfld.long 0x0 28.--29. "FIFORX,FIFO receive" "0: FIFO_2BYTE: 2 (or 3)-byte RX FIFO the default..,1: FIFO_4BYTE: 4-byte RX FIFO,2: FIFO_8BYTE: 8-byte RX FIFO,3: FIFO_16BYTE: 16-byte RX FIFO"
bitfld.long 0x0 26.--27. "FIFOTX,FIFO transmit" "0: FIFO_2BYTE: 2-byte TX FIFO the default FIFO..,1: FIFO_4BYTE: 4-byte TX FIFO,2: FIFO_8BYTE: 8-byte TX FIFO,3: FIFO_16BYTE: 16-byte TX FIFO"
newline
bitfld.long 0x0 23.--25. "EXTFIFO,External FIFO" "0: NO_EXT_FIFO: No external FIFO is available,1: STD_EXT_FIFO: standard available/free external..,2: REQUEST_EXT_FIFO: request track external FIFO,?,?,?,?,?"
bitfld.long 0x0 21. "TIMECTRL,Time control" "0: NO_TIME_CONTROL_TYPE: No time control is enabled,1: ATLEAST1_TIME_CONTROL: at least one time-control.."
newline
hexmask.long.byte 0x0 16.--20. 1. "IBI_MR_HJ,In-Band Interrupts Controller Requests Hot Join events"
hexmask.long.byte 0x0 12.--15. 1. "CCCHANDLE,Common Command Codes (CCC) handling"
newline
bitfld.long 0x0 10.--11. "SADDR,Static address" "0: NO_STATIC: No static address,1: STATIC: Static address is fixed in hardware,2: HW_CONTROL: Hardware controls the static address..,3: CONFIG: SCONFIG register supplies the static.."
bitfld.long 0x0 9. "MASTER,Controller" "0: MASTERNOTSUPPORTED: controller capability is not..,1: MASTERSUPPORTED: controller capability is.."
newline
bitfld.long 0x0 6.--7. "HDRSUPP,HDR support" "0,1,2,3"
hexmask.long.byte 0x0 2.--5. 1. "IDREG,ID register"
newline
bitfld.long 0x0 0.--1. "IDENA,ID 48b handler" "0: APPLICATION: Application handles ID 48b,1: HW: Hardware handles ID 48b,2: HW_BUT: in hardware but the I3C module instance..,3: PARTNO: a part number register (PARTNO) handles.."
group.long 0x64++0x17
line.long 0x0 "SDYNADDR,Slave Dynamic Address Register"
hexmask.long.word 0x0 16.--31. 1. "KEY,Key"
bitfld.long 0x0 12. "MAPSA,Map a Static Address" "0,1"
newline
hexmask.long.byte 0x0 8.--11. 1. "MAPIDX,Mapped Dynamic Address"
hexmask.long.byte 0x0 1.--7. 1. "DADDR,Dynamic address"
newline
bitfld.long 0x0 0. "DAVALID,DAVALID" "0: DANOTASSIGNED: a Dynamic Address is not assigned,1: DAASSIGNED: a Dynamic Address is assigned"
line.long 0x4 "SMAXLIMITS,Target Maximum Limits Register"
hexmask.long.word 0x4 16.--27. 1. "MAXWR,Maximum write length"
hexmask.long.word 0x4 0.--11. 1. "MAXRD,Maximum read length"
line.long 0x8 "SIDPARTNO,Target ID Part Number Register"
hexmask.long 0x8 0.--31. 1. "PARTNO,Part number"
line.long 0xC "SIDEXT,Target ID Extension Register"
hexmask.long.byte 0xC 16.--23. 1. "BCR,Bus Characteristics Register"
hexmask.long.byte 0xC 8.--15. 1. "DCR,Device Characteristic Register"
line.long 0x10 "SVENDORID,Target Vendor ID Register"
hexmask.long.word 0x10 0.--14. 1. "VID,Vendor ID"
line.long 0x14 "STCCLOCK,Target Time Control Clock Register"
hexmask.long.byte 0x14 8.--15. 1. "FREQ,Clock frequency"
hexmask.long.byte 0x14 0.--7. 1. "ACCURACY,Clock accuracy"
rgroup.long 0x7C++0x3
line.long 0x0 "SMSGLAST,Target Message Last Matched Register"
bitfld.long 0x0 22.--23. "LASTMODE2,Last Mode 2" "0: SDR mode (or I2C if static) was the last mode 2..,1: HDR-DDR was the last mode 2 previous accesses ago.,2: HDR-BT was the last mode 2 previous accesses ago.,?"
bitfld.long 0x0 21. "LASTGROUPM2,Last Match 2 Previous Was Group" "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MAPLASTM2,Previous match index 2"
bitfld.long 0x0 14.--15. "LASTMODE1,Last Mode 1" "0: SDR mode (or I2C if static) was the last mode.,1: HDR-DDR was the last mode.,2: HDR-BT was the last mode.,?"
newline
bitfld.long 0x0 13. "LASTGROUPM1,Last Match 1 Previous Was Group" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "MAPLASTM1,Previous match index 1"
newline
bitfld.long 0x0 6.--7. "LASTMODE,Last Mode" "0: SDR mode (or I2C if static) was the last mode.,1: HDR-DDR was the last mode.,2: HDR-BT was the last mode.,?"
bitfld.long 0x0 5. "LASTGROUP,Last Match Was Group" "0,1"
newline
bitfld.long 0x0 4. "LASTSTATIC,Last Static Address Matched" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "MAPLAST,Matched address index"
group.long 0x84++0xF
line.long 0x0 "MCTRL,Controller Main Control Register"
hexmask.long.byte 0x0 16.--23. 1. "RDTERM,Read terminate"
hexmask.long.byte 0x0 9.--15. 1. "ADDR,ADDR"
newline
bitfld.long 0x0 8. "DIR,DIR" "0: DIRWRITE: Write,1: DIRREAD: Read"
bitfld.long 0x0 6.--7. "IBIRESP,In-Band Interrupt (IBI) response" "0: ACK (acknowledge). When REQUEST = 1..,1: NACK: Not acknowledge,2: Acknowledge with mandatory byte. When REQUEST =..,3: Manual. When REQUEST = 1 or REQUEST = 7 stop and.."
newline
bitfld.long 0x0 4.--5. "TYPE,Bus type with START" "0: I3C: Normally the SDR mode of I3C. For ForceExit..,1: I2C: Normally the Standard I2C protocol.,2: DDR: (Double Data Rate): Normally the HDR-DDR..,3: For ForcedExit this is forced IBHR."
bitfld.long 0x0 0.--2. "REQUEST,Request" "0: NONE: Indicates that no request is present. The..,1: EMITSTARTADDR: Emit START with address and..,2: EMITSTOP: Emit a STOP on bus. Must be in Single..,3: IBIACKNACK: Manual In-Band Interrupt (IBI)..,4: PROCESSDAA: If not currently in Dynamic Address..,?,6: FORCEEXIT and IBHR: Emit an Exit Pattern from..,7: AUTOIBI: Hold in a stopped state but auto-emit.."
line.long 0x4 "MSTATUS,Controller Status Register"
hexmask.long.byte 0x4 24.--30. 1. "IBIADDR,IBI address"
bitfld.long 0x4 19. "NOWMASTER,Now controller (now this module is a controller)" "0,1"
newline
rbitfld.long 0x4 15. "ERRWARN,Error or warning" "0,1"
bitfld.long 0x4 13. "IBIWON,In-Band Interrupt (IBI) won" "0,1"
newline
rbitfld.long 0x4 12. "TXNOTFULL,TX Buffer or FIFO Not Full" "0,1"
rbitfld.long 0x4 11. "RXPEND,RXPEND" "0,1"
newline
bitfld.long 0x4 10. "COMPLETE,COMPLETE" "0,1"
bitfld.long 0x4 9. "MCTRLDONE,Controller control done" "0,1"
newline
bitfld.long 0x4 8. "SLVSTART,Target start" "0,1"
rbitfld.long 0x4 6.--7. "IBITYPE,In-Band Interrupt (IBI) type" "0: NONE: No IBI. This status occurs when..,1: IBI: In-Band Interrupt,2: MR: Controller Request,3: HJ: Hot-Join"
newline
rbitfld.long 0x4 5. "NACKED,Not acknowledged" "0,1"
rbitfld.long 0x4 4. "BETWEEN,Between messages or Dynamic Address Assignments (DAA)" "0,1"
newline
rbitfld.long 0x4 0.--2. "STATE,State of the controller" "0: IDLE: the bus has stopped.,1: SLVREQ: Target request. The bus has STOPped but..,2: MSGSDR: Single Data Rate Message mode from using..,3: NORMACT: normal active Single Data Rate (SDR)..,4: MSGDDR: Double Data Rate (DDR) Message mode..,5: DAA: in Enter Dynamic Address Assignment..,6: IBIACK: waiting for an In-Band Interrupt (IBI)..,7: IBIRCV: Receiving an In-Band Interrupt (IBI);.."
line.long 0x8 "MIBIRULES,Controller In-band Interrupt Registry and Rules Register"
bitfld.long 0x8 31. "NOBYTE,No IBI byte" "0,1"
bitfld.long 0x8 30. "MSB0,Set Most Significant address Bit to 0" "0,1"
newline
hexmask.long.byte 0x8 24.--29. 1. "ADDR4,ADDR4"
hexmask.long.byte 0x8 18.--23. 1. "ADDR3,ADDR3"
newline
hexmask.long.byte 0x8 12.--17. 1. "ADDR2,ADDR2"
hexmask.long.byte 0x8 6.--11. 1. "ADDR1,ADDR1"
newline
hexmask.long.byte 0x8 0.--5. 1. "ADDR0,ADDR0"
line.long 0xC "MINTSET,Controller Interrupt Set Register"
bitfld.long 0xC 19. "NOWMASTER,Now controller (now this I3C module is a controller) interrupt enable" "0,1"
bitfld.long 0xC 15. "ERRWARN,Error or warning (ERRWARN) interrupt enable" "0,1"
newline
bitfld.long 0xC 13. "IBIWON,In-Band Interrupt (IBI) won interrupt enable" "0,1"
bitfld.long 0xC 12. "TXNOTFULL,TX buffer/FIFO is not full interrupt enable" "0,1"
newline
bitfld.long 0xC 11. "RXPEND,RX pending interrupt enable" "0,1"
bitfld.long 0xC 10. "COMPLETE,Completed message interrupt enable" "0,1"
newline
bitfld.long 0xC 9. "MCTRLDONE,Controller control done interrupt enable" "0,1"
bitfld.long 0xC 8. "SLVSTART,Target start interrupt enable" "0,1"
wgroup.long 0x94++0x3
line.long 0x0 "MINTCLR,Controller Interrupt Clear Register"
bitfld.long 0x0 19. "NOWMASTER,NOWMASTER interrupt enable clear" "0,1"
bitfld.long 0x0 15. "ERRWARN,ERRWARN interrupt enable clear" "0,1"
newline
bitfld.long 0x0 13. "IBIWON,IBIWON interrupt enable clear" "0,1"
bitfld.long 0x0 12. "TXNOTFULL,TXNOTFULL interrupt enable clear" "0,1"
newline
bitfld.long 0x0 11. "RXPEND,RXPEND interrupt enable clear" "0,1"
bitfld.long 0x0 10. "COMPLETE,COMPLETE interrupt enable clear" "0,1"
newline
bitfld.long 0x0 9. "MCTRLDONE,MCTRLDONE interrupt enable clear" "0,1"
bitfld.long 0x0 8. "SLVSTART,SLVSTART interrupt enable clear" "0,1"
rgroup.long 0x98++0x3
line.long 0x0 "MINTMASKED,Controller Interrupt Mask Register"
bitfld.long 0x0 19. "NOWMASTER,NOWMASTER interrupt mask" "0,1"
bitfld.long 0x0 15. "ERRWARN,ERRWARN interrupt mask" "0,1"
newline
bitfld.long 0x0 13. "IBIWON,IBIWON interrupt mask" "0,1"
bitfld.long 0x0 12. "TXNOTFULL,TXNOTFULL interrupt mask" "0,1"
newline
bitfld.long 0x0 11. "RXPEND,RXPEND interrupt mask" "0,1"
bitfld.long 0x0 10. "COMPLETE,COMPLETE interrupt mask" "0,1"
newline
bitfld.long 0x0 9. "MCTRLDONE,MCTRLDONE interrupt mask" "0,1"
bitfld.long 0x0 8. "SLVSTART,SLVSTART interrupt mask" "0,1"
group.long 0x9C++0x7
line.long 0x0 "MERRWARN,Controller Errors and Warnings Register"
bitfld.long 0x0 20. "TIMEOUT,TIMEOUT error" "0,1"
bitfld.long 0x0 19. "INVREQ,Invalid request error" "0,1"
newline
bitfld.long 0x0 18. "MSGERR,Message error" "0,1"
bitfld.long 0x0 17. "OWRITE,Over-write error" "0: No error,1: Error"
newline
bitfld.long 0x0 16. "OREAD,Over-read error" "0: No error,1: Error"
bitfld.long 0x0 10. "HCRC,High data rate CRC error" "0: No error,1: Error"
newline
bitfld.long 0x0 9. "HPAR,High data rate parity" "0: No error,1: Error"
bitfld.long 0x0 4. "TERM,Terminate error" "0,1"
newline
bitfld.long 0x0 3. "WRABT,WRABT (Write abort) error" "0,1"
bitfld.long 0x0 2. "NACK,Not acknowledge (NACK) error" "0,1"
newline
bitfld.long 0x0 1. "URUN,Underrun error" "0,1"
line.long 0x4 "MDMACTRL,Controller DMA Control Register"
bitfld.long 0x4 4.--5. "DMAWIDTH,DMA width" "0: BYTE,1: BYTE_AGAIN,2: HALF_WORD: Half-word (16 bits). This will make..,?"
bitfld.long 0x4 2.--3. "DMATB,DMA to bus" "0: DMA is not used,1: Enable DMA for one frame (ended by DMA or..,2: Enable DMA until DMA is turned off. Normally DMA..,?"
newline
bitfld.long 0x4 0.--1. "DMAFB,DMA from bus" "0: DMA is not used,1: Enable DMA for one frame. STOP or repeated START..,2: Enable DMA until DMA is turned off,?"
group.long 0xAC++0x3
line.long 0x0 "MDATACTRL,Controller Data Control Register"
rbitfld.long 0x0 31. "RXEMPTY,Receive Is Empty" "0,1"
rbitfld.long 0x0 30. "TXFULL,Transmit Is Full" "0,1"
newline
hexmask.long.byte 0x0 24.--28. 1. "RXCOUNT,Receive Byte Count"
hexmask.long.byte 0x0 16.--20. 1. "TXCOUNT,Transmit Byte Count."
newline
bitfld.long 0x0 6.--7. "RXTRIG,Receive trigger level" "0,1,2,3"
bitfld.long 0x0 4.--5. "TXTRIG,Transmit trigger level" "0,1,2,3"
newline
bitfld.long 0x0 3. "UNLOCK,Unlock" "0,1"
bitfld.long 0x0 1. "FLUSHFB,Flush from-bus buffer/FIFO" "0,1"
newline
bitfld.long 0x0 0. "FLUSHTB,Flush to-bus buffer/FIFO" "0,1"
wgroup.long 0xB0++0xF
line.long 0x0 "MWDATAB,Controller Write Data Byte Register"
bitfld.long 0x0 16. "END_ALSO,End of message also" "0,1"
bitfld.long 0x0 8. "END,End of message" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data byte"
line.long 0x4 "MWDATABE,Controller Write Data Byte End Register"
hexmask.long.byte 0x4 0.--7. 1. "VALUE,Data"
line.long 0x8 "MWDATAH,Controller Write Data Half-word Register"
bitfld.long 0x8 16. "END,End of message" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "DATA1,Data byte 1"
newline
hexmask.long.byte 0x8 0.--7. 1. "DATA0,Data byte 0"
line.long 0xC "MWDATAHE,Controller Write Data Halfword End"
hexmask.long.byte 0xC 8.--15. 1. "DATA1,DATA 1"
hexmask.long.byte 0xC 0.--7. 1. "DATA0,DATA 0"
rgroup.long 0xC0++0x3
line.long 0x0 "MRDATAB,Controller Read Data Byte Register"
hexmask.long.byte 0x0 0.--7. 1. "VALUE,VALUE"
rgroup.long 0xC8++0x7
line.long 0x0 "MRDATAH,Controller Read Data Half-word Register"
hexmask.long.byte 0x0 8.--15. 1. "MSB,MSB"
hexmask.long.byte 0x0 0.--7. 1. "LSB,LSB"
line.long 0x4 "MWDATAB1,Controller Write Byte Data 1"
hexmask.long.byte 0x4 0.--7. 1. "VALUE,VALUE"
wgroup.long 0xD0++0x3
line.long 0x0 "MWMSG_SDR_CONTROL,Controller Write Message in SDR mode"
hexmask.long.byte 0x0 11.--15. 1. "LEN,Length"
bitfld.long 0x0 10. "I2C,I2C" "0: I3C message,1: I2C message"
newline
bitfld.long 0x0 8. "END,End of SDR message" "0: Not the end. SDR message ends waiting for a new..,1: End. SDR message ends at the STOP."
hexmask.long.byte 0x0 1.--7. 1. "ADDR,Contains address to be written."
newline
bitfld.long 0x0 0. "DIR,Direction" "0: Write,1: Read"
wgroup.long 0xD0++0x3
line.long 0x0 "MWMSG_SDR_DATA,Controller Write Message Data in SDR mode"
hexmask.long.word 0x0 0.--15. 1. "DATA16B,Data"
rgroup.long 0xD4++0x3
line.long 0x0 "MRMSG_SDR,Controller Read Message in SDR mode"
hexmask.long.word 0x0 0.--15. 1. "DATA,Data"
wgroup.long 0xD8++0x3
line.long 0x0 "MWMSG_DDR_CONTROL,Controller Write Message in DDR mode: First Control Word"
hexmask.long.word 0x0 0.--15. 1. "ADDRCMD,Address Command"
wgroup.long 0xD8++0x3
line.long 0x0 "MWMSG_DDR_DATA,Controller Write Message Data in DDR mode"
hexmask.long.word 0x0 0.--15. 1. "DATA16B,Data"
group.long 0xDC++0x3
line.long 0x0 "MRMSG_DDR,Controller Read Message in DDR mode"
hexmask.long.word 0x0 0.--15. 1. "DATA,Data"
group.long 0xE4++0x3
line.long 0x0 "MDYNADDR,Controller Dynamic Address"
hexmask.long.byte 0x0 1.--7. 1. "DADDR,Dynamic address"
bitfld.long 0x0 0. "DAVALID,Dynamic address valid" "0: No valid DA assigned,1: Valid DA assigned"
rgroup.long 0x11C++0x3
line.long 0x0 "SMAPCTRL0,Map Feature Control 0"
bitfld.long 0x0 8.--10. "CAUSE,Cause" "0: No information. This value occurs when not..,1: Set using ENTDAA,2: Set using SETDASA SETAASA or SETNEWDA,3: Cleared using RSTDAA,4: Auto MAP change happened last. The change may..,?,?,?"
hexmask.long.byte 0x0 1.--7. 1. "DA,Dynamic Address"
newline
bitfld.long 0x0 0. "ENA,Enable Primary Dynamic Address" "0: Disable,1: Enable"
rgroup.long 0xFFC++0x3
line.long 0x0 "SID,Slave Module ID Register"
hexmask.long 0x0 0.--31. 1. "ID,ID"
tree.end
tree "INPUTMUX (Input Multiplexing)"
base ad:0x4002C000
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "DMA_INMUX_INMUX[$1],DMA output trigger selection to become DMA trigger"
hexmask.long.byte 0x0 0.--4. 1. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 15)."
repeat.end
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "FTM0_INMUX[$1],input select register for FTM0"
hexmask.long.byte 0x0 0.--3. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = GPIO_INT4; 1 = GPIO_INT5; 2 = GPIO_INT6; 3 = GPIO_INT7; 4= ADC0_SEQA_IRQ; 5 = ADC0_SEQB_IRQ; 6 = COMP0_OUT; 7 = FTM0_INIT_TRIG ORed with FTM0_EXT_TRIG; 8 = FTM1_INIT_TRIG ORed.."
repeat.end
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--3. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = GPIO_INT4; 1 = GPIO_INT5; 2 = GPIO_INT6; 3 = GPIO_INT7; 4= ADC0_SEQA_IRQ; 5 = ADC0_SEQB_IRQ; 6 = COMP0_OUT; 7 = FTM0_INIT_TRIG ORed with FTM0_EXT_TRIG; 8 = FTM1_INIT_TRIG ORed.."
repeat.end
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xA0)++0x3
line.long 0x0 "FTM1_INMUX[$1],input select register for FTM1 input"
hexmask.long.byte 0x0 0.--3. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = GPIO_INT4; 1 = GPIO_INT5; 2 = GPIO_INT6; 3 = GPIO_INT7; 4= ADC0_SEQA_IRQ; 5 = ADC0_SEQB_IRQ; 6 = COMP0_OUT; 7 = FTM0_INIT_TRIG ORed with FTM0_EXT_TRIG; 8 = FTM1_INIT_TRIG ORed.."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xC0)++0x3
line.long 0x0 "FTM0_FLT_INMUX[$1],input select register for FTM0 FAULT"
hexmask.long.byte 0x0 0.--3. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = GPIO_INT4; 1 = GPIO_INT5; 2 = GPIO_INT6; 3 = GPIO_INT7; 4= ADC0_SEQA_IRQ; 5 = ADC0_SEQB_IRQ; 6 = COMP0_OUT; 7 = FTM0_INIT_TRIG ORed with FTM0_EXT_TRIG; 8 = FTM1_INIT_TRIG ORed.."
repeat.end
tree.end
tree "IOCON (I/O Configuration)"
base ad:0x40044000
group.long 0x0++0x2F
line.long 0x0 "PIO0_17,Digital I/O control for pins PIO0_17"
bitfld.long 0x0 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x0 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x0 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x0 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x0 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x4 "PIO0_13,Digital I/O control for pins PIO0_13"
bitfld.long 0x4 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x4 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x4 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x4 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x4 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x8 "PIO0_12,Digital I/O control for pins PIO0_12"
bitfld.long 0x8 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x8 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x8 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x8 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x8 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0xC "PIO0_5,Digital I/O control for pins PIO0_5"
bitfld.long 0xC 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0xC 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0xC 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0xC 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0xC 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x10 "PIO0_4,Digital I/O control for pins PIO0_4"
bitfld.long 0x10 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x10 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x10 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x10 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x10 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x14 "PIO0_3,Digital I/O control for pins PIO0_3"
bitfld.long 0x14 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x14 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x14 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x14 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x14 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x18 "PIO0_2,Digital I/O control for pins PIO0_2"
bitfld.long 0x18 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x18 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x18 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x18 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x18 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x18 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x1C "PIO0_11,Digital I/O control for pins PIO0_11"
bitfld.long 0x1C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x1C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x1C 8.--9. "I2CMODE,Selects I2C mode." "0: Standard mode/ Fast-mode I2C.,1: Standard GPIO functionality. Requires external..,2: Fast-mode Plus I2C,?"
bitfld.long 0x1C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
line.long 0x20 "PIO0_10,Digital I/O control for pins PIO0_10"
bitfld.long 0x20 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x20 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x20 8.--9. "I2CMODE,Selects I2C mode." "0: Standard mode/ Fast-mode I2C.,1: Standard GPIO functionality. Requires external..,2: Fast-mode Plus I2C,?"
bitfld.long 0x20 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
line.long 0x24 "PIO0_16,Digital I/O control for pins PIO0_16"
bitfld.long 0x24 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x24 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x24 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x24 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x24 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x24 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x28 "PIO0_15,Digital I/O control for pins PIO0_15"
bitfld.long 0x28 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x28 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x28 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x28 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x28 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x28 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x2C "PIO0_1,Digital I/O control for pins PIO0_1"
bitfld.long 0x2C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x2C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x2C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x2C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x2C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x2C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
group.long 0x34++0x17
line.long 0x0 "PIO0_9,Digital I/O control for pins PIO0_9"
bitfld.long 0x0 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x0 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x0 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x0 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x0 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x4 "PIO0_8,Digital I/O control for pins PIO0_8"
bitfld.long 0x4 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x4 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x4 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x4 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x4 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x8 "PIO0_7,Digital I/O control for pins PIO0_7"
bitfld.long 0x8 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x8 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x8 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x8 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x8 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0xC "PIO0_6,Digital I/O control for pins PIO0_6"
bitfld.long 0xC 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0xC 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0xC 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0xC 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0xC 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x10 "PIO0_0,Digital I/O control for pins PIO0_0"
bitfld.long 0x10 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x10 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x10 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x10 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x10 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x14 "PIO0_14,Digital I/O control for pins PIO0_14"
bitfld.long 0x14 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x14 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x14 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x14 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x14 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
group.long 0x50++0x8F
line.long 0x0 "PIO0_28,Digital I/O control for pins PIO0_28"
bitfld.long 0x0 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x0 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x0 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x0 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x0 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x4 "PIO0_27,Digital I/O control for pins PIO0_27"
bitfld.long 0x4 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x4 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x4 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x4 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x4 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x8 "PIO0_26,Digital I/O control for pins PIO0_26"
bitfld.long 0x8 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x8 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x8 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x8 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x8 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0xC "PIO0_25,Digital I/O control for pins PIO0_25"
bitfld.long 0xC 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0xC 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0xC 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0xC 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0xC 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x10 "PIO0_24,Digital I/O control for pins PIO0_24"
bitfld.long 0x10 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x10 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x10 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x10 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x10 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x14 "PIO0_23,Digital I/O control for pins PIO0_23"
bitfld.long 0x14 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x14 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x14 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x14 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x14 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x18 "PIO0_22,Digital I/O control for pins PIO0_22"
bitfld.long 0x18 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x18 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x18 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x18 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x18 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x18 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x1C "PIO0_21,Digital I/O control for pins PIO0_21"
bitfld.long 0x1C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x1C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x1C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x1C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x1C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x1C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x20 "PIO0_20,Digital I/O control for pins PIO0_20"
bitfld.long 0x20 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x20 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x20 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x20 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x20 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x20 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x24 "PIO0_19,Digital I/O control for pins PIO0_19"
bitfld.long 0x24 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x24 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x24 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x24 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x24 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x24 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x28 "PIO0_18,Digital I/O control for pins PIO0_18"
bitfld.long 0x28 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x28 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x28 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x28 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x28 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x28 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x2C "PIO1_8,Digital I/O control for pins PIO1_8"
bitfld.long 0x2C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x2C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x2C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x2C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x2C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x2C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x30 "PIO1_9,Digital I/O control for pins PIO1_9"
bitfld.long 0x30 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x30 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x30 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x30 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x30 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x30 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x34 "PIO1_12,Digital I/O control for pins PIO1_12"
bitfld.long 0x34 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x34 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x34 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x34 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x34 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x34 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x38 "PIO1_13,Digital I/O control for pins PIO1_13"
bitfld.long 0x38 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x38 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x38 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x38 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x38 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x38 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x3C "PIO0_31,Digital I/O control for pins PIO0_31"
bitfld.long 0x3C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x3C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x3C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x3C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x3C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x3C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x40 "PIO1_0,Digital I/O control for pins PIO1_0"
bitfld.long 0x40 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x40 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x40 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x40 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x40 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x40 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x44 "PIO1_1,Digital I/O control for pins PIO1_1"
bitfld.long 0x44 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x44 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x44 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x44 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x44 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x44 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x48 "PIO1_2,Digital I/O control for pins PIO1_2"
bitfld.long 0x48 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x48 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x48 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x48 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x48 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x48 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x4C "PIO1_14,Digital I/O control for pins PIO1_14"
bitfld.long 0x4C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x4C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x4C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x4C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x4C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x4C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x50 "PIO1_15,Digital I/O control for pins PIO1_15"
bitfld.long 0x50 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x50 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x50 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x50 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x50 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x50 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x54 "PIO1_3,Digital I/O control for pins PIO1_3"
bitfld.long 0x54 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x54 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x54 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x54 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x54 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x54 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x58 "PIO1_4,Digital I/O control for pins PIO1_4"
bitfld.long 0x58 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x58 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x58 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x58 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x58 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x58 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x5C "PIO1_5,Digital I/O control for pins PIO1_5"
bitfld.long 0x5C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x5C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x5C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x5C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x5C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x5C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x60 "PIO1_16,Digital I/O control for pins PIO1_16"
bitfld.long 0x60 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x60 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x60 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x60 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x60 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x60 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x64 "PIO1_17,Digital I/O control for pins PIO1_17"
bitfld.long 0x64 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x64 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x64 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x64 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x64 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x64 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x68 "PIO1_6,Digital I/O control for pins PIO1_6"
bitfld.long 0x68 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x68 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x68 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x68 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x68 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x68 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x6C "PIO1_18,Digital I/O control for pins PIO1_18"
bitfld.long 0x6C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x6C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x6C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x6C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x6C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x6C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x70 "PIO1_19,Digital I/O control for pins PIO1_19"
bitfld.long 0x70 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x70 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x70 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x70 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x70 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x70 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x74 "PIO1_7,Digital I/O control for pins PIO1_7"
bitfld.long 0x74 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x74 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x74 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x74 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x74 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x74 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x78 "PIO0_29,Digital I/O control for pins PIO0_29"
bitfld.long 0x78 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x78 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x78 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x78 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x78 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x78 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x7C "PIO0_30,Digital I/O control for pins PIO0_30"
bitfld.long 0x7C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x7C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x7C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x7C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x7C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x7C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x80 "PIO1_20,Digital I/O control for pins PIO1_20"
bitfld.long 0x80 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x80 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x80 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x80 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x80 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x80 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x84 "PIO1_21,Digital I/O control for pins PIO1_21"
bitfld.long 0x84 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x84 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x84 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x84 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
newline
bitfld.long 0x84 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x84 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x88 "PIO1_11,Digital I/O control for pins PIO1_11"
bitfld.long 0x88 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x88 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
newline
bitfld.long 0x88 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x88 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
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bitfld.long 0x88 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x88 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
line.long 0x8C "PIO1_10,Digital I/O control for pins PIO1_10"
bitfld.long 0x8C 13.--15. "CLK_DIV,Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved." "0: IOCONCLKDIV0,1: IOCONCLKDIV1,2: IOCONCLKDIV2,3: IOCONCLKDIV3,4: IOCONCLKDIV4,5: IOCONCLKDIV5,6: IOCONCLKDIV6,?"
bitfld.long 0x8C 11.--12. "S_MODE,Digital filter sample mode." "0: Bypass input filter.,1: 1 clock cycle. Input pulses shorter than one..,2: 2 clock cycles. Input pulses shorter than two..,3: 3 clock cycles. Input pulses shorter than three.."
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bitfld.long 0x8C 10. "OD,Open-drain mode." "0: Disable.,1: Open-drain mode enabled. Remark: This is not a.."
bitfld.long 0x8C 6. "INV,Invert input" "0: Input not inverted (HIGH on pin reads as 1; LOW..,1: Input inverted (HIGH on pin reads as 0 LOW on.."
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bitfld.long 0x8C 5. "HYS,Hysteresis." "0: Disable,1: Enable"
bitfld.long 0x8C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
tree.end
tree "MRT (Multi-Rate Timer)"
base ad:0x40004000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40004000 ad:0x40004010 ad:0x40004020 ad:0x40004030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long 0x0 0.--30. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long 0x0 0.--30. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x40004000
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
tree "PINT (Pin Interrupt Registers)"
base ad:0xA0004000
group.long 0x0++0x7
line.long 0x0 "ISEL,Pin Interrupt Mode register"
hexmask.long.byte 0x0 0.--7. 1. "PMODE,Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"
line.long 0x4 "IENR,Pin interrupt level or rising edge interrupt enable register"
hexmask.long.byte 0x4 0.--7. 1. "ENRL,Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."
wgroup.long 0x8++0x7
line.long 0x0 "SIENR,Pin interrupt level or rising edge interrupt set register"
hexmask.long.byte 0x0 0.--7. 1. "SETENRL,Ones written to this address set bits in the IENR thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt."
line.long 0x4 "CIENR,Pin interrupt level (rising edge interrupt) clear register"
hexmask.long.byte 0x4 0.--7. 1. "CENRL,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."
group.long 0x10++0x3
line.long 0x0 "IENF,Pin interrupt active level or falling edge interrupt enable register"
hexmask.long.byte 0x0 0.--7. 1. "ENAF,Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge.."
wgroup.long 0x14++0x7
line.long 0x0 "SIENF,Pin interrupt active level or falling edge interrupt set register"
hexmask.long.byte 0x0 0.--7. 1. "SETENAF,Ones written to this address set bits in the IENF thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."
line.long 0x4 "CIENF,Pin interrupt active level or falling edge interrupt clear register"
hexmask.long.byte 0x4 0.--7. 1. "CENAF,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."
group.long 0x1C++0x17
line.long 0x0 "RISE,Pin interrupt rising edge register"
hexmask.long.byte 0x0 0.--7. 1. "RDET,Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been.."
line.long 0x4 "FALL,Pin interrupt falling edge register"
hexmask.long.byte 0x4 0.--7. 1. "FDET,Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has.."
line.long 0x8 "IST,Pin interrupt status register"
hexmask.long.byte 0x8 0.--7. 1. "PSTAT,Pin interrupt status. Bit n returns the status clears the edge interrupt or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is.."
line.long 0xC "PMCTRL,Pattern match interrupt control register"
hexmask.long.byte 0xC 24.--31. 1. "PMAT,This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs."
bitfld.long 0xC 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true." "0: Disabled. RXEV output to the CPU is disabled.,1: Enabled. RXEV output to the CPU is enabled."
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bitfld.long 0xC 0. "SEL_PMATCH,Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function." "0: Pin interrupt. Interrupts are driven in response..,1: Pattern match. Interrupts are driven in response.."
line.long 0x10 "PMSRC,Pattern match interrupt bit-slice source register"
bitfld.long 0x10 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
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bitfld.long 0x10 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
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bitfld.long 0x10 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
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bitfld.long 0x10 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
line.long 0x14 "PMCFG,Pattern match interrupt bit slice configuration register"
bitfld.long 0x14 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
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bitfld.long 0x14 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
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bitfld.long 0x14 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
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bitfld.long 0x14 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
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bitfld.long 0x14 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint." "0: No effect. Slice 6 is not an endpoint.,1: endpoint. Slice 6 is the endpoint of a product.."
bitfld.long 0x14 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint." "0: No effect. Slice 5 is not an endpoint.,1: endpoint. Slice 5 is the endpoint of a product.."
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bitfld.long 0x14 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint." "0: No effect. Slice 4 is not an endpoint.,1: endpoint. Slice 4 is the endpoint of a product.."
bitfld.long 0x14 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint." "0: No effect. Slice 3 is not an endpoint.,1: endpoint. Slice 3 is the endpoint of a product.."
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bitfld.long 0x14 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint." "0: No effect. Slice 2 is not an endpoint.,1: endpoint. Slice 2 is the endpoint of a product.."
bitfld.long 0x14 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint." "0: No effect. Slice 1 is not an endpoint.,1: endpoint. Slice 1 is the endpoint of a product.."
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bitfld.long 0x14 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint." "0: No effect. Slice 0 is not an endpoint.,1: endpoint. Slice 0 is the endpoint of a product.."
tree.end
tree "PMU (Reduced Power Modes and Power Management)"
base ad:0x40020000
group.long 0x0++0x3
line.long 0x0 "PCON,Power control register"
bitfld.long 0x0 11. "DPDFLAG,Deep power-down flag" "0: Not Deep power-down. Read: Deep power-down mode..,1: Deep power-down. Read: Deep power-down mode.."
bitfld.long 0x0 8. "SLEEPFLAG,Sleep mode flag" "0: Active mode. Read: No power-down mode entered.,1: Low power mode. Read: Sleep Deep-sleep or.."
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bitfld.long 0x0 3. "NODPD,A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above the SLEEPDEEP bit is set and a WFI is executed. This bit is cleared only by power-on reset so writing a one to this bit locks the part in a mode in.." "0,1"
bitfld.long 0x0 0.--2. "PM,Power mode" "0: Default. The part is in active or sleep mode.,1: Deep-sleep mode. ARM WFI will enter Deep-sleep..,2: Power-down mode. ARM WFI will enter Power-down..,3: Deep power-down mode. ARM WFI will enter..,?,?,?,?"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4)++0x3
line.long 0x0 "GPREG[$1],General purpose register N"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode."
repeat.end
group.long 0x14++0x3
line.long 0x0 "DPDCTRL,Deep power-down control register. Also includes bits for general purpose storage."
hexmask.long.tbyte 0x0 8.--31. 1. "GPDATA,Data retained during Deep power-down mode."
bitfld.long 0x0 7. "RESET_DISABLE,RESET pin disable. Setting this bit disables the reset wake-up function so the pin can be used for other purposes. Remark: Setting this bit is not necessary if deep power-down mode is not used." "0: Enabled. The reset wake-up function is enabled..,1: Disabled. Setting this bit disables the wake-up.."
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bitfld.long 0x0 6. "RESETHYS,RESET pin hysteresis enable." "0: Disabled. Hysteresis for RESET pin disabled.,1: Enabled. Hysteresis for RESET pin enabled."
bitfld.long 0x0 5. "WAKECLKPAD_DISABLE,Disable the external clock input for the self-wake-up timer. Setting this bit enables the self-wake-up timer clock pin WKTCLKLIN. To minimize power consumption especially in deep power-down mode disable this clock input when not.." "0: Disabled. Setting this bit disables external..,1: Enabled. The external clock input for the self.."
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bitfld.long 0x0 4. "WAKEUPCLKHYS,External clock input for the self wake-up timer WKTCLKIN hysteresis enable." "0: Disabled. Hysteresis for WAKEUP clock pin..,1: Enabled. Hysteresis for WAKEUP clock pin enabled."
bitfld.long 0x0 3. "ULPOSCDPDEN,causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode." "0: Disabled.,1: Enabled."
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bitfld.long 0x0 2. "ULPOSCEN,Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by.." "0: Disabled.,1: Enabled."
bitfld.long 0x0 1. "WAKEPAD_DISABLE,WAKEUP pin disable. Setting this bit disables the wake-up pin so it can be used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin.." "0: Enabled. The wake-up function is enabled on pin..,1: Disabled. Setting this bit disables the wake-up.."
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bitfld.long 0x0 0. "WAKEUPHYS,WAKEUP pin hysteresis enable" "0: Disabled. Hysteresis for WAKEUP pin disabled.,1: Enabled. Hysteresis for WAKEUP pin enabled."
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI0"
base ad:0x40058000
group.long 0x0++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position"
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy and allows waking up the device from.." "0,1"
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
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bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs the receiver buffer contents are.." "0,1"
rbitfld.long 0x8 1. "TXRDY,Transmitter Ready flag. When 1 this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the.." "0,1"
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rbitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1 indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 5. "SSDEN,Determines whether an interrupt occurs when the Slave Select is deasserted." "0: No interrupt will be generated when all asserted..,1: An interrupt will be generated when all asserted.."
bitfld.long 0xC 4. "SSAEN,Determines whether an interrupt occurs when the Slave Select is asserted." "0: No interrupt will be generated when any Slave..,1: An interrupt will be generated when any Slave.."
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bitfld.long 0xC 3. "TXUREN,Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0: No interrupt will be generated when the..,1: An interrupt will be generated if the.."
bitfld.long 0xC 2. "RXOVEN,Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver.." "0: No interrupt will be generated when a receiver..,1: An interrupt will be generated if a receiver.."
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bitfld.long 0xC 1. "TXRDYEN,Determines whether an interrupt occurs when the transmitter holding register is available." "0: No interrupt will be generated when the..,1: An interrupt will be generated when data may be.."
bitfld.long 0xC 0. "RXRDYEN,Determines whether an interrupt occurs when receiver data is available." "0: No interrupt will be generated when receiver..,1: An interrupt will be generated when receiver.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXUREN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x0 2. "RXOVEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x0 1. "TXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x0 0. "RXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "RXDAT,SPI Receive Data"
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e. any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
group.long 0x18++0xF
line.long 0x0 "TXDATCTL,SPI Transmit Data with Control"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0: Received data must be read in order to allow..,1: Received data is ignored allowing transmission.."
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bitfld.long 0x0 21. "EOF,End of Frame. Between frames a delay may be inserted as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: This piece of data transmitted is not treated as..,1: This piece of data is treated as the end of a.."
bitfld.long 0x0 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: This piece of data is not treated as the end of..,1: This piece of data is treated as the end of a.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
line.long 0x4 "TXDAT,SPI Transmit Data."
hexmask.long.word 0x4 0.--15. 1. "DATA,Transmit Data. This field provides from 4 to 16 bits of data to be transmitted."
line.long 0x8 "TXCTL,SPI Transmit Control"
hexmask.long.byte 0x8 24.--27. 1. "LEN,Data transfer Length."
bitfld.long 0x8 22. "RXIGNORE,Receive Ignore." "0,1"
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bitfld.long 0x8 21. "EOF,End of Frame." "0,1"
bitfld.long 0x8 20. "EOT,End of Transfer." "0,1"
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bitfld.long 0x8 19. "TXSSEL3_N,Transmit Slave Select 3." "0,1"
bitfld.long 0x8 18. "TXSSEL2_N,Transmit Slave Select 2." "0,1"
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bitfld.long 0x8 17. "TXSSEL1_N,Transmit Slave Select 1." "0,1"
bitfld.long 0x8 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
line.long 0xC "DIV,SPI clock Divider"
hexmask.long.word 0xC 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1 the value 1 results in FCLK/2 up to the maximum possible divide.."
rgroup.long 0x28++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
bitfld.long 0x0 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
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bitfld.long 0x0 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
bitfld.long 0x0 1. "TXRDY,Transmitter Ready flag." "0,1"
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bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
tree.end
tree "SPI1"
base ad:0x4005C000
group.long 0x0++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position"
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy and allows waking up the device from.." "0,1"
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
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bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs the receiver buffer contents are.." "0,1"
rbitfld.long 0x8 1. "TXRDY,Transmitter Ready flag. When 1 this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the.." "0,1"
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rbitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1 indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 5. "SSDEN,Determines whether an interrupt occurs when the Slave Select is deasserted." "0: No interrupt will be generated when all asserted..,1: An interrupt will be generated when all asserted.."
bitfld.long 0xC 4. "SSAEN,Determines whether an interrupt occurs when the Slave Select is asserted." "0: No interrupt will be generated when any Slave..,1: An interrupt will be generated when any Slave.."
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bitfld.long 0xC 3. "TXUREN,Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0: No interrupt will be generated when the..,1: An interrupt will be generated if the.."
bitfld.long 0xC 2. "RXOVEN,Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver.." "0: No interrupt will be generated when a receiver..,1: An interrupt will be generated if a receiver.."
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bitfld.long 0xC 1. "TXRDYEN,Determines whether an interrupt occurs when the transmitter holding register is available." "0: No interrupt will be generated when the..,1: An interrupt will be generated when data may be.."
bitfld.long 0xC 0. "RXRDYEN,Determines whether an interrupt occurs when receiver data is available." "0: No interrupt will be generated when receiver..,1: An interrupt will be generated when receiver.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXUREN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x0 2. "RXOVEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x0 1. "TXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x0 0. "RXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "RXDAT,SPI Receive Data"
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e. any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
group.long 0x18++0xF
line.long 0x0 "TXDATCTL,SPI Transmit Data with Control"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0: Received data must be read in order to allow..,1: Received data is ignored allowing transmission.."
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bitfld.long 0x0 21. "EOF,End of Frame. Between frames a delay may be inserted as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: This piece of data transmitted is not treated as..,1: This piece of data is treated as the end of a.."
bitfld.long 0x0 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: This piece of data is not treated as the end of..,1: This piece of data is treated as the end of a.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
line.long 0x4 "TXDAT,SPI Transmit Data."
hexmask.long.word 0x4 0.--15. 1. "DATA,Transmit Data. This field provides from 4 to 16 bits of data to be transmitted."
line.long 0x8 "TXCTL,SPI Transmit Control"
hexmask.long.byte 0x8 24.--27. 1. "LEN,Data transfer Length."
bitfld.long 0x8 22. "RXIGNORE,Receive Ignore." "0,1"
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bitfld.long 0x8 21. "EOF,End of Frame." "0,1"
bitfld.long 0x8 20. "EOT,End of Transfer." "0,1"
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bitfld.long 0x8 19. "TXSSEL3_N,Transmit Slave Select 3." "0,1"
bitfld.long 0x8 18. "TXSSEL2_N,Transmit Slave Select 2." "0,1"
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bitfld.long 0x8 17. "TXSSEL1_N,Transmit Slave Select 1." "0,1"
bitfld.long 0x8 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
line.long 0xC "DIV,SPI clock Divider"
hexmask.long.word 0xC 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1 the value 1 results in FCLK/2 up to the maximum possible divide.."
rgroup.long 0x28++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
bitfld.long 0x0 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
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bitfld.long 0x0 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
bitfld.long 0x0 1. "TXRDY,Transmitter Ready flag." "0,1"
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bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
tree.end
tree.end
tree "SWM (Switch Matrix)"
base ad:0x4000C000
group.long 0x0++0x3
line.long 0x0 "PINASSIGN0,Pin assign register 0. Assign movable functions U0_TXD. U0_RXD. U0_RTS. U0_CTS."
hexmask.long.byte 0x0 24.--31. 1. "U0_CTS_I,U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "U0_RTS_O,U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "U0_RXD_I,U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "U0_TXD_O,U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35) ."
group.long 0x0++0x7
line.long 0x0 "PINASSIGN_DATA0,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN1,Pin assign register 1. Assign movable functions U0_SCLK. U1_TXD. U1_RXD. U1_RTS."
hexmask.long.byte 0x4 24.--31. 1. "U1_RTS_O,U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "U1_RXD_I,U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "U1_TXD_O,U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "U0_SCLK_IO,U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x4++0x7
line.long 0x0 "PINASSIGN_DATA1,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN2,Pin assign register 2. Assign movable functions U1_CTS. U1_SCLK. U2_TXD. U2_RXD."
hexmask.long.byte 0x4 24.--31. 1. "U2_RXD_I,U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "U2_TXD_O,U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "U1_SCLK_IO,U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "U1_CTS_I,U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x8++0x7
line.long 0x0 "PINASSIGN_DATA2,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN3,Pin assign register 3. Assign movable function U2_RTS. U2_CTS. U2_SCLK. SPI0_SCK."
hexmask.long.byte 0x4 24.--31. 1. "SPI0_SCK_IO,SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "U2_SCLK_IO,U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "U2_CTS_I,U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "U2_RTS_O,U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0xC++0x7
line.long 0x0 "PINASSIGN_DATA3,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN4,Pin assign register 4. Assign movable functions SPI0_MOSI. SPI0_MISO. SPI0_SSEL0. SPI0_SSEL1."
hexmask.long.byte 0x4 24.--31. 1. "SPI0_SSEL1_IO,SPI0_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "SPI0_SSEL0_IO,SPI0_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "SPI0_MISO_IO,SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "SPI0_MOSI_IO,SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x10++0x7
line.long 0x0 "PINASSIGN_DATA4,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN5,Pin assign register 5. Assign movable functions SPI0_SSEL2. SPI0_SSEL3. SPI1_SCK. SPI1_MOSI"
hexmask.long.byte 0x4 24.--31. 1. "SPI1_MOSI_IO,SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "SPI1_SCK_IO,SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "SPI0_SSEL3_IO,SPI0_SSEL3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "SPI0_SSEL2_IO,SPI0_SSEL2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x14++0x7
line.long 0x0 "PINASSIGN_DATA5,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN6,Pin assign register 6. Assign movable functions SPI1_MISO. SPI1_SSEL0. SPI1_SSEL1. SCT0_IN0."
hexmask.long.byte 0x4 24.--31. 1. "I2C0_SDA_IO,I2C0_SDA_IO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "SPI1_SSEL1_IO,SPI1_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "SPI1_SSEL0_IO,SPI1_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "SPI1_MISO_IO,SPI1_MISO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x18++0x7
line.long 0x0 "PINASSIGN_DATA6,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN7,Pin assign register 7. Assign movable functions SCT_IN1. SCT_IN2. SCT_IN3. SCT_OUT0."
hexmask.long.byte 0x4 24.--31. 1. "I3C0_PUR_IO,I3C0_PUR_IO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 16.--23. 1. "I3C0_SCL_IO,I3C0_SCL_IO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 8.--15. 1. "I3C0_SDA_IO,I3C0_SDA_IO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 0.--7. 1. "I2C0_SCL_IO,I2C0_SCL_IO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x1C++0x7
line.long 0x0 "PINASSIGN_DATA7,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
line.long 0x4 "PINASSIGN8,Pin assign register 8. Assign movable functions ACMP0_OUT. CLKOUT. GPIOINT_BMATCH."
hexmask.long.byte 0x4 16.--23. 1. "GPIO_INT_BMAT_O,GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x4 8.--15. 1. "CLKOUT_O,CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x4 0.--7. 1. "ACMP0_OUT_O,ACMP0_OUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x20++0x3
line.long 0x0 "PINASSIGN_DATA8,Pin assign register"
hexmask.long.byte 0x0 24.--31. 1. "DATA3,T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 16.--23. 1. "DATA2,T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
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hexmask.long.byte 0x0 8.--15. 1. "DATA1,T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
hexmask.long.byte 0x0 0.--7. 1. "DATA0,T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35)."
group.long 0x180++0x7
line.long 0x0 "FTM_PINASSIGN0,FlexTimer Pin assign register 0 Assign movable functions."
bitfld.long 0x0 30.--31. "FTM1_CH3,Assign movable function FTM1_CH3" "0,1,2,3"
bitfld.long 0x0 28.--29. "FTM1_CH2,Assign movable function FTM1_CH2" "0,1,2,3"
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bitfld.long 0x0 26.--27. "FTM1_CH1,Assign movable function FTM1_CH1" "0,1,2,3"
bitfld.long 0x0 24.--25. "FTM1_CH0,Assign movable function FTM1_CH0" "0,1,2,3"
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bitfld.long 0x0 22.--23. "FTM1_EXTCLK,Assign movable function FTM1_EXTCLK" "0,1,2,3"
bitfld.long 0x0 20.--21. "FTM0_FAULT3,Assign movable function FTM0_FAULT3" "0,1,2,3"
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bitfld.long 0x0 18.--19. "FTM0_FAULT2,Assign movable function FTM0_FAULT2" "0,1,2,3"
bitfld.long 0x0 16.--17. "FTM0_FAULT1,Assign movable function FTM0_FAULT1" "0,1,2,3"
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bitfld.long 0x0 14.--15. "FTM0_FAULT0,Assign movable function FTM0_FAULT0" "0,1,2,3"
bitfld.long 0x0 12.--13. "FTM0_CH5,Assign movable function FTM0_CH5" "0,1,2,3"
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bitfld.long 0x0 10.--11. "FTM0_CH4,Assign movable function FTM0_CH4" "0,1,2,3"
bitfld.long 0x0 8.--9. "FTM0_CH3,Assign movable function FTM0_CH3" "0,1,2,3"
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bitfld.long 0x0 6.--7. "FTM0_CH2,Assign movable function FTM0_CH2" "0,1,2,3"
bitfld.long 0x0 4.--5. "FTM0_CH1,Assign movable function FTM0_CH1" "0,1,2,3"
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bitfld.long 0x0 2.--3. "FTM0_CH0,Assign movable function FTM0_CH0" "0,1,2,3"
bitfld.long 0x0 0.--1. "FTM0_EXTCLK,Assign movable function FTM0_EXTCLK 00 = Selection 0 function pins 01 = Selection 1 function pins 10 = Selection 2 function pins 11 = Selection 3 function pins" "0: Selection 0 function pins,1: Selection 1 function pins,?,?"
line.long 0x4 "FTM_PINASSIGN1,FlexTimer Pin assign register 0 Assign movable functions."
bitfld.long 0x4 2.--3. "FTM1_QD_PHB,Assign movable function FTM1_QD_PHB" "0,1,2,3"
bitfld.long 0x4 0.--1. "FTM1_QD_PHA,Assign movable function FTM1_QD_PHA" "0,1,2,3"
group.long 0x1C0++0x3
line.long 0x0 "PINENABLE0,Pin enable register 0. Enables fixed-pin functions ACMP_I0. ACMP_I1. SWCLK. SWDIO. XTALIN. XTALOUT. RESET. CLKIN. VDDCMP and so on."
bitfld.long 0x0 23. "ADC_11,ADC_11 function select." "0: ADC_11 enabled on pin PIO0_4.,1: ADC_11 disabled."
bitfld.long 0x0 22. "ADC_10,ADC_10 function select." "0: ADC_10 enabled on pin PIO0_13.,1: ADC_10 disabled."
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bitfld.long 0x0 21. "ADC_9,ADC_9 function select." "0: ADC_9 enabled on pin PIO0_17.,1: ADC_9 disabled."
bitfld.long 0x0 20. "ADC_8,ADC_8 function select." "0: ADC_8 enabled on pin PIO0_18.,1: ADC_8 disabled."
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bitfld.long 0x0 19. "ADC_7,ADC_7 function select." "0: ADC_7 enabled on pin PIO0_19.,1: ADC_7 disabled."
bitfld.long 0x0 18. "ADC_6,ADC_6 function select." "0: ADC_6 enabled on pin PIO0_20.,1: ADC_6 disabled."
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bitfld.long 0x0 17. "ADC_5,ADC_5 function select." "0: ADC_5 enabled on pin PIO0_21.,1: ADC_5 disabled."
bitfld.long 0x0 16. "ADC_4,ADC_4 function select." "0: ADC_4 enabled on pin PIO0_22.,1: ADC_4 disabled."
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bitfld.long 0x0 15. "ADC_3,ADC_3 function select." "0: ADC_3 enabled on pin PIO0_23.,1: ADC_3 disabled."
bitfld.long 0x0 14. "ADC_2,ADC_2 function select." "0: ADC_2 enabled on pin PIO0_14.,1: ADC_2 disabled."
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bitfld.long 0x0 13. "ADC_1,ADC_1 function select." "0: ADC_1 enabled on pin PIO0_6.,1: ADC_1 disabled."
bitfld.long 0x0 12. "ADC_0,ADC_0 function select." "0: ADC_0 enabled on pin PIO0_7.,1: ADC_0 disabled."
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bitfld.long 0x0 11. "XTALOUT,XTALOUT function select." "0: XTALOUT enabled on pin PIO0_9.,1: XTALOUT disabled."
bitfld.long 0x0 10. "XTALIN,XTALIN function select." "0: XTALIN enabled on pin PIO0_8.,1: XTALIN disabled."
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bitfld.long 0x0 9. "CMPVREF,CMPVREF function select." "0: CMPVREF enabled on pin PIO0_6.,1: CMPVREF disabled."
bitfld.long 0x0 8. "CLKIN,CLKIN function select." "0: CLKIN enabled on pin PIO0_1.,1: CLKIN disabled."
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bitfld.long 0x0 7. "RESETN,RESETN function select." "0: RESETN enabled on pin PIO0_5.,1: RESETN disabled."
bitfld.long 0x0 6. "SWDIO,SWDIO function select." "0: SWDIO enabled on pin PIO0_2.,1: SWDIO disabled."
newline
bitfld.long 0x0 5. "SWCLK,SWCLK function select." "0: SWCLK enabled on pin PIO0_3.,1: SWCLK disabled."
bitfld.long 0x0 4. "ACMP_I5,ACMP_I5 function select." "0: ACMP_I5 enabled on pin PIO0_30.,1: ACMP_I5 disabled."
newline
bitfld.long 0x0 3. "ACMP_I4,ACMP_I4 function select." "0: ACMP_I4 enabled on pin PIO0_23.,1: ACMP_I4 disabled."
bitfld.long 0x0 2. "ACMP_I3,ACMP_I3 function select." "0: ACMP_I3 enabled on pin PIO0_14.,1: ACMP_I3 disabled."
newline
bitfld.long 0x0 1. "ACMP_I2,ACMP_I2 function select." "0: ACMP_I2 enabled on pin PIO0_1.,1: ACMP_I2 disabled."
bitfld.long 0x0 0. "ACMP_I1,ACMP_I1 function select." "0: ACMP_I1 enabled on pin PIO0_00.,1: ACMP_I1 disabled."
tree.end
tree "SYSCON (System Configuration)"
base ad:0x40048000
group.long 0x0++0x3
line.long 0x0 "SYSMEMREMAP,System Remap register"
bitfld.long 0x0 0.--1. "MAP,System memory remap. Value 0x3 is reserved." "0: Boot Loader Mode. Interrupt vectors are..,1: User RAM Mode. Interrupt vectors are re-mapped..,2: User Flash Mode. Interrupt vectors are not..,?"
group.long 0x8++0x3
line.long 0x0 "SYSPLLCTRL,PLL control"
bitfld.long 0x0 5.--6. "PSEL,Post divider ratio P. The division ratio is 2 x P." "0: P = 1,1: P = 2,2: P = 4,3: P = 8"
newline
hexmask.long.byte 0x0 0.--4. 1. "MSEL,Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32"
rgroup.long 0xC++0x3
line.long 0x0 "SYSPLLSTAT,PLL status"
bitfld.long 0x0 0. "LOCK,PLL0 lock indicator" "0,1"
group.long 0x20++0xB
line.long 0x0 "SYSOSCCTRL,system oscillator control"
bitfld.long 0x0 1. "FREQRANGE,oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1'" "0,1"
newline
bitfld.long 0x0 0. "BYPASS,oscillator (Xtal) Test Mode input (Active High)" "0,1"
line.long 0x4 "LPOSCCTRL,Low power oscillator control"
bitfld.long 0x4 31. "LPOSC_TST_IREF_EN,no description available" "0,1"
newline
bitfld.long 0x4 12.--14. "LPOSC_TRIM_C,no description available" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "LPOSC_TRIM_T,Select low power oscillator analog output frequency(Fclkana)"
newline
hexmask.long.byte 0x4 0.--7. 1. "LPOSC_TRIM,Select divider for Fclkana"
line.long 0x8 "FROOSCCTRL,FRO oscillator control"
bitfld.long 0x8 17. "FRO_DIRECT,fro direct clock select" "0: fro_osc out is divided by 2 (normal boot),1: fro clock is direct from FRO oscillator"
group.long 0x30++0x3
line.long 0x0 "FRODIRECTCLKUEN,FRO direct clock source update enable register"
bitfld.long 0x0 0. "ENA,Enable fro clock source update" "0: no change,1: update clock source"
group.long 0x38++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status." "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x40++0x1F
line.long 0x0 "SYSPLLCLKSEL,System PLL clock source select register"
bitfld.long 0x0 0.--1. "SEL,System PLL clock source" "0: FRO,1: External clock,2: Low power oscillator,3: FRO DIV"
line.long 0x4 "SYSPLLCLKUEN,System PLL clock source update enable register"
bitfld.long 0x4 0. "ENA,Enable system PLL clock source update" "0: no change,1: update clock source"
line.long 0x8 "MAINCLKPLLSEL,Main clock source select register"
bitfld.long 0x8 0.--1. "SEL,System PLL clock source" "0: main_clk_pre_pll,1: sys pll,2: none,3: none"
line.long 0xC "MAINCLKPLLUEN,Main clock source update enable register"
bitfld.long 0xC 0. "ENA,Enable main clock source update" "0: no change,1: update clock source"
line.long 0x10 "MAINCLKSEL,Main clock source select register"
bitfld.long 0x10 0.--1. "SEL,System PLL clock source" "0: FRO,1: External clock,2: Low power oscillator,3: FRO_DIV"
line.long 0x14 "MAINCLKUEN,Main clock source update enable register"
bitfld.long 0x14 0. "ENA,Enable main clock source update" "0: no change,1: update clock source"
line.long 0x18 "SYSAHBCLKDIV,System clock divider register"
hexmask.long.byte 0x18 0.--7. 1. "DIV,System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."
line.long 0x1C "SYSPLLDIV,System clock divider register"
hexmask.long.byte 0x1C 0.--7. 1. "DIV,System PLL clock divider values 0: System PLL clock disabled. 1: Divide by 1. to 255: Divide by 255."
group.long 0x64++0xB
line.long 0x0 "ADCCLKSEL,ADC clock source select register"
bitfld.long 0x0 0.--1. "SEL,Clock source for ADC clock" "0: FRO,1: sys pll,2: none,3: none"
line.long 0x4 "ADCCLKDIV,ADC clock divider register"
hexmask.long.byte 0x4 0.--7. 1. "DIV,ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255."
line.long 0x8 "WKTCLKSEL,ADC clock source select register"
bitfld.long 0x8 0. "SEL,WKT clock source selection" "0: FRO_INT,1: LPOSC"
group.long 0x74++0xF
line.long 0x0 "EXTCLKSEL,external clock source select register"
bitfld.long 0x0 0. "SEL,Clock source for external clock" "0: System oscillator,1: Clk_in"
line.long 0x4 "I3CCLKDIV,I3C clock divider register"
hexmask.long.byte 0x4 16.--23. 1. "I3C_SLOW_CLK_DIV,i3c_slow_clk divider"
newline
hexmask.long.byte 0x4 8.--15. 1. "I3C_SLOW_TC_CLK_DIV,i3c_slow_tc_clk clock divider"
newline
hexmask.long.byte 0x4 0.--7. 1. "I3C_FCLK_DIV,i3c_fclk fast clock divider"
line.long 0x8 "LPOSCEN,LPOSC enable register"
bitfld.long 0x8 1. "WKT_CLK_EN,WDT count clock enable" "0: disable,1: enable"
newline
bitfld.long 0x8 0. "WDT_CLK_EN,WDT count clock enable" "0: disable,1: enable"
line.long 0xC "SYSAHBCLKCTRL0,System clock group 0 control register"
bitfld.long 0xC 29. "DMA,Enables clock for DMA." "0: disable,1: enable"
newline
bitfld.long 0xC 28. "GPIO_INT,Enable clock for GPIO pin interrupt registers" "0: disable,1: enable"
newline
bitfld.long 0xC 24. "ADC,Enables clock for ADC." "0: disable,1: enable"
newline
bitfld.long 0xC 23. "I3C0,Enables clock to I3C." "0: disable,1: enable"
newline
bitfld.long 0xC 22. "FTM1,Enables clock for FTM1." "0: disable,1: enable"
newline
bitfld.long 0xC 21. "FTM0,Enables clock for FTM0." "0: disable,1: enable"
newline
bitfld.long 0xC 20. "GPIO1,Enables clock for GPIO1 port registers." "0: disable,1: enable"
newline
bitfld.long 0xC 19. "ACMP,Enables clock for analog comparator." "0: disable,1: enable"
newline
bitfld.long 0xC 18. "IOCON,Enables clock for IOCON." "0: disable,1: enable"
newline
bitfld.long 0xC 17. "WWDT,Enables clock for WWDT." "0: disable,1: enable"
newline
bitfld.long 0xC 16. "UART2,Enables clock for UART2." "0: disable,1: enable"
newline
bitfld.long 0xC 15. "UART1,Enables clock for UART1." "0: disable,1: enable"
newline
bitfld.long 0xC 14. "UART0,Enables clock for UART0." "0: disable,1: enable"
newline
bitfld.long 0xC 13. "CRC,Enables clock for CRC." "0: disable,1: enable"
newline
bitfld.long 0xC 12. "SPI1,Enables clock for SPI1." "0: disable,1: enable"
newline
bitfld.long 0xC 11. "SPI0,Enables clock for SPI0." "0: disable,1: enable"
newline
bitfld.long 0xC 10. "MRT,Enables clock for multi-rate timer." "0: disable,1: enable"
newline
bitfld.long 0xC 9. "WKT,Enables clock for self-wake-up timer." "0: disable,1: enable"
newline
bitfld.long 0xC 7. "SWM,Enables clock for switch matrix." "0: disable,1: enable"
newline
bitfld.long 0xC 6. "GPIO0,Enables clock for GPIO0 port registers." "0: disable,1: enable"
newline
bitfld.long 0xC 5. "I2C0,Enables clock for I2C0." "0: disable,1: enable"
newline
bitfld.long 0xC 4. "FLASH,Enables clock for flash." "0: disable,1: enable"
newline
bitfld.long 0xC 2. "RAM,Enables clock for SRAM." "0: disable,1: enable"
newline
bitfld.long 0xC 1. "ROM,Enables clock for ROM." "0: disable,1: enable"
newline
bitfld.long 0xC 0. "SYS,Enables the clock for the AHB the APB bridge the Cortex-M0+ core clocks SYSCON and the PMU. This bit is read only and always reads as 1." "0,1"
group.long 0x88++0x7
line.long 0x0 "PRESETCTRL0,Peripheral reset group 0 control register"
bitfld.long 0x0 29. "DMA_RST_N,DMA reset control" "0: Assert the DMA reset.,1: Clear the DMA reset."
newline
bitfld.long 0x0 28. "GPIOINT_RST_N,GPIOINT reset control" "0: Assert the GPIOINT reset.,1: Clear the GPIOINT reset."
newline
bitfld.long 0x0 24. "ADC_RST_N,ADC reset control" "0: Assert the ADC reset.,1: Clear the ADC reset."
newline
bitfld.long 0x0 23. "I3C_RST_N,I3C reset control" "0: Assert the I3C reset.,1: Clear the I3C reset."
newline
bitfld.long 0x0 22. "FTM1_RST_N,FTM1 reset control" "0: Assert the FTM1 reset.,1: Clear the FTM1 reset."
newline
bitfld.long 0x0 21. "FTM0_RST_N,FTM0 reset control" "0: Assert the FTM0 reset.,1: Clear the FTM0 reset."
newline
bitfld.long 0x0 20. "GPIO1_RST_N,GPIO1 reset control" "0: Assert the GPIO1 reset.,1: Clear the GPIO1 reset."
newline
bitfld.long 0x0 19. "ACMP_RST_N,Analog comparator reset control" "0: Assert the analog comparator reset.,1: Clear the analog comparator reset."
newline
bitfld.long 0x0 18. "IOCON_RST_N,IOCON reset control" "0: Assert the IOCON reset.,1: Clear the IOCON reset."
newline
bitfld.long 0x0 16. "UART2_RST_N,UART2 reset control" "0: Assert the UART2 reset.,1: Clear the UART2 reset."
newline
bitfld.long 0x0 15. "UART1_RST_N,UART1 reset control" "0: Assert the UART1 reset.,1: Clear the UART1 reset."
newline
bitfld.long 0x0 14. "UART0_RST_N,UART0 reset control" "0: Assert the UART0 reset.,1: Clear the UART0 reset."
newline
bitfld.long 0x0 13. "CRC_RST_N,CRC engine reset control" "0: Assert the CRC reset.,1: Clear the CRC reset."
newline
bitfld.long 0x0 12. "SPI1_RST_N,SPI1 reset control" "0: Assert the SPI1 reset.,1: Clear the SPI1 reset."
newline
bitfld.long 0x0 11. "SPI0_RST_N,SPI0 reset control" "0: Assert the SPI0 reset.,1: Clear the SPI0 reset."
newline
bitfld.long 0x0 10. "MRT_RST_N,Multi-rate timer (MRT) reset control" "0: Assert the MRT reset.,1: Clear the MRT reset."
newline
bitfld.long 0x0 9. "WKT_RST_N,Self-wake-up timer (WKT) reset control" "0: Assert the WKT reset.,1: Clear the WKT reset."
newline
bitfld.long 0x0 7. "SWM_RST_N,SWM reset control" "0: Assert the SWM reset.,1: Clear the SWM reset."
newline
bitfld.long 0x0 6. "GPIO0_RST_N,GPIO0 reset control" "0: Assert the GPIO0 reset.,1: Clear the GPIO0 reset."
newline
bitfld.long 0x0 5. "I2C0_RST_N,I2C0 reset control" "0: Assert the I2C0 reset.,1: Clear the I2C0 reset."
newline
bitfld.long 0x0 4. "FLASH_RST_N,flash controller reset control" "0: Assert the flash controller reset.,1: Clear the flash controller reset."
line.long 0x4 "PRESETCTRL1,Peripheral reset group 1 control register"
bitfld.long 0x4 4. "FRG1_RST_N,Fractional baud rate generator 1 reset control" "0: Assert the FRG1 reset.,1: Clear the FRG1 reset."
newline
bitfld.long 0x4 3. "FRG0_RST_N,Fractional baud rate generator 0 reset control" "0: Assert the FRG0 reset.,1: Clear the FRG0 reset."
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "FCLKSEL[$1],peripheral clock source select register. FCLK0SEL~FCLK2SEL are for UART0~UART2 clock source select register.FCLK3SEL~FCLK4SEL are reserved. FCLK5SEL is for I2C clock source select register."
bitfld.long 0x0 0.--2. "SEL,Peripheral clock source" "0: FRO,1: main clock,2: Frg0clk,3: Frg1clk,4: FRO_DIV,5: none,6: none,7: none"
repeat.end
group.long 0xA8++0x7
line.long 0x0 "I3CCLKSEL,I3C clock source select register"
bitfld.long 0x0 0.--2. "SEL,I3C clock source" "0: FRO,1: external clock,2: None,3: None,4: None,5: None,6: None,7: None"
line.long 0x4 "I3CSLOWTCCLKSEL,I3CSLOWTC clock source select register"
bitfld.long 0x4 0.--2. "SEL,I3C clock source" "0: I3CFCLK,1: Low power oscillator,2: None,3: None,4: None,5: None,6: None,7: None"
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xB4)++0x3
line.long 0x0 "FCLKSEL2[$1],peripheral clock source select register. FCLK0SEL2~FCLK2SEL2 are for SPI0~SPI1 clock source select register."
bitfld.long 0x0 0.--2. "SEL,Peripheral clock source" "0: FRO,1: main clock,2: Frg0clk,3: Frg1clk,4: FRO_DIV,5: none,6: none,7: none"
repeat.end
group.long 0xBC++0x3
line.long 0x0 "FTM0INTTRIGDIV,FTM0INTTRIGDIV register"
hexmask.long.byte 0x0 0.--6. 1. "FTM0_INT_TRIG_DIV,ftm0 ext_trigger_ftm0 or init_trigger_ftm0 divided by 1~128"
group.long 0xC8++0x3
line.long 0x0 "FTMFLTCFG,System clock divider register"
bitfld.long 0x0 4. "FTM0_SW_FAULT,Software fault." "0,1"
newline
bitfld.long 0x0 3. "FTM0_FAULT3_MUX_SEL,Mux selection FTM0 fault from external I/O or internal." "0: Select external I/O,1: Select internal"
newline
bitfld.long 0x0 2. "FTM0_FAULT2_MUX_SEL,Mux selection FTM0 fault from external I/O or internal." "0: Select external I/O,1: Select internal"
newline
bitfld.long 0x0 1. "FTM0_FAULT1_MUX_SEL,Mux selection FTM0 fault from external I/O or internal." "0: Select external I/O,1: Select internal"
newline
bitfld.long 0x0 0. "FTM0_FAULT0_MUX_SEL,Mux selection FTM0 fault from external I/O or internal." "0: Select external I/O,1: Select internal"
repeat 2. (list 0x0 0x1)(list ad:0x400480D0 ad:0x400480E0)
tree "FRG[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "FRGDIV,fractional generator N divider value register"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
line.long 0x4 "FRGMULT,fractional generator N multiplier value register"
hexmask.long.byte 0x4 0.--7. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
line.long 0x8 "FRGCLKSEL,FRG N clock source select register"
bitfld.long 0x8 0.--1. "SEL,Clock source for frgN_src clock" "0: FRO,1: main clock,2: sys pll,3: None"
tree.end
repeat.end
base ad:0x40048000
group.long 0xF0++0x7
line.long 0x0 "CLKOUTSEL,CLKOUT clock source select register"
bitfld.long 0x0 0.--2. "SEL,CLKOUT clock source" "0: FRO,1: main clock,2: sys pll,3: external clock,4: Low power oscillator,5: None,6: None,7: None"
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider registers"
hexmask.long.byte 0x4 0.--7. 1. "DIV,CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255."
group.long 0x134++0x23
line.long 0x0 "IOCONCLKDIV6,Peripheral clock 6 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0x0 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0x4 "IOCONCLKDIV5,Peripheral clock 6 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0x4 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0x8 "IOCONCLKDIV4,Peripheral clock 4 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0x8 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0xC "IOCONCLKDIV3,Peripheral clock 3 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0xC 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0x10 "IOCONCLKDIV2,Peripheral clock 2 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0x10 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0x14 "IOCONCLKDIV1,Peripheral clock 1 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0x14 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0x18 "IOCONCLKDIV0,Peripheral clock 0 to the IOCON block for programmable glitch filter"
hexmask.long.byte 0x18 0.--7. 1. "DIV,IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."
line.long 0x1C "BODCTRL,BOD control register"
bitfld.long 0x1C 4. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
newline
bitfld.long 0x1C 2.--3. "BODINTVAL,BOD interrupt level" "?,1: Level 1,2: Level 2,3: Level 3"
newline
bitfld.long 0x1C 0.--1. "BODRSTLEV,BOD reset level" "?,1: Level 1,2: Level 2,3: Level 3"
line.long 0x20 "SYSTCKCAL,System tick timer calibration register"
hexmask.long 0x20 0.--25. 1. "CAL,System tick timer calibration value."
group.long 0x170++0x7
line.long 0x0 "IRQLATENCY,IRQ latency register"
hexmask.long.byte 0x0 0.--7. 1. "LATENCY,8-bit latency value."
line.long 0x4 "NMISRC,NMI source selection register"
bitfld.long 0x4 31. "NMIEN,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." "0,1"
newline
hexmask.long.byte 0x4 0.--4. 1. "IRQN,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x178)++0x3
line.long 0x0 "PINTSEL[$1],Pin interrupt select registers N"
hexmask.long.byte 0x0 0.--5. 1. "INTPIN,Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63)."
repeat.end
group.long 0x204++0x3
line.long 0x0 "STARTERP0,Start logic 0 pin wake-up enable register 0"
bitfld.long 0x0 7. "PINT7,GPIO pin interrupt 7 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 6. "PINT6,GPIO pin interrupt 6 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "PINT5,GPIO pin interrupt 5 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "PINT4,GPIO pin interrupt 4 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 3. "PINT3,GPIO pin interrupt 3 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "PINT2,GPIO pin interrupt 2 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "PINT1,GPIO pin interrupt 1 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "PINT0,GPIO pin interrupt 0 wake-up" "0: Disabled,1: Enabled"
group.long 0x214++0x3
line.long 0x0 "STARTERP1,Start logic 0 pin wake-up enable register 1"
bitfld.long 0x0 15. "WKT,Self-wake-up timer interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 13. "BOD,BOD interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 12. "WWDT,WWDT interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 8. "I2C0,I2C0 interrupt wake-up." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "USART2,USART2 interrupt wake-up. Configure USART in synchronous slave mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "USART1,USART1 interrupt wake-up. Configure USART in synchronous slave mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 3. "USART0,USART0 interrupt wake-up. Configure USART in synchronous slave mode." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "SPI1,SPI1 interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "SPI0,SPI0 interrupt wake-up" "0: Disabled,1: Enabled"
group.long 0x230++0xB
line.long 0x0 "PDSLEEPCFG,Deep-sleep configuration register"
bitfld.long 0x0 6. "LPOSC_PD,Low power oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case the Low power oscillator is always running." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 3. "BOD_PD,BOD power-down control for Deep-sleep and Power-down mode" "0: powered,1: powered down"
line.long 0x4 "PDAWAKECFG,Wake-up configuration register"
bitfld.long 0x4 15. "ACMP,Analog comparator wake-up configuration" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 7. "SYSPLL_PD,System PLL wake-up configuration" "0: Disabled,1: Enabled"
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bitfld.long 0x4 6. "LPOSC_PD,Low power oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case the Low power oscillator is always running" "0: Disabled,1: Enabled"
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bitfld.long 0x4 5. "SYSOSC_PD,Crystal oscillator wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x4 4. "ADC_PD,ADC wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x4 3. "BOD_PD,BOD wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x4 2. "FLASH_PD,Flash wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x4 1. "FRO_PD,FRO oscillator power-down wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x4 0. "FROOUT_PD,FRO oscillator output wake-up configuration" "0: powered,1: powered down"
line.long 0x8 "PDRUNCFG,Power configuration register"
bitfld.long 0x8 15. "ACMP,Analog comparator wake-up configuration" "0: Disabled,1: Enabled"
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bitfld.long 0x8 7. "SYSPLL_PD,System PLL wake-up configuration" "0: Disabled,1: Enabled"
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bitfld.long 0x8 6. "LPOSC_PD,Low power oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case the Low power oscillator is always running" "0: Disabled,1: Enabled"
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bitfld.long 0x8 5. "SYSOSC_PD,Crystal oscillator wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x8 4. "ADC_PD,ADC wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x8 3. "BOD_PD,BOD wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x8 2. "FLASH_PD,Flash wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x8 1. "FRO_PD,FRO oscillator power-down wake-up configuration" "0: powered,1: powered down"
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bitfld.long 0x8 0. "FROOUT_PD,FRO oscillator output wake-up configuration" "0: powered,1: powered down"
group.long 0x240++0x3
line.long 0x0 "FLASHCACHECFG,Flash cache configuration register"
bitfld.long 0x0 2. "FLASH_CACHE_INVALID,Flash cache invalid" "0: disable,1: enable"
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bitfld.long 0x0 1. "FLASH_BUFFER_ENABLE,Flash buffer enable" "0: disable,1: enable"
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bitfld.long 0x0 0. "FLASH_CACHE_ENABLE,Flash cache enable" "0: disable,1: enable"
rgroup.long 0x3F8++0x3
line.long 0x0 "DEVICE_ID,Part ID register"
hexmask.long 0x0 0.--31. 1. "DEVICEID,Part ID"
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "USART0"
base ad:0x40064000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 18.--20. "RXIDLETOCFG,RX IDLE time out configuration" "0: 000b - 1 idle character,1: 001b - 2 idle characters,2: 010b - 4 idle characters,3: 011b - 8 idle characters,4: 100b - 16 idle characters,5: 101b - 32 idle characters,6: 110b - 64 idle characters,7: 111b - 128 idle characters"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
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bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
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bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
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bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 17. "RXIDLETO,RX IDLE Timeout flag. Set when the receiver has been idle for a certain period of time as specified by CTRL.RXIDLETOCFG. Writing 1 clears this bit and lowers the corresponding interrupt. Once cleared it cannot be set again until after the.." "0,1"
bitfld.long 0x8 16. "ABERR,Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured essentially an autobaud time-out." "0,1"
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bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
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bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs.Cleared by software." "0,1"
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
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bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs the newly received character in the shift register is lost." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Interrupt flag. When 1 this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1 this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
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rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0 indicates that the receiver is currently in the process of receiving data. When 1 indicates that the receiver is not currently in the process of receiving data." "0,1"
rbitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1 indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 17. "RXIDLETOEN,RX IDLE timeout interrupt enable. Write 1 to set the bit. Writing 0 has no effect. 0: RX IDLE time out interrupt is disabled. 1: When STAT.RXIDLETO is set interrupt is asserted." "0: RX IDLE time out interrupt is disabled,1: When STAT"
bitfld.long 0xC 16. "ABERREN,When 1 enables an interrupt when an autobaud error occurs." "0,1"
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bitfld.long 0xC 15. "RXNOISEEN,When 1 enables an interrupt when noise is detected." "0,1"
bitfld.long 0xC 14. "PARITYERREN,When 1 enables an interrupt when a parity error has been detected." "0,1"
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bitfld.long 0xC 13. "FRAMERREN,When 1 enables an interrupt when a framing error has been detected." "0,1"
bitfld.long 0xC 12. "STARTEN,When 1 enables an interrupt when a received start bit has been detected." "0,1"
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bitfld.long 0xC 11. "DELTARXBRKEN,When 1 enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
bitfld.long 0xC 8. "OVERRUNEN,When 1 enables an interrupt when an overrun error occurred." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1 enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1 enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1 enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
bitfld.long 0xC 2. "TXRDYEN,When 1 enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
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bitfld.long 0xC 0. "RXRDYEN,When 1 enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 17. "RXIDLETOEN,Writing 1 to clears INTENSET[RXIDLETOEN]. Writing 0 has no effect. The access for this bit is write-only." "0,1"
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISINTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
rgroup.long 0x14++0x7
line.long 0x0 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x0 0.--8. 1. "RXDAT,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x4 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x4 15. "RXNOISE,Received Noise flag." "0,1"
bitfld.long 0x4 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x4 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x4 0.--8. 1. "RXDAT,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
group.long 0x1C++0x7
line.long 0x0 "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x0 0.--8. 1. "TXDAT,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1) TXDIS bit = 0."
line.long 0x4 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x4 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 17. "RXIDLETOINT,RX IDLE timeout interrupt flag. The access of this bit is read-only." "0,1"
bitfld.long 0x0 16. "ABERR,Autobaud Error flag." "0,1"
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bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
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bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
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bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
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bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
tree "USART1"
base ad:0x40068000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 18.--20. "RXIDLETOCFG,RX IDLE time out configuration" "0: 000b - 1 idle character,1: 001b - 2 idle characters,2: 010b - 4 idle characters,3: 011b - 8 idle characters,4: 100b - 16 idle characters,5: 101b - 32 idle characters,6: 110b - 64 idle characters,7: 111b - 128 idle characters"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
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bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
newline
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 17. "RXIDLETO,RX IDLE Timeout flag. Set when the receiver has been idle for a certain period of time as specified by CTRL.RXIDLETOCFG. Writing 1 clears this bit and lowers the corresponding interrupt. Once cleared it cannot be set again until after the.." "0,1"
bitfld.long 0x8 16. "ABERR,Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured essentially an autobaud time-out." "0,1"
newline
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
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bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs.Cleared by software." "0,1"
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
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bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs the newly received character in the shift register is lost." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Interrupt flag. When 1 this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1 this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
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rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0 indicates that the receiver is currently in the process of receiving data. When 1 indicates that the receiver is not currently in the process of receiving data." "0,1"
rbitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1 indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 17. "RXIDLETOEN,RX IDLE timeout interrupt enable. Write 1 to set the bit. Writing 0 has no effect. 0: RX IDLE time out interrupt is disabled. 1: When STAT.RXIDLETO is set interrupt is asserted." "0: RX IDLE time out interrupt is disabled,1: When STAT"
bitfld.long 0xC 16. "ABERREN,When 1 enables an interrupt when an autobaud error occurs." "0,1"
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bitfld.long 0xC 15. "RXNOISEEN,When 1 enables an interrupt when noise is detected." "0,1"
bitfld.long 0xC 14. "PARITYERREN,When 1 enables an interrupt when a parity error has been detected." "0,1"
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bitfld.long 0xC 13. "FRAMERREN,When 1 enables an interrupt when a framing error has been detected." "0,1"
bitfld.long 0xC 12. "STARTEN,When 1 enables an interrupt when a received start bit has been detected." "0,1"
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bitfld.long 0xC 11. "DELTARXBRKEN,When 1 enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
bitfld.long 0xC 8. "OVERRUNEN,When 1 enables an interrupt when an overrun error occurred." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1 enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1 enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1 enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
bitfld.long 0xC 2. "TXRDYEN,When 1 enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
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bitfld.long 0xC 0. "RXRDYEN,When 1 enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 17. "RXIDLETOEN,Writing 1 to clears INTENSET[RXIDLETOEN]. Writing 0 has no effect. The access for this bit is write-only." "0,1"
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISINTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
rgroup.long 0x14++0x7
line.long 0x0 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x0 0.--8. 1. "RXDAT,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x4 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x4 15. "RXNOISE,Received Noise flag." "0,1"
bitfld.long 0x4 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x4 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x4 0.--8. 1. "RXDAT,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
group.long 0x1C++0x7
line.long 0x0 "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x0 0.--8. 1. "TXDAT,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1) TXDIS bit = 0."
line.long 0x4 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x4 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 17. "RXIDLETOINT,RX IDLE timeout interrupt flag. The access of this bit is read-only." "0,1"
bitfld.long 0x0 16. "ABERR,Autobaud Error flag." "0,1"
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bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
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bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
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bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
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bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
tree "USART2"
base ad:0x4006C000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 18.--20. "RXIDLETOCFG,RX IDLE time out configuration" "0: 000b - 1 idle character,1: 001b - 2 idle characters,2: 010b - 4 idle characters,3: 011b - 8 idle characters,4: 100b - 16 idle characters,5: 101b - 32 idle characters,6: 110b - 64 idle characters,7: 111b - 128 idle characters"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
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bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
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bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
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bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 17. "RXIDLETO,RX IDLE Timeout flag. Set when the receiver has been idle for a certain period of time as specified by CTRL.RXIDLETOCFG. Writing 1 clears this bit and lowers the corresponding interrupt. Once cleared it cannot be set again until after the.." "0,1"
bitfld.long 0x8 16. "ABERR,Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured essentially an autobaud time-out." "0,1"
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bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
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bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs.Cleared by software." "0,1"
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
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bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs the newly received character in the shift register is lost." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Interrupt flag. When 1 this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1 this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
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rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0 indicates that the receiver is currently in the process of receiving data. When 1 indicates that the receiver is not currently in the process of receiving data." "0,1"
rbitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1 indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 17. "RXIDLETOEN,RX IDLE timeout interrupt enable. Write 1 to set the bit. Writing 0 has no effect. 0: RX IDLE time out interrupt is disabled. 1: When STAT.RXIDLETO is set interrupt is asserted." "0: RX IDLE time out interrupt is disabled,1: When STAT"
bitfld.long 0xC 16. "ABERREN,When 1 enables an interrupt when an autobaud error occurs." "0,1"
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bitfld.long 0xC 15. "RXNOISEEN,When 1 enables an interrupt when noise is detected." "0,1"
bitfld.long 0xC 14. "PARITYERREN,When 1 enables an interrupt when a parity error has been detected." "0,1"
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bitfld.long 0xC 13. "FRAMERREN,When 1 enables an interrupt when a framing error has been detected." "0,1"
bitfld.long 0xC 12. "STARTEN,When 1 enables an interrupt when a received start bit has been detected." "0,1"
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bitfld.long 0xC 11. "DELTARXBRKEN,When 1 enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
bitfld.long 0xC 8. "OVERRUNEN,When 1 enables an interrupt when an overrun error occurred." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1 enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1 enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1 enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
bitfld.long 0xC 2. "TXRDYEN,When 1 enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
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bitfld.long 0xC 0. "RXRDYEN,When 1 enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 17. "RXIDLETOEN,Writing 1 to clears INTENSET[RXIDLETOEN]. Writing 0 has no effect. The access for this bit is write-only." "0,1"
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISINTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
rgroup.long 0x14++0x7
line.long 0x0 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x0 0.--8. 1. "RXDAT,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x4 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x4 15. "RXNOISE,Received Noise flag." "0,1"
bitfld.long 0x4 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x4 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x4 0.--8. 1. "RXDAT,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
group.long 0x1C++0x7
line.long 0x0 "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x0 0.--8. 1. "TXDAT,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1) TXDIS bit = 0."
line.long 0x4 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x4 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 17. "RXIDLETOINT,RX IDLE timeout interrupt flag. The access of this bit is read-only." "0,1"
bitfld.long 0x0 16. "ABERR,Autobaud Error flag." "0,1"
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bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
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bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
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bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
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bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
tree.end
tree "WKT (Self-Wake-Up Timer)"
base ad:0x40008000
group.long 0x0++0x3
line.long 0x0 "CTRL,Self wake-up timer control register."
bitfld.long 0x0 3. "SEL_EXTCLK,Select external or internal clock source for the self wake-up timer. The internal clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal." "0: Internal. The clock source is the internal clock..,1: External. The self wake-up timer uses the.."
bitfld.long 0x0 2. "CLEARCTR,Clears the self wake-up timer." "0: No effect. Reading this bit always returns 0.,1: Clear the counter. Counting is halted until a.."
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bitfld.long 0x0 1. "ALARMFLAG,Wake-up or alarm timer flag." "0: No time-out. The self wake-up timer has not..,1: Time-out. The self wake-up timer has timed out."
bitfld.long 0x0 0. "CLKSEL,Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set." "0: Divided FRO clock. This clock runs at 750 kHz..,1: This is the (nominally) 10 kHz clock and.."
group.long 0xC++0x3
line.long 0x0 "COUNT,Counter register."
hexmask.long 0x0 0.--31. 1. "VALUE,A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer."
tree.end
tree "WWDT (Windowed Watchdog Timer)"
base ad:0x40000000
group.long 0x0++0x7
line.long 0x0 "MOD,Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."
bitfld.long 0x0 5. "LOCK,Once this bit is set to one and a watchdog feed is performed disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset." "0,1"
bitfld.long 0x0 4. "WDPROTECT,Watchdog update mode. This bit can be set once by software and is only cleared by a reset." "0: Flexible. The watchdog time-out value (TC) can..,1: Threshold. The watchdog time-out value (TC) can.."
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bitfld.long 0x0 3. "WDINT,Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can.." "0,1"
bitfld.long 0x0 2. "WDTOF,Watchdog time-out flag. Set when the watchdog timer times out by a feed error or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1." "0,1"
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bitfld.long 0x0 1. "WDRESET,Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0." "0: Interrupt. A watchdog time-out will not cause a..,1: Reset. A watchdog time-out will cause a chip.."
bitfld.long 0x0 0. "WDEN,Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed the watchdog timer will run permanently." "0: Stop. The watchdog timer is stopped.,1: Run. The watchdog timer is running."
line.long 0x4 "TC,Watchdog timer constant register. This 24-bit register determines the time-out value."
hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Watchdog time-out value."
wgroup.long 0x8++0x3
line.long 0x0 "FEED,Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC."
hexmask.long.byte 0x0 0.--7. 1. "FEED,Feed value should be 0xAA followed by 0x55."
rgroup.long 0xC++0x3
line.long 0x0 "TV,Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer."
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter timer value."
group.long 0x14++0x7
line.long 0x0 "WARNINT,Watchdog Warning Interrupt compare value."
hexmask.long.word 0x0 0.--9. 1. "WARNINT,Watchdog warning interrupt compare value."
line.long 0x4 "WINDOW,Watchdog Window compare value."
hexmask.long.tbyte 0x4 0.--23. 1. "WINDOW,Watchdog window value."
tree.end
AUTOINDENT.OFF
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