18176 lines
1.4 MiB
18176 lines
1.4 MiB
; --------------------------------------------------------------------------------
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; @Title: IMXRT1010 On-Chip Peripherals
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; @Props: Released
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; @Author: KOL, KRZ
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; @Changelog: 2019-12-19 KOL
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; 2022-02-28 KRZ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: SVD generated, based on: MIMXRT1011.svd (Ver. 1.0)
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; @Core: Cortex-M7F
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; @Chip: IMXRT1011
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perimxrt1010.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
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line.long 0x08 "DCISW,Data cache invalidate by set/way"
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line.long 0x0C "DCCMVAU,Data cache by address to PoU"
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line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
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line.long 0x14 "DCCSW,Data cache clean by set/way"
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line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
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line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
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group.long 0xF90++0x13
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line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
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bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
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bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
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textline " "
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|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "AIPSTZ (AHB to IP Bridge Trust Zone)"
|
|
repeat 2. (list 1. 2.) (list ad:0x4007C000 ad:0x4017C000)
|
|
tree "AIPSTZ$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPR,Master Priviledge Registers"
|
|
bitfld.long 0x00 28.--31. "MPROT0,Master 0 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
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|
bitfld.long 0x00 24.--27. "MPROT1,Master 1 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
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|
newline
|
|
bitfld.long 0x00 20.--23. "MPROT2,Master 2 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
|
|
bitfld.long 0x00 16.--19. "MPROT3,Master 3 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MPROT5,Master 5 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "OPACR,Off-Platform Peripheral Access Control Registers"
|
|
bitfld.long 0x00 28.--31. "OPAC0,Off-platform Peripheral Access Control 0" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 24.--27. "OPAC1,Off-platform Peripheral Access Control 1" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "OPAC2,Off-platform Peripheral Access Control 2" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 16.--19. "OPAC3,Off-platform Peripheral Access Control 3" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "OPAC4,Off-platform Peripheral Access Control 4" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 8.--11. "OPAC5,Off-platform Peripheral Access Control 5" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OPAC6,Off-platform Peripheral Access Control 6" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 0.--3. "OPAC7,Off-platform Peripheral Access Control 7" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "OPACR1,Off-Platform Peripheral Access Control Registers"
|
|
bitfld.long 0x00 28.--31. "OPAC8,Off-platform Peripheral Access Control 8" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 24.--27. "OPAC9,Off-platform Peripheral Access Control 9" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "OPAC10,Off-platform Peripheral Access Control 10" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 16.--19. "OPAC11,Off-platform Peripheral Access Control 11" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "OPAC12,Off-platform Peripheral Access Control 12" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 8.--11. "OPAC13,Off-platform Peripheral Access Control 13" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OPAC14,Off-platform Peripheral Access Control 14" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 0.--3. "OPAC15,Off-platform Peripheral Access Control 15" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "OPACR2,Off-Platform Peripheral Access Control Registers"
|
|
bitfld.long 0x00 28.--31. "OPAC16,Off-platform Peripheral Access Control 16" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 24.--27. "OPAC17,Off-platform Peripheral Access Control 17" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "OPAC18,Off-platform Peripheral Access Control 18" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 16.--19. "OPAC19,Off-platform Peripheral Access Control 19" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "OPAC20,Off-platform Peripheral Access Control 20" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 8.--11. "OPAC21,Off-platform Peripheral Access Control 21" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OPAC22,Off-platform Peripheral Access Control 22" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 0.--3. "OPAC23,Off-platform Peripheral Access Control 23" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OPACR3,Off-Platform Peripheral Access Control Registers"
|
|
bitfld.long 0x00 28.--31. "OPAC24,Off-platform Peripheral Access Control 24" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 24.--27. "OPAC25,Off-platform Peripheral Access Control 25" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "OPAC26,Off-platform Peripheral Access Control 26" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 16.--19. "OPAC27,Off-platform Peripheral Access Control 27" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "OPAC28,Off-platform Peripheral Access Control 28" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 8.--11. "OPAC29,Off-platform Peripheral Access Control 29" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OPAC30,Off-platform Peripheral Access Control 30" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 0.--3. "OPAC31,Off-platform Peripheral Access Control 31" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OPACR4,Off-Platform Peripheral Access Control Registers"
|
|
bitfld.long 0x00 28.--31. "OPAC32,Off-platform Peripheral Access Control 32" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 24.--27. "OPAC33,Off-platform Peripheral Access Control 33" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DCDC"
|
|
base ad:0x40080000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "REG0,DCDC Register 0"
|
|
rbitfld.long 0x00 31. "STS_DC_OK,Status register to indicate DCDC status" "0: DCDC is settling,1: DCDC already settled"
|
|
bitfld.long 0x00 29. "XTAL_24M_OK,set to 1 to switch internal ring osc to xtal 24M" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "CURRENT_ALERT_RESET,reset current alert signal" "0,1"
|
|
bitfld.long 0x00 27. "XTALOK_DISABLE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "PWD_CMP_OFFSET,power down output range comparator" "0,1"
|
|
bitfld.long 0x00 21. "LP_HIGH_HYS,Adjust hysteretic value in low power from 12.5mV to 25mV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LP_OVERLOAD_FREQ_SEL,the period of counting the charging times in power save mode" "0: eight 32k cycle,1: sixteen 32k cycle"
|
|
bitfld.long 0x00 18.--19. "LP_OVERLOAD_THRSH,the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "PWD_HIGH_VOLT_DET,power down overvoltage detection comparator" "0,1"
|
|
bitfld.long 0x00 16. "EN_LP_OVERLOAD_SNS,enable the overload detection in power save mode if current is larger than the overloading threshold (typical value is 50 mA) DCDC will switch to the run mode automatically" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ADJ_POSLIMIT_BUCK,adjust value to poslimit_buck register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "PWD_CMP_BATT_DET,set to 1 to power down the low voltage detection comparator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OVERCUR_TRIG_ADJ,The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0" "0,1,2,3"
|
|
bitfld.long 0x00 8. "PWD_OVERCUR_DET,power down overcurrent detection comparator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "CUR_SNS_THRSH,Set the threshold of current detector if the peak current of the inductor exceeds the threshold the current detector will assert" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "PWD_CUR_SNS_CMP,The power down signal of the current detector" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PWD_OSC_INT,Power down internal osc" "0,1"
|
|
bitfld.long 0x00 2. "SEL_CLK,select 24 MHz Crystal clock for DCDC when dcdc_disable_auto_clk_switch is set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DISABLE_AUTO_CLK_SWITCH,Disable automatic clock switch from internal osc to xtal clock" "0,1"
|
|
bitfld.long 0x00 0. "PWD_ZCD,power down the zero cross detection function for discontinuous conductor mode" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "REG1,DCDC Register 1"
|
|
bitfld.long 0x00 24.--28. "VBG_TRIM,trim bandgap voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "LOOPCTRL_EN_HYST,Enable hysteresis in switching converter common mode analog comparators" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "LOOPCTRL_HST_THRESH,increase the threshold detection for common mode analog comparator" "0,1"
|
|
bitfld.long 0x00 12.--13. "LP_CMP_ISRC_SEL,set the current bias of low power comparator" "0: 50 nA,1: 100 nA,2: 200 nA,3: 400 nA"
|
|
newline
|
|
bitfld.long 0x00 9. "REG_RLOAD_SW,control the load resistor of the internal regulator of DCDC the load resistor is connected as default 1 and need set to 0 to disconnect the load resistor" "0,1"
|
|
bitfld.long 0x00 7.--8. "REG_FBK_SEL,select the feedback point of the internal regulator" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "REG2,DCDC Register 2"
|
|
bitfld.long 0x00 28. "DCM_SET_CTRL,Set high to improve the transition from heavy load to light load" "0,1"
|
|
bitfld.long 0x00 27. "DISABLE_PULSE_SKIP,Set to" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "BATTMONITOR_EN_BATADJ,This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field" "0,1"
|
|
bitfld.long 0x00 13. "LOOPCTRL_HYST_SIGN,Invert the sign of the hysteresis in DC-DC analog comparators" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "LOOPCTRL_RCSCALE_THRSH,Increase the threshold detection for RC scale circuit" "0,1"
|
|
bitfld.long 0x00 9.--11. "LOOPCTRL_EN_RCSCALE,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "LOOPCTRL_DC_FF,Two's complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--5. "LOOPCTRL_DC_R,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 0.--1. "LOOPCTRL_DC_C,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter and can be used to optimize efficiency and loop response" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "REG3,DCDC Register 3"
|
|
bitfld.long 0x00 30. "DISABLE_STEP,Disable stepping for the output VDD_SOC of DCDC" "0,1"
|
|
bitfld.long 0x00 28. "MISC_DISABLEFET_LOGIC,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MISC_DELAY_TIMING,Ajust delay to reduce ground noise" "0,1"
|
|
bitfld.long 0x00 24. "MINPWR_DC_HALFCLK,Set DCDC clock to half freqeuncy for continuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TARGET_LP,Target value of standby (low power) mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "TRG,Target value of VDD_SOC 25 mV each step" "0: 0.8V,?,?,?,?,?,?,?,?,?,?,?,?,?,14: 1.15V 0x1F,?..."
|
|
tree.end
|
|
tree "PIT"
|
|
base ad:0x40084000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,PIT Module Control Register"
|
|
bitfld.long 0x00 1. "MDIS,Module Disable for PIT" "0: Clock for standard PIT timers is enabled,1: Clock for standard PIT timers is disabled"
|
|
bitfld.long 0x00 0. "FRZ,Freeze" "0: Timers continue to run in Debug mode,1: Timers are stopped in Debug mode"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register"
|
|
hexmask.long 0x00 0.--31. 1. "LTH,Life Timer value"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "LTMR64L,PIT Lower Lifetime Timer Register"
|
|
hexmask.long 0x00 0.--31. 1. "LTL,Life Timer value"
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "TIMER[$1]"
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "LDVAL,Timer Load Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSV,Timer Start Value"
|
|
rgroup.long ($2+0x104)++0x03
|
|
line.long 0x00 "CVAL,Current Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TVL,Current Timer Value"
|
|
group.long ($2+0x108)++0x03
|
|
line.long 0x00 "TCTRL,Timer Control Register"
|
|
bitfld.long 0x00 2. "CHN,Chain Mode" "0: Timer is not chained,1: Timer is chained to a previous timer"
|
|
bitfld.long 0x00 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from Timer n are disabled,1: Interrupt is requested whenever TIF is set"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: Timer n is disabled,1: Timer n is enabled"
|
|
group.long ($2+0x10C)++0x03
|
|
line.long 0x00 "TFLG,Timer Flag Register"
|
|
eventfld.long 0x00 0. "TIF,Timer Interrupt Flag" "0: Timeout has not yet occurred,1: Timeout has occurred"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "ADC_ETC"
|
|
base ad:0x40088000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,ADC_ETC Global Control Register"
|
|
bitfld.long 0x00 31. "SOFTRST,Software reset high active" "0,1"
|
|
bitfld.long 0x00 30. "TSC_BYPASS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "DMA_MODE_SEL," "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRE_DIVIDER,Pre-divider for trig delay and interval"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "EXT1_TRIG_PRIORITY,External TSC1 trigger priority 7 is Highest 0 is lowest" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "EXT1_TRIG_ENABLE,TSC1 TRIG enable register" "0: disable external TSC1 trigger,1: enable external TSC1 trigger"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "EXT0_TRIG_PRIORITY,External TSC0 trigger priority 7 is Highest 0 is lowest" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "EXT0_TRIG_ENABLE,TSC0 TRIG enable register" "0: disable external TSC0 trigger,1: enable external TSC0 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIG_ENABLE,TRIG enable register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DONE0_1_IRQ,ETC DONE0 and DONE1 IRQ State Register"
|
|
bitfld.long 0x00 23. "TRIG7_DONE1,TRIG7 done1 interrupt detection" "0,1"
|
|
bitfld.long 0x00 22. "TRIG6_DONE1,TRIG6 done1 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "TRIG5_DONE1,TRIG5 done1 interrupt detection" "0,1"
|
|
bitfld.long 0x00 20. "TRIG4_DONE1,TRIG4 done1 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "TRIG3_DONE1,TRIG3 done1 interrupt detection" "0,1"
|
|
bitfld.long 0x00 18. "TRIG2_DONE1,TRIG2 done1 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "TRIG1_DONE1,TRIG1 done1 interrupt detection" "0,1"
|
|
bitfld.long 0x00 16. "TRIG0_DONE1,TRIG0 done1 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TRIG7_DONE0,TRIG7 done0 interrupt detection" "0,1"
|
|
bitfld.long 0x00 6. "TRIG6_DONE0,TRIG6 done0 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIG5_DONE0,TRIG5 done0 interrupt detection" "0,1"
|
|
bitfld.long 0x00 4. "TRIG4_DONE0,TRIG4 done0 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3_DONE0,TRIG3 done0 interrupt detection" "0,1"
|
|
bitfld.long 0x00 2. "TRIG2_DONE0,TRIG2 done0 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1_DONE0,TRIG1 done0 interrupt detection" "0,1"
|
|
bitfld.long 0x00 0. "TRIG0_DONE0,TRIG0 done0 interrupt detection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DONE2_ERR_IRQ,ETC DONE_2 and DONE_ERR IRQ State Register"
|
|
bitfld.long 0x00 23. "TRIG7_ERR,TRIG7 error interrupt detection" "0,1"
|
|
bitfld.long 0x00 22. "TRIG6_ERR,TRIG6 error interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "TRIG5_ERR,TRIG5 error interrupt detection" "0,1"
|
|
bitfld.long 0x00 20. "TRIG4_ERR,TRIG4 error interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "TRIG3_ERR,TRIG3 error interrupt detection" "0,1"
|
|
bitfld.long 0x00 18. "TRIG2_ERR,TRIG2 error interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "TRIG1_ERR,TRIG1 error interrupt detection" "0,1"
|
|
bitfld.long 0x00 16. "TRIG0_ERR,TRIG0 error interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "TRIG7_DONE3,TRIG7 done3 interrupt detection" "0,1"
|
|
bitfld.long 0x00 14. "TRIG6_DONE3,TRIG6 done3 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "TRIG5_DONE3,TRIG5 done3 interrupt detection" "0,1"
|
|
bitfld.long 0x00 12. "TRIG4_DONE3,TRIG4 done3 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TRIG3_DONE3,TRIG3 done3 interrupt detection" "0,1"
|
|
bitfld.long 0x00 10. "TRIG2_DONE3,TRIG2 done3 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TRIG1_DONE3,TRIG1 done3 interrupt detection" "0,1"
|
|
bitfld.long 0x00 8. "TRIG0_DONE3,TRIG0 done3 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TRIG7_DONE2,TRIG7 done2 interrupt detection" "0,1"
|
|
bitfld.long 0x00 6. "TRIG6_DONE2,TRIG6 done2 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIG5_DONE2,TRIG5 done2 interrupt detection" "0,1"
|
|
bitfld.long 0x00 4. "TRIG4_DONE2,TRIG4 done2 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3_DONE2,TRIG3 done2 interrupt detection" "0,1"
|
|
bitfld.long 0x00 2. "TRIG2_DONE2,TRIG2 done2 interrupt detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1_DONE2,TRIG1 done2 interrupt detection" "0,1"
|
|
bitfld.long 0x00 0. "TRIG0_DONE2,TRIG0 done2 interrupt detection" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMA_CTRL,ETC DMA control Register"
|
|
bitfld.long 0x00 23. "TRIG7_REQ,When TRIG7 done DMA request detection" "0,1"
|
|
bitfld.long 0x00 22. "TRIG6_REQ,When TRIG6 done DMA request detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "TRIG5_REQ,When TRIG5 done DMA request detection" "0,1"
|
|
bitfld.long 0x00 20. "TRIG4_REQ,When TRIG4 done DMA request detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "TRIG3_REQ,When TRIG3 done DMA request detection" "0,1"
|
|
bitfld.long 0x00 18. "TRIG2_REQ,When TRIG2 done DMA request detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "TRIG1_REQ,When TRIG1 done DMA request detection" "0,1"
|
|
bitfld.long 0x00 16. "TRIG0_REQ,When TRIG0 done DMA request detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TRIG7_ENABLE,When TRIG7 done enable DMA request" "0,1"
|
|
bitfld.long 0x00 6. "TRIG6_ENABLE,When TRIG6 done enable DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIG5_ENABLE,When TRIG5 done enable DMA request" "0,1"
|
|
bitfld.long 0x00 4. "TRIG4_ENABLE,When TRIG4 done enable DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3_ENABLE,When TRIG3 done enable DMA request" "0,1"
|
|
bitfld.long 0x00 2. "TRIG2_ENABLE,When TRIG2 done enable DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1_ENABLE,When TRIG1 done enable DMA request" "0,1"
|
|
bitfld.long 0x00 0. "TRIG0_ENABLE,When TRIG0 done enable DMA request" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRIG0_CTRL,ETC_TRIG Control Register"
|
|
abitfld.long 0x00 24.--31. "CHAINx_DONE,CHAINx done interrupt detection bit" "0x00=0: CHAIN0 done interrupt bit,0x01=1: CHAIN1 done interrupt bit,0x02=2: CHAIN2 done interrupt bit,0x03=3: CHAIN3 done interrupt bit,0x04=4: CHAIN4 done interrupt bit,0x05=5: CHAIN5 done interrupt bit,0x06=6: CHAIN6 done interrupt bit,0x07=7: CHAIN7 done interrupt The done.."
|
|
bitfld.long 0x00 16. "SYNC_MODE,TRIG mode control" "0: Disable sync mode,1: Enable sync mode"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "TRIG_PRIORITY,External trigger priority 7 is highest 0 is lowest" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "TRIG_CHAIN,TRIG chain length to the ADC" "0: Trig length is 1,?,?,?,?,?,?,7: Trig length is 8"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIG_MODE,TRIG mode register" "0: hardware trigger,1: software trigger"
|
|
bitfld.long 0x00 0. "SW_TRIG,Software write 1 as the TRIGGER" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRIG0_COUNTER,ETC_TRIG Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SAMPLE_INTERVAL,TRIGGER sampling interval counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT_DELAY,TRIGGER initial delay counter"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRIG0_CHAIN_1_0,ETC_TRIG Chain 0/1 Register"
|
|
bitfld.long 0x00 31. "IE1_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE1,CHAIN1 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B1,CHAIN1 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS1,CHAIN1 HWTS ADC hardware trigger selection"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL1,CHAIN1 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE0_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE0,CHAIN0 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
bitfld.long 0x00 12. "B2B0,CHAIN0 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS0,CHAIN0 HWTS ADC hardware trigger selection"
|
|
bitfld.long 0x00 0.--3. "CSEL0,CHAIN0 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRIG0_CHAIN_3_2,ETC_TRIG Chain 2/3 Register"
|
|
bitfld.long 0x00 31. "IE3_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE3,CHAIN3 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B3,CHAIN3 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS3,CHAIN3 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL3,CHAIN3 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE2_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE2,CHAIN2 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B2,CHAIN2 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS2,CHAIN2 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL2,CHAIN2 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRIG0_CHAIN_5_4,ETC_TRIG Chain 4/5 Register"
|
|
bitfld.long 0x00 31. "IE5_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE5,CHAIN5 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B5,CHAIN5 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS5,CHAIN5 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL5,CHAIN5 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE4_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE4,CHAIN4 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B4,CHAIN4 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS4,CHAIN4 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL4,CHAIN4 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRIG0_CHAIN_7_6,ETC_TRIG Chain 6/7 Register"
|
|
bitfld.long 0x00 31. "IE7_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE7,CHAIN7 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B7,CHAIN7 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS7,CHAIN7 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL7,CHAIN7 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE6_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE6,CHAIN6 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B6,CHAIN6 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS6,CHAIN6 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL6,CHAIN6 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRIG0_RESULT_1_0,ETC_TRIG Result Data 1/0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA1,Result DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA0,Result DATA0"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRIG0_RESULT_3_2,ETC_TRIG Result Data 3/2 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA3,Result DATA3"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA2,Result DATA2"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRIG0_RESULT_5_4,ETC_TRIG Result Data 5/4 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA5,Result DATA5"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA4,Result DATA4"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRIG0_RESULT_7_6,ETC_TRIG Result Data 7/6 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA7,Result DATA7"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA6,Result DATA6"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRIG1_CTRL,ETC_TRIG Control Register"
|
|
abitfld.long 0x00 24.--31. "CHAINx_DONE,CHAINx done interrupt detection bit" "0x00=0: CHAIN0 done interrupt bit,0x01=1: CHAIN1 done interrupt bit,0x02=2: CHAIN2 done interrupt bit,0x03=3: CHAIN3 done interrupt bit,0x04=4: CHAIN4 done interrupt bit,0x05=5: CHAIN5 done interrupt bit,0x06=6: CHAIN6 done interrupt bit,0x07=7: CHAIN7 done interrupt The done.."
|
|
bitfld.long 0x00 16. "SYNC_MODE,TRIG mode control" "0: Disable sync mode,1: Enable sync mode"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "TRIG_PRIORITY,External trigger priority 7 is highest 0 is lowest" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "TRIG_CHAIN,TRIG chain length to the ADC" "0: Trig length is 1,?,?,?,?,?,?,7: Trig length is 8"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIG_MODE,TRIG mode register" "0: hardware trigger,1: software trigger"
|
|
bitfld.long 0x00 0. "SW_TRIG,Software write 1 as the TRIGGER" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRIG1_COUNTER,ETC_TRIG Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SAMPLE_INTERVAL,TRIGGER sampling interval counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT_DELAY,TRIGGER initial delay counter"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRIG1_CHAIN_1_0,ETC_TRIG Chain 0/1 Register"
|
|
bitfld.long 0x00 31. "IE1_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE1,CHAIN1 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B1,CHAIN1 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS1,CHAIN1 HWTS ADC hardware trigger selection"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL1,CHAIN1 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE0_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE0,CHAIN0 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
bitfld.long 0x00 12. "B2B0,CHAIN0 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS0,CHAIN0 HWTS ADC hardware trigger selection"
|
|
bitfld.long 0x00 0.--3. "CSEL0,CHAIN0 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRIG1_CHAIN_3_2,ETC_TRIG Chain 2/3 Register"
|
|
bitfld.long 0x00 31. "IE3_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE3,CHAIN3 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B3,CHAIN3 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS3,CHAIN3 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL3,CHAIN3 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE2_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE2,CHAIN2 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B2,CHAIN2 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS2,CHAIN2 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL2,CHAIN2 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRIG1_CHAIN_5_4,ETC_TRIG Chain 4/5 Register"
|
|
bitfld.long 0x00 31. "IE5_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE5,CHAIN5 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B5,CHAIN5 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS5,CHAIN5 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL5,CHAIN5 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE4_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE4,CHAIN4 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B4,CHAIN4 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS4,CHAIN4 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL4,CHAIN4 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRIG1_CHAIN_7_6,ETC_TRIG Chain 6/7 Register"
|
|
bitfld.long 0x00 31. "IE7_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE7,CHAIN7 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B7,CHAIN7 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS7,CHAIN7 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL7,CHAIN7 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE6_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE6,CHAIN6 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B6,CHAIN6 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS6,CHAIN6 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL6,CHAIN6 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRIG1_RESULT_1_0,ETC_TRIG Result Data 1/0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA1,Result DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA0,Result DATA0"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRIG1_RESULT_3_2,ETC_TRIG Result Data 3/2 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA3,Result DATA3"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA2,Result DATA2"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRIG1_RESULT_5_4,ETC_TRIG Result Data 5/4 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA5,Result DATA5"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA4,Result DATA4"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRIG1_RESULT_7_6,ETC_TRIG Result Data 7/6 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA7,Result DATA7"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA6,Result DATA6"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRIG2_CTRL,ETC_TRIG Control Register"
|
|
abitfld.long 0x00 24.--31. "CHAINx_DONE,CHAINx done interrupt detection bit" "0x00=0: CHAIN0 done interrupt bit,0x01=1: CHAIN1 done interrupt bit,0x02=2: CHAIN2 done interrupt bit,0x03=3: CHAIN3 done interrupt bit,0x04=4: CHAIN4 done interrupt bit,0x05=5: CHAIN5 done interrupt bit,0x06=6: CHAIN6 done interrupt bit,0x07=7: CHAIN7 done interrupt The done.."
|
|
bitfld.long 0x00 16. "SYNC_MODE,TRIG mode control" "0: Disable sync mode,1: Enable sync mode"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "TRIG_PRIORITY,External trigger priority 7 is highest 0 is lowest" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "TRIG_CHAIN,TRIG chain length to the ADC" "0: Trig length is 1,?,?,?,?,?,?,7: Trig length is 8"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIG_MODE,TRIG mode register" "0: hardware trigger,1: software trigger"
|
|
bitfld.long 0x00 0. "SW_TRIG,Software write 1 as the TRIGGER" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRIG2_COUNTER,ETC_TRIG Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SAMPLE_INTERVAL,TRIGGER sampling interval counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT_DELAY,TRIGGER initial delay counter"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRIG2_CHAIN_1_0,ETC_TRIG Chain 0/1 Register"
|
|
bitfld.long 0x00 31. "IE1_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE1,CHAIN1 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B1,CHAIN1 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS1,CHAIN1 HWTS ADC hardware trigger selection"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL1,CHAIN1 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE0_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE0,CHAIN0 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
bitfld.long 0x00 12. "B2B0,CHAIN0 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS0,CHAIN0 HWTS ADC hardware trigger selection"
|
|
bitfld.long 0x00 0.--3. "CSEL0,CHAIN0 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRIG2_CHAIN_3_2,ETC_TRIG Chain 2/3 Register"
|
|
bitfld.long 0x00 31. "IE3_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE3,CHAIN3 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B3,CHAIN3 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS3,CHAIN3 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL3,CHAIN3 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE2_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE2,CHAIN2 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B2,CHAIN2 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS2,CHAIN2 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL2,CHAIN2 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRIG2_CHAIN_5_4,ETC_TRIG Chain 4/5 Register"
|
|
bitfld.long 0x00 31. "IE5_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE5,CHAIN5 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B5,CHAIN5 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS5,CHAIN5 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL5,CHAIN5 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE4_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE4,CHAIN4 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B4,CHAIN4 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS4,CHAIN4 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL4,CHAIN4 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRIG2_CHAIN_7_6,ETC_TRIG Chain 6/7 Register"
|
|
bitfld.long 0x00 31. "IE7_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE7,CHAIN7 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B7,CHAIN7 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS7,CHAIN7 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL7,CHAIN7 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE6_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE6,CHAIN6 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B6,CHAIN6 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS6,CHAIN6 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL6,CHAIN6 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRIG2_RESULT_1_0,ETC_TRIG Result Data 1/0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA1,Result DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA0,Result DATA0"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRIG2_RESULT_3_2,ETC_TRIG Result Data 3/2 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA3,Result DATA3"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA2,Result DATA2"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRIG2_RESULT_5_4,ETC_TRIG Result Data 5/4 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA5,Result DATA5"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA4,Result DATA4"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRIG2_RESULT_7_6,ETC_TRIG Result Data 7/6 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA7,Result DATA7"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA6,Result DATA6"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRIG3_CTRL,ETC_TRIG Control Register"
|
|
abitfld.long 0x00 24.--31. "CHAINx_DONE,CHAINx done interrupt detection bit" "0x00=0: CHAIN0 done interrupt bit,0x01=1: CHAIN1 done interrupt bit,0x02=2: CHAIN2 done interrupt bit,0x03=3: CHAIN3 done interrupt bit,0x04=4: CHAIN4 done interrupt bit,0x05=5: CHAIN5 done interrupt bit,0x06=6: CHAIN6 done interrupt bit,0x07=7: CHAIN7 done interrupt The done.."
|
|
bitfld.long 0x00 16. "SYNC_MODE,TRIG mode control" "0: Disable sync mode,1: Enable sync mode"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "TRIG_PRIORITY,External trigger priority 7 is highest 0 is lowest" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "TRIG_CHAIN,TRIG chain length to the ADC" "0: Trig length is 1,?,?,?,?,?,?,7: Trig length is 8"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIG_MODE,TRIG mode register" "0: hardware trigger,1: software trigger"
|
|
bitfld.long 0x00 0. "SW_TRIG,Software write 1 as the TRIGGER" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRIG3_COUNTER,ETC_TRIG Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SAMPLE_INTERVAL,TRIGGER sampling interval counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT_DELAY,TRIGGER initial delay counter"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRIG3_CHAIN_1_0,ETC_TRIG Chain 0/1 Register"
|
|
bitfld.long 0x00 31. "IE1_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE1,CHAIN1 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B1,CHAIN1 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS1,CHAIN1 HWTS ADC hardware trigger selection"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL1,CHAIN1 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE0_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE0,CHAIN0 IE" "0: Finished Interrupt on Done0,1: Finished Interrupt on Done1,2: Finished Interrupt on Done2,3: Finished Interrupt on Done3"
|
|
bitfld.long 0x00 12. "B2B0,CHAIN0 B2B" "0: Disable B2B wait until interval is reached,1: Enable B2B back to back ADC trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS0,CHAIN0 HWTS ADC hardware trigger selection"
|
|
bitfld.long 0x00 0.--3. "CSEL0,CHAIN0 CSEL ADC channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRIG3_CHAIN_3_2,ETC_TRIG Chain 2/3 Register"
|
|
bitfld.long 0x00 31. "IE3_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE3,CHAIN3 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B3,CHAIN3 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS3,CHAIN3 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL3,CHAIN3 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE2_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE2,CHAIN2 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B2,CHAIN2 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS2,CHAIN2 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL2,CHAIN2 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRIG3_CHAIN_5_4,ETC_TRIG Chain 4/5 Register"
|
|
bitfld.long 0x00 31. "IE5_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE5,CHAIN5 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B5,CHAIN5 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS5,CHAIN5 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL5,CHAIN5 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE4_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE4,CHAIN4 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B4,CHAIN4 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS4,CHAIN4 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL4,CHAIN4 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRIG3_CHAIN_7_6,ETC_TRIG Chain 6/7 Register"
|
|
bitfld.long 0x00 31. "IE7_EN,IRQ enable" "0,1"
|
|
bitfld.long 0x00 29.--30. "IE7,CHAIN7 IE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "B2B7,CHAIN7 B2B" "0,1"
|
|
hexmask.long.byte 0x00 20.--27. 1. "HWTS7,CHAIN7 HWTS"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "CSEL7,CHAIN7 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "IE6_EN,IRQ enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "IE6,CHAIN6 IE" "0,1,2,3"
|
|
bitfld.long 0x00 12. "B2B6,CHAIN6 B2B" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "HWTS6,CHAIN6 HWTS"
|
|
bitfld.long 0x00 0.--3. "CSEL6,CHAIN6 CSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRIG3_RESULT_1_0,ETC_TRIG Result Data 1/0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA1,Result DATA1"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA0,Result DATA0"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRIG3_RESULT_3_2,ETC_TRIG Result Data 3/2 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA3,Result DATA3"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA2,Result DATA2"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRIG3_RESULT_5_4,ETC_TRIG Result Data 5/4 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA5,Result DATA5"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA4,Result DATA4"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRIG3_RESULT_7_6,ETC_TRIG Result Data 7/6 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DATA7,Result DATA7"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA6,Result DATA6"
|
|
tree.end
|
|
tree "AOI (AND/OR/INVERT module)"
|
|
base ad:0x40094000
|
|
repeat 4. (strings "010" "011" "012" "013" )(list 0x0 0x4 0x8 0xC )
|
|
group.word ($2+0x00)++0x01
|
|
line.word 0x00 "BFCRT$1,Boolean Function Term 0 and 1 Configuration Register for EVENTn"
|
|
bitfld.word 0x00 14.--15. "PT0_AC,Product term 0 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
|
|
bitfld.word 0x00 12.--13. "PT0_BC,Product term 0 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
|
|
newline
|
|
bitfld.word 0x00 10.--11. "PT0_CC,Product term 0 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
|
|
bitfld.word 0x00 8.--9. "PT0_DC,Product term 0 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
|
|
newline
|
|
bitfld.word 0x00 6.--7. "PT1_AC,Product term 1 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
|
|
bitfld.word 0x00 4.--5. "PT1_BC,Product term 1 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
|
|
newline
|
|
bitfld.word 0x00 2.--3. "PT1_CC,Product term 1 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
|
|
bitfld.word 0x00 0.--1. "PT1_DC,Product term 1 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
|
|
repeat.end
|
|
repeat 4. (strings "230" "231" "232" "233" )(list 0x0 0x4 0x8 0xC )
|
|
group.word ($2+0x02)++0x01
|
|
line.word 0x00 "BFCRT$1,Boolean Function Term 2 and 3 Configuration Register for EVENTn"
|
|
bitfld.word 0x00 14.--15. "PT2_AC,Product term 2 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
|
|
bitfld.word 0x00 12.--13. "PT2_BC,Product term 2 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
|
|
newline
|
|
bitfld.word 0x00 10.--11. "PT2_CC,Product term 2 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
|
|
bitfld.word 0x00 8.--9. "PT2_DC,Product term 2 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
|
|
newline
|
|
bitfld.word 0x00 6.--7. "PT3_AC,Product term 3 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
|
|
bitfld.word 0x00 4.--5. "PT3_BC,Product term 3 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
|
|
newline
|
|
bitfld.word 0x00 2.--3. "PT3_CC,Product term 3 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
|
|
bitfld.word 0x00 0.--1. "PT3_DC,Product term 3 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
|
|
repeat.end
|
|
tree.end
|
|
tree "XBARA (Crossbar Switch)"
|
|
base ad:0x40098000
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SEL0,Crossbar A Select Register 0"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL1,Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL0,Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "SEL1,Crossbar A Select Register 1"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL3,Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL2,Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SEL2,Crossbar A Select Register 2"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL5,Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL4,Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SEL3,Crossbar A Select Register 3"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL7,Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL6,Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SEL4,Crossbar A Select Register 4"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL9,Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL8,Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "SEL5,Crossbar A Select Register 5"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL11,Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL10,Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SEL6,Crossbar A Select Register 6"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL13,Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL12,Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "SEL7,Crossbar A Select Register 7"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL15,Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL14,Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SEL8,Crossbar A Select Register 8"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL17,Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL16,Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "SEL9,Crossbar A Select Register 9"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL19,Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL18,Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "SEL10,Crossbar A Select Register 10"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL21,Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL20,Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "SEL11,Crossbar A Select Register 11"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL23,Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL22,Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SEL12,Crossbar A Select Register 12"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL25,Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL24,Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "SEL13,Crossbar A Select Register 13"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL27,Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL26,Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SEL14,Crossbar A Select Register 14"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL29,Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL28,Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "SEL15,Crossbar A Select Register 15"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL31,Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL30,Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SEL16,Crossbar A Select Register 16"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL33,Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL32,Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "SEL17,Crossbar A Select Register 17"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL35,Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL34,Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SEL18,Crossbar A Select Register 18"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL37,Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL36,Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "SEL19,Crossbar A Select Register 19"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL39,Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL38,Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SEL20,Crossbar A Select Register 20"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL41,Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL40,Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "SEL21,Crossbar A Select Register 21"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL43,Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL42,Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "SEL22,Crossbar A Select Register 22"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL45,Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL44,Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "SEL23,Crossbar A Select Register 23"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL47,Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL46,Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SEL24,Crossbar A Select Register 24"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL49,Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL48,Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "SEL25,Crossbar A Select Register 25"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL51,Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL50,Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SEL26,Crossbar A Select Register 26"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL53,Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL52,Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "SEL27,Crossbar A Select Register 27"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL55,Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL54,Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "SEL28,Crossbar A Select Register 28"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL57,Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL56,Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "SEL29,Crossbar A Select Register 29"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL59,Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL58,Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "SEL30,Crossbar A Select Register 30"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL61,Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL60,Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "SEL31,Crossbar A Select Register 31"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL63,Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL62,Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "SEL32,Crossbar A Select Register 32"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL65,Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL64,Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "SEL33,Crossbar A Select Register 33"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL67,Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL66,Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SEL34,Crossbar A Select Register 34"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL69,Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL68,Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "SEL35,Crossbar A Select Register 35"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL71,Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL70,Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "SEL36,Crossbar A Select Register 36"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL73,Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL72,Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x4A++0x01
|
|
line.word 0x00 "SEL37,Crossbar A Select Register 37"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL75,Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL74,Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "SEL38,Crossbar A Select Register 38"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL77,Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL76,Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x4E++0x01
|
|
line.word 0x00 "SEL39,Crossbar A Select Register 39"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL79,Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL78,Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "SEL40,Crossbar A Select Register 40"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL81,Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL80,Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "SEL41,Crossbar A Select Register 41"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL83,Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL82,Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "SEL42,Crossbar A Select Register 42"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL85,Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL84,Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x56++0x01
|
|
line.word 0x00 "SEL43,Crossbar A Select Register 43"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL87,Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL86,Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "SEL44,Crossbar A Select Register 44"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL89,Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL88,Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x5A++0x01
|
|
line.word 0x00 "SEL45,Crossbar A Select Register 45"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL91,Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL90,Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "SEL46,Crossbar A Select Register 46"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL93,Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL92,Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x5E++0x01
|
|
line.word 0x00 "SEL47,Crossbar A Select Register 47"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL95,Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL94,Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "SEL48,Crossbar A Select Register 48"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL97,Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL96,Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "SEL49,Crossbar A Select Register 49"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL99,Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL98,Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "SEL50,Crossbar A Select Register 50"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL101,Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL100,Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "SEL51,Crossbar A Select Register 51"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL103,Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL102,Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "SEL52,Crossbar A Select Register 52"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL105,Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL104,Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "SEL53,Crossbar A Select Register 53"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL107,Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL106,Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "SEL54,Crossbar A Select Register 54"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL109,Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL108,Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "SEL55,Crossbar A Select Register 55"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL111,Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL110,Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "SEL56,Crossbar A Select Register 56"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL113,Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL112,Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x72++0x01
|
|
line.word 0x00 "SEL57,Crossbar A Select Register 57"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL115,Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL114,Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x74++0x01
|
|
line.word 0x00 "SEL58,Crossbar A Select Register 58"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL117,Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL116,Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x76++0x01
|
|
line.word 0x00 "SEL59,Crossbar A Select Register 59"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL119,Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL118,Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x78++0x01
|
|
line.word 0x00 "SEL60,Crossbar A Select Register 60"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL121,Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL120,Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x7A++0x01
|
|
line.word 0x00 "SEL61,Crossbar A Select Register 61"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL123,Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL122,Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "SEL62,Crossbar A Select Register 62"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL125,Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL124,Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x7E++0x01
|
|
line.word 0x00 "SEL63,Crossbar A Select Register 63"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL127,Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL126,Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "SEL64,Crossbar A Select Register 64"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL129,Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL128,Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "SEL65,Crossbar A Select Register 65"
|
|
hexmask.word.byte 0x00 8.--14. 1. "SEL131,Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment)"
|
|
hexmask.word.byte 0x00 0.--6. 1. "SEL130,Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment)"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "CTRL0,Crossbar A Control Register 0"
|
|
eventfld.word 0x00 12. "STS1,Edge detection status for XBAR_OUT1" "0: Active edge not yet detected on XBAR_OUT1,1: Active edge detected on XBAR_OUT1"
|
|
bitfld.word 0x00 10.--11. "EDGE1,Active edge for edge detection on XBAR_OUT1" "0: STS1 never asserts,1: STS1 asserts on rising edges of XBAR_OUT1,2: STS1 asserts on falling edges of XBAR_OUT1,3: STS1 asserts on rising and falling edges of.."
|
|
newline
|
|
bitfld.word 0x00 9. "IEN1,Interrupt Enable for XBAR_OUT1" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.word 0x00 8. "DEN1,DMA Enable for XBAR_OUT1" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
eventfld.word 0x00 4. "STS0,Edge detection status for XBAR_OUT0" "0: Active edge not yet detected on XBAR_OUT0,1: Active edge detected on XBAR_OUT0"
|
|
bitfld.word 0x00 2.--3. "EDGE0,Active edge for edge detection on XBAR_OUT0" "0: STS0 never asserts,1: STS0 asserts on rising edges of XBAR_OUT0,2: STS0 asserts on falling edges of XBAR_OUT0,3: STS0 asserts on rising and falling edges of.."
|
|
newline
|
|
bitfld.word 0x00 1. "IEN0,Interrupt Enable for XBAR_OUT0" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.word 0x00 0. "DEN0,DMA Enable for XBAR_OUT0" "0: DMA disabled,1: DMA enabled"
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "CTRL1,Crossbar A Control Register 1"
|
|
eventfld.word 0x00 12. "STS3,Edge detection status for XBAR_OUT3" "0: Active edge not yet detected on XBAR_OUT3,1: Active edge detected on XBAR_OUT3"
|
|
bitfld.word 0x00 10.--11. "EDGE3,Active edge for edge detection on XBAR_OUT3" "0: STS3 never asserts,1: STS3 asserts on rising edges of XBAR_OUT3,2: STS3 asserts on falling edges of XBAR_OUT3,3: STS3 asserts on rising and falling edges of.."
|
|
newline
|
|
bitfld.word 0x00 9. "IEN3,Interrupt Enable for XBAR_OUT3" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.word 0x00 8. "DEN3,DMA Enable for XBAR_OUT3" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
eventfld.word 0x00 4. "STS2,Edge detection status for XBAR_OUT2" "0: Active edge not yet detected on XBAR_OUT2,1: Active edge detected on XBAR_OUT2"
|
|
bitfld.word 0x00 2.--3. "EDGE2,Active edge for edge detection on XBAR_OUT2" "0: STS2 never asserts,1: STS2 asserts on rising edges of XBAR_OUT2,2: STS2 asserts on falling edges of XBAR_OUT2,3: STS2 asserts on rising and falling edges of.."
|
|
newline
|
|
bitfld.word 0x00 1. "IEN2,Interrupt Enable for XBAR_OUT2" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.word 0x00 0. "DEN2,DMA Enable for XBAR_OUT2" "0: DMA disabled,1: DMA enabled"
|
|
tree.end
|
|
tree "FLEXSPI (FlexSPI)"
|
|
base ad:0x400A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR0,Module Control Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant"
|
|
hexmask.long.byte 0x00 16.--23. 1. "IPGRANTWAIT,Time out wait cycle for IP command grant"
|
|
newline
|
|
bitfld.long 0x00 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running" "0: SCKFREERUNEN_0,1: SCKFREERUNEN_1"
|
|
bitfld.long 0x00 13. "COMBINATIONEN,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0])" "0: COMBINATIONEN_0,1: COMBINATIONEN_1"
|
|
newline
|
|
bitfld.long 0x00 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled"
|
|
bitfld.long 0x00 11. "HSEN,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "SERCLKDIV,The serial root clock could be divided inside FlexSPI" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
|
|
bitfld.long 0x00 7. "ATDFEN,Enable AHB bus Write Access to IP TX FIFO" "0: IP TX FIFO should be written by IP Bus,1: IP TX FIFO should be written by AHB Bus"
|
|
newline
|
|
bitfld.long 0x00 6. "ARDFEN,Enable AHB bus Read Access to IP RX FIFO" "0: IP RX FIFO should be read by IP Bus,1: IP RX FIFO should be read by AHB Bus"
|
|
bitfld.long 0x00 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,?,3: Flash provided Read strobe and input from DQS.."
|
|
newline
|
|
bitfld.long 0x00 1. "MDIS,Module Disable" "0,1"
|
|
bitfld.long 0x00 0. "SWRESET,Software Reset" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MCR1,Module Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHBBUSWAIT,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles AHB Bus will get an error response"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR2,Module Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed"
|
|
bitfld.long 0x00 19. "SCKBDIFFOPT,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK)" "0: B_SCLK pad is used as port B SCLK clock output,1: B_SCLK pad is used as port A SCLK inverted.."
|
|
newline
|
|
bitfld.long 0x00 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register.."
|
|
bitfld.long 0x00 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CLRAHBBUFOPT,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK" "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AHBCR,AHB Bus Control Register"
|
|
bitfld.long 0x00 10. "READSZALIGN,AHB Read Size Alignment" "0: AHB read size will be decided by other..,1: AHB read size to up size to 8 bytes aligned.."
|
|
bitfld.long 0x00 6. "READADDROPT,AHB Read Address option bit" "0: There is AHB read burst start address..,1: There is no AHB read burst start address.."
|
|
newline
|
|
bitfld.long 0x00 5. "PREFETCHEN,AHB Read Prefetch Enable" "0,1"
|
|
bitfld.long 0x00 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CACHABLEEN,Enable AHB bus cachable read access support" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "CLRAHBTXBUF,Clear the status/pointers of AHB TX Buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CLRAHBRXBUF,Clear the status/pointers of AHB RX Buffer" "0,1"
|
|
bitfld.long 0x00 0. "APAREN,Parallel mode enabled for AHB triggered Command (both read and write)" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "KEYERROREN,OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details" "0,1"
|
|
bitfld.long 0x00 12. "KEYDONEEN,OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details" "0,1"
|
|
bitfld.long 0x00 10. "AHBBUSERROREN,AHB Bus error interrupt enable.Refer Interrupts chapter for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTR,Interrupt Register"
|
|
rbitfld.long 0x00 13. "KEYERROR,OTFAD key blob processing error interrupt" "0,1"
|
|
eventfld.long 0x00 12. "KEYDONE,OTFAD key blob processing done interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 11. "SEQTIMEOUT,Sequence execution timeout interrupt" "0,1"
|
|
eventfld.long 0x00 10. "AHBBUSERROR,AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1"
|
|
eventfld.long 0x00 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 6. "IPTXWE,IP TX FIFO watermark empty interrupt" "0,1"
|
|
eventfld.long 0x00 5. "IPRXWA,IP RX FIFO watermark available interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt" "0,1"
|
|
eventfld.long 0x00 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt" "0,1"
|
|
eventfld.long 0x00 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LUTKEY,LUT Key Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,The Key to lock or unlock LUT"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LUTCR,LUT Control Register"
|
|
bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1"
|
|
bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--25. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--25. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--25. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--25. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FLSHA1CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FLSHA2CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FLSHB1CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FLSHB2CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x70)++0x03
|
|
line.long 0x00 "FLSHCR1A$1,Flash Control Register $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
|
|
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x78)++0x03
|
|
line.long 0x00 "FLSHCR1B$1,Flash Control Register $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
|
|
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "FLSHCR2A$1,Flash Control Register 2"
|
|
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
|
|
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
|
|
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "FLSHCR2B$1,Flash Control Register 2"
|
|
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
|
|
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
|
|
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FLSHCR4,Flash Control Register 4"
|
|
bitfld.long 0x00 3. "WMENB,Write mask enable bit for flash device on port B" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
|
|
bitfld.long 0x00 2. "WMENA,Write mask enable bit for flash device on port A" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "WMOPT1,Write mask option bit 1" "0: DQS pin will be used as Write Mask when..,1: DQS pin will not be used as Write Mask when.."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "IPCR0,IP Control Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "SFAR,Serial Flash Address for IP command"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "IPCR1,IP Control Register 1"
|
|
bitfld.long 0x00 31. "IPAREN,Parallel mode Enabled for IP command" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
|
|
bitfld.long 0x00 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "ISEQID,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "IPCMD,IP Command Register"
|
|
bitfld.long 0x00 0. "TRG,Setting this bit will trigger an IP Command" "0,1"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "IPRXFCR,IP RX FIFO Control Register"
|
|
bitfld.long 0x00 2.--5. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "RXDMAEN,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA"
|
|
newline
|
|
bitfld.long 0x00 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO" "0,1"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "IPTXFCR,IP TX FIFO Control Register"
|
|
bitfld.long 0x00 2.--5. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "TXDMAEN,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA"
|
|
newline
|
|
bitfld.long 0x00 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DLLCRA,DLL Control Register 0"
|
|
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DLLCRB,DLL Control Register 0"
|
|
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "STS0,Status Register 0"
|
|
bitfld.long 0x00 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by..,1: Triggered by AHB write command (triggered by..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)"
|
|
bitfld.long 0x00 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface" "0,1"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "STS1,Status Register 1"
|
|
bitfld.long 0x00 24.--27. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected" "0: IPCMDERRCODE_0,?,2: IP command with JMP_ON_CS instruction used in..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,6: Flash access start address exceed the whole..,?,?,?,?,?,?,?,14: Sequence execution timeout,15: Flash boundary crossed"
|
|
bitfld.long 0x00 16.--19. "IPCMDERRID,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected" "0: AHBCMDERRCODE_0,?,2: AHB Write command with JMP_ON_CS instruction..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,?,?,?,?,?,?,?,?,14: Sequence execution timeout,?..."
|
|
bitfld.long 0x00 0.--3. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "STS2,Status Register 2"
|
|
bitfld.long 0x00 24.--29. "BREFSEL,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18.--23. "BSLVSEL,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17. "BREFLOCK,Flash B sample clock reference delay line locked" "0,1"
|
|
bitfld.long 0x00 16. "BSLVLOCK,Flash B sample clock slave delay line locked" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "AREFSEL,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2.--7. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 1. "AREFLOCK,Flash A sample clock reference delay line locked" "0,1"
|
|
bitfld.long 0x00 0. "ASLVLOCK,Flash A sample clock slave delay line locked" "0,1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)"
|
|
bitfld.long 0x00 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended" "0,1"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP RX FIFO"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP TX FIFO"
|
|
repeat 32. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x100)++0x03
|
|
line.long 0x00 "RFDR[$1],IP RX FIFO Data Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
|
|
repeat.end
|
|
repeat 32. (increment 0 1) (increment 0 0x04)
|
|
wgroup.long ($2+0x180)++0x03
|
|
line.long 0x00 "TFDR[$1],IP TX FIFO Data Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data"
|
|
repeat.end
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "LUT[$1],LUT 0"
|
|
bitfld.long 0x00 26.--31. "OPCODE1,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OPERAND1,OPERAND1"
|
|
bitfld.long 0x00 10.--15. "OPCODE0,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OPERAND0,OPERAND0"
|
|
repeat.end
|
|
tree.end
|
|
tree "OTFAD"
|
|
base ad:0x400A0000
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 31. "GE,Global OTFAD Enable" "0: OTFAD has decryption disabled,1: OTFAD has decryption enabled and processes.."
|
|
bitfld.long 0x00 30. "SKBP,Start key blob processing" "0: Key blob processing is not initiated,1: Properly-enabled key blob processing is.."
|
|
newline
|
|
bitfld.long 0x00 7. "RRAE,Restricted Register Access Enable" "0: Register access is fully enabled,1: Register access is restricted and only the CR.."
|
|
bitfld.long 0x00 6. "KBCE,Key Blob CRC Enable" "0: CRC-32 during key blob processing is disabled,1: CRC-32 during key blob processing is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "KBPE,Key Blob Processing Enable" "0: Key blob processing is disabled,1: Key blob processing is enabled"
|
|
bitfld.long 0x00 4. "KBSE,Key Blob Scramble Enable" "0: Key blob KEK scrambling is disabled,1: Key blob KEK scrambling is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FLDM,Force Logically Disabled Mode" "0: No effect on the operating mode,1: Force entry into LDM after a write with this.."
|
|
bitfld.long 0x00 2. "FSVM,Force Security Violation Mode" "0: No effect on the operating mode,1: Force entry into SVM after a write with this.."
|
|
newline
|
|
bitfld.long 0x00 1. "FERR,Force Error" "0: No effect on the SR[KBERE] indicator,1: SR[KBERR] is immediately set after a write.."
|
|
bitfld.long 0x00 0. "IRQE,IRQE" "0: SR[KBERR] = 1 does not generate an interrupt..,1: SR[KBERR] = 1 generates an interrupt request"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 31. "KBD,Key Blob Processing Done" "0: Key blob processing was not enabled or is not..,1: Key blob processing was enabled and is complete"
|
|
rbitfld.long 0x00 30. "KBPE,Key Blob Processing Enable" "0: Key blob processing is not enabled,1: Key blob processing is enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "GEM,Global Enable Mode" "0: OTFAD is disabled,1: OTFAD is enabled and processes data fetched.."
|
|
rbitfld.long 0x00 28. "RRAM,Restricted Register Access Mode" "0: Register access is fully enabled,1: Register access is restricted and only the CR.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 19. "CTXIE3,Context Integrity Error" "0: No key blob integrity error was detected for..,1: A key blob integrity error was detected in.."
|
|
newline
|
|
rbitfld.long 0x00 18. "CTXIE2,Context Integrity Error" "0: No key blob integrity error was detected for..,1: A key blob integrity error was detected in.."
|
|
rbitfld.long 0x00 17. "CTXIE1,Context Integrity Error" "0: No key blob integrity error was detected for..,1: A key blob integrity error was detected in.."
|
|
newline
|
|
rbitfld.long 0x00 16. "CTXIE0,Context Integrity Error" "0: No key blob integrity error was detected for..,1: A key blob integrity error was detected in.."
|
|
rbitfld.long 0x00 11. "CTXER3,Context Error" "0: No key blob error was detected for context n,1: Either a key blob integrity error or a key.."
|
|
newline
|
|
rbitfld.long 0x00 10. "CTXER2,Context Error" "0: No key blob error was detected for context n,1: Either a key blob integrity error or a key.."
|
|
rbitfld.long 0x00 9. "CTXER1,Context Error" "0: No key blob error was detected for context n,1: Either a key blob integrity error or a key.."
|
|
newline
|
|
rbitfld.long 0x00 8. "CTXER0,Context Error" "0: No key blob error was detected for context n,1: Either a key blob integrity error or a key.."
|
|
rbitfld.long 0x00 4.--7. "NCTX,Number of Contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 2.--3. "MODE,Operating Mode" "0: Operating in Normal mode (NRM),1: Unused (reserved),2: Operating in Security Violation Mode (SVM),3: Operating in Logically Disabled Mode (LDM)"
|
|
rbitfld.long 0x00 1. "MDPCP,MDPC Present" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "KBERR,Key Blob Error" "0: No key blob error detected,1: One or more key blob errors has been detected"
|
|
repeat 4. (increment 0 1)(increment 0 0x40)
|
|
tree "CTX[$1]"
|
|
group.long ($2+0xD00)++0x03
|
|
line.long 0x00 "CTX_KEY0,AES Key Word"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
|
|
group.long ($2+0xD04)++0x03
|
|
line.long 0x00 "CTX_KEY1,AES Key Word"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
|
|
group.long ($2+0xD08)++0x03
|
|
line.long 0x00 "CTX_KEY2,AES Key Word"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
|
|
group.long ($2+0xD0C)++0x03
|
|
line.long 0x00 "CTX_KEY3,AES Key Word"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
|
|
group.long ($2+0xD10)++0x03
|
|
line.long 0x00 "CTX_CTR0,AES Counter Word"
|
|
hexmask.long 0x00 0.--31. 1. "CTR,AES Counter"
|
|
group.long ($2+0xD14)++0x03
|
|
line.long 0x00 "CTX_CTR1,AES Counter Word"
|
|
hexmask.long 0x00 0.--31. 1. "CTR,AES Counter"
|
|
group.long ($2+0xD18)++0x03
|
|
line.long 0x00 "CTX_RGD_W0,AES Region Descriptor Word0"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "SRTADDR,Start Address"
|
|
group.long ($2+0xD1C)++0x03
|
|
line.long 0x00 "CTX_RGD_W1,AES Region Descriptor Word1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "ENDADDR,End Address"
|
|
bitfld.long 0x00 2. "RO,Read-Only" "0: The context registers can be accessed..,1: The context registers are read-only and.."
|
|
newline
|
|
bitfld.long 0x00 1. "ADE,AES Decryption Enable" "0: Bypass the fetched data,1: Perform the CTR-AES128 mode decryption on the.."
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Context is invalid,1: Context is valid"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "IOMUXC_SNVS_GPR (IOMUXC)"
|
|
base ad:0x400A4000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "GPR0,GPR0 General Purpose Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "GPR1,GPR1 General Purpose Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "GPR2,GPR2 General Purpose Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPR3,GPR3 General Purpose Register"
|
|
rbitfld.long 0x00 19. "DCDC_STS_DC_OK,DCDC status OK" "0,1"
|
|
rbitfld.long 0x00 18. "DCDC_OVER_VOL,DCDC output over voltage alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "DCDC_OVER_CUR,DCDC output over current alert" "0,1"
|
|
rbitfld.long 0x00 16. "DCDC_IN_LOW_VOL,DCDC_IN low voltage detect" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "POR_PULL_TYPE,POR_B pad control" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DCDC_STATUS_CAPT_CLR,DCDC captured status clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LPSR_MODE_ENABLE,Set to enable LPSR mode" "0,1"
|
|
tree.end
|
|
tree "IOMUXC_SNVS"
|
|
base ad:0x400A8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_PMIC_ON_REQ,SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad PMIC_ON_REQ"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,?,5: Select mux mode,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_TEST_MODE,SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register"
|
|
bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
|
bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
rbitfld.long 0x00 6.--7. "SPEED,Speed Field" "?,?,2: medium(100MHz),?..."
|
|
newline
|
|
bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1: DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_POR_B,SW_PAD_CTL_PAD_POR_B SW PAD Control Register"
|
|
bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
|
bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
rbitfld.long 0x00 6.--7. "SPEED,Speed Field" "?,?,2: medium(100MHz),?..."
|
|
newline
|
|
bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1: DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_ONOFF,SW_PAD_CTL_PAD_ONOFF SW PAD Control Register"
|
|
bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
|
bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
rbitfld.long 0x00 6.--7. "SPEED,Speed Field" "?,?,2: medium(100MHz),?..."
|
|
newline
|
|
bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1: DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_PMIC_ON_REQ,SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register"
|
|
bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
|
bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
rbitfld.long 0x00 6.--7. "SPEED,Speed Field" "?,?,2: medium(100MHz),?..."
|
|
newline
|
|
bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1: DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
tree.end
|
|
tree "IOMUXC_GPR (IOMUX Controller General Purpose Registers)"
|
|
base ad:0x400AC000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "GPR0,GPR0 General Purpose Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPR1,GPR1 General Purpose Register"
|
|
bitfld.long 0x00 31. "CM7_FORCE_HCLK_EN,ARM CM7 platform AHB clock enable" "0: AHB clock is not running (gated) when CM7 is..,1: AHB clock is running (enabled) when CM7 is.."
|
|
bitfld.long 0x00 22. "EXC_MON,Exclusive monitor response select of illegal command" "0: OKAY response,1: SLVError response"
|
|
newline
|
|
bitfld.long 0x00 21. "SAI3_MCLK_DIR,sai3.MCLK signal direction control" "0: sai3.MCLK is input signal,1: sai3.MCLK is output signal"
|
|
bitfld.long 0x00 19. "SAI1_MCLK_DIR,sai1.MCLK signal direction control" "0: sai1.MCLK is input signal,1: sai1.MCLK is output signal"
|
|
newline
|
|
bitfld.long 0x00 12. "GINT,Global Interrupt" "0: Global interrupt request is not asserted,1: Global interrupt request is asserted"
|
|
bitfld.long 0x00 10.--11. "SAI3_MCLK3_SEL,SAI3 MCLK3 source select" "0: ccm.spdif0_clk_root,1: SAI3_MCLK3_SEL_1,2: spdif.spdif_srclk,3: spdif.spdif_outclock"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SAI1_MCLK3_SEL,SAI1 MCLK3 source select" "0: ccm.spdif0_clk_root,1: SAI1_MCLK3_SEL_1,2: spdif.spdif_srclk,3: spdif.spdif_outclock"
|
|
bitfld.long 0x00 3.--5. "SAI1_MCLK2_SEL,SAI1 MCLK2 source select" "0: ccm.ssi1_clk_root,?,2: ccm.ssi3_clk_root,3: iomux.sai1_ipg_clk_sai_mclk,?,5: iomux.sai3_ipg_clk_sai_mclk,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SAI1_MCLK1_SEL,SAI1 MCLK1 source select" "0: ccm.ssi1_clk_root,?,2: ccm.ssi3_clk_root,3: iomux.sai1_ipg_clk_sai_mclk,?,5: iomux.sai3_ipg_clk_sai_mclk,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPR2,GPR2 General Purpose Register"
|
|
bitfld.long 0x00 26. "MQS_OVERSAMPLE,Medium Quality Sound (MQS) Oversample" "0: MQS_OVERSAMPLE_0,1: MQS_OVERSAMPLE_1"
|
|
bitfld.long 0x00 25. "MQS_EN,MQS enable" "0: Disable MQS,1: Enable MQS"
|
|
newline
|
|
bitfld.long 0x00 24. "MQS_SW_RST,MQS software reset" "0: Exit software reset for MQS,1: Enable software reset for MQS"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MQS_CLK_DIV,Divider ratio control for mclk from hmclk"
|
|
newline
|
|
bitfld.long 0x00 14. "L2_MEM_DEEPSLEEP,This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power but maintain memory contents outputs of memory are pulled low" "0: No force sleep control supported memory deep..,1: Force memory into deep sleep mode (OCRAM in.."
|
|
bitfld.long 0x00 13. "RAM_AUTO_CLK_GATING_EN,Automatically gate off RAM clock when RAM is not accessed" "0: disable automatically gate off RAM clock,1: enable automatically gate off RAM clock"
|
|
newline
|
|
bitfld.long 0x00 12. "L2_MEM_EN_POWERSAVING,Enable power saving features on L2 memory" "0: Enters power saving mode only when chip is in..,1: Controlled by L2_MEM_DEEPSLEEP bitfield"
|
|
bitfld.long 0x00 5. "AXBS_P_FORCE_ROUND_ROBIN,Force Round Robin in AXBS_P" "0: AXBS_P masters are not arbitored in round..,1: AXBS_P masters are arbitored in round robin"
|
|
newline
|
|
bitfld.long 0x00 4. "AXBS_P_M1_HIGH_PRIORITY,AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority" "0: AXBS_P M1 master does not have high priority,1: AXBS_P M1 master has high priority"
|
|
bitfld.long 0x00 3. "AXBS_P_M0_HIGH_PRIORITY,AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority" "0: AXBS_P M0 master doesn't have high priority,1: AXBS_P M0 master has high priority"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPR3,GPR3 General Purpose Register"
|
|
bitfld.long 0x00 4. "DCP_KEY_SEL,Select 128-bit DCP key from 256-bit key from SNVS Master Key" "0: Select [127:0] from SNVS Master Key as DCP key,1: Select [255:128] from SNVS Master Key as DCP.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPR4,GPR4 General Purpose Register"
|
|
rbitfld.long 0x00 28. "FLEXIO1_STOP_ACK,FLEXIO1 stop acknowledge" "0: FLEXIO1 stop acknowledge is not asserted,1: FLEXIO1 stop acknowledge is asserted"
|
|
rbitfld.long 0x00 27. "FLEXSPI_STOP_ACK,FLEXSPI stop acknowledge" "0: FLEXSPI stop acknowledge is not asserted,1: FLEXSPI stop acknowledge is asserted"
|
|
newline
|
|
rbitfld.long 0x00 26. "PIT_STOP_ACK,PIT stop acknowledge" "0: PIT stop acknowledge is not asserted,1: PIT stop acknowledge is asserted"
|
|
rbitfld.long 0x00 23. "SAI3_STOP_ACK,SAI3 stop acknowledge" "0: SAI3 stop acknowledge is not asserted,1: SAI3 stop acknowledge is asserted"
|
|
newline
|
|
rbitfld.long 0x00 21. "SAI1_STOP_ACK,SAI1 stop acknowledge" "0: SAI1 stop acknowledge is not asserted,1: SAI1 stop acknowledge is asserted"
|
|
rbitfld.long 0x00 19. "TRNG_STOP_ACK,TRNG stop acknowledge" "0: TRNG stop acknowledge is not asserted,1: TRNG stop acknowledge is asserted"
|
|
newline
|
|
rbitfld.long 0x00 16. "EDMA_STOP_ACK,EDMA stop acknowledge" "0: EDMA stop acknowledge is not asserted,1: EDMA stop acknowledge is asserted (EDMA is in.."
|
|
bitfld.long 0x00 12. "FLEXIO1_STOP_REQ,FlexIO1 stop request" "0: FLEXIO1_STOP_REQ_0,1: FLEXIO1_STOP_REQ_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLEXSPI_STOP_REQ,FlexSPI stop request" "0: FLEXSPI_STOP_REQ_0,1: FLEXSPI_STOP_REQ_1"
|
|
bitfld.long 0x00 10. "PIT_STOP_REQ,PIT stop request" "0: stop request off,1: stop request on"
|
|
newline
|
|
bitfld.long 0x00 7. "SAI3_STOP_REQ,SAI3 stop request" "0: stop request off,1: SAI3_STOP_REQ_1"
|
|
bitfld.long 0x00 5. "SAI1_STOP_REQ,SAI1 stop request" "0: stop request off,1: SAI1_STOP_REQ_1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRNG_STOP_REQ,TRNG stop request" "0: stop request off,1: TRNG_STOP_REQ_1"
|
|
bitfld.long 0x00 0. "EDMA_STOP_REQ,EDMA stop request" "0: stop request off,1: EDMA_STOP_REQ_1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPR5,GPR5 General Purpose Register"
|
|
bitfld.long 0x00 29. "VREF_1M_CLK_GPT2,GPT2 1 MHz clock source select" "0: GPT2 ipg_clk_highfreq driven by IPG_PERCLK,1: GPT2 ipg_clk_highfreq driven by anatop 1 MHz.."
|
|
bitfld.long 0x00 28. "VREF_1M_CLK_GPT1,GPT1 1 MHz clock source select" "0: GPT1 ipg_clk_highfreq driven by IPG_PERCLK,1: GPT1 ipg_clk_highfreq driven by anatop 1 MHz.."
|
|
newline
|
|
bitfld.long 0x00 7. "WDOG2_MASK,WDOG2 Timeout Mask" "0: WDOG2 Timeout behaves normally,1: WDOG2 Timeout is masked"
|
|
bitfld.long 0x00 6. "WDOG1_MASK,WDOG1 Timeout Mask" "0: WDOG1 Timeout behaves normally,1: WDOG1 Timeout is masked"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPR6,GPR6 General Purpose Register"
|
|
bitfld.long 0x00 17. "IOMUXC_XBAR_DIR_SEL_3,IOMUXC XBAR_INOUT3 function direction select" "0: IOMUXC_XBAR_DIR_SEL_3_0,1: IOMUXC_XBAR_DIR_SEL_3_1"
|
|
bitfld.long 0x00 16. "IOMUXC_XBAR_DIR_SEL_2,IOMUXC XBAR_INOUT2 function direction select" "0: IOMUXC_XBAR_DIR_SEL_2_0,1: IOMUXC_XBAR_DIR_SEL_2_1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPR7,GPR7 General Purpose Register"
|
|
rbitfld.long 0x00 27. "LPUART4_STOP_ACK,LPUART4 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
rbitfld.long 0x00 26. "LPUART3_STOP_ACK,LPUART3 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
newline
|
|
rbitfld.long 0x00 25. "LPUART2_STOP_ACK,LPUART1 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
rbitfld.long 0x00 24. "LPUART1_STOP_ACK,LPUART1 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
newline
|
|
rbitfld.long 0x00 21. "LPSPI2_STOP_ACK,LPSPI2 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
rbitfld.long 0x00 20. "LPSPI1_STOP_ACK,LPSPI1 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
newline
|
|
rbitfld.long 0x00 17. "LPI2C2_STOP_ACK,LPI2C2 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted"
|
|
rbitfld.long 0x00 16. "LPI2C1_STOP_ACK,LPI2C1 stop acknowledge" "0: stop acknowledge is not asserted,1: stop acknowledge is asserted (the module is.."
|
|
newline
|
|
bitfld.long 0x00 11. "LPUART4_STOP_REQ,LPUART4 stop request" "0: LPUART4_STOP_REQ_0,1: LPUART4_STOP_REQ_1"
|
|
bitfld.long 0x00 10. "LPUART3_STOP_REQ,LPUART3 stop request" "0: LPUART3_STOP_REQ_0,1: LPUART3_STOP_REQ_1"
|
|
newline
|
|
bitfld.long 0x00 9. "LPUART2_STOP_REQ,LPUART1 stop request" "0: LPUART2_STOP_REQ_0,1: LPUART2_STOP_REQ_1"
|
|
bitfld.long 0x00 8. "LPUART1_STOP_REQ,LPUART1 stop request" "0: LPUART1_STOP_REQ_0,1: LPUART1_STOP_REQ_1"
|
|
newline
|
|
bitfld.long 0x00 5. "LPSPI2_STOP_REQ,LPSPI2 stop request" "0: LPSPI2_STOP_REQ_0,1: LPSPI2_STOP_REQ_1"
|
|
bitfld.long 0x00 4. "LPSPI1_STOP_REQ,LPSPI1 stop request" "0: LPSPI1_STOP_REQ_0,1: LPSPI1_STOP_REQ_1"
|
|
newline
|
|
bitfld.long 0x00 1. "LPI2C2_STOP_REQ,LPI2C2 stop request" "0: LPI2C2_STOP_REQ_0,1: LPI2C2_STOP_REQ_1"
|
|
bitfld.long 0x00 0. "LPI2C1_STOP_REQ,LPI2C1 stop request" "0: LPI2C1_STOP_REQ_0,1: LPI2C1_STOP_REQ_1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPR8,GPR8 General Purpose Register"
|
|
bitfld.long 0x00 23. "LPUART4_IPG_DOZE,LPUART4 ipg_doze mode" "0: LPUART4_IPG_DOZE_0,1: LPUART4_IPG_DOZE_1"
|
|
bitfld.long 0x00 22. "LPUART4_IPG_STOP_MODE,LPUART4 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
newline
|
|
bitfld.long 0x00 21. "LPUART3_IPG_DOZE,LPUART3 ipg_doze mode" "0: LPUART3_IPG_DOZE_0,1: LPUART3_IPG_DOZE_1"
|
|
bitfld.long 0x00 20. "LPUART3_IPG_STOP_MODE,LPUART3 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
newline
|
|
bitfld.long 0x00 19. "LPUART2_IPG_DOZE,LPUART2 ipg_doze mode" "0: LPUART2_IPG_DOZE_0,1: LPUART2_IPG_DOZE_1"
|
|
bitfld.long 0x00 18. "LPUART2_IPG_STOP_MODE,LPUART2 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
newline
|
|
bitfld.long 0x00 17. "LPUART1_IPG_DOZE,LPUART1 ipg_doze mode" "0: LPUART1_IPG_DOZE_0,1: LPUART1_IPG_DOZE_1"
|
|
bitfld.long 0x00 16. "LPUART1_IPG_STOP_MODE,LPUART1 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
newline
|
|
bitfld.long 0x00 11. "LPSPI2_IPG_DOZE,LPSPI2 ipg_doze mode" "0: LPSPI2_IPG_DOZE_0,1: LPSPI2_IPG_DOZE_1"
|
|
bitfld.long 0x00 10. "LPSPI2_IPG_STOP_MODE,LPSPI2 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
newline
|
|
bitfld.long 0x00 9. "LPSPI1_IPG_DOZE,LPSPI1 ipg_doze mode" "0: LPSPI1_IPG_DOZE_0,1: LPSPI1_IPG_DOZE_1"
|
|
bitfld.long 0x00 8. "LPSPI1_IPG_STOP_MODE,LPSPI1 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
newline
|
|
bitfld.long 0x00 3. "LPI2C2_IPG_DOZE,LPI2C2 ipg_doze mode" "0: LPI2C2_IPG_DOZE_0,1: LPI2C2_IPG_DOZE_1"
|
|
bitfld.long 0x00 2. "LPI2C2_IPG_STOP_MODE,LPI2C2 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
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|
newline
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|
bitfld.long 0x00 1. "LPI2C1_IPG_DOZE,LPI2C1 ipg_doze mode" "0: LPI2C1_IPG_DOZE_0,1: LPI2C1_IPG_DOZE_1"
|
|
bitfld.long 0x00 0. "LPI2C1_IPG_STOP_MODE,LPI2C1 stop mode selection cannot change when ipg_stop is asserted" "0: the module is functional in Stop mode,1: the module is NOT functional in Stop mode.."
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "GPR9,GPR9 General Purpose Register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GPR10,GPR10 General Purpose Register"
|
|
bitfld.long 0x00 25.--29. "LOCK_OCRAM_TZ_ADDR,Lock OCRAM_TZ_ADDR field for changes" "0: LOCK_OCRAM_TZ_ADDR_0,1: Field is locked (read access only),?..."
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|
bitfld.long 0x00 24. "LOCK_OCRAM_TZ_EN,Lock OCRAM_TZ_EN field for changes" "0: Field is not locked,1: Field is locked (read access only)"
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|
newline
|
|
bitfld.long 0x00 20. "LOCK_DCPKEY_OCOTP_OR_KEYMUX,Lock DCP Key OCOTP/Key MUX selection bit" "0: LOCK_DCPKEY_OCOTP_OR_KEYMUX_0,1: Field is locked (read access only)"
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|
bitfld.long 0x00 18. "LOCK_SEC_ERR_RESP,Lock SEC_ERR_RESP field for changes" "0: LOCK_SEC_ERR_RESP_0,1: Field is locked (read access only)"
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|
newline
|
|
bitfld.long 0x00 17. "LOCK_DBG_EN,Lock DBG_EN field for changes" "0: Field is not locked,1: Field is locked (read access only)"
|
|
bitfld.long 0x00 16. "LOCK_NIDEN,Lock NIDEN field for changes" "0: Field is not locked,1: Field is locked (read access only)"
|
|
newline
|
|
bitfld.long 0x00 9.--13. "OCRAM_TZ_ADDR,OCRAM TrustZone (TZ) start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8. "OCRAM_TZ_EN,OCRAM TrustZone (TZ) enable" "0: The TrustZone feature is disabled,1: The TrustZone feature is enabled"
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|
newline
|
|
bitfld.long 0x00 4. "DCPKEY_OCOTP_OR_KEYMUX,DCP Key selection bit" "0: Select key from SNVS Master Key,1: Select key from OCOTP (SW_GP2)"
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|
bitfld.long 0x00 2. "SEC_ERR_RESP,Security error response enable for all security gaskets (on both AHB and AXI buses)" "0: SEC_ERR_RESP_0,1: SLVError (default)"
|
|
newline
|
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bitfld.long 0x00 1. "DBG_EN,ARM invasive debug enable" "0: Debug turned off,1: Debug enabled (default)"
|
|
bitfld.long 0x00 0. "NIDEN,ARM non-secure (non-invasive) debug enable" "0: Debug turned off,1: Debug enabled (default)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPR11,GPR11 General Purpose Register"
|
|
bitfld.long 0x00 22.--23. "LOCK_M7_APC_AC_R3_CTRL,Lock M7_APC_AC_R3_CTRL field for changes" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "LOCK_M7_APC_AC_R2_CTRL,Lock M7_APC_AC_R2_CTRL field for changes" "0,1,2,3"
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newline
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bitfld.long 0x00 18.--19. "LOCK_M7_APC_AC_R1_CTRL,Lock M7_APC_AC_R1_CTRL field for changes" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "LOCK_M7_APC_AC_R0_CTRL,Lock M7_APC_AC_R0_CTRL field for changes" "0,1,2,3"
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|
newline
|
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bitfld.long 0x00 6.--7. "M7_APC_AC_R3_CTRL,Access control of memory region-3" "0: No access protection,1: M7 debug protection enabled,?..."
|
|
bitfld.long 0x00 4.--5. "M7_APC_AC_R2_CTRL,Access control of memory region-2" "0: No access protection,1: M7 debug protection enabled,?..."
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|
newline
|
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bitfld.long 0x00 2.--3. "M7_APC_AC_R1_CTRL,Access control of memory region-1" "0: No access protection,1: M7 debug protection enabled,?..."
|
|
bitfld.long 0x00 0.--1. "M7_APC_AC_R0_CTRL,Access control of memory region-0" "0: No access protection,1: M7 debug protection enabled,?..."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPR12,GPR12 General Purpose Register"
|
|
bitfld.long 0x00 1. "FLEXIO1_IPG_DOZE,FLEXIO1 ipg_doze mode" "0: FLEXIO1 is not in doze mode,1: FLEXIO1 is in doze mode"
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|
bitfld.long 0x00 0. "FLEXIO1_IPG_STOP_MODE,FlexIO1 stop mode selection" "0: FlexIO1 is functional in Stop mode,1: When this bit is equal to 1'b1 and ipg_stop.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPR13,GPR13 General Purpose Register"
|
|
bitfld.long 0x00 13. "CACHE_USB,USB block cacheable attribute value of AXI transactions" "0: Cacheable attribute is off for read/write..,1: Cacheable attribute is on for read/write.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPR14,GPR14 General Purpose Register"
|
|
bitfld.long 0x00 20.--23. "CM7_CFGDTCMSZ,DTCM total size configuration" "0: CM7_CFGDTCMSZ_0,?,?,3: CM7_CFGDTCMSZ_3,4: CM7_CFGDTCMSZ_4,5: CM7_CFGDTCMSZ_5,6: CM7_CFGDTCMSZ_6,7: CM7_CFGDTCMSZ_7,8: CM7_CFGDTCMSZ_8,?..."
|
|
bitfld.long 0x00 16.--19. "CM7_CFGITCMSZ,ITCM total size configuration" "0: CM7_CFGITCMSZ_0,?,?,3: CM7_CFGITCMSZ_3,4: CM7_CFGITCMSZ_4,5: CM7_CFGITCMSZ_5,6: CM7_CFGITCMSZ_6,7: CM7_CFGITCMSZ_7,8: CM7_CFGITCMSZ_8,?..."
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "GPR15,GPR15 General Purpose Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPR16,GPR16 General Purpose Register"
|
|
hexmask.long 0x00 7.--31. 1. "CM7_INIT_VTOR,Vector table offset register out of reset"
|
|
bitfld.long 0x00 6. "LOCK_VTOR,Lock CM7_INIT_VTOR field for changes" "0: CM7_INIT_VTOR field is not locked,1: CM7_INIT_VTOR field is locked (read access.."
|
|
newline
|
|
bitfld.long 0x00 2. "FLEXRAM_BANK_CFG_SEL,FlexRAM bank config source select" "0: use fuse value to config,1: use FLEXRAM_BANK_CFG to config"
|
|
bitfld.long 0x00 1. "INIT_DTCM_EN,DTCM enable initialization out of reset" "0: DTCM is disabled,1: DTCM is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "INIT_ITCM_EN,ITCM enable initialization out of reset" "0: ITCM is disabled,1: ITCM is enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPR17,GPR17 General Purpose Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FLEXRAM_BANK_CFG,FlexRAM bank config value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPR18,GPR18 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R0_BOT,APC end address of memory region-0"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R0_BOT,lock M7_APC_AC_R0_BOT field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPR19,GPR19 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R0_TOP,APC start address of memory region-0"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R0_TOP,lock M7_APC_AC_R0_TOP field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GPR20,GPR20 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R1_BOT,APC end address of memory region-1"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R1_BOT,lock M7_APC_AC_R1_BOT field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPR21,GPR21 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R1_TOP,APC start address of memory region-1"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R1_TOP,lock M7_APC_AC_R1_TOP field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GPR22,GPR22 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R2_BOT,APC end address of memory region-2"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R2_BOT,lock M7_APC_AC_R2_BOT field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GPR23,GPR23 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R2_TOP,APC start address of memory region-2"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R2_TOP,lock M7_APC_AC_R2_TOP field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GPR24,GPR24 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R3_BOT,APC end address of memory region-3"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R3_BOT,lock M7_APC_AC_R3_BOT field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "GPR25,GPR25 General Purpose Register"
|
|
hexmask.long 0x00 3.--31. 1. "M7_APC_AC_R3_TOP,APC start address of memory region-3"
|
|
bitfld.long 0x00 0. "LOCK_M7_APC_AC_R3_TOP,lock M7_APC_AC_R3_TOP field for changes" "0: Register field [31:1] is not locked,1: Register field [31:1] is locked (read access.."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "GPR26,GPR26 General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "GPIO_SEL,Select GPIO1 or GPIO2"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "GPR27,GPR27 General Purpose Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "FLEXSPI_REMAP_ADDR_START,Start address of flexspi1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "GPR28,GPR28 General Purpose Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "FLEXSPI_REMAP_ADDR_END,End address of flexspi1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "GPR29,GPR29 General Purpose Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "FLEXSPI_REMAP_ADDR_OFFSET,Offset address of flexspi1"
|
|
tree.end
|
|
tree "FLEXRAM"
|
|
base ad:0x400B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCM_CTRL,TCM CRTL Register"
|
|
bitfld.long 0x00 2. "FORCE_CLK_ON,Force RAM Clock Always On" "0,1"
|
|
bitfld.long 0x00 1. "TCM_RWAIT_EN,TCM Read Wait Mode Enable" "0: TCM read fast mode,1: TCM read wait mode"
|
|
newline
|
|
bitfld.long 0x00 0. "TCM_WWAIT_EN,TCM Write Wait Mode Enable" "0: TCM write fast mode,1: TCM write wait mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OCRAM_MAGIC_ADDR,OCRAM Magic Address Register"
|
|
hexmask.long.word 0x00 1.--14. 1. "OCRAM_MAGIC_ADDR,OCRAM Magic Address"
|
|
bitfld.long 0x00 0. "OCRAM_WR_RD_SEL,OCRAM Write Read Select" "0: When OCRAM read access hits magic address it..,1: When OCRAM write access hits magic address it.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DTCM_MAGIC_ADDR,DTCM Magic Address Register"
|
|
hexmask.long.word 0x00 1.--14. 1. "DTCM_MAGIC_ADDR,DTCM Magic Address"
|
|
bitfld.long 0x00 0. "DTCM_WR_RD_SEL,DTCM Write Read Select" "0: When DTCM read access hits magic address it..,1: When DTCM write access hits magic address it.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ITCM_MAGIC_ADDR,ITCM Magic Address Register"
|
|
hexmask.long.word 0x00 1.--14. 1. "ITCM_MAGIC_ADDR,ITCM Magic Address"
|
|
bitfld.long 0x00 0. "ITCM_WR_RD_SEL,ITCM Write Read Select" "0: When ITCM read access hits magic address it..,1: When ITCM write access hits magic address it.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INT_STATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 5. "OCRAM_ERR_STATUS,OCRAM Access Error Status" "0: OCRAM access error does not happen,1: OCRAM access error happens"
|
|
eventfld.long 0x00 4. "DTCM_ERR_STATUS,DTCM Access Error Status" "0: DTCM access error does not happen,1: DTCM access error happens"
|
|
newline
|
|
eventfld.long 0x00 3. "ITCM_ERR_STATUS,ITCM Access Error Status" "0: ITCM access error does not happen,1: ITCM access error happens"
|
|
eventfld.long 0x00 2. "OCRAM_MAM_STATUS,OCRAM Magic Address Match Status" "0: OCRAM did not access magic address,1: OCRAM accessed magic address"
|
|
newline
|
|
eventfld.long 0x00 1. "DTCM_MAM_STATUS,DTCM Magic Address Match Status" "0: DTCM did not access magic address,1: DTCM accessed magic address"
|
|
eventfld.long 0x00 0. "ITCM_MAM_STATUS,ITCM Magic Address Match Status" "0: ITCM did not access magic address,1: ITCM accessed magic address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INT_STAT_EN,Interrupt Status Enable Register"
|
|
bitfld.long 0x00 5. "OCRAM_ERR_STAT_EN,OCRAM Access Error Status Enable" "0: OCRAM_ERR_STAT_EN_0,1: OCRAM_ERR_STAT_EN_1"
|
|
bitfld.long 0x00 4. "DTCM_ERR_STAT_EN,DTCM Access Error Status Enable" "0: DTCM_ERR_STAT_EN_0,1: DTCM_ERR_STAT_EN_1"
|
|
newline
|
|
bitfld.long 0x00 3. "ITCM_ERR_STAT_EN,ITCM Access Error Status Enable" "0: ITCM_ERR_STAT_EN_0,1: ITCM_ERR_STAT_EN_1"
|
|
bitfld.long 0x00 2. "OCRAM_MAM_STAT_EN,OCRAM Magic Address Match Status Enable" "0: OCRAM_MAM_STAT_EN_0,1: OCRAM_MAM_STAT_EN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "DTCM_MAM_STAT_EN,DTCM Magic Address Match Status Enable" "0: DTCM_MAM_STAT_EN_0,1: DTCM_MAM_STAT_EN_1"
|
|
bitfld.long 0x00 0. "ITCM_MAM_STAT_EN,ITCM Magic Address Match Status Enable" "0: ITCM_MAM_STAT_EN_0,1: ITCM_MAM_STAT_EN_1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "INT_SIG_EN,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. "OCRAM_ERR_SIG_EN,OCRAM Access Error Interrupt Enable" "0: OCRAM_ERR_SIG_EN_0,1: OCRAM_ERR_SIG_EN_1"
|
|
bitfld.long 0x00 4. "DTCM_ERR_SIG_EN,DTCM Access Error Interrupt Enable" "0: DTCM_ERR_SIG_EN_0,1: DTCM_ERR_SIG_EN_1"
|
|
newline
|
|
bitfld.long 0x00 3. "ITCM_ERR_SIG_EN,ITCM Access Error Interrupt Enable" "0: ITCM_ERR_SIG_EN_0,1: ITCM_ERR_SIG_EN_1"
|
|
bitfld.long 0x00 2. "OCRAM_MAM_SIG_EN,OCRAM Magic Address Match Interrupt Enable" "0: OCRAM_MAM_SIG_EN_0,1: OCRAM_MAM_SIG_EN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "DTCM_MAM_SIG_EN,DTCM Magic Address Match Interrupt Enable" "0: DTCM_MAM_SIG_EN_0,1: DTCM_MAM_SIG_EN_1"
|
|
bitfld.long 0x00 0. "ITCM_MAM_SIG_EN,ITCM Magic Address Match Interrupt Enable" "0: ITCM_MAM_SIG_EN_0,1: ITCM_MAM_SIG_EN_1"
|
|
tree.end
|
|
tree "EWM"
|
|
base ad:0x400B4000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CTRL,Control Register"
|
|
bitfld.byte 0x00 3. "INTEN,Interrupt Enable" "0,1"
|
|
bitfld.byte 0x00 2. "INEN,Input Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ASSIN,EWM_in's Assertion State Select" "0,1"
|
|
bitfld.byte 0x00 0. "EWMEN,EWM enable" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SERV,Service Register"
|
|
hexmask.byte 0x00 0.--7. 1. "SERVICE,SERVICE"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "CMPL,Compare Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "COMPAREL,COMPAREL"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "CMPH,Compare High Register"
|
|
hexmask.byte 0x00 0.--7. 1. "COMPAREH,COMPAREH"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "CLKCTRL,Clock Control Register"
|
|
bitfld.byte 0x00 0.--1. "CLKSEL,CLKSEL" "0,1,2,3"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register"
|
|
hexmask.byte 0x00 0.--7. 1. "CLK_DIV,CLK_DIV"
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer Unit)"
|
|
repeat 2. (list 1. 2.) (list ad:0x400B8000 ad:0x400D0000)
|
|
tree "WDOG$1"
|
|
base $2
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "WCR,Watchdog Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "WT,WT"
|
|
bitfld.word 0x00 7. "WDW,WDW" "0: Continue WDOG timer operation (Default),1: Suspend WDOG timer operation"
|
|
newline
|
|
bitfld.word 0x00 6. "SRE,software reset extension an option way to generate software reset" "0: using original way to generate software reset..,1: using new way to generate software reset"
|
|
bitfld.word 0x00 5. "WDA,WDA" "0: Assert WDOG_B output,1: No effect on system (Default)"
|
|
newline
|
|
bitfld.word 0x00 4. "SRS,SRS" "0: Assert system reset signal,1: No effect on the system (Default)"
|
|
bitfld.word 0x00 3. "WDT,WDT" "0: No effect on WDOG_B (Default),1: Assert WDOG_B upon a Watchdog Time-out event"
|
|
newline
|
|
bitfld.word 0x00 2. "WDE,WDE" "0: Disable the Watchdog (Default),1: Enable the Watchdog"
|
|
bitfld.word 0x00 1. "WDBG,WDBG" "0: Continue WDOG timer operation (Default),1: Suspend the watchdog timer"
|
|
newline
|
|
bitfld.word 0x00 0. "WDZST,WDZST" "0: Continue timer operation (Default),1: Suspend the watchdog timer"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "WSR,Watchdog Service Register"
|
|
hexmask.word 0x00 0.--15. 1. "WSR,WSR"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "WRSR,Watchdog Reset Status Register"
|
|
bitfld.word 0x00 4. "POR,POR" "0: Reset is not the result of a power on reset,1: Reset is the result of a power on reset"
|
|
bitfld.word 0x00 1. "TOUT,TOUT" "0: Reset is not the result of a WDOG timeout,1: Reset is the result of a WDOG timeout"
|
|
newline
|
|
bitfld.word 0x00 0. "SFTW,SFTW" "0: Reset is not the result of a software reset,1: Reset is the result of a software reset"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "WICR,Watchdog Interrupt Control Register"
|
|
bitfld.word 0x00 15. "WIE,WIE" "0: Disable Interrupt (Default),1: Enable Interrupt"
|
|
eventfld.word 0x00 14. "WTIS,WTIS" "0: No interrupt has occurred (Default),1: Interrupt has occurred"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "WICT,WICT"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "WMCR,Watchdog Miscellaneous Control Register"
|
|
bitfld.word 0x00 0. "PDE,PDE" "0: Power Down Counter of WDOG is disabled,1: Power Down Counter of WDOG is enabled (Default)"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RTWDOG (WDOG)"
|
|
base ad:0x400BC000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
eventfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0: Bus clock,1: LPO clock,2: INTCLK (internal clock),3: ERCLK (external reference clock)"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x400C4000
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "HC$1,Control register for hardware triggers"
|
|
bitfld.long 0x00 7. "AIEN,Conversion Complete Interrupt Enable/Disable Control" "0: Conversion complete interrupt disabled,1: Conversion complete interrupt enabled"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input Channel Select" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: External channel selection from ADC_ETC,?,?,?,?,?,?,?,?,25: VREFSH = internal channel for ADC self-test..,?,?,?,?,?,31: Conversion Disabled"
|
|
repeat.end
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "HS,Status register for HW triggers"
|
|
bitfld.long 0x00 0. "COCO0,Conversion Complete Flag" "0,1"
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "R$1,Data result register for HW triggers"
|
|
hexmask.long.word 0x00 0.--11. 1. "CDATA,Data (result of an ADC conversion)"
|
|
repeat.end
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CFG,Configuration register"
|
|
bitfld.long 0x00 16. "OVWREN,Data Overwrite Enable" "0: Disable the overwriting,1: Enable the overwriting"
|
|
bitfld.long 0x00 14.--15. "AVGS,Hardware Average select" "0: 4 samples averaged,1: 8 samples averaged,2: 16 samples averaged,3: 32 samples averaged"
|
|
newline
|
|
bitfld.long 0x00 13. "ADTRG,Conversion Trigger Select" "0: Software trigger selected,1: Hardware trigger selected"
|
|
bitfld.long 0x00 11.--12. "REFSEL,Voltage Reference Selection" "0: Selects VREFH/VREFL as reference voltage,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "ADHSC,High Speed Configuration" "0: Normal conversion selected,1: High speed conversion selected"
|
|
bitfld.long 0x00 8.--9. "ADSTS,Defines the sample time duration" "0: Sample period (ADC clocks) = 2 if ADLSMP=0b..,1: Sample period (ADC clocks) = 4 if ADLSMP=0b..,2: Sample period (ADC clocks) = 6 if ADLSMP=0b..,3: Sample period (ADC clocks) = 8 if ADLSMP=0b.."
|
|
newline
|
|
bitfld.long 0x00 7. "ADLPC,Low-Power Configuration" "0: ADC hard block not in low power mode,1: ADC hard block in low power mode"
|
|
bitfld.long 0x00 5.--6. "ADIV,Clock Divide Select" "0: Input clock,1: Input clock / 2,2: Input clock / 4,3: Input clock / 8"
|
|
newline
|
|
bitfld.long 0x00 4. "ADLSMP,Long Sample Time Configuration" "0: Short sample mode,1: Long sample mode"
|
|
bitfld.long 0x00 2.--3. "MODE,Conversion Mode Selection" "0: 8-bit conversion,1: 10-bit conversion,2: 12-bit conversion,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ADICLK,Input Clock Select" "0: IPG clock,1: IPG clock divided by 2,2: Alternate clock (ALTCLK),3: Asynchronous clock (ADACK)"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GC,General control register"
|
|
bitfld.long 0x00 7. "CAL,Calibration" "0,1"
|
|
bitfld.long 0x00 6. "ADCO,Continuous Conversion Enable" "0: One conversion or one set of conversions if..,1: Continuous conversions or sets of conversions.."
|
|
newline
|
|
bitfld.long 0x00 5. "AVGE,Hardware average enable" "0: Hardware average function disabled,1: Hardware average function enabled"
|
|
bitfld.long 0x00 4. "ACFE,Compare Function Enable" "0: Compare function disabled,1: Compare function enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "ACFGT,Compare Function Greater Than Enable" "0: Configures Less Than Threshold Outside Range..,1: Configures Greater Than Or Equal To Threshold.."
|
|
bitfld.long 0x00 2. "ACREN,Compare Function Range Enable" "0: Range function disabled,1: Range function enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DMAEN,DMA Enable" "0: DMA disabled (default),1: DMA enabled"
|
|
bitfld.long 0x00 0. "ADACKEN,Asynchronous clock output enable" "0: Asynchronous clock output disabled..,1: Asynchronous clock and clock output enabled.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GS,General status register"
|
|
eventfld.long 0x00 2. "AWKST,Asynchronous wakeup interrupt status" "0: No asynchronous interrupt,1: Asynchronous wake up interrupt occurred in.."
|
|
eventfld.long 0x00 1. "CALF,Calibration Failed Flag" "0: Calibration completed normally,1: Calibration failed"
|
|
newline
|
|
rbitfld.long 0x00 0. "ADACT,Conversion Active" "0: Conversion not in progress,1: Conversion in progress"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CV,Compare value register"
|
|
hexmask.long.word 0x00 16.--27. 1. "CV2,Compare Value 2"
|
|
hexmask.long.word 0x00 0.--11. 1. "CV1,Compare Value 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OFS,Offset correction value register"
|
|
bitfld.long 0x00 12. "SIGN,Sign bit" "0: The offset value is added with the raw result,1: The offset value is subtracted from the raw.."
|
|
hexmask.long.word 0x00 0.--11. 1. "OFS,Offset value"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CAL,Calibration value register"
|
|
bitfld.long 0x00 0.--3. "CAL_CODE,Calibration Result Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "TRNG"
|
|
base ad:0x400CC000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. "PRGM,Programming Mode Select" "0,1"
|
|
bitfld.long 0x00 14. "LRUN_CONT,Long run count continues between entropy generations" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "TSTOP_OK,TRNG_OK_TO_STOP" "0,1"
|
|
eventfld.long 0x00 12. "ERR,Read: Error status" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "TST_OUT,Read only: Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. "ENT_VAL,Read only: Entropy Valid" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "FCT_VAL,Read only: Frequency Count Valid" "0,1"
|
|
rbitfld.long 0x00 8. "FCT_FAIL,Read only: Frequency Count Fail" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "FOR_SCLK,Force System Clock" "0,1"
|
|
bitfld.long 0x00 6. "RST_DEF,Reset Defaults" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "UNUSED5,This bit is unused" "0,1"
|
|
rbitfld.long 0x00 4. "UNUSED4,This bit is unused" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "OSC_DIV,Oscillator Divide" "0: use ring oscillator with no divide,1: use ring oscillator divided-by-2,2: use ring oscillator divided-by-4,3: use ring oscillator divided-by-8"
|
|
bitfld.long 0x00 0.--1. "SAMP_MODE,Sample Mode" "0: use Von Neumann data into both Entropy..,1: use raw data into both Entropy shifter and..,2: use Von Neumann data into Entropy shifter,3: undefined/reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SCMISC,Statistical Check Miscellaneous Register"
|
|
bitfld.long 0x00 16.--19. "RTY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LRUN_MAX,LONG RUN MAX LIMIT"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PKRRNG,Poker Range Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_RNG,Poker Range"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PKRMAX,Poker Maximum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_MAX,Poker Maximum Limit"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKRSQ,Poker Square Calculation Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_SQ,Poker Square Calculation Result"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SDCTL,Seed Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ENT_DLY,Entropy Delay"
|
|
hexmask.long.word 0x00 0.--15. 1. "SAMP_SIZE,Sample Size"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SBLIM,Sparse Bit Limit Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SB_LIM,Sparse Bit Limit"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TOTSAM,Total Samples Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "TOT_SAM,Total Samples"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FRQMIN,Frequency Count Minimum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MIN,Frequency Count Minimum Limit"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FRQCNT,Frequency Count Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_CT,Frequency Count"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FRQMAX,Frequency Count Maximum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MAX,Frequency Counter Maximum Limit"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SCMC,Statistical Check Monobit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MONO_CT,Monobit Count"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCML,Statistical Check Monobit Limit Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "MONO_RNG,Monobit Range"
|
|
hexmask.long.word 0x00 0.--15. 1. "MONO_MAX,Monobit Maximum Limit"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SCR1C,Statistical Check Run Length 1 Count Register"
|
|
hexmask.long.word 0x00 16.--30. 1. "R1_1_CT,Runs of One Length 1 Count"
|
|
hexmask.long.word 0x00 0.--14. 1. "R1_0_CT,Runs of Zero Length 1 Count"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCR1L,Statistical Check Run Length 1 Limit Register"
|
|
hexmask.long.word 0x00 16.--30. 1. "RUN1_RNG,Run Length 1 Range"
|
|
hexmask.long.word 0x00 0.--14. 1. "RUN1_MAX,Run Length 1 Maximum Limit"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCR2C,Statistical Check Run Length 2 Count Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "R2_1_CT,Runs of One Length 2 Count"
|
|
hexmask.long.word 0x00 0.--13. 1. "R2_0_CT,Runs of Zero Length 2 Count"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SCR2L,Statistical Check Run Length 2 Limit Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "RUN2_RNG,Run Length 2 Range"
|
|
hexmask.long.word 0x00 0.--13. 1. "RUN2_MAX,Run Length 2 Maximum Limit"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SCR3C,Statistical Check Run Length 3 Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. "R3_1_CT,Runs of Ones Length 3 Count"
|
|
hexmask.long.word 0x00 0.--12. 1. "R3_0_CT,Runs of Zeroes Length 3 Count"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCR3L,Statistical Check Run Length 3 Limit Register"
|
|
hexmask.long.word 0x00 16.--28. 1. "RUN3_RNG,Run Length 3 Range"
|
|
hexmask.long.word 0x00 0.--12. 1. "RUN3_MAX,Run Length 3 Maximum Limit"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SCR4C,Statistical Check Run Length 4 Count Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "R4_1_CT,Runs of One Length 4 Count"
|
|
hexmask.long.word 0x00 0.--11. 1. "R4_0_CT,Runs of Zero Length 4 Count"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SCR4L,Statistical Check Run Length 4 Limit Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "RUN4_RNG,Run Length 4 Range"
|
|
hexmask.long.word 0x00 0.--11. 1. "RUN4_MAX,Run Length 4 Maximum Limit"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SCR5C,Statistical Check Run Length 5 Count Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "R5_1_CT,Runs of One Length 5 Count"
|
|
hexmask.long.word 0x00 0.--10. 1. "R5_0_CT,Runs of Zero Length 5 Count"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SCR5L,Statistical Check Run Length 5 Limit Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "RUN5_RNG,Run Length 5 Range"
|
|
hexmask.long.word 0x00 0.--10. 1. "RUN5_MAX,Run Length 5 Maximum Limit"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SCR6PC,Statistical Check Run Length 6+ Count Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "R6P_1_CT,Runs of One Length 6+ Count"
|
|
hexmask.long.word 0x00 0.--10. 1. "R6P_0_CT,Runs of Zero Length 6+ Count"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCR6PL,Statistical Check Run Length 6+ Limit Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "RUN6P_RNG,Run Length 6+ Range"
|
|
hexmask.long.word 0x00 0.--10. 1. "RUN6P_MAX,Run Length 6+ Maximum Limit"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 16.--19. "RETRY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TFMB,Test Fail Mono Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TFP,Test Fail Poker" "0,1"
|
|
bitfld.long 0x00 13. "TFLR,Test Fail Long Run" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TFSB,Test Fail Sparse Bit" "0,1"
|
|
bitfld.long 0x00 11. "TF6PBR1,Test Fail 6 Plus Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TF6PBR0,Test Fail 6 Plus Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 9. "TF5BR1,Test Fail 5-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TF5BR0,Test Fail 5-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 7. "TF4BR1,Test Fail 4-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TF4BR0,Test Fail 4-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 5. "TF3BR1,Test Fail 3-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TF3BR0,Test Fail 3-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 3. "TF2BR1,Test Fail 2-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TF2BR0,Test Fail 2-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 1. "TF1BR1,Test Fail 1-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TF1BR0,Test Fail 1-Bit Run Sampling 0s" "0,1"
|
|
repeat 16. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "ENT[$1],Entropy Read Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PKRCNT10,Statistical Check Poker Count 1 and 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_1_CT,Poker 1h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_0_CT,Poker 0h Count"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PKRCNT32,Statistical Check Poker Count 3 and 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_3_CT,Poker 3h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_2_CT,Poker 2h Count"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PKRCNT54,Statistical Check Poker Count 5 and 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_5_CT,Poker 5h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_4_CT,Poker 4h Count"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "PKRCNT76,Statistical Check Poker Count 7 and 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_7_CT,Poker 7h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_6_CT,Poker 6h Count"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKRCNT98,Statistical Check Poker Count 9 and 8 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_9_CT,Poker 9h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_8_CT,Poker 8h Count"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKRCNTBA,Statistical Check Poker Count B and A Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_B_CT,Poker Bh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_A_CT,Poker Ah Count"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKRCNTDC,Statistical Check Poker Count D and C Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_D_CT,Poker Dh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_C_CT,Poker Ch Count"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PKRCNTFE,Statistical Check Poker Count F and E Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_F_CT,Poker Fh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_E_CT,Poker Eh Count"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SEC_CFG,Security Configuration Register"
|
|
bitfld.long 0x00 2. "UNUSED2,This bit is unused" "0,1"
|
|
bitfld.long 0x00 1. "NO_PRGM,If set the TRNG registers cannot be programmed" "0: Programability of registers controlled only..,1: Overides Miscellaneous Control Register.."
|
|
newline
|
|
bitfld.long 0x00 0. "UNUSED0,This bit is unused" "0,1"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "INT_CTRL,Interrupt Control Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
newline
|
|
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted" "0: Corresponding bit of INT_STATUS register..,1: Corresponding bit of INT_STATUS register active"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "INT_MASK,Mask Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
newline
|
|
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted" "0: Corresponding interrupt of INT_STATUS is masked,1: Corresponding bit of INT_STATUS is active"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "INT_STATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Read only: Frequency Count Fail" "0: No hardware nor self test frequency errors,1: The frequency counter has detected a failure"
|
|
bitfld.long 0x00 1. "ENT_VAL,Read only: Entropy Valid" "0: Busy generation entropy,1: TRNG can be stopped and entropy is valid if"
|
|
newline
|
|
bitfld.long 0x00 0. "HW_ERR,Read: Error status" "0: HW_ERR_0,1: error detected"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "VID1,Version ID Register (MS)"
|
|
hexmask.long.word 0x00 16.--31. 1. "IP_ID,Shows the IP ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MAJ_REV,Shows the IP's Major revision of the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "MIN_REV,Shows the IP's Minor revision of the TRNG"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "VID2,Version ID Register (LS)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ERA,Shows the compile options for the TRNG"
|
|
hexmask.long.byte 0x00 16.--23. 1. "INTG_OPT,Shows the integration options for the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ECO_REV,Shows the IP's ECO revision of the TRNG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CONFIG_OPT,Shows the IP's Configuaration options for the TRNG"
|
|
tree.end
|
|
tree "SVNS (Secure Non-Volatile Storage)"
|
|
base ad:0x400D4000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "HPLR,SNVS_HP Lock Register"
|
|
bitfld.long 0x00 18. "HAC_L,High Assurance Counter Lock When set prevents any writes to HPHACIVR HPHACR and HAC_EN bit of HPCOMR" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 17. "HPSICR_L,HP Security Interrupt Control Register Lock When set prevents any writes to the HPSICR" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 16. "HPSVCR_L,HP Security Violation Control Register Lock When set prevents any writes to the HPSVCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 9. "MKS_SL,Master Key Select Soft Lock When set prevents any writes to the MASTER_KEY_SEL field of the LPMKCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 8. "LPTDCR_SL,LP Tamper Detectors Configuration Register Soft Lock When set prevents any writes to the LPTDCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 6. "LPSVCR_SL,LP Security Violation Control Register Soft Lock When set prevents any writes to the LPSVCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 5. "GPR_SL,General Purpose Register Soft Lock When set prevents any writes to the GPR" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 4. "MC_SL,Monotonic Counter Soft Lock When set prevents any writes (increments) to the MC Registers and MC_ENV bit" "0: Write access (increment) is allowed,1: Write access (increment) is not allowed"
|
|
newline
|
|
bitfld.long 0x00 3. "LPCALB_SL,LP Calibration Soft Lock When set prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 2. "SRTC_SL,Secure Real Time Counter Soft Lock When set prevents any writes to the SRTC Registers SRTC_ENV and SRTC_INV_EN bits" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 1. "ZMK_RSL,Zeroizable Master Key Read Soft Lock When set prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR" "0: Read access is allowed (only in software..,1: Read access is not allowed"
|
|
bitfld.long 0x00 0. "ZMK_WSL,Zeroizable Master Key Write Soft Lock When set prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP ZMK_VAL and ZMK_ECC_EN fields of the LPMKCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HPCOMR,SNVS_HP Command Register"
|
|
bitfld.long 0x00 31. "NPSWA_EN,Non-Privileged Software Access Enable When set allows non-privileged software to access all SNVS registers including those that are privileged software read/write access only" "0,1"
|
|
bitfld.long 0x00 19. "HAC_STOP,High Assurance Counter Stop This bit can be set only when SSM is in soft fail state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HAC_CLEAR,High Assurance Counter Clear When set it clears the High Assurance Counter Register" "0: HAC_CLEAR_0,1: Clear the HAC"
|
|
bitfld.long 0x00 17. "HAC_LOAD,High Assurance Counter Load When set it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register" "0: HAC_LOAD_0,1: Load the HAC"
|
|
newline
|
|
bitfld.long 0x00 16. "HAC_EN,High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state" "0: High Assurance Counter is disabled,1: High Assurance Counter is enabled"
|
|
bitfld.long 0x00 13. "MKS_EN,Master Key Select Enable When not set the one time programmable (OTP) master key is selected by default" "0: OTP master key is selected as an SNVS master..,1: SNVS master key is selected according to the.."
|
|
newline
|
|
bitfld.long 0x00 12. "PROG_ZMK,Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism" "0: PROG_ZMK_0,1: Activate hardware key programming mechanism"
|
|
bitfld.long 0x00 10. "SW_LPSV,LP Software Security Violation When set SNVS_LP treats this bit as a security violation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SW_FSV,Software Fatal Security Violation When set the system security monitor treats this bit as a fatal security violation" "0,1"
|
|
bitfld.long 0x00 8. "SW_SV,Software Security Violation When set the system security monitor treats this bit as a non-fatal security violation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "LP_SWR_DIS,LP Software Reset Disable When set disables the LP software reset" "0: LP software reset is enabled,1: LP software reset is disabled"
|
|
bitfld.long 0x00 4. "LP_SWR,LP Software Reset When set to 1 most registers in the SNVS_LP section are reset but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set" "0: No Action,1: Reset LP section"
|
|
newline
|
|
bitfld.long 0x00 2. "SSM_SFNS_DIS,SSM Soft Fail to Non-Secure State Transition Disable When set it disables the SSM transition from soft fail to non-secure state" "0: Soft Fail to Non-Secure State transition is..,1: Soft Fail to Non-Secure State transition is.."
|
|
bitfld.long 0x00 1. "SSM_ST_DIS,SSM Secure to Trusted State Transition Disable When set disables the SSM transition from secure to trusted state" "0: Secure to Trusted State transition is enabled,1: Secure to Trusted State transition is disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SSM_ST,SSM State Transition Transition state of the system security monitor" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HPCR,SNVS_HP Control Register"
|
|
bitfld.long 0x00 27. "BTN_MASK,Button interrupt mask" "0,1"
|
|
bitfld.long 0x00 24.--26. "BTN_CONFIG,Button Configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "HP_TS,HP Time Synchronize" "0: No Action,1: Synchronize the HP Time Counter to the LP.."
|
|
bitfld.long 0x00 10.--14. "HPCALB_VAL,HP Calibration Value Defines signed calibration value for the HP Real Time Counter" "0: +0 counts per each 32768 ticks of the counter,1: +1 counts per each 32768 ticks of the counter,2: +2 counts per each 32768 ticks of the counter,?,?,?,?,?,?,?,?,?,?,?,?,15: +15 counts per each 32768 ticks of the counter,16: -16 counts per each 32768 ticks of the counter,17: -15 counts per each 32768 ticks of the counter,?,?,?,?,?,?,?,?,?,?,?,?,30: -2 counts per each 32768 ticks of the counter,31: -1 counts per each 32768 ticks of the counter"
|
|
newline
|
|
bitfld.long 0x00 8. "HPCALB_EN,HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled" "0: HP Timer calibration disabled,1: HP Timer calibration enabled"
|
|
bitfld.long 0x00 4.--7. "PI_FREQ,Periodic Interrupt Frequency Defines frequency of the periodic interrupt" "0: - bit 0 of the HPRTCLR is selected as a..,1: - bit 1 of the HPRTCLR is selected as a..,2: - bit 2 of the HPRTCLR is selected as a..,3: - bit 3 of the HPRTCLR is selected as a..,4: - bit 4 of the HPRTCLR is selected as a..,5: - bit 5 of the HPRTCLR is selected as a..,6: - bit 6 of the HPRTCLR is selected as a..,7: - bit 7 of the HPRTCLR is selected as a..,8: - bit 8 of the HPRTCLR is selected as a..,9: - bit 9 of the HPRTCLR is selected as a..,10: - bit 10 of the HPRTCLR is selected as a..,11: - bit 11 of the HPRTCLR is selected as a..,12: - bit 12 of the HPRTCLR is selected as a..,13: - bit 13 of the HPRTCLR is selected as a..,14: - bit 14 of the HPRTCLR is selected as a..,15: - bit 15 of the HPRTCLR is selected as a.."
|
|
newline
|
|
bitfld.long 0x00 3. "PI_EN,HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled" "0: HP Periodic Interrupt is disabled,1: HP Periodic Interrupt is enabled"
|
|
bitfld.long 0x00 2. "DIS_PI,Disable periodic interrupt in the functional interrupt" "0: Periodic interrupt will trigger a functional..,1: Disable periodic interrupt in the function.."
|
|
newline
|
|
bitfld.long 0x00 1. "HPTA_EN,HP Time Alarm Enable When set the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter" "0: HP Time Alarm Interrupt is disabled,1: HP Time Alarm Interrupt is enabled"
|
|
bitfld.long 0x00 0. "RTC_EN,HP Real Time Counter Enable" "0: RTC is disabled,1: RTC is enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HPSICR,SNVS_HP Security Interrupt Control Register"
|
|
bitfld.long 0x00 31. "LPSVI_EN,LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section" "0: LP Security Violation Interrupt is Disabled,1: LP Security Violation Interrupt is Enabled"
|
|
bitfld.long 0x00 5. "SV5_EN,Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation" "0: Security Violation 5 Interrupt is Disabled,1: Security Violation 5 Interrupt is Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "SV4_EN,Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation" "0: Security Violation 4 Interrupt is Disabled,1: Security Violation 4 Interrupt is Enabled"
|
|
bitfld.long 0x00 3. "SV3_EN,Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation" "0: Security Violation 3 Interrupt is Disabled,1: Security Violation 3 Interrupt is Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SV2_EN,Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation" "0: Security Violation 2 Interrupt is Disabled,1: Security Violation 2 Interrupt is Enabled"
|
|
bitfld.long 0x00 1. "SV1_EN,Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation" "0: Security Violation 1 Interrupt is Disabled,1: Security Violation 1 Interrupt is Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SV0_EN,Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation" "0: Security Violation 0 Interrupt is Disabled,1: Security Violation 0 Interrupt is Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HPSVCR,SNVS_HP Security Violation Control Register"
|
|
bitfld.long 0x00 30.--31. "LPSV_CFG,LP Security Violation Configuration This field configures the LP security violation source" "0: LP security violation is disabled,1: LP security violation is a non-fatal violation,2: LP security violation is a fatal violation,3: LP security violation is a fatal violation"
|
|
bitfld.long 0x00 5.--6. "SV5_CFG,Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input" "0: Security Violation 5 is disabled,1: Security Violation 5 is a non-fatal violation,2: Security Violation 5 is a fatal violation,3: Security Violation 5 is a fatal violation"
|
|
newline
|
|
bitfld.long 0x00 4. "SV4_CFG,Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input" "0: Security Violation 4 is a non-fatal violation,1: Security Violation 4 is a fatal violation"
|
|
bitfld.long 0x00 3. "SV3_CFG,Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input" "0: Security Violation 3 is a non-fatal violation,1: Security Violation 3 is a fatal violation"
|
|
newline
|
|
bitfld.long 0x00 2. "SV2_CFG,Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input" "0: Security Violation 2 is a non-fatal violation,1: Security Violation 2 is a fatal violation"
|
|
bitfld.long 0x00 1. "SV1_CFG,Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input" "0: Security Violation 1 is a non-fatal violation,1: Security Violation 1 is a fatal violation"
|
|
newline
|
|
bitfld.long 0x00 0. "SV0_CFG,Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input" "0: Security Violation 0 is a non-fatal violation,1: Security Violation 0 is a fatal violation"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HPSR,SNVS_HP Status Register"
|
|
rbitfld.long 0x00 31. "ZMK_ZERO,Zeroizable Master Key is Equal to Zero" "0: The ZMK is not zero,1: The ZMK is zero"
|
|
rbitfld.long 0x00 27. "OTPMK_ZERO,One Time Programmable Master Key is Equal to Zero" "0: The OTPMK is not zero,1: The OTPMK is zero"
|
|
newline
|
|
hexmask.long.word 0x00 16.--24. 1. "OTPMK_SYNDROME,One Time Programmable Master Key Syndrome In the case of a single-bit error the eight lower bits of this value indicate the bit number of error location"
|
|
rbitfld.long 0x00 12.--15. "SECURITY_CONFIG,Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS" "0: FAB configuration,1: OPEN configuration,2: OPEN configuration,3: OPEN configuration,4: FIELD RETURN configuration,5: FIELD RETURN configuration,6: FIELD RETURN configuration,7: FIELD RETURN configuration,8: FAB configuration,9: CLOSED configuration,10: CLOSED configuration,11: CLOSED configuration,12: FIELD RETURN configuration,13: FIELD RETURN configuration,14: FIELD RETURN configuration,15: FIELD RETURN configuration"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "SSM_STATE,System Security Monitor State This field contains the encoded state of the SSM's state machine" "0: SSM_STATE_0,1: SSM_STATE_1,?,3: SSM_STATE_3,?,?,?,?,8: Init Intermediate (transition state between..,9: SSM_STATE_9,?,11: SSM_STATE_11,?,13: SSM_STATE_13,?,15: SSM_STATE_15"
|
|
eventfld.long 0x00 7. "BI,Button Interrupt Signal ipi_snvs_btn_int_b was asserted" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "BTN,Button Value of the BTN input" "0,1"
|
|
rbitfld.long 0x00 4. "LPDIS,Low Power Disable If 1 the low power section has been disabled by means of an input signal to SNVS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "PI,Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared" "0: No periodic interrupt occurred,1: A periodic interrupt occurred"
|
|
eventfld.long 0x00 0. "HPTA,HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared" "0: No time alarm interrupt occurred,1: A time alarm interrupt occurred"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "HPSVSR,SNVS_HP Security Violation Status Register"
|
|
rbitfld.long 0x00 31. "LP_SEC_VIO,LP Security Violation A security volation was detected in the SNVS low power section" "0,1"
|
|
eventfld.long 0x00 27. "ZMK_ECC_FAIL,Zeroizable Master Key Error Correcting Code Check Failure When set this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section which clears security sensitive data" "0: ZMK ECC Failure was not detected,1: ZMK ECC Failure was detected"
|
|
newline
|
|
hexmask.long.word 0x00 16.--24. 1. "ZMK_SYNDROME,Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register"
|
|
rbitfld.long 0x00 15. "SW_LPSV,LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 14. "SW_FSV,Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register" "0,1"
|
|
rbitfld.long 0x00 13. "SW_SV,Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register" "0,1"
|
|
newline
|
|
eventfld.long 0x00 5. "SV5,Security Violation 5 security violation was detected" "0: No Security Violation 5 security violation..,1: Security Violation 5 security violation was.."
|
|
eventfld.long 0x00 4. "SV4,Security Violation 4 security violation was detected" "0: No Security Violation 4 security violation..,1: Security Violation 4 security violation was.."
|
|
newline
|
|
eventfld.long 0x00 3. "SV3,Security Violation 3 security violation was detected" "0: No Security Violation 3 security violation..,1: Security Violation 3 security violation was.."
|
|
eventfld.long 0x00 2. "SV2,Security Violation 2 security violation was detected" "0: No Security Violation 2 security violation..,1: Security Violation 2 security violation was.."
|
|
newline
|
|
eventfld.long 0x00 1. "SV1,Security Violation 1 security violation was detected" "0: No Security Violation 1 security violation..,1: Security Violation 1 security violation was.."
|
|
eventfld.long 0x00 0. "SV0,Security Violation 0 security violation was detected" "0: No Security Violation 0 security violation..,1: Security Violation 0 security violation was.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HPHACIVR,SNVS_HP High Assurance Counter IV Register"
|
|
hexmask.long 0x00 0.--31. 1. "HAC_COUNTER_IV,High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "HPHACR,SNVS_HP High Assurance Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "HAC_COUNTER,High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state this counter starts to count down with the system clock"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HPRTCMR,SNVS_HP Real Time Counter MSB Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "RTC,HP Real Time Counter The most-significant 15 bits of the RTC"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HPRTCLR,SNVS_HP Real Time Counter LSB Register"
|
|
hexmask.long 0x00 0.--31. 1. "RTC,HP Real Time Counter least-significant 32 bits"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HPTAMR,SNVS_HP Time Alarm MSB Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "HPTA_MS,HP Time Alarm most-significant 15 bits"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HPTALR,SNVS_HP Time Alarm LSB Register"
|
|
hexmask.long 0x00 0.--31. 1. "HPTA_LS,HP Time Alarm 32 least-significant bits"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "LPLR,SNVS_LP Lock Register"
|
|
bitfld.long 0x00 9. "MKS_HL,Master Key Select Hard Lock When set prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 8. "LPTDCR_HL,LP Tamper Detectors Configuration Register Hard Lock When set prevents any writes to the LPTDCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 6. "LPSVCR_HL,LP Security Violation Control Register Hard Lock When set prevents any writes to the LPSVCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 5. "GPR_HL,General Purpose Register Hard Lock When set prevents any writes to the GPR" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 4. "MC_HL,Monotonic Counter Hard Lock When set prevents any writes (increments) to the MC Registers and MC_ENV bit" "0: Write access (increment) is allowed,1: Write access (increment) is not allowed"
|
|
bitfld.long 0x00 3. "LPCALB_HL,LP Calibration Hard Lock When set prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)" "0: Write access is allowed,1: Write access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 2. "SRTC_HL,Secure Real Time Counter Hard Lock When set prevents any writes to the SRTC registers SRTC_ENV and SRTC_INV_EN bits" "0: Write access is allowed,1: Write access is not allowed"
|
|
bitfld.long 0x00 1. "ZMK_RHL,Zeroizable Master Key Read Hard Lock When set prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR" "0: Read access is allowed (only in software..,1: Read access is not allowed"
|
|
newline
|
|
bitfld.long 0x00 0. "ZMK_WHL,Zeroizable Master Key Write Hard Lock When set prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP ZMK_VAL and ZMK_ECC_EN fields of the LPMKCR" "0: Write access is allowed,1: Write access is not allowed"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "LPCR,SNVS_LP Control Register"
|
|
bitfld.long 0x00 24. "GPR_Z_DIS,General Purpose Registers Zeroization Disable" "0,1"
|
|
bitfld.long 0x00 23. "PK_OVERRIDE,PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "PK_EN,PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en" "0,1"
|
|
bitfld.long 0x00 20.--21. "ON_TIME,The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "DEBOUNCE,This field configures the amount of debounce time for the BTN input signal" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "BTN_PRESS_TIME,This field configures the button press time out values for the PMIC Logic" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "LPCALB_VAL,LP Calibration Value Defines signed calibration value for SRTC" "0: +0 counts per each 32768 ticks of the counter..,1: +1 counts per each 32768 ticks of the counter..,2: +2 counts per each 32768 ticks of the counter..,?,?,?,?,?,?,?,?,?,?,?,?,15: +15 counts per each 32768 ticks of the..,16: -16 counts per each 32768 ticks of the..,17: -15 counts per each 32768 ticks of the..,?,?,?,?,?,?,?,?,?,?,?,?,30: -2 counts per each 32768 ticks of the..,31: -1 counts per each 32768 ticks of the.."
|
|
bitfld.long 0x00 8. "LPCALB_EN,LP Calibration Enable When set enables the SRTC calibration mechanism" "0: SRTC Time calibration is disabled,1: SRTC Time calibration is enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "PWR_GLITCH_EN,Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted" "0,1"
|
|
bitfld.long 0x00 6. "TOP,Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power" "0: Leave system power on,1: Turn off system power"
|
|
newline
|
|
bitfld.long 0x00 5. "DP_EN,Dumb PMIC Enabled When set software can control the system power" "0: Smart PMIC enabled,1: Dumb PMIC enabled"
|
|
bitfld.long 0x00 4. "SRTC_INV_EN,If this bit is 1 in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared)" "0: SRTC stays valid in the case of security..,1: SRTC is invalidated in the case of security.."
|
|
newline
|
|
bitfld.long 0x00 3. "LPWUI_EN,LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event MC rollover SRTC rollover or time alarm )" "0,1"
|
|
bitfld.long 0x00 2. "MC_ENV,Monotonic Counter Enabled and Valid When set the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)" "0: MC is disabled or invalid,1: MC is enabled and valid"
|
|
newline
|
|
bitfld.long 0x00 1. "LPTA_EN,LP Time Alarm Enable When set the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter" "0: LP time alarm interrupt is disabled,1: LP time alarm interrupt is enabled"
|
|
bitfld.long 0x00 0. "SRTC_ENV,Secure Real Time Counter Enabled and Valid When set the SRTC becomes operational" "0: SRTC is disabled or invalid,1: SRTC is enabled and valid"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "LPMKCR,SNVS_LP Master Key Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. "ZMK_ECC_VALUE,Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register"
|
|
bitfld.long 0x00 4. "ZMK_ECC_EN,Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register" "0: ZMK ECC check is disabled,1: ZMK ECC check is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "ZMK_VAL,Zeroizable Master Key Valid When set the ZMK value can be selected by the master key control block for use by cryptographic modules" "0: ZMK is not valid,1: ZMK is valid"
|
|
bitfld.long 0x00 2. "ZMK_HWP,Zeroizable Master Key hardware Programming mode When set only the hardware key programming mechanism can set the ZMK and software cannot read it" "0: ZMK is in the software programming mode,1: ZMK is in the hardware programming mode"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "MASTER_KEY_SEL,Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR" "0: Select one time programmable master key,1: Select one time programmable master key,2: Select zeroizable master key when MKS_EN bit..,3: Select combined master key when MKS_EN bit is.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "LPSVCR,SNVS_LP Security Violation Control Register"
|
|
bitfld.long 0x00 5. "SV5_EN,Security Violation 5 Enable This bit enables Security Violation 5 Input" "0: Security Violation 5 is disabled in the LP..,1: Security Violation 5 is enabled in the LP.."
|
|
bitfld.long 0x00 4. "SV4_EN,Security Violation 4 Enable This bit enables Security Violation 4 Input" "0: Security Violation 4 is disabled in the LP..,1: Security Violation 4 is enabled in the LP.."
|
|
newline
|
|
bitfld.long 0x00 3. "SV3_EN,Security Violation 3 Enable This bit enables Security Violation 3 Input" "0: Security Violation 3 is disabled in the LP..,1: Security Violation 3 is enabled in the LP.."
|
|
bitfld.long 0x00 2. "SV2_EN,Security Violation 2 Enable This bit enables Security Violation 2 Input" "0: Security Violation 2 is disabled in the LP..,1: Security Violation 2 is enabled in the LP.."
|
|
newline
|
|
bitfld.long 0x00 1. "SV1_EN,Security Violation 1 Enable This bit enables Security Violation 1 Input" "0: Security Violation 1 is disabled in the LP..,1: Security Violation 1 is enabled in the LP.."
|
|
bitfld.long 0x00 0. "SV0_EN,Security Violation 0 Enable This bit enables Security Violation 0 Input" "0: Security Violation 0 is disabled in the LP..,1: Security Violation 0 is enabled in the LP.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "LPTDCR,SNVS_LP Tamper Detectors Configuration Register"
|
|
bitfld.long 0x00 28. "OSCB,Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted" "0: Normal SRTC clock oscillator not bypassed,1: Normal SRTC clock oscillator bypassed"
|
|
bitfld.long 0x00 15. "POR_OBSERV,Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "PFD_OBSERV,System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block)" "0,1"
|
|
bitfld.long 0x00 11. "ET1P,External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1" "0: External tamper 1 is active low,1: External tamper 1 is active high"
|
|
newline
|
|
bitfld.long 0x00 9. "ET1_EN,External Tampering 1 Enable When set external tampering 1 detection generates an LP security violation" "0: External tamper 1 is disabled,1: External tamper 1 is enabled"
|
|
bitfld.long 0x00 2. "MCR_EN,MC Rollover Enable When set an MC Rollover event generates an LP security violation" "0: MC rollover is disabled,1: MC rollover is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SRTCR_EN,SRTC Rollover Enable When set an SRTC rollover event generates an LP security violation" "0: SRTC rollover is disabled,1: SRTC rollover is enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "LPSR,SNVS_LP Status Register"
|
|
rbitfld.long 0x00 31. "LPS,LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state" "0: LP section was not programmed in secure or..,1: LP section was programmed in secure or.."
|
|
rbitfld.long 0x00 30. "LPNS,LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state" "0: LP section was not programmed in the..,1: LP section was programmed in the non-secure.."
|
|
newline
|
|
eventfld.long 0x00 20. "SED,Scan Exit Detected" "0: Scan exit was not detected,1: Scan exit was detected"
|
|
eventfld.long 0x00 18. "SPO,Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time" "0: Set Power Off was not detected,1: Set Power Off was detected"
|
|
newline
|
|
eventfld.long 0x00 17. "EO,Emergency Off This bit is set when a power off is requested" "0: Emergency off was not detected,1: Emergency off was detected"
|
|
eventfld.long 0x00 16. "ESVD,External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports" "0: No external security violation,1: External security violation is detected"
|
|
newline
|
|
eventfld.long 0x00 9. "ET1D,External Tampering 1 Detected" "0: External tampering 1 not detected,1: External tampering 1 detected"
|
|
eventfld.long 0x00 3. "PGD,Power Supply Glitch Detected 0 No power supply glitch" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "MCR,Monotonic Counter Rollover" "0: MC has not reached its maximum value,1: MC has reached its maximum value"
|
|
eventfld.long 0x00 1. "SRTCR,Secure Real Time Counter Rollover" "0: SRTC has not reached its maximum value,1: SRTC has reached its maximum value"
|
|
newline
|
|
eventfld.long 0x00 0. "LPTA,LP Time Alarm" "0: No time alarm interrupt occurred,1: A time alarm interrupt occurred"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "LPSRTCMR,SNVS_LP Secure Real Time Counter MSB Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "SRTC,LP Secure Real Time Counter The most-significant 15 bits of the SRTC"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LPSRTCLR,SNVS_LP Secure Real Time Counter LSB Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRTC,LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked meaning the SRTC_ENV SRTC_SL and SRTC_HL bits are not set"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LPTAR,SNVS_LP Time Alarm Register"
|
|
hexmask.long 0x00 0.--31. 1. "LPTA,LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set)"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LPSMCMR,SNVS_LP Secure Monotonic Counter MSB Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "MC_ERA_BITS,Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses"
|
|
hexmask.long.word 0x00 0.--15. 1. "MON_COUNTER,Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "LPSMCLR,SNVS_LP Secure Monotonic Counter LSB Register"
|
|
hexmask.long 0x00 0.--31. 1. "MON_COUNTER,Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "LPPGDR,SNVS_LP Power Glitch Detector Register"
|
|
hexmask.long 0x00 0.--31. 1. "PGD,Power Glitch Detector Value"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "LPGPR0_legacy_alias,SNVS_LP General Purpose Register 0 (legacy alias)"
|
|
hexmask.long 0x00 0.--31. 1. "GPR,General Purpose Register When GPR_SL or GPR_HL bit is set the register cannot be programmed"
|
|
repeat 8. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x6C)++0x03
|
|
line.long 0x00 "LPZMKR[$1],SNVS_LP Zeroizable Master Key Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "ZMK,Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x90)++0x03
|
|
line.long 0x00 "LPGPR_alias[$1],SNVS_LP General Purpose Registers 0"
|
|
hexmask.long 0x00 0.--31. 1. "GPR,General Purpose Register When GPR_SL or GPR_HL bit is set the register cannot be programmed"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "LPGPR[$1],SNVS_LP General Purpose Registers 0"
|
|
hexmask.long 0x00 0.--31. 1. "GPR,General Purpose Register When GPR_SL or GPR_HL bit is set the register cannot be programmed"
|
|
repeat.end
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "HPVIDR1,SNVS_HP Version ID Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "IP_ID,SNVS block ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MAJOR_REV,SNVS block major version number"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "MINOR_REV,SNVS block minor version number"
|
|
rgroup.long 0xBFC++0x03
|
|
line.long 0x00 "HPVIDR2,SNVS_HP Version ID Register 2"
|
|
abitfld.long 0x00 24.--31. "IP_ERA,IP Era" "0x00=0: Era 1 or 2,0x03=3: Era 3,0x04=4: Era 4,0x05=5: Era 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. "INTG_OPT,SNVS Integration Options"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ECO_REV,SNVS ECO Revision"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CONFIG_OPT,SNVS Configuration Options"
|
|
tree.end
|
|
tree "CCM_ANALOG"
|
|
base ad:0x400D8000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLL_USB1,Analog USB1 480MHz PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable the PLL clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWER,Powers up the PLL" "0,1"
|
|
bitfld.long 0x00 6. "EN_USB_CLKS,Powers the 9-phase PLL outputs for USBPHYn" "0: PLL outputs for USBPHYn off,1: PLL outputs for USBPHYn on"
|
|
newline
|
|
bitfld.long 0x00 1. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLL_USB1_SET,Analog USB1 480MHz PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable the PLL clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWER,Powers up the PLL" "0,1"
|
|
bitfld.long 0x00 6. "EN_USB_CLKS,Powers the 9-phase PLL outputs for USBPHYn" "0: PLL outputs for USBPHYn off,1: PLL outputs for USBPHYn on"
|
|
newline
|
|
bitfld.long 0x00 1. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PLL_USB1_CLR,Analog USB1 480MHz PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable the PLL clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWER,Powers up the PLL" "0,1"
|
|
bitfld.long 0x00 6. "EN_USB_CLKS,Powers the 9-phase PLL outputs for USBPHYn" "0: PLL outputs for USBPHYn off,1: PLL outputs for USBPHYn on"
|
|
newline
|
|
bitfld.long 0x00 1. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PLL_USB1_TOG,Analog USB1 480MHz PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable the PLL clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWER,Powers up the PLL" "0,1"
|
|
bitfld.long 0x00 6. "EN_USB_CLKS,Powers the 9-phase PLL outputs for USBPHYn" "0: PLL outputs for USBPHYn off,1: PLL outputs for USBPHYn on"
|
|
newline
|
|
bitfld.long 0x00 1. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PLL_SYS,Analog System PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
bitfld.long 0x00 0. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PLL_SYS_SET,Analog System PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
bitfld.long 0x00 0. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PLL_SYS_CLR,Analog System PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
bitfld.long 0x00 0. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PLL_SYS_TOG,Analog System PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
bitfld.long 0x00 0. "DIV_SELECT,This field controls the PLL loop divider" "0: Fout=Fref*20,1: Fout=Fref*22"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PLL_SYS_SS,528MHz System PLL Spread Spectrum Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "STOP,Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz"
|
|
bitfld.long 0x00 15. "ENABLE,Enable bit" "0: Spread spectrum modulation disabled,1: Soread spectrum modulation enabled"
|
|
newline
|
|
hexmask.long.word 0x00 0.--14. 1. "STEP,Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PLL_SYS_NUM,Numerator of 528MHz System PLL Fractional Loop Divider Register"
|
|
hexmask.long 0x00 0.--29. 1. "A,30 bit numerator (A) of fractional loop divider (signed integer)"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PLL_SYS_DENOM,Denominator of 528MHz System PLL Fractional Loop Divider Register"
|
|
hexmask.long 0x00 0.--29. 1. "B,30 bit denominator (B) of fractional loop divider (unsigned integer)"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PLL_AUDIO,Analog Audio PLL control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 19.--20. "POST_DIV_SELECT,These bits implement a divider after the PLL but before the enable and bypass mux" "0: POST_DIV_SELECT_0,1: POST_DIV_SELECT_1,2: POST_DIV_SELECT_2,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "DIV_SELECT,This field controls the PLL loop divider"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PLL_AUDIO_SET,Analog Audio PLL control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 19.--20. "POST_DIV_SELECT,These bits implement a divider after the PLL but before the enable and bypass mux" "0: POST_DIV_SELECT_0,1: POST_DIV_SELECT_1,2: POST_DIV_SELECT_2,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "DIV_SELECT,This field controls the PLL loop divider"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PLL_AUDIO_CLR,Analog Audio PLL control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 19.--20. "POST_DIV_SELECT,These bits implement a divider after the PLL but before the enable and bypass mux" "0: POST_DIV_SELECT_0,1: POST_DIV_SELECT_1,2: POST_DIV_SELECT_2,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "DIV_SELECT,This field controls the PLL loop divider"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PLL_AUDIO_TOG,Analog Audio PLL control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 19.--20. "POST_DIV_SELECT,These bits implement a divider after the PLL but before the enable and bypass mux" "0: POST_DIV_SELECT_0,1: POST_DIV_SELECT_1,2: POST_DIV_SELECT_2,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "ENABLE,Enable PLL output" "0,1"
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "DIV_SELECT,This field controls the PLL loop divider"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PLL_AUDIO_NUM,Numerator of Audio PLL Fractional Loop Divider Register"
|
|
hexmask.long 0x00 0.--29. 1. "A,30 bit numerator of fractional loop divider"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PLL_AUDIO_DENOM,Denominator of Audio PLL Fractional Loop Divider Register"
|
|
hexmask.long 0x00 0.--29. 1. "B,30 bit denominator of fractional loop divider"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PLL_ENET,Analog ENET PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 22. "ENET_500M_REF_EN,Enable the PLL providing ENET 500 MHz reference clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PLL_ENET_SET,Analog ENET PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 22. "ENET_500M_REF_EN,Enable the PLL providing ENET 500 MHz reference clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PLL_ENET_CLR,Analog ENET PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 22. "ENET_500M_REF_EN,Enable the PLL providing ENET 500 MHz reference clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PLL_ENET_TOG,Analog ENET PLL Control Register"
|
|
rbitfld.long 0x00 31. "LOCK," "0,1"
|
|
bitfld.long 0x00 22. "ENET_500M_REF_EN,Enable the PLL providing ENET 500 MHz reference clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BYPASS,Bypass the PLL" "0,1"
|
|
bitfld.long 0x00 14.--15. "BYPASS_CLK_SRC,Determines the bypass source" "0: Select the 24MHz oscillator as source,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "POWERDOWN,Powers down the PLL" "0,1"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PFD_480,480MHz Clock (PLL3) Phase Fractional Divider Control Register"
|
|
bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PFD_480_SET,480MHz Clock (PLL3) Phase Fractional Divider Control Register"
|
|
bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PFD_480_CLR,480MHz Clock (PLL3) Phase Fractional Divider Control Register"
|
|
bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PFD_480_TOG,480MHz Clock (PLL3) Phase Fractional Divider Control Register"
|
|
bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
|
|
rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
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rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x100++0x03
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line.long 0x00 "PFD_528,528MHz Clock (PLL2) Phase Fractional Divider Control Register"
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bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
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rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x104++0x03
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line.long 0x00 "PFD_528_SET,528MHz Clock (PLL2) Phase Fractional Divider Control Register"
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bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
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rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x108++0x03
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line.long 0x00 "PFD_528_CLR,528MHz Clock (PLL2) Phase Fractional Divider Control Register"
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bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
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rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x10C++0x03
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line.long 0x00 "PFD_528_TOG,528MHz Clock (PLL2) Phase Fractional Divider Control Register"
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bitfld.long 0x00 31. "PFD3_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 30. "PFD3_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 24.--29. "PFD3_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 23. "PFD2_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 22. "PFD2_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 16.--21. "PFD2_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "PFD1_CLKGATE,IO Clock Gate" "0,1"
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rbitfld.long 0x00 14. "PFD1_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 8.--13. "PFD1_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "PFD0_CLKGATE,If set to 1 the IO fractional divider clock (reference ref_pfd0) is off (power savings)" "0,1"
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rbitfld.long 0x00 6. "PFD0_STABLE,This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code" "0,1"
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bitfld.long 0x00 0.--5. "PFD0_FRAC,This field controls the fractional divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x150++0x03
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line.long 0x00 "MISC0,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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bitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: All analog except RTC powered down on stop..,1: Beside RTC analog bandgap 1p1 and 2p5..,2: Beside RTC 1p1 and 2p5 regulators are also on..,3: Beside RTC low-power bandgap is selected and.."
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to CCM" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "MISC0_SET,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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bitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: All analog except RTC powered down on stop..,1: Beside RTC analog bandgap 1p1 and 2p5..,2: Beside RTC 1p1 and 2p5 regulators are also on..,3: Beside RTC low-power bandgap is selected and.."
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to CCM" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x158++0x03
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line.long 0x00 "MISC0_CLR,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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bitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: All analog except RTC powered down on stop..,1: Beside RTC analog bandgap 1p1 and 2p5..,2: Beside RTC 1p1 and 2p5 regulators are also on..,3: Beside RTC low-power bandgap is selected and.."
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to CCM" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x15C++0x03
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line.long 0x00 "MISC0_TOG,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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bitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: All analog except RTC powered down on stop..,1: Beside RTC analog bandgap 1p1 and 2p5..,2: Beside RTC 1p1 and 2p5 regulators are also on..,3: Beside RTC low-power bandgap is selected and.."
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to CCM" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x160++0x03
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line.long 0x00 "MISC1,Miscellaneous Register 1"
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eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
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eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
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eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
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eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
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eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
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bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
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bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
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group.long 0x164++0x03
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line.long 0x00 "MISC1_SET,Miscellaneous Register 1"
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eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
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eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
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eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
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eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
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eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
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bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
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bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
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group.long 0x168++0x03
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line.long 0x00 "MISC1_CLR,Miscellaneous Register 1"
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eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
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eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
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newline
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eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
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eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
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eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
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bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
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newline
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bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
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group.long 0x16C++0x03
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line.long 0x00 "MISC1_TOG,Miscellaneous Register 1"
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eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
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eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
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newline
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eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
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eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
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eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
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bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
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newline
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bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
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group.long 0x170++0x03
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line.long 0x00 "MISC2,Miscellaneous Register 2"
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bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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newline
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bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
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rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
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bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
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rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit.Not related to CCM" "0,1"
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rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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newline
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bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
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rbitfld.long 0x00 14. "REG1_OK,GPU supply Not related to CCM" "0,1"
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newline
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bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
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rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
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newline
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rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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bitfld.long 0x00 7. "PLL3_DISABLE,When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode" "0: PLL3 is being used by peripherals and is..,1: PLL3 can be disabled when the SoC is not in.."
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newline
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rbitfld.long 0x00 6. "REG0_OK,ARM supply Not related to CCM" "0,1"
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bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
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newline
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rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit.Not related to CCM" "?,1: Brownout supply is below target minus.."
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rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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group.long 0x174++0x03
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line.long 0x00 "MISC2_SET,Miscellaneous Register 2"
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bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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newline
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bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
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newline
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rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
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bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
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newline
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rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit.Not related to CCM" "0,1"
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rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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newline
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bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
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rbitfld.long 0x00 14. "REG1_OK,GPU supply Not related to CCM" "0,1"
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newline
|
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bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
|
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rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
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newline
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rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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bitfld.long 0x00 7. "PLL3_DISABLE,When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode" "0: PLL3 is being used by peripherals and is..,1: PLL3 can be disabled when the SoC is not in.."
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newline
|
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rbitfld.long 0x00 6. "REG0_OK,ARM supply Not related to CCM" "0,1"
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bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
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newline
|
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rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit.Not related to CCM" "?,1: Brownout supply is below target minus.."
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rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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group.long 0x178++0x03
|
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line.long 0x00 "MISC2_CLR,Miscellaneous Register 2"
|
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bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
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newline
|
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bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
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bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
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newline
|
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rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
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bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
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newline
|
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rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit.Not related to CCM" "0,1"
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rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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newline
|
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bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
|
rbitfld.long 0x00 14. "REG1_OK,GPU supply Not related to CCM" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
|
|
rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
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newline
|
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rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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bitfld.long 0x00 7. "PLL3_DISABLE,When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode" "0: PLL3 is being used by peripherals and is..,1: PLL3 can be disabled when the SoC is not in.."
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newline
|
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rbitfld.long 0x00 6. "REG0_OK,ARM supply Not related to CCM" "0,1"
|
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bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
|
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newline
|
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rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit.Not related to CCM" "?,1: Brownout supply is below target minus.."
|
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rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "MISC2_TOG,Miscellaneous Register 2"
|
|
bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
newline
|
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bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock).Not related to CCM" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
|
|
newline
|
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rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
|
bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
|
|
newline
|
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rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit.Not related to CCM" "0,1"
|
|
rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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newline
|
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bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
|
rbitfld.long 0x00 14. "REG1_OK,GPU supply Not related to CCM" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
|
|
rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
newline
|
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rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
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bitfld.long 0x00 7. "PLL3_DISABLE,When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode" "0: PLL3 is being used by peripherals and is..,1: PLL3 can be disabled when the SoC is not in.."
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|
newline
|
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rbitfld.long 0x00 6. "REG0_OK,ARM supply Not related to CCM" "0,1"
|
|
bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection.Not related to CCM" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit.Not related to CCM" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
tree.end
|
|
tree "PMU (Program Memory Unit)"
|
|
base ad:0x400D8000
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "REG_1P1,Regulator 1P1 Register"
|
|
bitfld.long 0x00 19. "SELREF_WEAK_LINREG,Selects the source for the reference voltage of the weak 1p1 regulator" "0: Weak-linreg output tracks low-power-bandgap..,1: Weak-linreg output tracks VDD_SOC_IN voltage"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 1p1 regulator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "OK_VDD1P1,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD1P1,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "?,?,?,?,4: OUTPUT_TRG_4,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?..."
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "REG_1P1_SET,Regulator 1P1 Register"
|
|
bitfld.long 0x00 19. "SELREF_WEAK_LINREG,Selects the source for the reference voltage of the weak 1p1 regulator" "0: Weak-linreg output tracks low-power-bandgap..,1: Weak-linreg output tracks VDD_SOC_IN voltage"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 1p1 regulator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "OK_VDD1P1,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD1P1,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "?,?,?,?,4: OUTPUT_TRG_4,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?..."
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "REG_1P1_CLR,Regulator 1P1 Register"
|
|
bitfld.long 0x00 19. "SELREF_WEAK_LINREG,Selects the source for the reference voltage of the weak 1p1 regulator" "0: Weak-linreg output tracks low-power-bandgap..,1: Weak-linreg output tracks VDD_SOC_IN voltage"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 1p1 regulator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "OK_VDD1P1,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD1P1,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "?,?,?,?,4: OUTPUT_TRG_4,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?..."
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "REG_1P1_TOG,Regulator 1P1 Register"
|
|
bitfld.long 0x00 19. "SELREF_WEAK_LINREG,Selects the source for the reference voltage of the weak 1p1 regulator" "0: Weak-linreg output tracks low-power-bandgap..,1: Weak-linreg output tracks VDD_SOC_IN voltage"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 1p1 regulator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "OK_VDD1P1,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD1P1,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "?,?,?,?,4: OUTPUT_TRG_4,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?..."
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "REG_3P0,Regulator 3P0 Register"
|
|
rbitfld.long 0x00 17. "OK_VDD3P0,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD3P0,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: OUTPUT_TRG_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
bitfld.long 0x00 7. "VBUS_SEL,Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS" "0: Utilize VBUS OTG2 power,1: Utilize VBUS OTG1 power"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "REG_3P0_SET,Regulator 3P0 Register"
|
|
rbitfld.long 0x00 17. "OK_VDD3P0,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD3P0,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: OUTPUT_TRG_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
bitfld.long 0x00 7. "VBUS_SEL,Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS" "0: Utilize VBUS OTG2 power,1: Utilize VBUS OTG1 power"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "REG_3P0_CLR,Regulator 3P0 Register"
|
|
rbitfld.long 0x00 17. "OK_VDD3P0,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD3P0,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: OUTPUT_TRG_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
bitfld.long 0x00 7. "VBUS_SEL,Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS" "0: Utilize VBUS OTG2 power,1: Utilize VBUS OTG1 power"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference" "0,1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "REG_3P0_TOG,Regulator 3P0 Register"
|
|
rbitfld.long 0x00 17. "OK_VDD3P0,Status bit that signals when the regulator output is ok" "0,1"
|
|
rbitfld.long 0x00 16. "BO_VDD3P0,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: OUTPUT_TRG_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
bitfld.long 0x00 7. "VBUS_SEL,Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS" "0: Utilize VBUS OTG2 power,1: Utilize VBUS OTG1 power"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference" "0,1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "REG_2P5,Regulator 2P5 Register"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 2p5 regulator" "0,1"
|
|
rbitfld.long 0x00 17. "OK_VDD2P5,Status bit that signals when the regulator output is ok" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "BO_VDD2P5,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "REG_2P5_SET,Regulator 2P5 Register"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 2p5 regulator" "0,1"
|
|
rbitfld.long 0x00 17. "OK_VDD2P5,Status bit that signals when the regulator output is ok" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "BO_VDD2P5,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "REG_2P5_CLR,Regulator 2P5 Register"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 2p5 regulator" "0,1"
|
|
rbitfld.long 0x00 17. "OK_VDD2P5,Status bit that signals when the regulator output is ok" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "BO_VDD2P5,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "REG_2P5_TOG,Regulator 2P5 Register"
|
|
bitfld.long 0x00 18. "ENABLE_WEAK_LINREG,Enables the weak 2p5 regulator" "0,1"
|
|
rbitfld.long 0x00 17. "OK_VDD2P5,Status bit that signals when the regulator output is ok" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "BO_VDD2P5,Status bit that signals when a brownout is detected on the regulator output" "0,1"
|
|
bitfld.long 0x00 8.--12. "OUTPUT_TRG,Control bits to adjust the regulator output voltage" "0: OUTPUT_TRG_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: OUTPUT_TRG_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: OUTPUT_TRG_31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BO_OFFSET,Control bits to adjust the regulator brownout offset voltage in 25mV steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "ENABLE_PULLDOWN,Control bit to enable the pull-down circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_ILIMIT,Control bit to enable the current-limit circuitry in the regulator" "0,1"
|
|
bitfld.long 0x00 1. "ENABLE_BO,Control bit to enable the brownout circuitry in the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE_LINREG,Control bit to enable the regulator output" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "REG_CORE,Digital Regulator Core Register"
|
|
bitfld.long 0x00 29. "FET_ODRIVE,If set increases the gate drive on power gating FETs to reduce leakage in the off state" "0,1"
|
|
bitfld.long 0x00 27.--28. "RAMP_RATE,Regulator voltage ramp rate" "0: RAMP_RATE_0,1: RAMP_RATE_1,2: RAMP_RATE_2,3: RAMP_RATE_3"
|
|
newline
|
|
bitfld.long 0x00 23.--26. "REG2_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg2" "0: No adjustment,1: REG2_ADJ_1,2: REG2_ADJ_2,3: REG2_ADJ_3,4: REG2_ADJ_4,5: REG2_ADJ_5,6: REG2_ADJ_6,7: REG2_ADJ_7,8: REG2_ADJ_8,9: REG2_ADJ_9,10: REG2_ADJ_10,11: REG2_ADJ_11,12: REG2_ADJ_12,13: REG2_ADJ_13,14: REG2_ADJ_14,15: REG2_ADJ_15"
|
|
bitfld.long 0x00 18.--22. "REG2_TARG,This field defines the target voltage for the SOC power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
|
|
newline
|
|
bitfld.long 0x00 14.--17. "REG1_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg1" "0: No adjustment,1: REG1_ADJ_1,2: REG1_ADJ_2,3: REG1_ADJ_3,4: REG1_ADJ_4,5: REG1_ADJ_5,6: REG1_ADJ_6,7: REG1_ADJ_7,8: REG1_ADJ_8,9: REG1_ADJ_9,10: REG1_ADJ_10,11: REG1_ADJ_11,12: REG1_ADJ_12,13: REG1_ADJ_13,14: REG1_ADJ_14,15: REG1_ADJ_15"
|
|
bitfld.long 0x00 9.--13. "REG1_TARG,This bit field defines the target voltage for the vpu/gpu power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "REG0_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg0" "0: No adjustment,1: REG0_ADJ_1,2: REG0_ADJ_2,3: REG0_ADJ_3,4: REG0_ADJ_4,5: REG0_ADJ_5,6: REG0_ADJ_6,7: REG0_ADJ_7,8: REG0_ADJ_8,9: REG0_ADJ_9,10: REG0_ADJ_10,11: REG0_ADJ_11,12: REG0_ADJ_12,13: REG0_ADJ_13,14: REG0_ADJ_14,15: REG0_ADJ_15"
|
|
bitfld.long 0x00 0.--4. "REG0_TARG,This field defines the target voltage for the ARM core power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "REG_CORE_SET,Digital Regulator Core Register"
|
|
bitfld.long 0x00 29. "FET_ODRIVE,If set increases the gate drive on power gating FETs to reduce leakage in the off state" "0,1"
|
|
bitfld.long 0x00 27.--28. "RAMP_RATE,Regulator voltage ramp rate" "0: RAMP_RATE_0,1: RAMP_RATE_1,2: RAMP_RATE_2,3: RAMP_RATE_3"
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bitfld.long 0x00 23.--26. "REG2_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg2" "0: No adjustment,1: REG2_ADJ_1,2: REG2_ADJ_2,3: REG2_ADJ_3,4: REG2_ADJ_4,5: REG2_ADJ_5,6: REG2_ADJ_6,7: REG2_ADJ_7,8: REG2_ADJ_8,9: REG2_ADJ_9,10: REG2_ADJ_10,11: REG2_ADJ_11,12: REG2_ADJ_12,13: REG2_ADJ_13,14: REG2_ADJ_14,15: REG2_ADJ_15"
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bitfld.long 0x00 18.--22. "REG2_TARG,This field defines the target voltage for the SOC power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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bitfld.long 0x00 14.--17. "REG1_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg1" "0: No adjustment,1: REG1_ADJ_1,2: REG1_ADJ_2,3: REG1_ADJ_3,4: REG1_ADJ_4,5: REG1_ADJ_5,6: REG1_ADJ_6,7: REG1_ADJ_7,8: REG1_ADJ_8,9: REG1_ADJ_9,10: REG1_ADJ_10,11: REG1_ADJ_11,12: REG1_ADJ_12,13: REG1_ADJ_13,14: REG1_ADJ_14,15: REG1_ADJ_15"
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bitfld.long 0x00 9.--13. "REG1_TARG,This bit field defines the target voltage for the vpu/gpu power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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bitfld.long 0x00 5.--8. "REG0_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg0" "0: No adjustment,1: REG0_ADJ_1,2: REG0_ADJ_2,3: REG0_ADJ_3,4: REG0_ADJ_4,5: REG0_ADJ_5,6: REG0_ADJ_6,7: REG0_ADJ_7,8: REG0_ADJ_8,9: REG0_ADJ_9,10: REG0_ADJ_10,11: REG0_ADJ_11,12: REG0_ADJ_12,13: REG0_ADJ_13,14: REG0_ADJ_14,15: REG0_ADJ_15"
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bitfld.long 0x00 0.--4. "REG0_TARG,This field defines the target voltage for the ARM core power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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group.long 0x148++0x03
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line.long 0x00 "REG_CORE_CLR,Digital Regulator Core Register"
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bitfld.long 0x00 29. "FET_ODRIVE,If set increases the gate drive on power gating FETs to reduce leakage in the off state" "0,1"
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bitfld.long 0x00 27.--28. "RAMP_RATE,Regulator voltage ramp rate" "0: RAMP_RATE_0,1: RAMP_RATE_1,2: RAMP_RATE_2,3: RAMP_RATE_3"
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bitfld.long 0x00 23.--26. "REG2_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg2" "0: No adjustment,1: REG2_ADJ_1,2: REG2_ADJ_2,3: REG2_ADJ_3,4: REG2_ADJ_4,5: REG2_ADJ_5,6: REG2_ADJ_6,7: REG2_ADJ_7,8: REG2_ADJ_8,9: REG2_ADJ_9,10: REG2_ADJ_10,11: REG2_ADJ_11,12: REG2_ADJ_12,13: REG2_ADJ_13,14: REG2_ADJ_14,15: REG2_ADJ_15"
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bitfld.long 0x00 18.--22. "REG2_TARG,This field defines the target voltage for the SOC power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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bitfld.long 0x00 14.--17. "REG1_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg1" "0: No adjustment,1: REG1_ADJ_1,2: REG1_ADJ_2,3: REG1_ADJ_3,4: REG1_ADJ_4,5: REG1_ADJ_5,6: REG1_ADJ_6,7: REG1_ADJ_7,8: REG1_ADJ_8,9: REG1_ADJ_9,10: REG1_ADJ_10,11: REG1_ADJ_11,12: REG1_ADJ_12,13: REG1_ADJ_13,14: REG1_ADJ_14,15: REG1_ADJ_15"
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bitfld.long 0x00 9.--13. "REG1_TARG,This bit field defines the target voltage for the vpu/gpu power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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bitfld.long 0x00 5.--8. "REG0_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg0" "0: No adjustment,1: REG0_ADJ_1,2: REG0_ADJ_2,3: REG0_ADJ_3,4: REG0_ADJ_4,5: REG0_ADJ_5,6: REG0_ADJ_6,7: REG0_ADJ_7,8: REG0_ADJ_8,9: REG0_ADJ_9,10: REG0_ADJ_10,11: REG0_ADJ_11,12: REG0_ADJ_12,13: REG0_ADJ_13,14: REG0_ADJ_14,15: REG0_ADJ_15"
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bitfld.long 0x00 0.--4. "REG0_TARG,This field defines the target voltage for the ARM core power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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group.long 0x14C++0x03
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line.long 0x00 "REG_CORE_TOG,Digital Regulator Core Register"
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bitfld.long 0x00 29. "FET_ODRIVE,If set increases the gate drive on power gating FETs to reduce leakage in the off state" "0,1"
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bitfld.long 0x00 27.--28. "RAMP_RATE,Regulator voltage ramp rate" "0: RAMP_RATE_0,1: RAMP_RATE_1,2: RAMP_RATE_2,3: RAMP_RATE_3"
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bitfld.long 0x00 23.--26. "REG2_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg2" "0: No adjustment,1: REG2_ADJ_1,2: REG2_ADJ_2,3: REG2_ADJ_3,4: REG2_ADJ_4,5: REG2_ADJ_5,6: REG2_ADJ_6,7: REG2_ADJ_7,8: REG2_ADJ_8,9: REG2_ADJ_9,10: REG2_ADJ_10,11: REG2_ADJ_11,12: REG2_ADJ_12,13: REG2_ADJ_13,14: REG2_ADJ_14,15: REG2_ADJ_15"
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bitfld.long 0x00 18.--22. "REG2_TARG,This field defines the target voltage for the SOC power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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bitfld.long 0x00 14.--17. "REG1_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg1" "0: No adjustment,1: REG1_ADJ_1,2: REG1_ADJ_2,3: REG1_ADJ_3,4: REG1_ADJ_4,5: REG1_ADJ_5,6: REG1_ADJ_6,7: REG1_ADJ_7,8: REG1_ADJ_8,9: REG1_ADJ_9,10: REG1_ADJ_10,11: REG1_ADJ_11,12: REG1_ADJ_12,13: REG1_ADJ_13,14: REG1_ADJ_14,15: REG1_ADJ_15"
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bitfld.long 0x00 9.--13. "REG1_TARG,This bit field defines the target voltage for the vpu/gpu power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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bitfld.long 0x00 5.--8. "REG0_ADJ,This bit field defines the adjustment bits to calibrate the target value of Reg0" "0: No adjustment,1: REG0_ADJ_1,2: REG0_ADJ_2,3: REG0_ADJ_3,4: REG0_ADJ_4,5: REG0_ADJ_5,6: REG0_ADJ_6,7: REG0_ADJ_7,8: REG0_ADJ_8,9: REG0_ADJ_9,10: REG0_ADJ_10,11: REG0_ADJ_11,12: REG0_ADJ_12,13: REG0_ADJ_13,14: REG0_ADJ_14,15: REG0_ADJ_15"
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bitfld.long 0x00 0.--4. "REG0_TARG,This field defines the target voltage for the ARM core power domain" "0: Power gated off,1: Target core voltage = 0.725V,2: Target core voltage = 0.750V,3: Target core voltage = 0.775V,?,?,?,?,?,?,?,?,?,?,?,?,16: Target core voltage = 1.100V,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Target core voltage = 1.450V,31: Power FET switched full on"
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group.long 0x150++0x03
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line.long 0x00 "MISC0,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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newline
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: STOP_MODE_CONFIG_0,1: Analog regulators are ON,2: STOP_MODE_CONFIG_2,3: STOP (very lower power)"
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,no description available" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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newline
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bitfld.long 0x00 2. "REFTOP_LOWPOWER,Control bit to enable the low-power mode in the analog bandgap" "0,1"
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bitfld.long 0x00 1. "REFTOP_PWDVBGUP,Control bit to power down the VBG-up detection circuitry in the analog bandgap" "0,1"
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newline
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "MISC0_SET,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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newline
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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newline
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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newline
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: STOP_MODE_CONFIG_0,1: Analog regulators are ON,2: STOP_MODE_CONFIG_2,3: STOP (very lower power)"
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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newline
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,no description available" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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newline
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bitfld.long 0x00 2. "REFTOP_LOWPOWER,Control bit to enable the low-power mode in the analog bandgap" "0,1"
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bitfld.long 0x00 1. "REFTOP_PWDVBGUP,Control bit to power down the VBG-up detection circuitry in the analog bandgap" "0,1"
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newline
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x158++0x03
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line.long 0x00 "MISC0_CLR,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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newline
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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newline
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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newline
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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newline
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: STOP_MODE_CONFIG_0,1: Analog regulators are ON,2: STOP_MODE_CONFIG_2,3: STOP (very lower power)"
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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newline
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,no description available" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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newline
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bitfld.long 0x00 2. "REFTOP_LOWPOWER,Control bit to enable the low-power mode in the analog bandgap" "0,1"
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bitfld.long 0x00 1. "REFTOP_PWDVBGUP,Control bit to power down the VBG-up detection circuitry in the analog bandgap" "0,1"
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newline
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
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group.long 0x15C++0x03
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line.long 0x00 "MISC0_TOG,Miscellaneous Register 0"
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bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
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rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
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newline
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bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
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bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
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newline
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bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
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rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
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newline
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bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
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newline
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bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode" "0: STOP_MODE_CONFIG_0,1: Analog regulators are ON,2: STOP_MODE_CONFIG_2,3: STOP (very lower power)"
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
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newline
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bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,no description available" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
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bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
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newline
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bitfld.long 0x00 2. "REFTOP_LOWPOWER,Control bit to enable the low-power mode in the analog bandgap" "0,1"
|
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bitfld.long 0x00 1. "REFTOP_PWDVBGUP,Control bit to power down the VBG-up detection circuitry in the analog bandgap" "0,1"
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newline
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bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MISC1,Miscellaneous Register 1"
|
|
eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
|
|
eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
|
|
eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
|
|
bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MISC1_SET,Miscellaneous Register 1"
|
|
eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
|
|
eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
|
|
eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
|
|
bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MISC1_CLR,Miscellaneous Register 1"
|
|
eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
|
|
eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
|
|
eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
|
|
bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MISC1_TOG,Miscellaneous Register 1"
|
|
eventfld.long 0x00 31. "IRQ_DIG_BO,This status bit is set to one when when any of the digital regulator brownout interrupts assert" "0,1"
|
|
eventfld.long 0x00 30. "IRQ_ANA_BO,This status bit is set to one when when any of the analog regulator brownout interrupts assert" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "IRQ_TEMPHIGH,This status bit is set to one when the temperature sensor high interrupt asserts for high temperature" "0,1"
|
|
eventfld.long 0x00 28. "IRQ_TEMPLOW,This status bit is set to one when the temperature sensor low interrupt asserts for low temperature" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "IRQ_TEMPPANIC,This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature" "0,1"
|
|
bitfld.long 0x00 17. "PFD_528_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PFD_480_AUTOGATE_EN,This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "MISC2,Miscellaneous Control Register"
|
|
bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
|
|
newline
|
|
rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
|
bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit" "0,1"
|
|
rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
|
bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 7. "PLL3_disable,Default value of 0" "0,1"
|
|
bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "MISC2_SET,Miscellaneous Control Register"
|
|
bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
|
|
newline
|
|
rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
|
bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit" "0,1"
|
|
rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
|
bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 7. "PLL3_disable,Default value of 0" "0,1"
|
|
bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MISC2_CLR,Miscellaneous Control Register"
|
|
bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
|
|
newline
|
|
rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
|
bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit" "0,1"
|
|
rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
|
bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 7. "PLL3_disable,Default value of 0" "0,1"
|
|
bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "MISC2_TOG,Miscellaneous Control Register"
|
|
bitfld.long 0x00 28.--29. "REG2_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 26.--27. "REG1_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "REG0_STEP_TIME,Number of clock periods (24MHz clock)" "0: 64_CLOCKS,1: 128_CLOCKS,2: 256_CLOCKS,3: 512_CLOCKS"
|
|
bitfld.long 0x00 23. "AUDIO_DIV_MSB,MSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_MSB_1"
|
|
newline
|
|
rbitfld.long 0x00 22. "REG2_OK,Signals that the voltage is above the brownout level for the SOC supply" "0,1"
|
|
bitfld.long 0x00 21. "REG2_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "REG2_BO_STATUS,Reg2 brownout status bit" "0,1"
|
|
rbitfld.long 0x00 16.--18. "REG2_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 15. "AUDIO_DIV_LSB,LSB of Post-divider for Audio PLL" "0: divide by 1 (Default),1: AUDIO_DIV_LSB_1"
|
|
bitfld.long 0x00 13. "REG1_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "REG1_BO_STATUS,Reg1 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 8.--10. "REG1_BO_OFFSET,This field defines the brown out voltage offset for the xPU power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
newline
|
|
bitfld.long 0x00 7. "PLL3_disable,Default value of 0" "0,1"
|
|
bitfld.long 0x00 5. "REG0_ENABLE_BO,Enables the brownout detection" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "REG0_BO_STATUS,Reg0 brownout status bit" "?,1: Brownout supply is below target minus.."
|
|
rbitfld.long 0x00 0.--2. "REG0_BO_OFFSET,This field defines the brown out voltage offset for the CORE power domain" "?,?,?,?,4: Brownout offset = 0.100V,?,?,7: Brownout offset = 0.175V"
|
|
tree.end
|
|
tree "TEMPMON (Temperature Monitor)"
|
|
base ad:0x400D8000
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TEMPSENSE0,Tempsensor Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "ALARM_VALUE,This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 8.--19. 1. "TEMP_CNT,This bit field contains the last measured temperature count"
|
|
newline
|
|
rbitfld.long 0x00 2. "FINISHED,Indicates that the latest temp is valid" "0: Last measurement is not ready yet,1: Last measurement is valid"
|
|
bitfld.long 0x00 1. "MEASURE_TEMP,Starts the measurement process" "0: Do not start the measurement process,1: Start the measurement process"
|
|
newline
|
|
bitfld.long 0x00 0. "POWER_DOWN,This bit powers down the temperature sensor" "0: Enable power to the temperature sensor,1: Power down the temperature sensor"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TEMPSENSE0_SET,Tempsensor Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "ALARM_VALUE,This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 8.--19. 1. "TEMP_CNT,This bit field contains the last measured temperature count"
|
|
newline
|
|
rbitfld.long 0x00 2. "FINISHED,Indicates that the latest temp is valid" "0: Last measurement is not ready yet,1: Last measurement is valid"
|
|
bitfld.long 0x00 1. "MEASURE_TEMP,Starts the measurement process" "0: Do not start the measurement process,1: Start the measurement process"
|
|
newline
|
|
bitfld.long 0x00 0. "POWER_DOWN,This bit powers down the temperature sensor" "0: Enable power to the temperature sensor,1: Power down the temperature sensor"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TEMPSENSE0_CLR,Tempsensor Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "ALARM_VALUE,This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 8.--19. 1. "TEMP_CNT,This bit field contains the last measured temperature count"
|
|
newline
|
|
rbitfld.long 0x00 2. "FINISHED,Indicates that the latest temp is valid" "0: Last measurement is not ready yet,1: Last measurement is valid"
|
|
bitfld.long 0x00 1. "MEASURE_TEMP,Starts the measurement process" "0: Do not start the measurement process,1: Start the measurement process"
|
|
newline
|
|
bitfld.long 0x00 0. "POWER_DOWN,This bit powers down the temperature sensor" "0: Enable power to the temperature sensor,1: Power down the temperature sensor"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TEMPSENSE0_TOG,Tempsensor Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "ALARM_VALUE,This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 8.--19. 1. "TEMP_CNT,This bit field contains the last measured temperature count"
|
|
newline
|
|
rbitfld.long 0x00 2. "FINISHED,Indicates that the latest temp is valid" "0: Last measurement is not ready yet,1: Last measurement is valid"
|
|
bitfld.long 0x00 1. "MEASURE_TEMP,Starts the measurement process" "0: Do not start the measurement process,1: Start the measurement process"
|
|
newline
|
|
bitfld.long 0x00 0. "POWER_DOWN,This bit powers down the temperature sensor" "0: Enable power to the temperature sensor,1: Power down the temperature sensor"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TEMPSENSE1,Tempsensor Control Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "MEASURE_FREQ,This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TEMPSENSE1_SET,Tempsensor Control Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "MEASURE_FREQ,This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TEMPSENSE1_CLR,Tempsensor Control Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "MEASURE_FREQ,This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TEMPSENSE1_TOG,Tempsensor Control Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "MEASURE_FREQ,This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "TEMPSENSE2,Tempsensor Control Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "PANIC_ALARM_VALUE,This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 0.--11. 1. "LOW_ALARM_VALUE,This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "TEMPSENSE2_SET,Tempsensor Control Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "PANIC_ALARM_VALUE,This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 0.--11. 1. "LOW_ALARM_VALUE,This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "TEMPSENSE2_CLR,Tempsensor Control Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "PANIC_ALARM_VALUE,This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 0.--11. 1. "LOW_ALARM_VALUE,This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "TEMPSENSE2_TOG,Tempsensor Control Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "PANIC_ALARM_VALUE,This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field"
|
|
hexmask.long.word 0x00 0.--11. 1. "LOW_ALARM_VALUE,This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT"
|
|
tree.end
|
|
tree "USB_ANALOG (USB Analog)"
|
|
base ad:0x400D8000
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT,USB VBUS Detect Register"
|
|
bitfld.long 0x00 27. "CHARGE_VBUS,USB OTG charge VBUS" "0,1"
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,USB OTG discharge VBUS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VBUSVALID_PWRUP_CMPS,Powers up comparators for vbus_valid detector" "0,1"
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Set the threshold for the VBUSVALID comparator" "0: 4.0V,1: 4.1V,2: 4.2V,3: 4.3V,4: 4.4V (default),5: 4.5V,6: 4.6V,7: 4.7V"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_SET,USB VBUS Detect Register"
|
|
bitfld.long 0x00 27. "CHARGE_VBUS,USB OTG charge VBUS" "0,1"
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,USB OTG discharge VBUS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VBUSVALID_PWRUP_CMPS,Powers up comparators for vbus_valid detector" "0,1"
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Set the threshold for the VBUSVALID comparator" "0: 4.0V,1: 4.1V,2: 4.2V,3: 4.3V,4: 4.4V (default),5: 4.5V,6: 4.6V,7: 4.7V"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_CLR,USB VBUS Detect Register"
|
|
bitfld.long 0x00 27. "CHARGE_VBUS,USB OTG charge VBUS" "0,1"
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,USB OTG discharge VBUS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VBUSVALID_PWRUP_CMPS,Powers up comparators for vbus_valid detector" "0,1"
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Set the threshold for the VBUSVALID comparator" "0: 4.0V,1: 4.1V,2: 4.2V,3: 4.3V,4: 4.4V (default),5: 4.5V,6: 4.6V,7: 4.7V"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_TOG,USB VBUS Detect Register"
|
|
bitfld.long 0x00 27. "CHARGE_VBUS,USB OTG charge VBUS" "0,1"
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,USB OTG discharge VBUS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VBUSVALID_PWRUP_CMPS,Powers up comparators for vbus_valid detector" "0,1"
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Set the threshold for the VBUSVALID comparator" "0: 4.0V,1: 4.1V,2: 4.2V,3: 4.3V,4: 4.4V (default),5: 4.5V,6: 4.6V,7: 4.7V"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT,USB Charger Detect Register"
|
|
bitfld.long 0x00 20. "EN_B,Control the charger detector" "0: Enable the charger detector,1: Disable the charger detector"
|
|
bitfld.long 0x00 19. "CHK_CHRG_B,Check the charger connection" "0: Check whether a charger (either a dedicated..,1: Do not check whether a charger is connected.."
|
|
newline
|
|
bitfld.long 0x00 18. "CHK_CONTACT,Check the contact of USB plug" "0: Do not check the contact of USB plug,1: Check whether the USB plug has been in.."
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_SET,USB Charger Detect Register"
|
|
bitfld.long 0x00 20. "EN_B,Control the charger detector" "0: Enable the charger detector,1: Disable the charger detector"
|
|
bitfld.long 0x00 19. "CHK_CHRG_B,Check the charger connection" "0: Check whether a charger (either a dedicated..,1: Do not check whether a charger is connected.."
|
|
newline
|
|
bitfld.long 0x00 18. "CHK_CONTACT,Check the contact of USB plug" "0: Do not check the contact of USB plug,1: Check whether the USB plug has been in.."
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_CLR,USB Charger Detect Register"
|
|
bitfld.long 0x00 20. "EN_B,Control the charger detector" "0: Enable the charger detector,1: Disable the charger detector"
|
|
bitfld.long 0x00 19. "CHK_CHRG_B,Check the charger connection" "0: Check whether a charger (either a dedicated..,1: Do not check whether a charger is connected.."
|
|
newline
|
|
bitfld.long 0x00 18. "CHK_CONTACT,Check the contact of USB plug" "0: Do not check the contact of USB plug,1: Check whether the USB plug has been in.."
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_TOG,USB Charger Detect Register"
|
|
bitfld.long 0x00 20. "EN_B,Control the charger detector" "0: Enable the charger detector,1: Disable the charger detector"
|
|
bitfld.long 0x00 19. "CHK_CHRG_B,Check the charger connection" "0: Check whether a charger (either a dedicated..,1: Do not check whether a charger is connected.."
|
|
newline
|
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bitfld.long 0x00 18. "CHK_CONTACT,Check the contact of USB plug" "0: Do not check the contact of USB plug,1: Check whether the USB plug has been in.."
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_STAT,USB VBUS Detect Status Register"
|
|
bitfld.long 0x00 3. "VBUS_VALID,VBus valid for USB OTG" "0,1"
|
|
bitfld.long 0x00 2. "AVALID,Indicates VBus is valid for a A-peripheral" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "BVALID,Indicates VBus is valid for a B-peripheral" "0,1"
|
|
bitfld.long 0x00 0. "SESSEND,Session End for USB OTG" "0,1"
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_STAT,USB Charger Detect Status Register"
|
|
bitfld.long 0x00 3. "DP_STATE,DP line state output of the charger detector" "0,1"
|
|
bitfld.long 0x00 2. "DM_STATE,DM line state output of the charger detector" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CHRG_DETECTED,State of charger detection" "0: The USB port is not connected to a charger,1: A charger (either a dedicated charger or a.."
|
|
bitfld.long 0x00 0. "PLUG_CONTACT,State of the USB plug contact detector" "0: The USB plug has not made contact,1: The USB plug has made good contact"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "USB1_LOOPBACK,USB Loopback Test Register"
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,Setting this bit can enable 1" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_SET,USB Loopback Test Register"
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,Setting this bit can enable 1" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_CLR,USB Loopback Test Register"
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,Setting this bit can enable 1" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_TOG,USB Loopback Test Register"
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,Setting this bit can enable 1" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "USB1_MISC,USB Misc Register"
|
|
bitfld.long 0x00 30. "EN_CLK_UTMI,Enables the clk to the UTMI block" "0,1"
|
|
bitfld.long 0x00 1. "EN_DEGLITCH,Enable the deglitching circuit of the USB PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_USE_EXTERNAL_R,Use external resistor to generate the current bias for the high speed transmitter" "0,1"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "USB1_MISC_SET,USB Misc Register"
|
|
bitfld.long 0x00 30. "EN_CLK_UTMI,Enables the clk to the UTMI block" "0,1"
|
|
bitfld.long 0x00 1. "EN_DEGLITCH,Enable the deglitching circuit of the USB PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_USE_EXTERNAL_R,Use external resistor to generate the current bias for the high speed transmitter" "0,1"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "USB1_MISC_CLR,USB Misc Register"
|
|
bitfld.long 0x00 30. "EN_CLK_UTMI,Enables the clk to the UTMI block" "0,1"
|
|
bitfld.long 0x00 1. "EN_DEGLITCH,Enable the deglitching circuit of the USB PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_USE_EXTERNAL_R,Use external resistor to generate the current bias for the high speed transmitter" "0,1"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "USB1_MISC_TOG,USB Misc Register"
|
|
bitfld.long 0x00 30. "EN_CLK_UTMI,Enables the clk to the UTMI block" "0,1"
|
|
bitfld.long 0x00 1. "EN_DEGLITCH,Enable the deglitching circuit of the USB PLL output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HS_USE_EXTERNAL_R,Use external resistor to generate the current bias for the high speed transmitter" "0,1"
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "DIGPROG,Chip Silicon Version"
|
|
hexmask.long 0x00 0.--31. 1. "SILICON_REVISION,Chip silicon revision"
|
|
tree.end
|
|
tree "XTALOSC24M"
|
|
base ad:0x400D8000
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MISC0,Miscellaneous Register 0"
|
|
bitfld.long 0x00 31. "VID_PLL_PREDIV,Predivider for the source clock of the PLL's" "0: VID_PLL_PREDIV_0,1: VID_PLL_PREDIV_1"
|
|
bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
|
|
bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
|
|
newline
|
|
bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
|
|
bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
|
|
bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
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|
newline
|
|
bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
|
|
bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode.Not related to oscillator" "0: All analog except rtc powered down on stop..,1: Certain analog functions such as certain..,2: XtalOsc=off RCOsc=on Old BG=on New BG=off,3: XtalOsc=off RCOsc=on Old BG=off New BG=on"
|
|
newline
|
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bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
|
|
bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to oscillator" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
|
|
newline
|
|
bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
|
|
bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MISC0_SET,Miscellaneous Register 0"
|
|
bitfld.long 0x00 31. "VID_PLL_PREDIV,Predivider for the source clock of the PLL's" "0: VID_PLL_PREDIV_0,1: VID_PLL_PREDIV_1"
|
|
bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
|
|
bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
|
|
newline
|
|
bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
|
|
bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
|
|
bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
|
|
newline
|
|
bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
|
|
bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode.Not related to oscillator" "0: All analog except rtc powered down on stop..,1: Certain analog functions such as certain..,2: XtalOsc=off RCOsc=on Old BG=on New BG=off,3: XtalOsc=off RCOsc=on Old BG=off New BG=on"
|
|
newline
|
|
bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
|
|
bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to oscillator" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
|
|
newline
|
|
bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
|
|
bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MISC0_CLR,Miscellaneous Register 0"
|
|
bitfld.long 0x00 31. "VID_PLL_PREDIV,Predivider for the source clock of the PLL's" "0: VID_PLL_PREDIV_0,1: VID_PLL_PREDIV_1"
|
|
bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
|
|
bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
|
|
newline
|
|
bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
|
|
bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
|
|
bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
|
|
newline
|
|
bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
|
|
bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode.Not related to oscillator" "0: All analog except rtc powered down on stop..,1: Certain analog functions such as certain..,2: XtalOsc=off RCOsc=on Old BG=on New BG=off,3: XtalOsc=off RCOsc=on Old BG=off New BG=on"
|
|
newline
|
|
bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
|
|
bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to oscillator" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
|
|
newline
|
|
bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
|
|
bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MISC0_TOG,Miscellaneous Register 0"
|
|
bitfld.long 0x00 31. "VID_PLL_PREDIV,Predivider for the source clock of the PLL's" "0: VID_PLL_PREDIV_0,1: VID_PLL_PREDIV_1"
|
|
bitfld.long 0x00 30. "XTAL_24M_PWD,This field powers down the 24M crystal oscillator if set true" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "RTC_XTAL_SOURCE,This field indicates which chip source is being used for the rtc clock" "0: Internal ring oscillator,1: RTC_XTAL_SOURCE_1"
|
|
bitfld.long 0x00 26.--28. "CLKGATE_DELAY,This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0: CLKGATE_DELAY_0,1: CLKGATE_DELAY_1,2: CLKGATE_DELAY_2,3: CLKGATE_DELAY_3,4: CLKGATE_DELAY_4,5: CLKGATE_DELAY_5,6: CLKGATE_DELAY_6,7: CLKGATE_DELAY_7"
|
|
newline
|
|
bitfld.long 0x00 25. "CLKGATE_CTRL,This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block" "0: Allow the logic to automatically gate the..,1: Prevent the logic from ever gating off the.."
|
|
bitfld.long 0x00 16. "OSC_XTALOK_EN,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. "OSC_XTALOK,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1"
|
|
bitfld.long 0x00 13.--14. "OSC_I,This field determines the bias current in the 24MHz oscillator" "0: NOMINAL,1: Decrease current by 12.5%,2: Decrease current by 25.0%,3: Decrease current by 37.5%"
|
|
newline
|
|
bitfld.long 0x00 12. "DISCON_HIGH_SNVS,This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN" "0: DISCON_HIGH_SNVS_0,1: Turn off the switch"
|
|
bitfld.long 0x00 10.--11. "STOP_MODE_CONFIG,Configure the analog behavior in stop mode.Not related to oscillator" "0: All analog except rtc powered down on stop..,1: Certain analog functions such as certain..,2: XtalOsc=off RCOsc=on Old BG=on New BG=off,3: XtalOsc=off RCOsc=on Old BG=off New BG=on"
|
|
newline
|
|
bitfld.long 0x00 7. "REFTOP_VBGUP,Status bit that signals the analog bandgap voltage is up and stable" "0,1"
|
|
bitfld.long 0x00 4.--6. "REFTOP_VBGADJ,Not related to oscillator" "0: REFTOP_VBGADJ_0,1: REFTOP_VBGADJ_1,2: REFTOP_VBGADJ_2,3: REFTOP_VBGADJ_3,4: REFTOP_VBGADJ_4,5: REFTOP_VBGADJ_5,6: REFTOP_VBGADJ_6,7: REFTOP_VBGADJ_7"
|
|
newline
|
|
bitfld.long 0x00 3. "REFTOP_SELFBIASOFF,Control bit to disable the self-bias circuit in the analog bandgap" "0: Uses coarse bias currents for startup,1: Uses bandgap-based bias currents for best.."
|
|
bitfld.long 0x00 0. "REFTOP_PWD,Control bit to power-down the analog bandgap reference circuitry" "0,1"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "LOWPWR_CTRL,XTAL OSC (LP) Control Register"
|
|
bitfld.long 0x00 18. "GPU_PWRGATE,GPU power gate control" "0,1"
|
|
bitfld.long 0x00 17. "MIX_PWRGATE,Display power gate control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "XTALOSC_PWRUP_STAT,Status of the 24MHz xtal oscillator" "0: XTALOSC_PWRUP_STAT_0,1: Stable and ready to use"
|
|
bitfld.long 0x00 14.--15. "XTALOSC_PWRUP_DELAY,Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use" "0: XTALOSC_PWRUP_DELAY_0,1: XTALOSC_PWRUP_DELAY_1,2: XTALOSC_PWRUP_DELAY_2,3: XTALOSC_PWRUP_DELAY_3"
|
|
newline
|
|
bitfld.long 0x00 13. "RCOSC_CG_OVERRIDE,For debug purposes only" "0,1"
|
|
bitfld.long 0x00 11. "DISPLAY_PWRGATE,Display logic power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CPU_PWRGATE,CPU power gate control" "0,1"
|
|
bitfld.long 0x00 9. "L2_PWRGATE,L2 power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "L1_PWRGATE,L1 power gate control" "0,1"
|
|
bitfld.long 0x00 7. "REFTOP_IBIAS_OFF,Low power reftop ibias disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LPBG_TEST,Low power bandgap test bit" "0,1"
|
|
bitfld.long 0x00 5. "LPBG_SEL,Bandgap select" "0: Normal power bandgap,1: Low power bandgap"
|
|
newline
|
|
bitfld.long 0x00 4. "OSC_SEL,Select the source for the 24MHz clock" "0: OSC_SEL_0,1: OSC_SEL_1"
|
|
bitfld.long 0x00 0. "RC_OSC_EN,RC Osc" "0: Use XTAL OSC to source the 24MHz clock,1: RC_OSC_EN_1"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "LOWPWR_CTRL_SET,XTAL OSC (LP) Control Register"
|
|
bitfld.long 0x00 18. "GPU_PWRGATE,GPU power gate control" "0,1"
|
|
bitfld.long 0x00 17. "MIX_PWRGATE,Display power gate control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "XTALOSC_PWRUP_STAT,Status of the 24MHz xtal oscillator" "0: XTALOSC_PWRUP_STAT_0,1: Stable and ready to use"
|
|
bitfld.long 0x00 14.--15. "XTALOSC_PWRUP_DELAY,Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use" "0: XTALOSC_PWRUP_DELAY_0,1: XTALOSC_PWRUP_DELAY_1,2: XTALOSC_PWRUP_DELAY_2,3: XTALOSC_PWRUP_DELAY_3"
|
|
newline
|
|
bitfld.long 0x00 13. "RCOSC_CG_OVERRIDE,For debug purposes only" "0,1"
|
|
bitfld.long 0x00 11. "DISPLAY_PWRGATE,Display logic power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CPU_PWRGATE,CPU power gate control" "0,1"
|
|
bitfld.long 0x00 9. "L2_PWRGATE,L2 power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "L1_PWRGATE,L1 power gate control" "0,1"
|
|
bitfld.long 0x00 7. "REFTOP_IBIAS_OFF,Low power reftop ibias disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LPBG_TEST,Low power bandgap test bit" "0,1"
|
|
bitfld.long 0x00 5. "LPBG_SEL,Bandgap select" "0: Normal power bandgap,1: Low power bandgap"
|
|
newline
|
|
bitfld.long 0x00 4. "OSC_SEL,Select the source for the 24MHz clock" "0: OSC_SEL_0,1: OSC_SEL_1"
|
|
bitfld.long 0x00 0. "RC_OSC_EN,RC Osc" "0: Use XTAL OSC to source the 24MHz clock,1: RC_OSC_EN_1"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "LOWPWR_CTRL_CLR,XTAL OSC (LP) Control Register"
|
|
bitfld.long 0x00 18. "GPU_PWRGATE,GPU power gate control" "0,1"
|
|
bitfld.long 0x00 17. "MIX_PWRGATE,Display power gate control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "XTALOSC_PWRUP_STAT,Status of the 24MHz xtal oscillator" "0: XTALOSC_PWRUP_STAT_0,1: Stable and ready to use"
|
|
bitfld.long 0x00 14.--15. "XTALOSC_PWRUP_DELAY,Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use" "0: XTALOSC_PWRUP_DELAY_0,1: XTALOSC_PWRUP_DELAY_1,2: XTALOSC_PWRUP_DELAY_2,3: XTALOSC_PWRUP_DELAY_3"
|
|
newline
|
|
bitfld.long 0x00 13. "RCOSC_CG_OVERRIDE,For debug purposes only" "0,1"
|
|
bitfld.long 0x00 11. "DISPLAY_PWRGATE,Display logic power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CPU_PWRGATE,CPU power gate control" "0,1"
|
|
bitfld.long 0x00 9. "L2_PWRGATE,L2 power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "L1_PWRGATE,L1 power gate control" "0,1"
|
|
bitfld.long 0x00 7. "REFTOP_IBIAS_OFF,Low power reftop ibias disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LPBG_TEST,Low power bandgap test bit" "0,1"
|
|
bitfld.long 0x00 5. "LPBG_SEL,Bandgap select" "0: Normal power bandgap,1: Low power bandgap"
|
|
newline
|
|
bitfld.long 0x00 4. "OSC_SEL,Select the source for the 24MHz clock" "0: OSC_SEL_0,1: OSC_SEL_1"
|
|
bitfld.long 0x00 0. "RC_OSC_EN,RC Osc" "0: Use XTAL OSC to source the 24MHz clock,1: RC_OSC_EN_1"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "LOWPWR_CTRL_TOG,XTAL OSC (LP) Control Register"
|
|
bitfld.long 0x00 18. "GPU_PWRGATE,GPU power gate control" "0,1"
|
|
bitfld.long 0x00 17. "MIX_PWRGATE,Display power gate control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "XTALOSC_PWRUP_STAT,Status of the 24MHz xtal oscillator" "0: XTALOSC_PWRUP_STAT_0,1: Stable and ready to use"
|
|
bitfld.long 0x00 14.--15. "XTALOSC_PWRUP_DELAY,Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use" "0: XTALOSC_PWRUP_DELAY_0,1: XTALOSC_PWRUP_DELAY_1,2: XTALOSC_PWRUP_DELAY_2,3: XTALOSC_PWRUP_DELAY_3"
|
|
newline
|
|
bitfld.long 0x00 13. "RCOSC_CG_OVERRIDE,For debug purposes only" "0,1"
|
|
bitfld.long 0x00 11. "DISPLAY_PWRGATE,Display logic power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CPU_PWRGATE,CPU power gate control" "0,1"
|
|
bitfld.long 0x00 9. "L2_PWRGATE,L2 power gate control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "L1_PWRGATE,L1 power gate control" "0,1"
|
|
bitfld.long 0x00 7. "REFTOP_IBIAS_OFF,Low power reftop ibias disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LPBG_TEST,Low power bandgap test bit" "0,1"
|
|
bitfld.long 0x00 5. "LPBG_SEL,Bandgap select" "0: Normal power bandgap,1: Low power bandgap"
|
|
newline
|
|
bitfld.long 0x00 4. "OSC_SEL,Select the source for the 24MHz clock" "0: OSC_SEL_0,1: OSC_SEL_1"
|
|
bitfld.long 0x00 0. "RC_OSC_EN,RC Osc" "0: Use XTAL OSC to source the 24MHz clock,1: RC_OSC_EN_1"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "OSC_CONFIG0,XTAL OSC Configuration 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RC_OSC_PROG_CUR,The current tuning value in use"
|
|
bitfld.long 0x00 16.--19. "HYST_MINUS,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HYST_PLUS,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 4.--11. 1. "RC_OSC_PROG,RC osc"
|
|
newline
|
|
bitfld.long 0x00 3. "INVERT,Invert the stepping of the calculated RC tuning value" "0,1"
|
|
bitfld.long 0x00 2. "BYPASS,Bypasses any calculated RC tuning value and uses the programmed register value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Enables the tuning logic to calculate new RC tuning values" "0,1"
|
|
bitfld.long 0x00 0. "START,Start/stop bit for the RC tuning calculation logic" "0,1"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "OSC_CONFIG0_SET,XTAL OSC Configuration 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RC_OSC_PROG_CUR,The current tuning value in use"
|
|
bitfld.long 0x00 16.--19. "HYST_MINUS,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HYST_PLUS,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 4.--11. 1. "RC_OSC_PROG,RC osc"
|
|
newline
|
|
bitfld.long 0x00 3. "INVERT,Invert the stepping of the calculated RC tuning value" "0,1"
|
|
bitfld.long 0x00 2. "BYPASS,Bypasses any calculated RC tuning value and uses the programmed register value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Enables the tuning logic to calculate new RC tuning values" "0,1"
|
|
bitfld.long 0x00 0. "START,Start/stop bit for the RC tuning calculation logic" "0,1"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "OSC_CONFIG0_CLR,XTAL OSC Configuration 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RC_OSC_PROG_CUR,The current tuning value in use"
|
|
bitfld.long 0x00 16.--19. "HYST_MINUS,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HYST_PLUS,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 4.--11. 1. "RC_OSC_PROG,RC osc"
|
|
newline
|
|
bitfld.long 0x00 3. "INVERT,Invert the stepping of the calculated RC tuning value" "0,1"
|
|
bitfld.long 0x00 2. "BYPASS,Bypasses any calculated RC tuning value and uses the programmed register value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Enables the tuning logic to calculate new RC tuning values" "0,1"
|
|
bitfld.long 0x00 0. "START,Start/stop bit for the RC tuning calculation logic" "0,1"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "OSC_CONFIG0_TOG,XTAL OSC Configuration 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RC_OSC_PROG_CUR,The current tuning value in use"
|
|
bitfld.long 0x00 16.--19. "HYST_MINUS,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HYST_PLUS,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 4.--11. 1. "RC_OSC_PROG,RC osc"
|
|
newline
|
|
bitfld.long 0x00 3. "INVERT,Invert the stepping of the calculated RC tuning value" "0,1"
|
|
bitfld.long 0x00 2. "BYPASS,Bypasses any calculated RC tuning value and uses the programmed register value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE,Enables the tuning logic to calculate new RC tuning values" "0,1"
|
|
bitfld.long 0x00 0. "START,Start/stop bit for the RC tuning calculation logic" "0,1"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "OSC_CONFIG1,XTAL OSC Configuration 1 Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "COUNT_RC_CUR,The current tuning value in use"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_RC_TRG,The target count used to tune the RC OSC frequency"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "OSC_CONFIG1_SET,XTAL OSC Configuration 1 Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "COUNT_RC_CUR,The current tuning value in use"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_RC_TRG,The target count used to tune the RC OSC frequency"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "OSC_CONFIG1_CLR,XTAL OSC Configuration 1 Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "COUNT_RC_CUR,The current tuning value in use"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_RC_TRG,The target count used to tune the RC OSC frequency"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "OSC_CONFIG1_TOG,XTAL OSC Configuration 1 Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "COUNT_RC_CUR,The current tuning value in use"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_RC_TRG,The target count used to tune the RC OSC frequency"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "OSC_CONFIG2,XTAL OSC Configuration 2 Register"
|
|
bitfld.long 0x00 31. "CLK_1M_ERR_FL,Flag indicates that the count_1m count wasn't reached within 1 32kHz period" "0,1"
|
|
bitfld.long 0x00 17. "MUX_1M,Mux the corrected or uncorrected 1MHz clock to the output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENABLE_1M,Enable the 1MHz clock output" "0: disabled,1: enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_1M_TRG,The target count used to tune the 1MHz clock frequency"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "OSC_CONFIG2_SET,XTAL OSC Configuration 2 Register"
|
|
bitfld.long 0x00 31. "CLK_1M_ERR_FL,Flag indicates that the count_1m count wasn't reached within 1 32kHz period" "0,1"
|
|
bitfld.long 0x00 17. "MUX_1M,Mux the corrected or uncorrected 1MHz clock to the output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENABLE_1M,Enable the 1MHz clock output" "0: disabled,1: enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_1M_TRG,The target count used to tune the 1MHz clock frequency"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "OSC_CONFIG2_CLR,XTAL OSC Configuration 2 Register"
|
|
bitfld.long 0x00 31. "CLK_1M_ERR_FL,Flag indicates that the count_1m count wasn't reached within 1 32kHz period" "0,1"
|
|
bitfld.long 0x00 17. "MUX_1M,Mux the corrected or uncorrected 1MHz clock to the output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENABLE_1M,Enable the 1MHz clock output" "0: disabled,1: enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_1M_TRG,The target count used to tune the 1MHz clock frequency"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "OSC_CONFIG2_TOG,XTAL OSC Configuration 2 Register"
|
|
bitfld.long 0x00 31. "CLK_1M_ERR_FL,Flag indicates that the count_1m count wasn't reached within 1 32kHz period" "0,1"
|
|
bitfld.long 0x00 17. "MUX_1M,Mux the corrected or uncorrected 1MHz clock to the output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENABLE_1M,Enable the 1MHz clock output" "0: disabled,1: enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. "COUNT_1M_TRG,The target count used to tune the 1MHz clock frequency"
|
|
tree.end
|
|
tree "USBPHY (USBPHY Register Reference Index)"
|
|
base ad:0x400D9000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWD,USB PHY Power-Down Register"
|
|
hexmask.long.word 0x00 21.--31. 1. "RSVD2,Reserved"
|
|
bitfld.long 0x00 20. "RXPWDRX," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF," "0,1"
|
|
bitfld.long 0x00 18. "RXPWD1PT1," "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV," "0,1"
|
|
rbitfld.long 0x00 13.--16. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I," "0,1"
|
|
bitfld.long 0x00 11. "TXPWDIBIAS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS," "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "RSVD0,Reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWD_SET,USB PHY Power-Down Register"
|
|
hexmask.long.word 0x00 21.--31. 1. "RSVD2,Reserved"
|
|
bitfld.long 0x00 20. "RXPWDRX," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF," "0,1"
|
|
bitfld.long 0x00 18. "RXPWD1PT1," "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV," "0,1"
|
|
rbitfld.long 0x00 13.--16. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I," "0,1"
|
|
bitfld.long 0x00 11. "TXPWDIBIAS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS," "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "RSVD0,Reserved"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWD_CLR,USB PHY Power-Down Register"
|
|
hexmask.long.word 0x00 21.--31. 1. "RSVD2,Reserved"
|
|
bitfld.long 0x00 20. "RXPWDRX," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF," "0,1"
|
|
bitfld.long 0x00 18. "RXPWD1PT1," "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV," "0,1"
|
|
rbitfld.long 0x00 13.--16. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I," "0,1"
|
|
bitfld.long 0x00 11. "TXPWDIBIAS," "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS," "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "RSVD0,Reserved"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWD_TOG,USB PHY Power-Down Register"
|
|
hexmask.long.word 0x00 21.--31. 1. "RSVD2,Reserved"
|
|
bitfld.long 0x00 20. "RXPWDRX," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF," "0,1"
|
|
bitfld.long 0x00 18. "RXPWD1PT1," "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV," "0,1"
|
|
rbitfld.long 0x00 13.--16. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I," "0,1"
|
|
bitfld.long 0x00 11. "TXPWDIBIAS," "0,1"
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|
newline
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bitfld.long 0x00 10. "TXPWDFS," "0,1"
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|
hexmask.long.word 0x00 0.--9. 1. "RSVD0,Reserved"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "TX,USB PHY Transmitter Control Register"
|
|
rbitfld.long 0x00 29.--31. "RSVD5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--28. "USBPHY_TX_EDGECTRL,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7"
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|
newline
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rbitfld.long 0x00 20.--25. "RSVD2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 12.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "TXCAL45DN,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "D_CAL,Resistor Trimming Code" "0: 0.16%,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: +25%"
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|
group.long 0x14++0x03
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line.long 0x00 "TX_SET,USB PHY Transmitter Control Register"
|
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rbitfld.long 0x00 29.--31. "RSVD5,Reserved" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 26.--28. "USBPHY_TX_EDGECTRL,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7"
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|
newline
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rbitfld.long 0x00 20.--25. "RSVD2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "TXCAL45DN,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "D_CAL,Resistor Trimming Code" "0: 0.16%,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: +25%"
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|
group.long 0x18++0x03
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line.long 0x00 "TX_CLR,USB PHY Transmitter Control Register"
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rbitfld.long 0x00 29.--31. "RSVD5,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26.--28. "USBPHY_TX_EDGECTRL,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 20.--25. "RSVD2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "TXCAL45DN,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "D_CAL,Resistor Trimming Code" "0: 0.16%,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: +25%"
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|
group.long 0x1C++0x03
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line.long 0x00 "TX_TOG,USB PHY Transmitter Control Register"
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rbitfld.long 0x00 29.--31. "RSVD5,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 26.--28. "USBPHY_TX_EDGECTRL,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 20.--25. "RSVD2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "TXCAL45DN,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "D_CAL,Resistor Trimming Code" "0: 0.16%,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: +25%"
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group.long 0x20++0x03
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line.long 0x00 "RX,USB PHY Receiver Control Register"
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hexmask.long.word 0x00 23.--31. 1. "RSVD2,Reserved"
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bitfld.long 0x00 22. "RXDBYPASS," "0,1"
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newline
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hexmask.long.word 0x00 7.--21. 1. "RSVD1,Reserved"
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bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 3. "RSVD0,Reserved" "0,1"
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bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0,1,2,3,4,5,6,7"
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group.long 0x24++0x03
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line.long 0x00 "RX_SET,USB PHY Receiver Control Register"
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hexmask.long.word 0x00 23.--31. 1. "RSVD2,Reserved"
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bitfld.long 0x00 22. "RXDBYPASS," "0,1"
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newline
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hexmask.long.word 0x00 7.--21. 1. "RSVD1,Reserved"
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bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 3. "RSVD0,Reserved" "0,1"
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bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0,1,2,3,4,5,6,7"
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group.long 0x28++0x03
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line.long 0x00 "RX_CLR,USB PHY Receiver Control Register"
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hexmask.long.word 0x00 23.--31. 1. "RSVD2,Reserved"
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bitfld.long 0x00 22. "RXDBYPASS," "0,1"
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newline
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hexmask.long.word 0x00 7.--21. 1. "RSVD1,Reserved"
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bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 3. "RSVD0,Reserved" "0,1"
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bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0,1,2,3,4,5,6,7"
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group.long 0x2C++0x03
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line.long 0x00 "RX_TOG,USB PHY Receiver Control Register"
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hexmask.long.word 0x00 23.--31. 1. "RSVD2,Reserved"
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bitfld.long 0x00 22. "RXDBYPASS," "0,1"
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newline
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hexmask.long.word 0x00 7.--21. 1. "RSVD1,Reserved"
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bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 3. "RSVD0,Reserved" "0,1"
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bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0,1,2,3,4,5,6,7"
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group.long 0x30++0x03
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line.long 0x00 "CTRL,USB PHY General Control Register"
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bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHYx_PWD USBPHYx_TX USBPHYx_RX and USBPHYx_CTRL registers" "0,1"
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bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
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newline
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rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
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bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with LS timing" "0,1"
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newline
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rbitfld.long 0x00 27. "OTG_ID_VALUE,Almost same as OTGID_STATUS in USBPHYx_STATUS Register" "0,1"
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rbitfld.long 0x00 25.--26. "RSVD1,Reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
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bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "0,1"
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newline
|
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bitfld.long 0x00 22. "ENIDCHG_WKUP,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "0,1"
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bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "0,1"
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newline
|
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bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "0,1"
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bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
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newline
|
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bitfld.long 0x00 18. "ENAUTO_PWRON_PLL,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "0,1"
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bitfld.long 0x00 17. "WAKEUP_IRQ,Indicates that there is a wakeup event" "0,1"
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newline
|
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bitfld.long 0x00 16. "ENIRQWAKEUP,Enables interrupt for the wakeup events" "0,1"
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bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level3" "0,1"
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newline
|
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bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level2" "0,1"
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bitfld.long 0x00 13. "DATA_ON_LRADC,Enables the LRADC to monitor USB_DP and USB_DM" "0,1"
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newline
|
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bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
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bitfld.long 0x00 11. "ENIRQDEVPLUGIN,Enables interrupt for the detection of connectivity to the USB line" "0,1"
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newline
|
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bitfld.long 0x00 10. "RESUME_IRQ,Indicates that the host is sending a wake-up after suspend" "0,1"
|
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bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enables interrupt for detection of a non-J state on the USB line" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "RESUMEIRQSTICKY,Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
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bitfld.long 0x00 7. "ENOTGIDDETECT,Enables circuit to detect resistance of MiniAB ID pin" "0,1"
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newline
|
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bitfld.long 0x00 6. "OTG_ID_CHG_IRQ,OTG ID change interrupt" "0,1"
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bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "ENDEVPLUGINDETECT,For device mode enables 200-KOhm pullups for detecting connectivity to the host" "0,1"
|
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bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in high-speed mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
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newline
|
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bitfld.long 0x00 0. "ENOTG_ID_CHG_IRQ,Enable OTG_ID_CHG_IRQ" "0,1"
|
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group.long 0x34++0x03
|
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line.long 0x00 "CTRL_SET,USB PHY General Control Register"
|
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bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHYx_PWD USBPHYx_TX USBPHYx_RX and USBPHYx_CTRL registers" "0,1"
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bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
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rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with LS timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Almost same as OTGID_STATUS in USBPHYx_STATUS Register" "0,1"
|
|
rbitfld.long 0x00 25.--26. "RSVD1,Reserved" "0,1,2,3"
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|
newline
|
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bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "ENIDCHG_WKUP,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "0,1"
|
|
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "ENAUTO_PWRON_PLL,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "0,1"
|
|
bitfld.long 0x00 17. "WAKEUP_IRQ,Indicates that there is a wakeup event" "0,1"
|
|
newline
|
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bitfld.long 0x00 16. "ENIRQWAKEUP,Enables interrupt for the wakeup events" "0,1"
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level2" "0,1"
|
|
bitfld.long 0x00 13. "DATA_ON_LRADC,Enables the LRADC to monitor USB_DP and USB_DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
bitfld.long 0x00 11. "ENIRQDEVPLUGIN,Enables interrupt for the detection of connectivity to the USB line" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "RESUME_IRQ,Indicates that the host is sending a wake-up after suspend" "0,1"
|
|
bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enables interrupt for detection of a non-J state on the USB line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RESUMEIRQSTICKY,Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
|
|
bitfld.long 0x00 7. "ENOTGIDDETECT,Enables circuit to detect resistance of MiniAB ID pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "OTG_ID_CHG_IRQ,OTG ID change interrupt" "0,1"
|
|
bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDETECT,For device mode enables 200-KOhm pullups for detecting connectivity to the host" "0,1"
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in high-speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENOTG_ID_CHG_IRQ,Enable OTG_ID_CHG_IRQ" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CTRL_CLR,USB PHY General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHYx_PWD USBPHYx_TX USBPHYx_RX and USBPHYx_CTRL registers" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with LS timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Almost same as OTGID_STATUS in USBPHYx_STATUS Register" "0,1"
|
|
rbitfld.long 0x00 25.--26. "RSVD1,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "ENIDCHG_WKUP,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "0,1"
|
|
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "ENAUTO_PWRON_PLL,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "0,1"
|
|
bitfld.long 0x00 17. "WAKEUP_IRQ,Indicates that there is a wakeup event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENIRQWAKEUP,Enables interrupt for the wakeup events" "0,1"
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level2" "0,1"
|
|
bitfld.long 0x00 13. "DATA_ON_LRADC,Enables the LRADC to monitor USB_DP and USB_DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
bitfld.long 0x00 11. "ENIRQDEVPLUGIN,Enables interrupt for the detection of connectivity to the USB line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RESUME_IRQ,Indicates that the host is sending a wake-up after suspend" "0,1"
|
|
bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enables interrupt for detection of a non-J state on the USB line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RESUMEIRQSTICKY,Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
|
|
bitfld.long 0x00 7. "ENOTGIDDETECT,Enables circuit to detect resistance of MiniAB ID pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "OTG_ID_CHG_IRQ,OTG ID change interrupt" "0,1"
|
|
bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDETECT,For device mode enables 200-KOhm pullups for detecting connectivity to the host" "0,1"
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in high-speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENOTG_ID_CHG_IRQ,Enable OTG_ID_CHG_IRQ" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CTRL_TOG,USB PHY General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHYx_PWD USBPHYx_TX USBPHYx_RX and USBPHYx_CTRL registers" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with LS timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Almost same as OTGID_STATUS in USBPHYx_STATUS Register" "0,1"
|
|
rbitfld.long 0x00 25.--26. "RSVD1,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "ENIDCHG_WKUP,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "0,1"
|
|
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "ENAUTO_PWRON_PLL,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "0,1"
|
|
bitfld.long 0x00 17. "WAKEUP_IRQ,Indicates that there is a wakeup event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ENIRQWAKEUP,Enables interrupt for the wakeup events" "0,1"
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level2" "0,1"
|
|
bitfld.long 0x00 13. "DATA_ON_LRADC,Enables the LRADC to monitor USB_DP and USB_DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
bitfld.long 0x00 11. "ENIRQDEVPLUGIN,Enables interrupt for the detection of connectivity to the USB line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RESUME_IRQ,Indicates that the host is sending a wake-up after suspend" "0,1"
|
|
bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enables interrupt for detection of a non-J state on the USB line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RESUMEIRQSTICKY,Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
|
|
bitfld.long 0x00 7. "ENOTGIDDETECT,Enables circuit to detect resistance of MiniAB ID pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "OTG_ID_CHG_IRQ,OTG ID change interrupt" "0,1"
|
|
bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDETECT,For device mode enables 200-KOhm pullups for detecting connectivity to the host" "0,1"
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in high-speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENOTG_ID_CHG_IRQ,Enable OTG_ID_CHG_IRQ" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "STATUS,USB PHY Status Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "RSVD4,Reserved"
|
|
rbitfld.long 0x00 10. "RESUME_STATUS,Indicates that the host is sending a wake-up after suspend and has triggered an interrupt" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "RSVD3,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "OTGID_STATUS,Indicates the results of ID pin on MiniAB plug" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "RSVD2,Reserved" "0,1"
|
|
rbitfld.long 0x00 6. "DEVPLUGIN_STATUS,Indicates that the device has been connected on the USB_DP and USB_DM lines" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "RSVD1,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 3. "HOSTDISCONDETECT_STATUS,Indicates that the device has disconnected while in high-speed host mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DEBUG,USB PHY Debug Register"
|
|
rbitfld.long 0x00 31. "RSVD3,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
rbitfld.long 0x00 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RSVD0,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,Set bit 3 to 1 to pull down 15-KOhm on USB_DP line" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS use this to hold the value" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DEBUG_SET,USB PHY Debug Register"
|
|
rbitfld.long 0x00 31. "RSVD3,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
rbitfld.long 0x00 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RSVD0,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,Set bit 3 to 1 to pull down 15-KOhm on USB_DP line" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS use this to hold the value" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DEBUG_CLR,USB PHY Debug Register"
|
|
rbitfld.long 0x00 31. "RSVD3,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
rbitfld.long 0x00 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RSVD0,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,Set bit 3 to 1 to pull down 15-KOhm on USB_DP line" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS use this to hold the value" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DEBUG_TOG,USB PHY Debug Register"
|
|
rbitfld.long 0x00 31. "RSVD3,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
rbitfld.long 0x00 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RSVD0,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,Set bit 3 to 1 to pull down 15-KOhm on USB_DP line" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS use this to hold the value" "0,1"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "DEBUG0_STATUS,UTMI Debug Status Register 0"
|
|
bitfld.long 0x00 26.--31. "SQUELCH_COUNT,Running count of the squelch reset instead of normal end for HS RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "UTMI_RXERROR_FAIL_COUNT,Running count of the UTMI_RXERROR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "LOOP_BACK_FAIL_COUNT,Running count of the failed pseudo-random generator loopback"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DEBUG1,UTMI Debug Status Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RSVD1,Reserved"
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: Delay is +20%,2: Delay is -20%,3: Delay is -40%"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "RSVD0,Reserved"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DEBUG1_SET,UTMI Debug Status Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RSVD1,Reserved"
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: Delay is +20%,2: Delay is -20%,3: Delay is -40%"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "RSVD0,Reserved"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DEBUG1_CLR,UTMI Debug Status Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RSVD1,Reserved"
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: Delay is +20%,2: Delay is -20%,3: Delay is -40%"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "RSVD0,Reserved"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DEBUG1_TOG,UTMI Debug Status Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RSVD1,Reserved"
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: Delay is +20%,2: Delay is -20%,3: Delay is -40%"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "RSVD0,Reserved"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "VERSION,UTMI RTL Version"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR field of the RTL version"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
|
|
tree.end
|
|
tree "CSU (CSU registers)"
|
|
base ad:0x400DC000
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CSL$1,Config security level register"
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|
bitfld.long 0x00 24. "LOCK_S1,The lock bit corresponding to the first slave" "0: Not locked,1: The bits 16-23 are locked and can't be.."
|
|
bitfld.long 0x00 23. "NSW_S1,Non-secure supervisor write access control for the first slave" "0: The non-secure supervisor write access is..,1: The non-secure supervisor write access is.."
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|
newline
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|
bitfld.long 0x00 22. "NUW_S1,Non-secure user write access control for the first slave" "0: The non-secure user write access is disabled..,1: The non-secure user write access is enabled.."
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|
bitfld.long 0x00 21. "SSW_S1,Secure supervisor write access control for the first slave" "0: The secure supervisor write access is..,1: The secure supervisor write access is enabled.."
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|
newline
|
|
bitfld.long 0x00 20. "SUW_S1,Secure user write access control for the first slave" "0: The secure user write access is disabled for..,1: The secure user write access is enabled for.."
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|
bitfld.long 0x00 19. "NSR_S1,Non-secure supervisor read access control for the first slave" "0: The non-secure supervisor read access is..,1: The non-secure supervisor read access is.."
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|
newline
|
|
bitfld.long 0x00 18. "NUR_S1,Non-secure user read access control for the first slave" "0: The non-secure user read access is disabled..,1: The non-secure user read access is enabled.."
|
|
bitfld.long 0x00 17. "SSR_S1,Secure supervisor read access control for the first slave" "0: The secure supervisor read access is disabled..,1: The secure supervisor read access is enabled.."
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|
newline
|
|
bitfld.long 0x00 16. "SUR_S1,Secure user read access control for the first slave" "0: The secure user read access is disabled for..,1: The secure user read access is enabled for.."
|
|
bitfld.long 0x00 8. "LOCK_S2,The lock bit corresponding to the second slave" "0: Not locked,1: Bits 7-0 are locked and cannot be written by.."
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|
newline
|
|
bitfld.long 0x00 7. "NSW_S2,Non-secure supervisor write access control for the second slave" "0: The non-secure supervisor write access is..,1: The non-secure supervisor write access is.."
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|
bitfld.long 0x00 6. "NUW_S2,Non-secure user write access control for the second slave" "0: The non-secure user write access is disabled..,1: The non-secure user write access is enabled.."
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|
newline
|
|
bitfld.long 0x00 5. "SSW_S2,Secure supervisor write access control for the second slave" "0: The secure supervisor write access is..,1: The secure supervisor write access is enabled.."
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|
bitfld.long 0x00 4. "SUW_S2,Secure user write access control for the second slave" "0: The secure user write access is disabled for..,1: The secure user write access is enabled for.."
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|
newline
|
|
bitfld.long 0x00 3. "NSR_S2,Non-secure supervisor read access control for the second slave" "0: The non-secure supervisor read access is..,1: The non-secure supervisor read access is.."
|
|
bitfld.long 0x00 2. "NUR_S2,Non-secure user read access control for the second slave" "0: The non-secure user read access is disabled..,1: The non-secure user read access is enabled.."
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|
newline
|
|
bitfld.long 0x00 1. "SSR_S2,Secure supervisor read access control for the second slave" "0: The secure supervisor read access is disabled..,1: The secure supervisor read access is enabled.."
|
|
bitfld.long 0x00 0. "SUR_S2,Secure user read access control for the second slave" "0: The secure user read access is disabled for..,1: The secure user read access is enabled for.."
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|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
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|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "CSL$1,Config security level register"
|
|
bitfld.long 0x00 24. "LOCK_S1,The lock bit corresponding to the first slave" "0: Not locked,1: The bits 16-23 are locked and can't be.."
|
|
bitfld.long 0x00 23. "NSW_S1,Non-secure supervisor write access control for the first slave" "0: The non-secure supervisor write access is..,1: The non-secure supervisor write access is.."
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|
newline
|
|
bitfld.long 0x00 22. "NUW_S1,Non-secure user write access control for the first slave" "0: The non-secure user write access is disabled..,1: The non-secure user write access is enabled.."
|
|
bitfld.long 0x00 21. "SSW_S1,Secure supervisor write access control for the first slave" "0: The secure supervisor write access is..,1: The secure supervisor write access is enabled.."
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|
newline
|
|
bitfld.long 0x00 20. "SUW_S1,Secure user write access control for the first slave" "0: The secure user write access is disabled for..,1: The secure user write access is enabled for.."
|
|
bitfld.long 0x00 19. "NSR_S1,Non-secure supervisor read access control for the first slave" "0: The non-secure supervisor read access is..,1: The non-secure supervisor read access is.."
|
|
newline
|
|
bitfld.long 0x00 18. "NUR_S1,Non-secure user read access control for the first slave" "0: The non-secure user read access is disabled..,1: The non-secure user read access is enabled.."
|
|
bitfld.long 0x00 17. "SSR_S1,Secure supervisor read access control for the first slave" "0: The secure supervisor read access is disabled..,1: The secure supervisor read access is enabled.."
|
|
newline
|
|
bitfld.long 0x00 16. "SUR_S1,Secure user read access control for the first slave" "0: The secure user read access is disabled for..,1: The secure user read access is enabled for.."
|
|
bitfld.long 0x00 8. "LOCK_S2,The lock bit corresponding to the second slave" "0: Not locked,1: Bits 7-0 are locked and cannot be written by.."
|
|
newline
|
|
bitfld.long 0x00 7. "NSW_S2,Non-secure supervisor write access control for the second slave" "0: The non-secure supervisor write access is..,1: The non-secure supervisor write access is.."
|
|
bitfld.long 0x00 6. "NUW_S2,Non-secure user write access control for the second slave" "0: The non-secure user write access is disabled..,1: The non-secure user write access is enabled.."
|
|
newline
|
|
bitfld.long 0x00 5. "SSW_S2,Secure supervisor write access control for the second slave" "0: The secure supervisor write access is..,1: The secure supervisor write access is enabled.."
|
|
bitfld.long 0x00 4. "SUW_S2,Secure user write access control for the second slave" "0: The secure user write access is disabled for..,1: The secure user write access is enabled for.."
|
|
newline
|
|
bitfld.long 0x00 3. "NSR_S2,Non-secure supervisor read access control for the second slave" "0: The non-secure supervisor read access is..,1: The non-secure supervisor read access is.."
|
|
bitfld.long 0x00 2. "NUR_S2,Non-secure user read access control for the second slave" "0: The non-secure user read access is disabled..,1: The non-secure user read access is enabled.."
|
|
newline
|
|
bitfld.long 0x00 1. "SSR_S2,Secure supervisor read access control for the second slave" "0: The secure supervisor read access is disabled..,1: The secure supervisor read access is enabled.."
|
|
bitfld.long 0x00 0. "SUR_S2,Secure user read access control for the second slave" "0: The secure user read access is disabled for..,1: The secure user read access is enabled for.."
|
|
repeat.end
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "HP0,HP0 register"
|
|
bitfld.long 0x00 23. "L_USB,Lock bit set by the TZ software for the USB" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 22. "HP_USB,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 21. "L_TPSMP,Lock bit set by the TZ software for the TPSMP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 20. "HP_TPSMP,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 19. "L_USDHC2,Lock bit set by the TZ software for the USDHC2" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 18. "HP_USDHC2,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 17. "L_USDHC1,Lock bit set by the TZ software for the USDHC1" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 16. "HP_USDHC1,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 15. "L_ENET,Lock bit set by the TZ software for the ENET" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 14. "HP_ENET,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 11. "L_DCP,Lock bit set by the TZ software for the DCP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit cannot be.."
|
|
bitfld.long 0x00 10. "HP_DCP,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 9. "L_PXP,Lock bit set by the TZ software for the PXP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 8. "HP_PXP,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 7. "L_CSI,Lock bit set by the TZ software for the CSI" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 6. "HP_CSI,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 5. "L_LCDIF,Lock bit set by the TZ software for the LCDIF" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 4. "HP_LCDIF,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
newline
|
|
bitfld.long 0x00 3. "L_DMA,Lock bit set by the TZ software for the eDMA" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 2. "HP_DMA,Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA" "0: The hprot1 input signal value is routed to..,1: The HP register bit is routed to the.."
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "SA,Secure access register"
|
|
bitfld.long 0x00 23. "L_USB,Lock bit set by the TZ software for the USB" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 22. "NSA_USB,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 21. "L_TPSMP,Lock bit set by the TZ software for the TPSMP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 20. "NSA_TPSMP,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 19. "L_USDHC2,Lock bit set by the TZ software for the USDHC2" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 18. "NSA_USDHC2,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 17. "L_USDHC1,Lock bit set by the TZ software for the USDHC1" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 16. "NSA_USDHC1,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 15. "L_ENET,Lock bit set by the TZ software for the ENET1 and ENET2" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 14. "NSA_ENET,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 11. "L_DCP,Lock bit set by the TZ software for the DCP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 10. "NSA_DCP,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 9. "L_PXP,Lock bit set by the TZ software for the PXP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 8. "NSA_PXP,Non-Secure Access Policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 7. "L_CSI,Lock bit set by the TZ software for the CSI" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 6. "NSA_CSI,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "L_LCDIF,Lock bit set by the TZ software for the LCDIF" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 4. "NSA_LCDIF,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "L_DMA,Lock bit set by the TZ software for the eDMA" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 2. "NSA_DMA,Non-secure access policy indicator bit" "0: Secure access for the corresponding type-1..,1: Non-secure access for the corresponding.."
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "HPCONTROL0,HPCONTROL0 register"
|
|
bitfld.long 0x00 23. "L_USB,Lock bit set by the TZ software for the USB" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 22. "HPC_USB,Indicates the privilege/user mode for the USB" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 21. "L_TPSMP,Lock bit set by the TZ software for the TPSMP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 20. "HPC_TPSMP,Indicates the privilege/user mode for the TPSMP" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 19. "L_USDHC2,Lock bit set by the TZ software for the USDHC2" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 18. "HPC_USDHC2,Indicates the privilege/user mode for the USDHC2" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 17. "L_USDHC1,Lock bit set by the TZ software for the USDHC1" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 16. "HPC_USDHC1,Indicates the privilege/user mode for the USDHC1" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 15. "L_ENET,Lock bit set by the TZ software for the ENET" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 14. "HPC_ENET,Indicates the privilege/user mode for the ENET" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 11. "L_DCP,Lock bit set by the TZ software for the DCP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 10. "HPC_DCP,Indicates the privilege/user mode for the DCP" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 9. "L_PXP,Lock bit set by the TZ software for the PXP" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 8. "HPC_PXP,Indicates the privilege/user mode for the PXP" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 7. "L_CSI,Lock bit set by the TZ software for the CSI" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 6. "HPC_CSI,Indicates the privilege/user mode for the CSI" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 5. "L_LCDIF,Lock bit set by the TZ software for the LCDIF" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 4. "HPC_LCDIF,Indicates the privilege/user mode for the LCDIF" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
newline
|
|
bitfld.long 0x00 3. "L_DMA,Lock bit set by the TZ software for the eDMA" "0: No lock-the adjacent (next lower) bit can be..,1: Lock-the adjacent (next lower) bit can't be.."
|
|
bitfld.long 0x00 2. "HPC_DMA,Indicates the privilege/user mode for the eDMA" "0: User mode for the corresponding master,1: Supervisor mode for the corresponding master"
|
|
tree.end
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0x400E4000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,Identification register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "REVISION,Revision number of the controller core"
|
|
bitfld.long 0x00 8.--13. "NID,Complement version of ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ID,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "HWGENERAL,Hardware General"
|
|
bitfld.long 0x00 9.--10. "SM,Serial interface mode capability" "0: No Serial Engine always use parallel signalling,1: Serial Engine present always use serial..,2: Software programmable - Reset to use parallel..,3: Software programmable - Reset to use serial.."
|
|
bitfld.long 0x00 6.--8. "PHYM,Transciever type" "0: UTMI/UMTI+,1: ULPI DDR,2: PHYM_2,3: Serial Only,4: Software programmable - reset to UTMI/UTMI+,5: Software programmable - reset to ULPI DDR,6: Software programmable - reset to ULPI,7: Software programmable - reset to Serial"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PHYW,Data width of the transciever connected to the controller core" "0: 8 bit wide data bus Software non-programmable,1: 16 bit wide data bus Software non-programmable,2: Reset to 8 bit wide data bus Software..,3: Reset to 16 bit wide data bus Software.."
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "HWHOST,Host Hardware Parameters"
|
|
bitfld.long 0x00 1.--3. "NPORT,The Nmber of downstream ports supported by the host controller is (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "HC,Host Capable" "0: Not supported,1: Supported"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "HWDEVICE,Device Hardware Parameters"
|
|
bitfld.long 0x00 1.--5. "DEVEP,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. "DC,Device Capable" "0: Not supported,1: Supported"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HWTXBUF,TX Buffer Hardware Parameters"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXCHANADD,TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXBURST,Default burst size for memory to TX buffer transfer"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "HWRXBUF,RX Buffer Hardware Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXADD,Buffer total size for all receive endpoints is (2^RXADD)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXBURST,Default burst size for memory to RX buffer transfer"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPTIMER0LD,General Purpose Timer #0 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x00 31. "GPTRUN,General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit" "0: Stop counting,1: GPTRUN_1"
|
|
bitfld.long 0x00 30. "GPTRST,General Purpose Timer Reset" "0: No action,1: Load counter value from GPTLD bits in.."
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|
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bitfld.long 0x00 24. "GPTMODE,General Purpose Timer Mode In one shot mode the timer will count down to zero generate an interrupt and stop until the counter is reset by software In repeat mode the timer will count down to zero generate an interrupt and automatically reload.." "0: One Shot Mode,1: Repeat Mode"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,General Purpose Timer Counter"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GPTIMER1LD,General Purpose Timer #1 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x00 31. "GPTRUN,General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit" "0: Stop counting,1: GPTRUN_1"
|
|
bitfld.long 0x00 30. "GPTRST,General Purpose Timer Reset" "0: No action,1: Load counter value from GPTLD bits in.."
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|
newline
|
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bitfld.long 0x00 24. "GPTMODE,General Purpose Timer Mode In one shot mode the timer will count down to zero generate an interrupt and stop until the counter is reset by software" "0: One Shot Mode,1: Repeat Mode"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,General Purpose Timer Counter"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. "AHBBRST,AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority)" "0: Incremental burst of unspecified length only,1: INCR4 burst then single transfer,2: INCR8 burst INCR4 burst then single transfer,3: INCR16 burst INCR8 burst INCR4 burst then..,?,5: INCR4 burst then incremental burst of..,6: INCR8 burst INCR4 burst then incremental..,7: INCR16 burst INCR8 burst INCR4 burst then.."
|
|
rgroup.byte 0x100++0x00
|
|
line.byte 0x00 "CAPLENGTH,Capability Registers Length"
|
|
hexmask.byte 0x00 0.--7. 1. "CAPLENGTH,These bits are used as an offset to add to register base to find the beginning of the Operational Register"
|
|
rgroup.word 0x102++0x01
|
|
line.word 0x00 "HCIVERSION,Host Controller Interface Version"
|
|
hexmask.word 0x00 0.--15. 1. "HCIVERSION,Host Controller Interface Version Number Default value is '10h' which means EHCI rev1.0"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters"
|
|
bitfld.long 0x00 24.--27. "N_TT,Number of Transaction Translators (N_TT)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 20.--23. "N_PTT,Number of Ports per Transaction Translator (N_PTT)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16. "PI,Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control" "0,1"
|
|
bitfld.long 0x00 12.--15. "N_CC,Number of Companion Controller (N_CC)" "0: There is no internal Companion Controller and..,1: There are internal companion controller(s)..,?..."
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|
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bitfld.long 0x00 8.--11. "N_PCC,Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4. "PPC,Port Power Control This field indicates whether the host controller implementation includes port power control" "0,1"
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bitfld.long 0x00 0.--3. "N_PORTS,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "HCCPARAMS,Host Controller Capability Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EECP,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x00 4.--7. "IST,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 2. "ASP,Asynchronous Schedule Park Capability If this bit is set to a one then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule" "0,1"
|
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bitfld.long 0x00 1. "PFL,Programmable Frame List Flag If this bit is set to zero then the system software must use a frame list length of 1024 elements with this host controller" "0,1"
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bitfld.long 0x00 0. "ADC,64-bit Addressing Capability This bit is set '0b' in all controller core no 64-bit addressing capability is supported" "0,1"
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "DCIVERSION,Device Controller Interface Version"
|
|
hexmask.word 0x00 0.--15. 1. "DCIVERSION,Device Controller Interface Version Number Default value is '01h' which means rev0.1"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DCCPARAMS,Device Controller Capability Parameters"
|
|
bitfld.long 0x00 8. "HC,Host Capable When this bit is 1 this controller is capable of operating as an EHCI compatible USB 2" "0,1"
|
|
bitfld.long 0x00 7. "DC,Device Capable When this bit is 1 this controller is capable of operating as a USB 2.0 device" "0,1"
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|
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bitfld.long 0x00 0.--4. "DEN,Device Endpoint Number This field indicates the number of endpoints built into the device controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ITC,Interrupt Threshold Control -Read/"
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bitfld.long 0x00 15. "FS_2,Frame List Size - (Read/Write or Read Only)" "0: 1024 elements (4096 bytes) Default value,1: 512 elements (2048 bytes)"
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bitfld.long 0x00 14. "ATDTW,Add dTD TripWire - Read/" "0,1"
|
|
bitfld.long 0x00 13. "SUTW,Setup TripWire - Read/" "0,1"
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|
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|
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bitfld.long 0x00 11. "ASPE,Asynchronous Schedule Park Mode Enable - Read/" "0,1"
|
|
bitfld.long 0x00 8.--9. "ASP,Asynchronous Schedule Park Mode Count - Read/" "0,1,2,3"
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bitfld.long 0x00 6. "IAA,Interrupt on Async Advance Doorbell - Read/" "0,1"
|
|
bitfld.long 0x00 5. "ASE,Asynchronous Schedule Enable - Read/" "0: Do not process the Asynchronous Schedule,1: Use the ASYNCLISTADDR register to access the.."
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|
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bitfld.long 0x00 4. "PSE,Periodic Schedule Enable- Read/" "0: Do not process the Periodic Schedule,1: Use the PERIODICLISTBASE register to access.."
|
|
bitfld.long 0x00 2.--3. "FS_1,See description at bit 15" "0,1,2,3"
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|
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bitfld.long 0x00 1. "RST,Controller Reset (RESET) - Read/" "0,1"
|
|
bitfld.long 0x00 0. "RS,Run/Stop (RS) - Read/" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USBSTS,USB Status Register"
|
|
bitfld.long 0x00 25. "TI1,General Purpose Timer Interrupt 1(GPTINT1)--R/WC" "0,1"
|
|
bitfld.long 0x00 24. "TI0,General Purpose Timer Interrupt 0(GPTINT0)--R/WC" "0,1"
|
|
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|
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rbitfld.long 0x00 16. "NAKI,NAK Interrupt Bit--RO" "0,1"
|
|
bitfld.long 0x00 15. "AS,Asynchronous Schedule Status - Read Only" "0,1"
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|
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|
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bitfld.long 0x00 14. "PS,Periodic Schedule Status - Read Only" "0,1"
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|
bitfld.long 0x00 13. "RCL,Reclamation - Read Only" "0,1"
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|
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bitfld.long 0x00 12. "HCH,HCHaIted - Read Only" "0,1"
|
|
bitfld.long 0x00 10. "ULPII,ULPI Interrupt - R/WC" "0,1"
|
|
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|
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bitfld.long 0x00 8. "SLI,DCSuspend - R/WC" "0,1"
|
|
bitfld.long 0x00 7. "SRI,SOF Received - R/WC" "0,1"
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|
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|
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bitfld.long 0x00 6. "URI,USB Reset Received - R/WC" "0,1"
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|
bitfld.long 0x00 5. "AAI,Interrupt on Async Advance - R/WC" "0,1"
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|
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|
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bitfld.long 0x00 4. "SEI,System Error- R/WC" "0,1"
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|
bitfld.long 0x00 3. "FRI,Frame List Rollover - R/WC" "0,1"
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|
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|
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bitfld.long 0x00 2. "PCI,Port Change Detect - R/WC" "0,1"
|
|
bitfld.long 0x00 1. "UEI,USB Error Interrupt (USBERRINT) - R/WC" "0,1"
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|
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bitfld.long 0x00 0. "UI,USB Interrupt (USBINT) - R/WC" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USBINTR,Interrupt Enable Register"
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bitfld.long 0x00 25. "TIE1,General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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|
bitfld.long 0x00 24. "TIE0,General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 19. "UPIE,USB Host Periodic Interrupt Enable When this bit is one and the UPI bit in the n_USBSTS register is one host controller will issue an interrupt at the next interrupt threshold" "0,1"
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bitfld.long 0x00 18. "UAIE,USB Host Asynchronous Interrupt Enable When this bit is one and the UAI bit in the n_USBSTS register is one host controller will issue an interrupt at the next interrupt threshold" "0,1"
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bitfld.long 0x00 16. "NAKE,NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 10. "ULPIE,ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 8. "SLE,Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt" "0,1"
|
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bitfld.long 0x00 7. "SRE,SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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|
newline
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bitfld.long 0x00 6. "URE,USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 5. "AAE,Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 4. "SEE,System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 3. "FRE,Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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bitfld.long 0x00 2. "PCE,Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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|
bitfld.long 0x00 1. "UEE,USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
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|
newline
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bitfld.long 0x00 0. "UE,USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "FRINDEX,USB Frame Index"
|
|
hexmask.long.word 0x00 0.--13. 1. "FRINDEX,Frame Index"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "DEVICEADDR,Device Address"
|
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hexmask.long.byte 0x00 25.--31. 1. "USBADR,Device Address"
|
|
bitfld.long 0x00 24. "USBADRA,Device Address Advance" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PERIODICLISTBASE,Frame List Base Address"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "BASEADR,Base Address (Low)"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "ASYNCLISTADDR,Next Asynch"
|
|
hexmask.long 0x00 5.--31. 1. "ASYBASE,Link Pointer Low (LPL)"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "ENDPTLISTADDR,Endpoint List Address"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "EPBASE,Endpoint List Pointer(Low)"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. "TXPBURST,Programmable TX Burst Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXPBURST,Programmable RX Burst Size"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TXFILLTUNING,TX FIFO Fill Tuning"
|
|
bitfld.long 0x00 16.--21. "TXFIFOTHRES,FIFO Burst Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--12. "TXSCHHEALTH,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "TXSCHOH,Scheduler Overhead"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "ENDPTNAK,Endpoint NAK"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EPTN,TX Endpoint NAK - R/WC"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EPRN,RX Endpoint NAK - R/WC"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "ENDPTNAKEN,Endpoint NAK Enable"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EPTNE,TX Endpoint NAK Enable - R/W"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EPRNE,RX Endpoint NAK Enable - R/W"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. "CF,Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller" "0: Port routing control logic default-routes..,1: Port routing control logic default-routes all.."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "PORTSC1,Port Status & Control"
|
|
bitfld.long 0x00 30.--31. "PTS_1,All USB port interface modes are listed in this field description but not all are supported" "0,1,2,3"
|
|
bitfld.long 0x00 29. "STS,Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel.." "0,1"
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|
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|
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bitfld.long 0x00 28. "PTW,Parallel Transceiver Width This bit has no effect if serial interface engine is used" "0: Select the 8-bit UTMI interface [60MHz],1: Select the 16-bit UTMI interface [30MHz]"
|
|
bitfld.long 0x00 26.--27. "PSPD,Port Speed - Read Only" "0: Full Speed,1: Low Speed,2: High Speed,3: Undefined"
|
|
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|
|
bitfld.long 0x00 25. "PTS_2,See description at bits 31-30" "0,1"
|
|
bitfld.long 0x00 24. "PFSC,Port Force Full Speed Connect - Read/" "0: Normal operation,1: Forced to full speed"
|
|
newline
|
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bitfld.long 0x00 23. "PHCD,PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/" "0: Enable PHY clock,1: Disable PHY clock"
|
|
bitfld.long 0x00 22. "WKOC,Wake on Over-current Enable (WKOC_E) - Read/" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WKDC,Wake on Disconnect Enable (WKDSCNNT_E) - Read/" "0,1"
|
|
bitfld.long 0x00 20. "WKCN,Wake on Connect Enable (WKCNNT_E) - Read/" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PTC,Port Test Control - Read/" "0: TEST_MODE_DISABLE,1: J_STATE,2: K_STATE,3: SE0 (host) / NAK (device),4: Packet,5: FORCE_ENABLE_HS,6: FORCE_ENABLE_FS,7: FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. "PIC,Port Indicator Control - Read/" "0: Port indicators are off,1: PIC_1,2: PIC_2,3: Undefined"
|
|
newline
|
|
bitfld.long 0x00 13. "PO,Port Owner-Read/" "0,1"
|
|
bitfld.long 0x00 12. "PP,Port Power (PP)-Read/Write or Read Only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LS,Line Status-Read Only" "0: LS_0,1: K-state,2: J-state,3: Undefined"
|
|
rbitfld.long 0x00 9. "HSP,High-Speed Port - Read Only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PR,Port Reset - Read/Write or Read Only" "0,1"
|
|
bitfld.long 0x00 7. "SUSP,Suspend - Read/Write or Read Only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FPR,Force Port Resume -Read/" "0,1"
|
|
bitfld.long 0x00 5. "OCC,Over-current Change-R/WC" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "OCA,Over-current Active-Read Only" "0: This port does not have an over-current..,1: This port currently has an over-current.."
|
|
bitfld.long 0x00 3. "PEC,Port Enable/Disable Change-R/WC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,Port Enabled/Disabled-Read/" "0,1"
|
|
bitfld.long 0x00 1. "CSC,Connect Status Change-R/WC" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "CCS,Current Connect Status-Read Only" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "OTGSC,On-The-Go Status & control"
|
|
bitfld.long 0x00 30. "DPIE,Data Pulse Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 29. "EN_1MS,1 millisecond timer Interrupt Enable - Read/" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "BSEIE,B Session End Interrupt Enable - Read/" "0,1"
|
|
bitfld.long 0x00 27. "BSVIE,B Session Valid Interrupt Enable - Read/" "0,1"
|
|
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|
|
bitfld.long 0x00 26. "ASVIE,A Session Valid Interrupt Enable - Read/" "0,1"
|
|
bitfld.long 0x00 25. "AVVIE,A VBus Valid Interrupt Enable - Read/" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "IDIE,USB ID Interrupt Enable - Read/" "0,1"
|
|
bitfld.long 0x00 22. "DPIS,Data Pulse Interrupt Status - Read/Write to Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "STATUS_1MS,1 millisecond timer Interrupt Status - Read/Write to Clear" "0,1"
|
|
bitfld.long 0x00 20. "BSEIS,B Session End Interrupt Status - Read/Write to Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BSVIS,B Session Valid Interrupt Status - Read/Write to Clear" "0,1"
|
|
bitfld.long 0x00 18. "ASVIS,A Session Valid Interrupt Status - Read/Write to Clear" "0,1"
|
|
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|
|
bitfld.long 0x00 17. "AVVIS,A VBus Valid Interrupt Status - Read/Write to Clear" "0,1"
|
|
bitfld.long 0x00 16. "IDIS,USB ID Interrupt Status - Read/" "0,1"
|
|
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|
|
rbitfld.long 0x00 14. "DPS,Data Bus Pulsing Status - Read Only" "0,1"
|
|
rbitfld.long 0x00 13. "TOG_1MS,1 millisecond timer toggle - Read Only" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 12. "BSE,B Session End - Read Only" "0,1"
|
|
rbitfld.long 0x00 11. "BSV,B Session Valid - Read Only" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "ASV,A Session Valid - Read Only" "0,1"
|
|
rbitfld.long 0x00 9. "AVV,A VBus Valid - Read Only" "0,1"
|
|
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|
|
rbitfld.long 0x00 8. "ID,USB ID - Read Only" "0: A device,1: B device"
|
|
bitfld.long 0x00 5. "IDPU,ID Pullup - Read/Write This bit provide control over the ID pull-up resistor" "0: off,1: on"
|
|
newline
|
|
bitfld.long 0x00 4. "DP,Data Pulsing - Read/" "0,1"
|
|
bitfld.long 0x00 3. "OT,OTG Termination - Read/" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VC,VBUS Charge - Read/" "0,1"
|
|
bitfld.long 0x00 0. "VD,VBUS_Discharge - Read/" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "USBMODE,USB Device Mode"
|
|
bitfld.long 0x00 4. "SDIS,Stream Disable Mode" "0,1"
|
|
bitfld.long 0x00 3. "SLOM,Setup Lockout Mode" "0: Setup Lockouts On (default),1: Setup Lockouts Off (DCD requires use of Setup.."
|
|
newline
|
|
bitfld.long 0x00 2. "ES,Endian Select - Read/" "0: Little Endian [Default],1: Big Endian"
|
|
bitfld.long 0x00 0.--1. "CM,Controller Mode - R/WO" "0: Idle [Default for combination host/device],?,2: Device Controller [Default for device only..,3: Host Controller [Default for host only.."
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status"
|
|
hexmask.long.word 0x00 0.--15. 1. "ENDPTSETUPSTAT,Setup Endpoint Status"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "ENDPTPRIME,Endpoint Prime"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PETB,Prime Endpoint Transmit Buffer - R/WS"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PERB,Prime Endpoint Receive Buffer - R/WS"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "ENDPTFLUSH,Endpoint Flush"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FETB,Flush Endpoint Transmit Buffer - R/WS"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FERB,Flush Endpoint Receive Buffer - R/WS"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "ENDPTSTAT,Endpoint Status"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETBR,Endpoint Transmit Buffer Ready -- Read Only"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERBR,Endpoint Receive Buffer Ready -- Read Only"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "ENDPTCOMPLETE,Endpoint Complete"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETCE,Endpoint Transmit Complete Event - R/WC"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERCE,Endpoint Receive Complete Event - RW/C"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "ENDPTCTRL0,Endpoint Control0"
|
|
bitfld.long 0x00 23. "TXE,TX Endpoint Enable 1 Enabled Endpoint0 is always enabled" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,TX Endpoint Type - Read/" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16. "TXS,TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host" "0,1"
|
|
bitfld.long 0x00 7. "RXE,RX Endpoint Enable 1 Enabled Endpoint0 is always enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RXT,RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RXS,RX Endpoint Stall - Read/Write 0 End Point OK" "0,1"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x1C4)++0x03
|
|
line.long 0x00 "ENDPTCTRL$1,Endpoint Control $1"
|
|
bitfld.long 0x00 23. "TXE,TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured" "0,1"
|
|
bitfld.long 0x00 22. "TXR,TX Data Toggle Reset (WS)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "TXI,TX Data Toggle Inhibit 0 PID Sequencing Enabled" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "TXD,TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0" "0,1"
|
|
bitfld.long 0x00 16. "TXS,TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RXE,RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured" "0,1"
|
|
bitfld.long 0x00 6. "RXR,RX Data Toggle Reset (WS)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RXI,RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero" "0,1"
|
|
bitfld.long 0x00 2.--3. "RXT,RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RXD,RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero" "0,1"
|
|
bitfld.long 0x00 0. "RXS,RX Endpoint Stall - Read/Write 0 End Point OK" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree "USBNC"
|
|
base ad:0x400E4000
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "USB_OTG1_CTRL,USB OTG1 Control Register"
|
|
rbitfld.long 0x00 31. "WIR,OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port" "0: No wake-up interrupt request received,1: Wake-up Interrupt Request received"
|
|
bitfld.long 0x00 29. "WKUP_DPDM_EN,Wake-up on DPDM change enable" "0: DPDM changes wake-up to be disabled only when..,1: (Default) DPDM changes wake-up to be enabled.."
|
|
newline
|
|
bitfld.long 0x00 17. "WKUP_VBUS_EN,OTG1 wake-up on VBUS change enable" "0: WKUP_VBUS_EN_0,1: WKUP_VBUS_EN_1"
|
|
bitfld.long 0x00 16. "WKUP_ID_EN,OTG1 Wake-up on ID change enable" "0: WKUP_ID_EN_0,1: WKUP_ID_EN_1"
|
|
newline
|
|
bitfld.long 0x00 15. "WKUP_SW,OTG1 Software Wake-up" "0: WKUP_SW_0,1: Force wake-up"
|
|
bitfld.long 0x00 14. "WKUP_SW_EN,OTG1 Software Wake-up Enable" "0: WKUP_SW_EN_0,1: WKUP_SW_EN_1"
|
|
newline
|
|
bitfld.long 0x00 10. "WIE,OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 9. "PWR_POL,OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity" "0: PMIC Power Pin is Low active,1: PMIC Power Pin is High active"
|
|
newline
|
|
bitfld.long 0x00 8. "OVER_CUR_POL,OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event" "0: High active (high on this signal represents..,1: Low active (low on this signal represents an.."
|
|
bitfld.long 0x00 7. "OVER_CUR_DIS,Disable OTG1 Overcurrent Detection" "0: Enables overcurrent detection,1: Disables overcurrent detection"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "USB_OTG1_PHY_CTRL_0,OTG1 UTMI PHY Control 0 Register"
|
|
bitfld.long 0x00 31. "UTMI_CLK_VLD,Indicating whether OTG1 UTMI PHY clock is valid" "0: UTMI_CLK_VLD_0,1: UTMI_CLK_VLD_1"
|
|
tree.end
|
|
tree "DMA"
|
|
base ad:0x400E8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
bitfld.long 0x00 17. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 16. "ECX,Error Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer in the.."
|
|
bitfld.long 0x00 7. "EMLM,Enable Minor Loop Mapping" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "CLM,Continuous Link Mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.."
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
newline
|
|
bitfld.long 0x00 4. "HOE,Halt On Error" "0: Normal operation,1: Any error causes the HALT bit to set"
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Fixed priority arbitration is used for..,1: Round robin arbitration is used for channel.."
|
|
newline
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: When in debug mode the DMA continues to operate,1: When in debug mode the DMA stalls the start.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. "VLD,VLD" "0: No ERR bits are set,1: At least one ERR bit is set indicating a.."
|
|
bitfld.long 0x00 16. "ECX,Transfer Canceled" "0: No canceled transfers,1: The last recorded entry was a canceled.."
|
|
newline
|
|
bitfld.long 0x00 14. "CPE,Channel Priority Error" "0: No channel priority error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 8.--11. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: The last recorded error was a bus error on a.."
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: The last recorded error was a bus error on a.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
bitfld.long 0x00 15. "ERQ15,Enable DMA Request 15" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 14. "ERQ14,Enable DMA Request 14" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 13. "ERQ13,Enable DMA Request 13" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 12. "ERQ12,Enable DMA Request 12" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 11. "ERQ11,Enable DMA Request 11" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 10. "ERQ10,Enable DMA Request 10" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 9. "ERQ9,Enable DMA Request 9" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 8. "ERQ8,Enable DMA Request 8" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 7. "ERQ7,Enable DMA Request 7" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 6. "ERQ6,Enable DMA Request 6" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "ERQ5,Enable DMA Request 5" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 4. "ERQ4,Enable DMA Request 4" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "ERQ3,Enable DMA Request 3" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 2. "ERQ2,Enable DMA Request 2" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "ERQ1,Enable DMA Request 1" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 0. "ERQ0,Enable DMA Request 0" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
bitfld.long 0x00 15. "EEI15,Enable Error Interrupt 15" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 14. "EEI14,Enable Error Interrupt 14" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 13. "EEI13,Enable Error Interrupt 13" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 12. "EEI12,Enable Error Interrupt 12" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 11. "EEI11,Enable Error Interrupt 11" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 10. "EEI10,Enable Error Interrupt 10" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 9. "EEI9,Enable Error Interrupt 9" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 8. "EEI8,Enable Error Interrupt 8" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 7. "EEI7,Enable Error Interrupt 7" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 6. "EEI6,Enable Error Interrupt 6" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 5. "EEI5,Enable Error Interrupt 5" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 4. "EEI4,Enable Error Interrupt 4" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 3. "EEI3,Enable Error Interrupt 3" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 2. "EEI2,Enable Error Interrupt 2" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 1. "EEI1,Enable Error Interrupt 1" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 0. "EEI0,Enable Error Interrupt 0" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEE,Clear All Enable Error Interrupts" "0: Clear only the EEI bit specified in the CEEI..,1: Clear all bits in EEI"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CEEI,Clear Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAEE,Sets All Enable Error Interrupts" "0: Set only the EEI bit specified in the SEEI..,1: Sets all bits in EEI"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SEEI,Set Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAER,Clear All Enable Requests" "0: Clear only the ERQ bit specified in the CERQ..,1: Clear all bits in ERQ"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CERQ,Clear Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAER,Set All Enable Requests" "0: Set only the ERQ bit specified in the SERQ..,1: Set all bits in ERQ"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SERQ,Set Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CADN,Clears All DONE Bits" "0: Clears only the TCDn_CSR[DONE] bit specified..,1: Clears all bits in TCDn_CSR[DONE]"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CDNE,Clear DONE Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAST,Set All START Bits (activates all channels)" "0: Set only the TCDn_CSR[START] bit specified in..,1: Set all bits in TCDn_CSR[START]"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SSRT,Set START Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "CERR,Clear Error Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEI,Clear All Error Indicators" "0: Clear only the ERR bit specified in the CERR..,1: Clear all bits in ERR"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CERR,Clear Error Indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAIR,Clear All Interrupt Requests" "0: Clear only the INT bit specified in the CINT..,1: Clear all bits in INT"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CINT,Clear Interrupt Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
eventfld.long 0x00 15. "INT15,Interrupt Request 15" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 14. "INT14,Interrupt Request 14" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 13. "INT13,Interrupt Request 13" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 12. "INT12,Interrupt Request 12" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 11. "INT11,Interrupt Request 11" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 10. "INT10,Interrupt Request 10" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 9. "INT9,Interrupt Request 9" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 8. "INT8,Interrupt Request 8" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 7. "INT7,Interrupt Request 7" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 6. "INT6,Interrupt Request 6" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 5. "INT5,Interrupt Request 5" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 4. "INT4,Interrupt Request 4" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 3. "INT3,Interrupt Request 3" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 2. "INT2,Interrupt Request 2" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 1. "INT1,Interrupt Request 1" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 0. "INT0,Interrupt Request 0" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
eventfld.long 0x00 15. "ERR15,Error In Channel 15" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 14. "ERR14,Error In Channel 14" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 13. "ERR13,Error In Channel 13" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 12. "ERR12,Error In Channel 12" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 11. "ERR11,Error In Channel 11" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 10. "ERR10,Error In Channel 10" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 9. "ERR9,Error In Channel 9" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 8. "ERR8,Error In Channel 8" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 7. "ERR7,Error In Channel 7" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 6. "ERR6,Error In Channel 6" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 5. "ERR5,Error In Channel 5" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 4. "ERR4,Error In Channel 4" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 3. "ERR3,Error In Channel 3" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 2. "ERR2,Error In Channel 2" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 1. "ERR1,Error In Channel 1" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 0. "ERR0,Error In Channel 0" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 15. "HRS15,Hardware Request Status Channel 15" "0: A hardware service request for channel 15 is..,1: A hardware service request for channel 15 is.."
|
|
bitfld.long 0x00 14. "HRS14,Hardware Request Status Channel 14" "0: A hardware service request for channel 14 is..,1: A hardware service request for channel 14 is.."
|
|
newline
|
|
bitfld.long 0x00 13. "HRS13,Hardware Request Status Channel 13" "0: A hardware service request for channel 13 is..,1: A hardware service request for channel 13 is.."
|
|
bitfld.long 0x00 12. "HRS12,Hardware Request Status Channel 12" "0: A hardware service request for channel 12 is..,1: A hardware service request for channel 12 is.."
|
|
newline
|
|
bitfld.long 0x00 11. "HRS11,Hardware Request Status Channel 11" "0: A hardware service request for channel 11 is..,1: A hardware service request for channel 11 is.."
|
|
bitfld.long 0x00 10. "HRS10,Hardware Request Status Channel 10" "0: A hardware service request for channel 10 is..,1: A hardware service request for channel 10 is.."
|
|
newline
|
|
bitfld.long 0x00 9. "HRS9,Hardware Request Status Channel 9" "0: A hardware service request for channel 9 is..,1: A hardware service request for channel 9 is.."
|
|
bitfld.long 0x00 8. "HRS8,Hardware Request Status Channel 8" "0: A hardware service request for channel 8 is..,1: A hardware service request for channel 8 is.."
|
|
newline
|
|
bitfld.long 0x00 7. "HRS7,Hardware Request Status Channel 7" "0: A hardware service request for channel 7 is..,1: A hardware service request for channel 7 is.."
|
|
bitfld.long 0x00 6. "HRS6,Hardware Request Status Channel 6" "0: A hardware service request for channel 6 is..,1: A hardware service request for channel 6 is.."
|
|
newline
|
|
bitfld.long 0x00 5. "HRS5,Hardware Request Status Channel 5" "0: A hardware service request for channel 5 is..,1: A hardware service request for channel 5 is.."
|
|
bitfld.long 0x00 4. "HRS4,Hardware Request Status Channel 4" "0: A hardware service request for channel 4 is..,1: A hardware service request for channel 4 is.."
|
|
newline
|
|
bitfld.long 0x00 3. "HRS3,Hardware Request Status Channel 3" "0: A hardware service request for channel 3 is..,1: A hardware service request for channel 3 is.."
|
|
bitfld.long 0x00 2. "HRS2,Hardware Request Status Channel 2" "0: A hardware service request for channel 2 is..,1: A hardware service request for channel 2 is.."
|
|
newline
|
|
bitfld.long 0x00 1. "HRS1,Hardware Request Status Channel 1" "0: A hardware service request for channel 1 is..,1: A hardware service request for channel 1 is.."
|
|
bitfld.long 0x00 0. "HRS0,Hardware Request Status Channel 0" "0: A hardware service request for channel 0 is..,1: A hardware service request for channel 0 is.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
bitfld.long 0x00 15. "EDREQ_15,Enable asynchronous DMA request in stop mode for channel 15" "0: Disable asynchronous DMA request for channel 15,1: Enable asynchronous DMA request for channel 15"
|
|
bitfld.long 0x00 14. "EDREQ_14,Enable asynchronous DMA request in stop mode for channel 14" "0: Disable asynchronous DMA request for channel 14,1: Enable asynchronous DMA request for channel 14"
|
|
newline
|
|
bitfld.long 0x00 13. "EDREQ_13,Enable asynchronous DMA request in stop mode for channel 13" "0: Disable asynchronous DMA request for channel 13,1: Enable asynchronous DMA request for channel 13"
|
|
bitfld.long 0x00 12. "EDREQ_12,Enable asynchronous DMA request in stop mode for channel 12" "0: Disable asynchronous DMA request for channel 12,1: Enable asynchronous DMA request for channel 12"
|
|
newline
|
|
bitfld.long 0x00 11. "EDREQ_11,Enable asynchronous DMA request in stop mode for channel 11" "0: Disable asynchronous DMA request for channel 11,1: Enable asynchronous DMA request for channel 11"
|
|
bitfld.long 0x00 10. "EDREQ_10,Enable asynchronous DMA request in stop mode for channel 10" "0: Disable asynchronous DMA request for channel 10,1: Enable asynchronous DMA request for channel 10"
|
|
newline
|
|
bitfld.long 0x00 9. "EDREQ_9,Enable asynchronous DMA request in stop mode for channel 9" "0: Disable asynchronous DMA request for channel 9,1: Enable asynchronous DMA request for channel 9"
|
|
bitfld.long 0x00 8. "EDREQ_8,Enable asynchronous DMA request in stop mode for channel 8" "0: Disable asynchronous DMA request for channel 8,1: Enable asynchronous DMA request for channel 8"
|
|
newline
|
|
bitfld.long 0x00 7. "EDREQ_7,Enable asynchronous DMA request in stop mode for channel 7" "0: Disable asynchronous DMA request for channel 7,1: Enable asynchronous DMA request for channel 7"
|
|
bitfld.long 0x00 6. "EDREQ_6,Enable asynchronous DMA request in stop mode for channel 6" "0: Disable asynchronous DMA request for channel 6,1: Enable asynchronous DMA request for channel 6"
|
|
newline
|
|
bitfld.long 0x00 5. "EDREQ_5,Enable asynchronous DMA request in stop mode for channel 5" "0: Disable asynchronous DMA request for channel 5,1: Enable asynchronous DMA request for channel 5"
|
|
bitfld.long 0x00 4. "EDREQ_4,Enable asynchronous DMA request in stop mode for channel 4" "0: Disable asynchronous DMA request for channel 4,1: Enable asynchronous DMA request for channel 4"
|
|
newline
|
|
bitfld.long 0x00 3. "EDREQ_3,Enable asynchronous DMA request in stop mode for channel 3" "0: Disable asynchronous DMA request for channel 3,1: Enable asynchronous DMA request for channel 3"
|
|
bitfld.long 0x00 2. "EDREQ_2,Enable asynchronous DMA request in stop mode for channel 2" "0: Disable asynchronous DMA request for channel 2,1: Enable asynchronous DMA request for channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "EDREQ_1,Enable asynchronous DMA request in stop mode for channel 1" "0: Disable asynchronous DMA request for channel 1,1: Enable asynchronous DMA request for channel 1"
|
|
bitfld.long 0x00 0. "EDREQ_0,Enable asynchronous DMA request in stop mode for channel 0" "0: Disable asynchronous DMA request for channel 0,1: Enable asynchronous DMA request for channel 0"
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI$1,Channel Priority Register"
|
|
bitfld.byte 0x00 7. "ECP,Enable Channel Preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.."
|
|
bitfld.byte 0x00 6. "DPA,Disable Preempt Ability" "0: Channel n can suspend a lower priority channel,1: Channel n cannot suspend any channel.."
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CHPRI,Channel n Arbitration Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1004++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1006++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1014++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x101C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x103C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1044++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1046++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1054++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x105C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1064++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1066++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1074++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x107C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1084++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1086++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1094++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x109C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10A4++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10A6++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10B4++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10BC++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10C4++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10C6++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10D4++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10DC++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10E4++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10E6++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10F4++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10FC++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1104++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1106++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1114++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x111C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1124++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1126++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1134++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x113C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1144++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1146++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x114C++0x03
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1154++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x115C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1164++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1166++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x116C++0x03
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1174++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x117C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1184++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1186++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x118C++0x03
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1194++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x119C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11A4++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11A6++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11B4++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11BC++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11C4++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11C6++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11CC++0x03
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11D4++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11DC++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11E4++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11E6++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,?,5: 32-byte burst (4 beats of 64 bits),?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11EC++0x03
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11F4++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11FC++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
tree.end
|
|
tree "DMAMUX"
|
|
base ad:0x400EC000
|
|
repeat 16. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CHCFG[$1],Channel 0 Configuration Register $1"
|
|
bitfld.long 0x00 31. "ENBL,DMA Mux Channel Enable" "0: DMA Mux channel is disabled,1: DMA Mux channel is enabled"
|
|
bitfld.long 0x00 30. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled,1: Triggering is enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "A_ON,DMA Channel Always Enable" "0: DMA Channel Always ON function is disabled,1: DMA Channel Always ON function is enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. "SOURCE,DMA Channel Source (Slot Number)"
|
|
repeat.end
|
|
tree.end
|
|
tree "DCP"
|
|
base ad:0x400F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,DCP control register 0"
|
|
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable a normal DCP operation" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for a normal operation" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "PRESENT_CRYPTO,Indicates whether the crypto (cipher/hash) functions are present" "0: Absent,1: Present"
|
|
rbitfld.long 0x00 28. "PRESENT_SHA,Indicates whether the SHA1/SHA2 functions are present" "0: Absent,1: Present"
|
|
newline
|
|
bitfld.long 0x00 23. "GATHER_RESIDUAL_WRITES,The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations" "0,1"
|
|
bitfld.long 0x00 22. "ENABLE_CONTEXT_CACHING,The software must set this bit to enable the caching of contexts between the operations" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ENABLE_CONTEXT_SWITCHING,Enable automatic context switching for the channels" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL_INTERRUPT_ENABLE,Per-channel interrupt enable bit"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL_SET,DCP control register 0"
|
|
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable a normal DCP operation" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for a normal operation" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "PRESENT_CRYPTO,Indicates whether the crypto (cipher/hash) functions are present" "0: Absent,1: Present"
|
|
rbitfld.long 0x00 28. "PRESENT_SHA,Indicates whether the SHA1/SHA2 functions are present" "0: Absent,1: Present"
|
|
newline
|
|
bitfld.long 0x00 23. "GATHER_RESIDUAL_WRITES,The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations" "0,1"
|
|
bitfld.long 0x00 22. "ENABLE_CONTEXT_CACHING,The software must set this bit to enable the caching of contexts between the operations" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ENABLE_CONTEXT_SWITCHING,Enable automatic context switching for the channels" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL_INTERRUPT_ENABLE,Per-channel interrupt enable bit"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL_CLR,DCP control register 0"
|
|
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable a normal DCP operation" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for a normal operation" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "PRESENT_CRYPTO,Indicates whether the crypto (cipher/hash) functions are present" "0: Absent,1: Present"
|
|
rbitfld.long 0x00 28. "PRESENT_SHA,Indicates whether the SHA1/SHA2 functions are present" "0: Absent,1: Present"
|
|
newline
|
|
bitfld.long 0x00 23. "GATHER_RESIDUAL_WRITES,The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations" "0,1"
|
|
bitfld.long 0x00 22. "ENABLE_CONTEXT_CACHING,The software must set this bit to enable the caching of contexts between the operations" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ENABLE_CONTEXT_SWITCHING,Enable automatic context switching for the channels" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL_INTERRUPT_ENABLE,Per-channel interrupt enable bit"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTRL_TOG,DCP control register 0"
|
|
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable a normal DCP operation" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for a normal operation" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "PRESENT_CRYPTO,Indicates whether the crypto (cipher/hash) functions are present" "0: Absent,1: Present"
|
|
rbitfld.long 0x00 28. "PRESENT_SHA,Indicates whether the SHA1/SHA2 functions are present" "0: Absent,1: Present"
|
|
newline
|
|
bitfld.long 0x00 23. "GATHER_RESIDUAL_WRITES,The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations" "0,1"
|
|
bitfld.long 0x00 22. "ENABLE_CONTEXT_CACHING,The software must set this bit to enable the caching of contexts between the operations" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ENABLE_CONTEXT_SWITCHING,Enable automatic context switching for the channels" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL_INTERRUPT_ENABLE,Per-channel interrupt enable bit"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STAT,DCP status register"
|
|
rbitfld.long 0x00 28. "OTP_KEY_READY,When set it indicates that the OTP key is shifted from the fuse block and is ready for use" "0,1"
|
|
rbitfld.long 0x00 24.--27. "CUR_CHANNEL,Current (active) channel (encoded)" "0: None,1: CH0,2: CH1,3: CH2,4: CH3,?..."
|
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "READY_CHANNELS,Indicates which channels are ready to proceed with a transfer (the active channel is also included)"
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|
bitfld.long 0x00 0.--3. "IRQ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT_SET,DCP status register"
|
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rbitfld.long 0x00 28. "OTP_KEY_READY,When set it indicates that the OTP key is shifted from the fuse block and is ready for use" "0,1"
|
|
rbitfld.long 0x00 24.--27. "CUR_CHANNEL,Current (active) channel (encoded)" "0: None,1: CH0,2: CH1,3: CH2,4: CH3,?..."
|
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "READY_CHANNELS,Indicates which channels are ready to proceed with a transfer (the active channel is also included)"
|
|
bitfld.long 0x00 0.--3. "IRQ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x18++0x03
|
|
line.long 0x00 "STAT_CLR,DCP status register"
|
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rbitfld.long 0x00 28. "OTP_KEY_READY,When set it indicates that the OTP key is shifted from the fuse block and is ready for use" "0,1"
|
|
rbitfld.long 0x00 24.--27. "CUR_CHANNEL,Current (active) channel (encoded)" "0: None,1: CH0,2: CH1,3: CH2,4: CH3,?..."
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|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "READY_CHANNELS,Indicates which channels are ready to proceed with a transfer (the active channel is also included)"
|
|
bitfld.long 0x00 0.--3. "IRQ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x1C++0x03
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line.long 0x00 "STAT_TOG,DCP status register"
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rbitfld.long 0x00 28. "OTP_KEY_READY,When set it indicates that the OTP key is shifted from the fuse block and is ready for use" "0,1"
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|
rbitfld.long 0x00 24.--27. "CUR_CHANNEL,Current (active) channel (encoded)" "0: None,1: CH0,2: CH1,3: CH2,4: CH3,?..."
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|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "READY_CHANNELS,Indicates which channels are ready to proceed with a transfer (the active channel is also included)"
|
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bitfld.long 0x00 0.--3. "IRQ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x20++0x03
|
|
line.long 0x00 "CHANNELCTRL,DCP channel control register"
|
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bitfld.long 0x00 16. "CH0_IRQ_MERGED,Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "HIGH_PRIORITY_CHANNEL,Setting a bit in this field causes the corresponding channel to have high-priority arbitration"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "ENABLE_CHANNEL,Setting a bit in this field enables the DMA channel associated with it"
|
|
group.long 0x24++0x03
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line.long 0x00 "CHANNELCTRL_SET,DCP channel control register"
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bitfld.long 0x00 16. "CH0_IRQ_MERGED,Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "HIGH_PRIORITY_CHANNEL,Setting a bit in this field causes the corresponding channel to have high-priority arbitration"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "ENABLE_CHANNEL,Setting a bit in this field enables the DMA channel associated with it"
|
|
group.long 0x28++0x03
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line.long 0x00 "CHANNELCTRL_CLR,DCP channel control register"
|
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bitfld.long 0x00 16. "CH0_IRQ_MERGED,Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "HIGH_PRIORITY_CHANNEL,Setting a bit in this field causes the corresponding channel to have high-priority arbitration"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "ENABLE_CHANNEL,Setting a bit in this field enables the DMA channel associated with it"
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group.long 0x2C++0x03
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line.long 0x00 "CHANNELCTRL_TOG,DCP channel control register"
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bitfld.long 0x00 16. "CH0_IRQ_MERGED,Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "HIGH_PRIORITY_CHANNEL,Setting a bit in this field causes the corresponding channel to have high-priority arbitration"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "ENABLE_CHANNEL,Setting a bit in this field enables the DMA channel associated with it"
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group.long 0x30++0x03
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line.long 0x00 "CAPABILITY0,DCP capability 0 register"
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bitfld.long 0x00 31. "DISABLE_DECRYPT,Write to 1 to disable the decryption" "0,1"
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bitfld.long 0x00 29. "DISABLE_UNIQUE_KEY,Write to a 1 to disable the per-device unique key" "0,1"
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newline
|
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rbitfld.long 0x00 8.--11. "NUM_CHANNELS,Encoded value indicating the number of channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "NUM_KEYS,Encoded value indicating the number of key-storage locations implemented in the design"
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rgroup.long 0x40++0x03
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line.long 0x00 "CAPABILITY1,DCP capability 1 register"
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hexmask.long.word 0x00 16.--31. 1. "HASH_ALGORITHMS,One-hot field indicating which hashing features are implemented in the hardware"
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hexmask.long.word 0x00 0.--15. 1. "CIPHER_ALGORITHMS,One-hot field indicating which cipher algorithms are available"
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group.long 0x50++0x03
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line.long 0x00 "CONTEXT,DCP context buffer pointer"
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hexmask.long 0x00 0.--31. 1. "ADDR,Context pointer address"
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group.long 0x60++0x03
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line.long 0x00 "KEY,DCP key index"
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bitfld.long 0x00 4.--5. "INDEX,Key index pointer" "0,1,2,3"
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bitfld.long 0x00 0.--1. "SUBWORD,Key subword pointer" "0,1,2,3"
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group.long 0x70++0x03
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line.long 0x00 "KEYDATA,DCP key data"
|
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hexmask.long 0x00 0.--31. 1. "DATA,Word 0 data for the key"
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rgroup.long 0x80++0x03
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line.long 0x00 "PACKET0,DCP work packet 0 status register"
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hexmask.long 0x00 0.--31. 1. "ADDR,Next pointer register"
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rgroup.long 0x90++0x03
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line.long 0x00 "PACKET1,DCP work packet 1 status register"
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hexmask.long.byte 0x00 24.--31. 1. "TAG,Packet Tag"
|
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bitfld.long 0x00 23. "OUTPUT_WORDSWAP,Reflects whether the DCP engine wordswaps the output data (big-endian data)" "0,1"
|
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newline
|
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bitfld.long 0x00 22. "OUTPUT_BYTESWAP,Reflects whether the DCP engine byteswaps the output data (big-endian data)" "0,1"
|
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bitfld.long 0x00 21. "INPUT_WORDSWAP,Reflects whether the DCP engine wordswaps the input data (big-endian data)" "0,1"
|
|
newline
|
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bitfld.long 0x00 20. "INPUT_BYTESWAP,Reflects whether the DCP engine byteswaps the input data (big-endian data)" "0,1"
|
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bitfld.long 0x00 19. "KEY_WORDSWAP,Reflects whether the DCP engine swaps the key words (big-endian key)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "KEY_BYTESWAP,Reflects whether the DCP engine swaps the key bytes (big-endian key)" "0,1"
|
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bitfld.long 0x00 17. "TEST_SEMA_IRQ,This bit is used to test the channel semaphore transition to 0" "0,1"
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newline
|
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bitfld.long 0x00 16. "CONSTANT_FILL,When this bit is set (MEMCOPY and BLIT modes only) the DCP simply fills the destination buffer with the value found in the source address field" "0,1"
|
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bitfld.long 0x00 15. "HASH_OUTPUT,When the hashing is enabled this bit controls whether the input or output data is hashed" "0: INPUT,1: OUTPUT"
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|
newline
|
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bitfld.long 0x00 14. "CHECK_HASH,Reflects whether the calculated hash value must be compared to the hash provided in the payload" "0,1"
|
|
bitfld.long 0x00 13. "HASH_TERM,Reflects whether the current hashing block is the final block in the hashing operation so the hash padding must be applied by the hardware" "0,1"
|
|
newline
|
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bitfld.long 0x00 12. "HASH_INIT,Reflects whether the current hashing block is the initial block in the hashing operation so the hash registers must be initialized before the operation" "0,1"
|
|
bitfld.long 0x00 11. "PAYLOAD_KEY,When set it indicates the payload contains the key" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "OTP_KEY,Reflects whether a hardware-based key must be used" "0,1"
|
|
bitfld.long 0x00 9. "CIPHER_INIT,Reflects whether the cipher block must load the initialization vector from the payload for this operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CIPHER_ENCRYPT,When the cipher block is enabled this bit indicates whether the operation is encryption or decryption" "0: DECRYPT,1: ENCRYPT"
|
|
bitfld.long 0x00 7. "ENABLE_BLIT,Reflects whether the DCP must perform a blit operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "ENABLE_HASH,Reflects whether the selected hashing function must be enabled for this operation" "0,1"
|
|
bitfld.long 0x00 5. "ENABLE_CIPHER,Reflects whether the selected cipher function must be enabled for this operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENABLE_MEMCOPY,Reflects whether the selected hashing function should be enabled for this operation" "0,1"
|
|
bitfld.long 0x00 3. "CHAIN_CONTIGUOUS,Reflects whether the next packet's address is located following this packet's payload" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer" "0,1"
|
|
bitfld.long 0x00 1. "DECR_SEMAPHORE,Reflects whether the channel's semaphore must be decremented at the end of the current operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTERRUPT,Reflects whether the channel must issue an interrupt upon the completion of the packet" "0,1"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "PACKET2,DCP work packet 2 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CIPHER_CFG,Cipher configuration bits"
|
|
bitfld.long 0x00 16.--19. "HASH_SELECT,Hash Selection Field" "0: SHA1,1: CRC32,2: SHA256,?..."
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "KEY_SELECT,Key selection field"
|
|
bitfld.long 0x00 4.--7. "CIPHER_MODE,Cipher mode selection field" "0: ECB,1: CBC,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CIPHER_SELECT,Cipher selection field" "0: AES128,?..."
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "PACKET3,DCP work packet 3 status register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Source buffer address pointer"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "PACKET4,DCP work packet 4 status register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Destination buffer address pointer"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "PACKET5,DCP work packet 5 status register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Byte count register"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PACKET6,DCP work packet 6 status register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,This regiser reflects the payload pointer for the current control packet"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CH0CMDPTR,DCP channel 0 command pointer address register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Pointer to the descriptor structure to be processed for channel 0"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CH0SEMA,DCP channel 0 semaphore register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "VALUE,This read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT,The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CH0STAT,DCP channel 0 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet payload" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CH0STAT_SET,DCP channel 0 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet payload" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CH0STAT_CLR,DCP channel 0 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet payload" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CH0STAT_TOG,DCP channel 0 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet payload" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CH0OPTS,DCP channel 0 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CH0OPTS_SET,DCP channel 0 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CH0OPTS_CLR,DCP channel 0 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CH0OPTS_TOG,DCP channel 0 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CH1CMDPTR,DCP channel 1 command pointer address register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Pointer to the descriptor structure to be processed for channel 1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CH1SEMA,DCP channel 1 semaphore register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "VALUE,This read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT,The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CH1STAT,DCP channel 1 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CH1STAT_SET,DCP channel 1 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CH1STAT_CLR,DCP channel 1 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CH1STAT_TOG,DCP channel 1 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates the additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CH1OPTS,DCP channel 1 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CH1OPTS_SET,DCP channel 1 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CH1OPTS_CLR,DCP channel 1 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CH1OPTS_TOG,DCP channel 1 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CH2CMDPTR,DCP channel 2 command pointer address register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Pointer to the descriptor structure to be processed for channel 2"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CH2SEMA,DCP channel 2 semaphore register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "VALUE,This read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT,The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CH2STAT,DCP channel 2 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CH2STAT_SET,DCP channel 2 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CH2STAT_CLR,DCP channel 2 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CH2STAT_TOG,DCP channel 2 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CH2OPTS,DCP channel 2 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CH2OPTS_SET,DCP channel 2 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CH2OPTS_CLR,DCP channel 2 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CH2OPTS_TOG,DCP channel 2 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CH3CMDPTR,DCP channel 3 command pointer address register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Pointer to the descriptor structure to be processed for channel 3"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CH3SEMA,DCP channel 3 semaphore register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "VALUE,This read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT,The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CH3STAT,DCP channel 3 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CH3STAT_SET,DCP channel 3 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CH3STAT_CLR,DCP channel 3 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CH3STAT_TOG,DCP channel 3 status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TAG,Indicates the tag from the last completed packet in the command structure"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ERROR_CODE,Indicates additional error codes for some of the error conditions"
|
|
newline
|
|
bitfld.long 0x00 6. "ERROR_PAGEFAULT,This bit indicates that a page fault occurred while converting a virtual address to a physical address" "0,1"
|
|
bitfld.long 0x00 5. "ERROR_DST,This bit indicates that a bus error occurred when storing to the destination buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ERROR_SRC,This bit indicates that a bus error occurred when reading from the source buffer" "0,1"
|
|
bitfld.long 0x00 3. "ERROR_PACKET,This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERROR_SETUP,This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)" "0,1"
|
|
bitfld.long 0x00 1. "HASH_MISMATCH,This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "CH3OPTS,DCP channel 3 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "CH3OPTS_SET,DCP channel 3 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CH3OPTS_CLR,DCP channel 3 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CH3OPTS_TOG,DCP channel 3 options register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RECOVERY_TIMER,This field indicates the recovery time for the channel"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DBGSELECT,DCP debug select register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INDEX,Selects a value to read via the debug data register"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "DBGDATA,DCP debug data register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Debug data"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "PAGETABLE,DCP page table register"
|
|
hexmask.long 0x00 2.--31. 1. "BASE,Page table base address"
|
|
bitfld.long 0x00 1. "FLUSH,Page table flush control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Page table enable control" "0,1"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "VERSION,DCP version register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR version of the design implementation"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR version of the design implementation"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the version of the design implementation"
|
|
tree.end
|
|
tree "GPC"
|
|
base ad:0x400F4000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNTR,GPC Interface control register"
|
|
bitfld.long 0x00 22. "PDRAM0_PGE,FlexRAM PDRAM0 Power Gate Enable" "0: FlexRAM PDRAM0 domain will keep power even if..,1: FlexRAM PDRAM0 domain will be powered down.."
|
|
bitfld.long 0x00 3. "MEGA_PUP_REQ,MEGA domain power up request" "0: MEGA_PUP_REQ_0,1: Request power up sequence"
|
|
newline
|
|
bitfld.long 0x00 2. "MEGA_PDN_REQ,MEGA domain power down request" "0: MEGA_PDN_REQ_0,1: Request power down sequence"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IMR1,IRQ masking register 1"
|
|
hexmask.long 0x00 0.--31. 1. "IMR1,IRQ[31:0] masking bits: 1-irq masked 0-irq is not masked"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IMR2,IRQ masking register 2"
|
|
hexmask.long 0x00 0.--31. 1. "IMR2,IRQ[63:32] masking bits: 1-irq masked 0-irq is not masked"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR3,IRQ masking register 3"
|
|
hexmask.long 0x00 0.--31. 1. "IMR3,IRQ[95:64] masking bits: 1-irq masked 0-irq is not masked"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IMR4,IRQ masking register 4"
|
|
hexmask.long 0x00 0.--31. 1. "IMR4,IRQ[127:96] masking bits: 1-irq masked 0-irq is not masked"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ISR1,IRQ status resister 1"
|
|
hexmask.long 0x00 0.--31. 1. "ISR1,IRQ[31:0] status read only"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR2,IRQ status resister 2"
|
|
hexmask.long 0x00 0.--31. 1. "ISR2,IRQ[63:32] status read only"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ISR3,IRQ status resister 3"
|
|
hexmask.long 0x00 0.--31. 1. "ISR3,IRQ[95:64] status read only"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ISR4,IRQ status resister 4"
|
|
hexmask.long 0x00 0.--31. 1. "ISR4,IRQ[127:96] status read only"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IMR5,IRQ masking register 5"
|
|
hexmask.long 0x00 0.--31. 1. "IMR5,IRQ[159:128] masking bits: 1-irq masked 0-irq is not masked"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ISR5,IRQ status resister 5"
|
|
hexmask.long 0x00 0.--31. 1. "ISR4,IRQ[159:128] status read only"
|
|
tree.end
|
|
tree "PGC"
|
|
base ad:0x400F4000
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "MEGA_CTRL,PGC Mega Control Register"
|
|
bitfld.long 0x00 0. "PCR,Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "MEGA_PUPSCR,PGC Mega Power Up Sequence Control Register"
|
|
bitfld.long 0x00 8.--13. "SW2ISO,After asserting power toggle on/off signal (switch_b) the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "MEGA_PDNSCR,PGC Mega Pull Down Sequence Control Register"
|
|
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "MEGA_SR,PGC Mega Power Gating Controller Status Register"
|
|
bitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CPU_CTRL,PGC CPU Control Register"
|
|
bitfld.long 0x00 0. "PCR,Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "CPU_PUPSCR,PGC CPU Power Up Sequence Control Register"
|
|
bitfld.long 0x00 8.--13. "SW2ISO,There are two different silicon revisions: 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "SW,There are two different silicon revisions: 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "CPU_PDNSCR,PGC CPU Pull Down Sequence Control Register"
|
|
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "CPU_SR,PGC CPU Power Gating Controller Status Register"
|
|
bitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
|
|
tree.end
|
|
tree "SRC (System Reset Controller)"
|
|
base ad:0x400F8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCR,SRC Control Register"
|
|
bitfld.long 0x00 28.--31. "mask_wdog3_rst,Mask wdog3_rst_b source" "?,?,?,?,?,5: wdog3_rst_b is masked,?,?,?,?,10: wdog3_rst_b is not masked,?..."
|
|
bitfld.long 0x00 25. "dbg_rst_msk_pg,Do not assert debug resets after power gating event of core" "0: do not mask core debug resets (debug resets..,1: mask core debug resets (debug resets won't be.."
|
|
newline
|
|
bitfld.long 0x00 17. "core0_dbg_rst,Software reset for core0 debug only" "0: do not assert core0 debug reset,1: assert core0 debug reset"
|
|
bitfld.long 0x00 13. "core0_rst,Software reset for core0 only" "0: do not assert core0 reset,1: assert core0 reset"
|
|
newline
|
|
bitfld.long 0x00 7.--10. "mask_wdog_rst,Mask wdog_rst_b source" "?,?,?,?,?,5: wdog_rst_b is masked,?,?,?,?,10: wdog_rst_b is not masked (default),?..."
|
|
bitfld.long 0x00 4. "lockup_rst,lockup reset enable bit" "0: lockup_rst_0,1: lockup_rst_1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SBMR1,SRC Boot Mode Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BOOT_CFG4,Refer to fusemap"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BOOT_CFG3,Refer to fusemap"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BOOT_CFG2,Refer to fusemap"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BOOT_CFG1,Refer to fusemap"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRSR,SRC Reset Status Register"
|
|
bitfld.long 0x00 8. "tempsense_rst_b,Temper Sensor software reset" "0: Reset is not a result of software reset from..,1: Reset is a result of software reset from.."
|
|
eventfld.long 0x00 7. "wdog3_rst_b,IC Watchdog3 Time-out reset" "0: Reset is not a result of the watchdog3..,1: Reset is a result of the watchdog3 time-out.."
|
|
newline
|
|
eventfld.long 0x00 6. "jtag_sw_rst,JTAG software reset" "0: Reset is not a result of the mentioned case,1: Reset is not a result of the mentioned case"
|
|
eventfld.long 0x00 5. "jtag_rst_b,HIGH - Z JTAG reset" "0: Reset is not a result of HIGH-Z reset from JTAG,1: Reset is a result of HIGH-Z reset from JTAG"
|
|
newline
|
|
eventfld.long 0x00 4. "wdog_rst_b,IC Watchdog Time-out reset" "0: Reset is not a result of the watchdog..,1: Reset is a result of the watchdog time-out.."
|
|
eventfld.long 0x00 3. "ipp_user_reset_b,Indicates whether the reset was the result of the ipp_user_reset_b qualified reset" "0: Reset is not a result of the ipp_user_reset_b..,1: Reset is a result of the ipp_user_reset_b.."
|
|
newline
|
|
eventfld.long 0x00 2. "csu_reset_b,Indicates whether the reset was the result of the csu_reset_b input" "0: Reset is not a result of the csu_reset_b event,1: Reset is a result of the csu_reset_b event"
|
|
eventfld.long 0x00 1. "lockup,Indicates a reset has been caused by CPU lockup" "0: Reset is not a result of the mentioned case,1: Reset is a result of the mentioned case"
|
|
newline
|
|
eventfld.long 0x00 0. "ipp_reset_b,Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)" "0: Reset is not a result of ipp_reset_b pin,1: Reset is a result of ipp_reset_b pin"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SBMR2,SRC Boot Mode Register 2"
|
|
bitfld.long 0x00 24.--25. "BMOD,BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B" "0,1,2,3"
|
|
bitfld.long 0x00 4. "BT_FUSE_SEL,BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DIR_BT_DIS,DIR_BT_DIS shows the state of the DIR_BT_DIS fuse" "0,1"
|
|
bitfld.long 0x00 0.--1. "SEC_CONFIG,SECONFIG[1] shows the state of the SECONFIG[1] fuse" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPR1,SRC General Purpose Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "PERSISTENT_ENTRY0,Holds entry function for core0 for waking-up from low power mode"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPR2,SRC General Purpose Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "PERSISTENT_ARG0,Holds argument of entry function for core0 for waking-up from low power mode"
|
|
repeat 7. (strings "3" "4" "5" "6" "7" "8" "9" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "GPR$1,SRC General Purpose Register $1"
|
|
repeat.end
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPR10,SRC General Purpose Register 10"
|
|
bitfld.long 0x00 30. "PERSIST_SECONDARY_BOOT,This bit identifies which image must be used - primary and secondary" "0,1"
|
|
bitfld.long 0x00 26.--27. "PERSIST_REDUNDANT_BOOT,This field identifies which image must be used - 0/1/2/3" "0,1,2,3"
|
|
tree.end
|
|
tree "CCM (Clock Controller Module)"
|
|
base ad:0x400FC000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CCR,CCM Control Register"
|
|
bitfld.long 0x00 27. "RBC_EN,Enable for REG_BYPASS_COUNTER" "0: REG_BYPASS_COUNTER disabled,1: REG_BYPASS_COUNTER enabled"
|
|
bitfld.long 0x00 21.--26. "REG_BYPASS_COUNT,Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ" "0: REG_BYPASS_COUNT_0,1: 1 CKIL clock period delay,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: 63 CKIL clock periods delay"
|
|
newline
|
|
bitfld.long 0x00 12. "COSC_EN,On chip oscillator enable bit - this bit value is reflected on the output cosc_en" "0: disable on chip oscillator,1: enable on chip oscillator"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OSCNT,Oscillator ready counter value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CSR,CCM Status Register"
|
|
bitfld.long 0x00 5. "COSC_READY,Status indication of on board oscillator" "0: on board oscillator is not ready,1: on board oscillator is ready"
|
|
bitfld.long 0x00 3. "CAMP2_READY,Status indication of CAMP2" "0: CAMP2 is not ready,1: CAMP2 is ready"
|
|
newline
|
|
bitfld.long 0x00 0. "REF_EN_B,Status of the value of CCM_REF_EN_B output of ccm" "0: value of CCM_REF_EN_B is '0',1: value of CCM_REF_EN_B is '1'"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CCSR,CCM Clock Switcher Register"
|
|
bitfld.long 0x00 0. "PLL3_SW_CLK_SEL,Selects source to generate pll3_sw_clk" "0: PLL3_SW_CLK_SEL_0,1: PLL3_SW_CLK_SEL_1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CBCDR,CCM Bus Clock Divider Register"
|
|
bitfld.long 0x00 25. "PERIPH_CLK_SEL,Selector for peripheral main clock" "0: derive clock selected by..,1: derive clock selected by.."
|
|
bitfld.long 0x00 10.--12. "AHB_PODF,Divider for AHB PODF" "0: divide by 1,1: divide by 2,2: divide by 3,3: divide by 4,4: divide by 5,5: divide by 6,6: divide by 7,7: divide by 8"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IPG_PODF,Divider for ipg podf" "0: divide by 1,1: divide by 2,2: divide by 3,3: divide by 4"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CBCMR,CCM Bus Clock Multiplexer Register"
|
|
bitfld.long 0x00 26.--29. "LPSPI_PODF,Divider for LPSPI" "0: LPSPI_PODF_0,1: LPSPI_PODF_1,2: LPSPI_PODF_2,3: LPSPI_PODF_3,4: LPSPI_PODF_4,5: LPSPI_PODF_5,6: LPSPI_PODF_6,7: LPSPI_PODF_7,8: LPSPI_PODF_8,9: LPSPI_PODF_9,10: LPSPI_PODF_10,11: LPSPI_PODF_11,12: LPSPI_PODF_12,13: LPSPI_PODF_13,14: LPSPI_PODF_14,15: LPSPI_PODF_15"
|
|
bitfld.long 0x00 18.--19. "PRE_PERIPH_CLK_SEL,Selector for pre_periph clock multiplexer" "0: derive clock from PLL2,1: derive clock from PLL3 PFD3,2: derive clock from PLL2 PFD3,3: derive clock from PLL6"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "TRACE_CLK_SEL,Selector for Trace clock multiplexer" "0: derive clock from PLL2,1: derive clock from PLL2 PFD2,2: derive clock from PLL2 PFD0,3: derive clock from PLL2 PFD1"
|
|
bitfld.long 0x00 12.--13. "PERIPH_CLK2_SEL,Selector for peripheral clk2 clock multiplexer" "0: derive clock from pll3_sw_clk,1: derive clock from osc_clk,2: derive clock from pll2_bypass_clk,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "LPSPI_CLK_SEL,Selector for lpspi clock multiplexer" "0: derive clock from PLL3 PFD1 clk,1: derive clock from PLL3 PFD0,2: derive clock from PLL2,3: derive clock from PLL2 PFD2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CSCMR1,CCM Serial Clock Multiplexer Register 1"
|
|
bitfld.long 0x00 31. "FLEXSPI_CLK_SRC,Select for source of flexspi_clk_root" "0: derive clock selected by..,1: derive clock selected by.."
|
|
bitfld.long 0x00 29.--30. "FLEXSPI_CLK_SEL,Selector for flexspi clock multiplexer" "0: derive clock from PLL2,1: derive clock from pll3_sw_clk,2: derive clock from PLL2 PFD2,3: derive clock from PLL3 PFD0"
|
|
newline
|
|
bitfld.long 0x00 23.--25. "FLEXSPI_PODF,Divider for flexspi clock root" "0: FLEXSPI_PODF_0,1: FLEXSPI_PODF_1,2: FLEXSPI_PODF_2,3: FLEXSPI_PODF_3,4: FLEXSPI_PODF_4,5: FLEXSPI_PODF_5,6: FLEXSPI_PODF_6,7: FLEXSPI_PODF_7"
|
|
bitfld.long 0x00 14.--15. "SAI3_CLK_SEL,Selector for sai3 clock multiplexer" "0: derive clock from PLL3 PFD2,1: derive from pll3_sw_clk,2: derive clock from PLL4,?..."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "SAI1_CLK_SEL,Selector for sai1 clock multiplexer" "0: derive clock from PLL3 PFD2,1: derive from pll3_sw_clk,2: derive clock from PLL4,?..."
|
|
bitfld.long 0x00 6. "PERCLK_CLK_SEL,Selector for the perclk clock multiplexor" "0: derive clock from ipg clk root,1: derive clock from osc_clk"
|
|
newline
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bitfld.long 0x00 0.--5. "PERCLK_PODF,Divider for perclk podf" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16,16: Divide by 17,17: Divide by 18,18: Divide by 19,19: Divide by 20,20: Divide by 21,21: Divide by 22,22: Divide by 23,23: Divide by 24,24: Divide by 25,25: Divide by 26,26: Divide by 27,27: Divide by 28,28: Divide by 29,29: Divide by 30,30: Divide by 31,31: Divide by 32,32: Divide by 33,33: Divide by 34,34: Divide by 35,35: Divide by 36,36: Divide by 37,37: Divide by 38,38: Divide by 39,39: Divide by 40,40: Divide by 41,41: Divide by 42,42: Divide by 43,43: Divide by 44,44: Divide by 45,45: Divide by 46,46: Divide by 47,47: Divide by 48,48: Divide by 49,49: Divide by 50,50: Divide by 51,51: Divide by 52,52: Divide by 53,53: Divide by 54,54: Divide by 55,55: Divide by 56,56: Divide by 57,57: Divide by 58,58: Divide by 59,59: Divide by 60,60: Divide by 61,61: Divide by 62,62: Divide by 63,63: Divide by 64"
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group.long 0x20++0x03
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line.long 0x00 "CSCMR2,CCM Serial Clock Multiplexer Register 2"
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bitfld.long 0x00 31. "ADC_ACLK_EN,Enable ADC alt_clk so that ADC alt_clk can be driven be divided pll3_sw_clk" "0: ADC alt_clk source is disabled,1: ADC alt_clk source is enabled"
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bitfld.long 0x00 27.--30. "ADC_ACLK_PODF,Divider for ADC alt_clk as the list below (other values reserved)" "?,?,?,?,?,?,?,7: ADC_ACLK_PODF_7,?,?,?,11: ADC_ACLK_PODF_11,?,?,?,15: ADC_ACLK_PODF_15"
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bitfld.long 0x00 19.--20. "FLEXIO1_CLK_SEL,Selector for flexio1 clock multiplexer" "0: derive clock from PLL4 divided clock,1: derive clock from PLL3 PFD2 clock,2: FLEXIO1_CLK_SEL_2,3: derive clock from pll3_sw_clk"
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group.long 0x24++0x03
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line.long 0x00 "CSCDR1,CCM Serial Clock Divider Register 1"
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bitfld.long 0x00 25.--28. "TRACE_PODF,Divider for trace clock" "0: TRACE_PODF_0,1: TRACE_PODF_1,2: TRACE_PODF_2,3: TRACE_PODF_3,4: TRACE_PODF_4,5: TRACE_PODF_5,6: TRACE_PODF_6,7: TRACE_PODF_7,8: TRACE_PODF_8,9: TRACE_PODF_9,10: TRACE_PODF_10,11: TRACE_PODF_11,12: TRACE_PODF_12,13: TRACE_PODF_13,14: TRACE_PODF_14,15: TRACE_PODF_15"
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bitfld.long 0x00 6.--7. "UART_CLK_SEL,Selector for the UART clock multiplexor" "0: derive clock from pll3_80m,1: derive clock from osc_clk,2: derive clock from per_clk_root,?..."
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newline
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bitfld.long 0x00 0.--5. "UART_CLK_PODF,Divider for uart clock podf" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16,16: Divide by 17,17: Divide by 18,18: Divide by 19,19: Divide by 20,20: Divide by 21,21: Divide by 22,22: Divide by 23,23: Divide by 24,24: Divide by 25,25: Divide by 26,26: Divide by 27,27: Divide by 28,28: Divide by 29,29: Divide by 30,30: Divide by 31,31: Divide by 32,32: Divide by 33,33: Divide by 34,34: Divide by 35,35: Divide by 36,36: Divide by 37,37: Divide by 38,38: Divide by 39,39: Divide by 40,40: Divide by 41,41: Divide by 42,42: Divide by 43,43: Divide by 44,44: Divide by 45,45: Divide by 46,46: Divide by 47,47: Divide by 48,48: Divide by 49,49: Divide by 50,50: Divide by 51,51: Divide by 52,52: Divide by 53,53: Divide by 54,54: Divide by 55,55: Divide by 56,56: Divide by 57,57: Divide by 58,58: Divide by 59,59: Divide by 60,60: Divide by 61,61: Divide by 62,62: Divide by 63,63: Divide by 64"
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group.long 0x28++0x03
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line.long 0x00 "CS1CDR,CCM Clock Divider Register"
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bitfld.long 0x00 25.--28. "FLEXIO1_CLK_PODF,Divider for flexio1 clock" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
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bitfld.long 0x00 22.--24. "SAI3_CLK_PRED,Divider for sai3 clock pred" "0: SAI3_CLK_PRED_0,1: SAI3_CLK_PRED_1,2: SAI3_CLK_PRED_2,3: SAI3_CLK_PRED_3,4: SAI3_CLK_PRED_4,5: SAI3_CLK_PRED_5,6: SAI3_CLK_PRED_6,7: SAI3_CLK_PRED_7"
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bitfld.long 0x00 16.--21. "SAI3_CLK_PODF,Divider for sai3 clock podf" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16,16: Divide by 17,17: Divide by 18,18: Divide by 19,19: Divide by 20,20: Divide by 21,21: Divide by 22,22: Divide by 23,23: Divide by 24,24: Divide by 25,25: Divide by 26,26: Divide by 27,27: Divide by 28,28: Divide by 29,29: Divide by 30,30: Divide by 31,31: Divide by 32,32: Divide by 33,33: Divide by 34,34: Divide by 35,35: Divide by 36,36: Divide by 37,37: Divide by 38,38: Divide by 39,39: Divide by 40,40: Divide by 41,41: Divide by 42,42: Divide by 43,43: Divide by 44,44: Divide by 45,45: Divide by 46,46: Divide by 47,47: Divide by 48,48: Divide by 49,49: Divide by 50,50: Divide by 51,51: Divide by 52,52: Divide by 53,53: Divide by 54,54: Divide by 55,55: Divide by 56,56: Divide by 57,57: Divide by 58,58: Divide by 59,59: Divide by 60,60: Divide by 61,61: Divide by 62,62: Divide by 63,63: Divide by 64"
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bitfld.long 0x00 9.--11. "FLEXIO1_CLK_PRED,Divider for flexio1 clock" "0: FLEXIO1_CLK_PRED_0,1: FLEXIO1_CLK_PRED_1,2: FLEXIO1_CLK_PRED_2,3: FLEXIO1_CLK_PRED_3,4: FLEXIO1_CLK_PRED_4,5: FLEXIO1_CLK_PRED_5,6: FLEXIO1_CLK_PRED_6,7: FLEXIO1_CLK_PRED_7"
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bitfld.long 0x00 6.--8. "SAI1_CLK_PRED,Divider for sai1 clock pred" "0: SAI1_CLK_PRED_0,1: SAI1_CLK_PRED_1,2: SAI1_CLK_PRED_2,3: SAI1_CLK_PRED_3,4: SAI1_CLK_PRED_4,5: SAI1_CLK_PRED_5,6: SAI1_CLK_PRED_6,7: SAI1_CLK_PRED_7"
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bitfld.long 0x00 0.--5. "SAI1_CLK_PODF,Divider for sai1 clock podf" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16,16: Divide by 17,17: Divide by 18,18: Divide by 19,19: Divide by 20,20: Divide by 21,21: Divide by 22,22: Divide by 23,23: Divide by 24,24: Divide by 25,25: Divide by 26,26: Divide by 27,27: Divide by 28,28: Divide by 29,29: Divide by 30,30: Divide by 31,31: Divide by 32,32: Divide by 33,33: Divide by 34,34: Divide by 35,35: Divide by 36,36: Divide by 37,37: Divide by 38,38: Divide by 39,39: Divide by 40,40: Divide by 41,41: Divide by 42,42: Divide by 43,43: Divide by 44,44: Divide by 45,45: Divide by 46,46: Divide by 47,47: Divide by 48,48: Divide by 49,49: Divide by 50,50: Divide by 51,51: Divide by 52,52: Divide by 53,53: Divide by 54,54: Divide by 55,55: Divide by 56,56: Divide by 57,57: Divide by 58,58: Divide by 59,59: Divide by 60,60: Divide by 61,61: Divide by 62,62: Divide by 63,63: Divide by 64"
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group.long 0x30++0x03
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line.long 0x00 "CDCDR,CCM D1 Clock Divider Register"
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bitfld.long 0x00 25.--27. "SPDIF0_CLK_PRED,Divider for spdif0 clock pred" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
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bitfld.long 0x00 22.--24. "SPDIF0_CLK_PODF,Divider for spdif0 clock podf" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
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bitfld.long 0x00 20.--21. "SPDIF0_CLK_SEL,Selector for spdif0 clock multiplexer" "0: derive clock from PLL4,1: derive clock from PLL3 PFD2,?,3: derive clock from pll3_sw_clk"
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group.long 0x38++0x03
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line.long 0x00 "CSCDR2,CCM Serial Clock Divider Register 2"
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bitfld.long 0x00 19.--24. "LPI2C_CLK_PODF,Divider for lpi2c clock podf" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16,16: Divide by 17,17: Divide by 18,18: Divide by 19,19: Divide by 20,20: Divide by 21,21: Divide by 22,22: Divide by 23,23: Divide by 24,24: Divide by 25,25: Divide by 26,26: Divide by 27,27: Divide by 28,28: Divide by 29,29: Divide by 30,30: Divide by 31,31: Divide by 32,32: Divide by 33,33: Divide by 34,34: Divide by 35,35: Divide by 36,36: Divide by 37,37: Divide by 38,38: Divide by 39,39: Divide by 40,40: Divide by 41,41: Divide by 42,42: Divide by 43,43: Divide by 44,44: Divide by 45,45: Divide by 46,46: Divide by 47,47: Divide by 48,48: Divide by 49,49: Divide by 50,50: Divide by 51,51: Divide by 52,52: Divide by 53,53: Divide by 54,54: Divide by 55,55: Divide by 56,56: Divide by 57,57: Divide by 58,58: Divide by 59,59: Divide by 60,60: Divide by 61,61: Divide by 62,62: Divide by 63,63: Divide by 64"
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bitfld.long 0x00 18. "LPI2C_CLK_SEL,Selector for the LPI2C clock multiplexor" "0: derive clock from pll3_60m,1: derive clock from osc_clk"
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rgroup.long 0x48++0x03
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line.long 0x00 "CDHIPR,CCM Divider Handshake In-Process Register"
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bitfld.long 0x00 5. "PERIPH_CLK_SEL_BUSY,Busy indicator for periph_clk_sel mux control" "0: mux is not busy and its value represents the..,1: mux is busy with handshake process with module"
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bitfld.long 0x00 4. "PERCLK_PODF_BUSY,Busy indicator for perclk_podf" "0: divider is not busy and its value represents..,1: divider is busy with handshake process with.."
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bitfld.long 0x00 3. "FLEXSPI_PODF_BUSY,Busy indicator for flexspi_podf" "0: divider is not busy and its value represents..,1: divider is busy with handshake process with.."
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bitfld.long 0x00 1. "AHB_PODF_BUSY,Busy indicator for ahb_podf" "0: divider is not busy and its value represents..,1: divider is busy with handshake process with.."
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group.long 0x54++0x03
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line.long 0x00 "CLPCR,CCM Low Power Control Register"
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bitfld.long 0x00 27. "MASK_L2CC_IDLE,Mask L2CC IDLE for entering low power mode" "0: L2CC IDLE is not masked,1: L2CC IDLE is masked"
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bitfld.long 0x00 26. "MASK_SCU_IDLE,Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request" "0: SCU IDLE is not masked,1: SCU IDLE is masked"
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bitfld.long 0x00 22. "MASK_CORE0_WFI,Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request" "0: WFI of core0 is not masked,1: WFI of core0 is masked"
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bitfld.long 0x00 11. "COSC_PWRDOWN,In run mode software can manually control powering down of on chip oscillator i" "0: On chip oscillator will not be powered down i.e,1: On chip oscillator will be powered down i.e"
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bitfld.long 0x00 9.--10. "STBY_COUNT,Standby counter definition" "0: CCM will wait (1*pmic_delay_scaler)+1 ckil..,1: CCM will wait (3*pmic_delay_scaler)+1 ckil..,2: CCM will wait (7*pmic_delay_scaler)+1 ckil..,3: CCM will wait (15*pmic_delay_scaler)+1 ckil.."
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bitfld.long 0x00 8. "VSTBY,Voltage standby request bit" "0: Voltage will not be changed to standby..,1: Voltage will be requested to change to.."
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bitfld.long 0x00 7. "DIS_REF_OSC,dis_ref_osc - in run mode software can manually control closing of external reference oscillator clock i" "0: external high frequency oscillator will be..,1: external high frequency oscillator will be.."
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bitfld.long 0x00 6. "SBYOS,Standby clock oscillator bit" "0: On-chip oscillator will not be powered down..,1: On-chip oscillator will be powered down after.."
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bitfld.long 0x00 5. "ARM_CLK_DIS_ON_LPM,Define if ARM clocks (arm_clk soc_mxclk soc_pclk soc_dbg_pclk vl_wrck) will be disabled on wait mode" "0: ARM clock enabled on wait mode,1: ARM clock disabled on wait mode"
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bitfld.long 0x00 0.--1. "LPM,Setting the low power mode that system will enter on next assertion of dsm_request signal" "0: Remain in run mode,1: Transfer to wait mode,2: Transfer to stop mode,?..."
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group.long 0x58++0x03
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line.long 0x00 "CISR,CCM Interrupt Status Register"
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eventfld.long 0x00 22. "PERIPH_CLK_SEL_LOADED,CCM interrupt request 1 generated due to update of periph_clk_sel" "0: interrupt is not generated due to update of..,1: interrupt generated due to update of.."
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eventfld.long 0x00 20. "AHB_PODF_LOADED,CCM interrupt request 1 generated due to frequency change of ahb_podf" "0: interrupt is not generated due to frequency..,1: interrupt generated due to frequency change.."
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eventfld.long 0x00 18. "PERCLK_PODF_LOADED,CCM interrupt request 1 generated due to frequency change of perclk_podf" "0: interrupt is not generated due to frequency..,1: interrupt generated due to frequency change.."
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eventfld.long 0x00 16. "FLEXSPI_PODF_LOADED,CCM interrupt request 1 generated due to frequency change of flexspi_podf" "0: interrupt is not generated due to frequency..,1: interrupt generated due to frequency change.."
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eventfld.long 0x00 6. "COSC_READY,CCM interrupt request 2 generated due to on board oscillator ready i" "0: interrupt is not generated due to on board..,1: interrupt generated due to on board.."
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eventfld.long 0x00 0. "LRF_PLL,CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs" "0: interrupt is not generated due to lock ready..,1: interrupt generated due to lock ready of all.."
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group.long 0x5C++0x03
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line.long 0x00 "CIMR,CCM Interrupt Mask Register"
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bitfld.long 0x00 22. "MASK_PERIPH_CLK_SEL_LOADED,mask interrupt generation due to update of periph_clk_sel" "0: don't mask interrupt due to update of..,1: mask interrupt due to update of periph_clk_sel"
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bitfld.long 0x00 20. "MASK_AHB_PODF_LOADED,mask interrupt generation due to frequency change of ahb_podf" "0: don't mask interrupt due to frequency change..,1: mask interrupt due to frequency change of.."
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newline
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bitfld.long 0x00 18. "MASK_PERCLK_PODF_LOADED,mask interrupt generation due to update of perclk_podf" "0: don't mask interrupt due to update of..,1: mask interrupt due to update of perclk_podf"
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bitfld.long 0x00 16. "MASK_FLEXSPI_PODF_LOADED,mask interrupt generation due to update of flexspi_podf" "0: don't mask interrupt due to update of..,1: mask interrupt due to update of flexspi_podf"
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bitfld.long 0x00 6. "MASK_COSC_READY,mask interrupt generation due to on board oscillator ready" "0: don't mask interrupt due to on board..,1: mask interrupt due to on board oscillator ready"
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bitfld.long 0x00 0. "MASK_LRF_PLL,mask interrupt generation due to lrf of PLLs" "0: don't mask interrupt due to lrf of PLLs -..,1: mask interrupt due to lrf of PLLs"
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group.long 0x60++0x03
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line.long 0x00 "CCOSR,CCM Clock Output Source Register"
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bitfld.long 0x00 24. "CLKO2_EN,Enable of CCM_CLKO2 clock" "0: CCM_CLKO2 disabled,1: CCM_CLKO2 enabled"
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bitfld.long 0x00 21.--23. "CLKO2_DIV,Setting the divider of CCM_CLKO2" "0: CLKO2_DIV_0,1: CLKO2_DIV_1,2: CLKO2_DIV_2,3: CLKO2_DIV_3,4: CLKO2_DIV_4,5: CLKO2_DIV_5,6: CLKO2_DIV_6,7: CLKO2_DIV_7"
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bitfld.long 0x00 16.--20. "CLKO2_SEL,Selection of the clock to be generated on CCM_CLKO2" "?,?,?,?,?,?,6: lpi2c_clk_root,?,?,?,?,?,?,?,14: CLKO2_SEL_14,?,16: lpspi_clk_root,?,18: sai1_clk_root,?,20: sai3_clk_root,?,22: trace_clk_root,?,?,?,?,27: flexspi_clk_root,28: uart_clk_root,29: spdif0_clk_root,?..."
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bitfld.long 0x00 8. "CLK_OUT_SEL,CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks" "0: CCM_CLKO1 output drives CCM_CLKO1 clock,1: CCM_CLKO1 output drives CCM_CLKO2 clock"
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bitfld.long 0x00 7. "CLKO1_EN,Enable of CCM_CLKO1 clock" "0: CCM_CLKO1 disabled,1: CCM_CLKO1 enabled"
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bitfld.long 0x00 4.--6. "CLKO1_DIV,Setting the divider of CCM_CLKO1" "0: CLKO1_DIV_0,1: CLKO1_DIV_1,2: CLKO1_DIV_2,3: CLKO1_DIV_3,4: CLKO1_DIV_4,5: CLKO1_DIV_5,6: CLKO1_DIV_6,7: CLKO1_DIV_7"
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bitfld.long 0x00 0.--3. "CLKO1_SEL,Selection of the clock to be generated on CCM_CLKO1" "0: pll3_sw_clk (divided by 2),1: PLL2 (divided by 2),2: ENET PLL (divided by 2),?,?,?,?,?,?,?,?,11: core_clk_root,12: CLKO1_SEL_12,13: CLKO1_SEL_13,?,15: pll4_main_clk"
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group.long 0x64++0x03
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line.long 0x00 "CGPR,CCM General Purpose Register"
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bitfld.long 0x00 17. "INT_MEM_CLK_LPM,Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal" "0: Disable the clock to the ARM platform..,1: Keep the clocks to the ARM platform memories.."
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bitfld.long 0x00 16. "FPL,Fast PLL enable" "0: Engage PLL enable default way,1: Engage PLL enable 3 CKIL clocks earlier at.."
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bitfld.long 0x00 14.--15. "SYS_MEM_DS_CTRL,System memory DS control" "0: Disable memory DS mode always,1: Enable memory (outside ARM platform) DS mode..,2: enable memory (outside ARM platform) DS mode..,3: enable memory (outside ARM platform) DS mode.."
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bitfld.long 0x00 4. "EFUSE_PROG_SUPPLY_GATE,Defines the value of the output signal cgpr_dout[4]" "0: fuse programing supply voltage is gated off..,1: EFUSE_PROG_SUPPLY_GATE_1"
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bitfld.long 0x00 0. "PMIC_DELAY_SCALER,Defines clock dividion of clock for stby_count (pmic delay counter)" "0: clock is not divided,1: PMIC_DELAY_SCALER_1"
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group.long 0x68++0x03
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line.long 0x00 "CCGR0,CCM Clock Gating Register 0"
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bitfld.long 0x00 30.--31. "CG15,gpio2_clocks (gpio2_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 28.--29. "CG14,lpuart2 clock (lpuart2_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 26.--27. "CG13,gpt2 serial clocks (gpt2_serial_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 24.--25. "CG12,gpt2 bus clocks (gpt2_bus_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 22.--23. "CG11,trace clock (trace_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 20.--21. "CG10,Reserved" "0,1,2,3"
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bitfld.long 0x00 18.--19. "CG9,Reserved" "0,1,2,3"
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bitfld.long 0x00 16.--17. "CG8,Reserved" "0,1,2,3"
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bitfld.long 0x00 14.--15. "CG7,Reserved" "0,1,2,3"
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bitfld.long 0x00 12.--13. "CG6,lpuart3 clock (lpuart3_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 10.--11. "CG5,dcp clock (dcp_clk_enable)" "0,1,2,3"
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bitfld.long 0x00 8.--9. "CG4,sim_m_clk_r_clk_enable" "0,1,2,3"
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bitfld.long 0x00 6.--7. "CG3,flexspi_exsc clock (flexspi_exsc_clk_enable)" "0,1,2,3"
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|
bitfld.long 0x00 4.--5. "CG2,mqs clock ( mqs_hmclk_clock_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,aips_tz2 clocks (aips_tz2_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,aips_tz1 clocks (aips_tz1_clk_enable)" "0,1,2,3"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CCGR1,CCM Clock Gating Register 1"
|
|
bitfld.long 0x00 30.--31. "CG15,gpio5 clock (gpio5_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CG14,csu clock (csu_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CG13,gpio1 clock (gpio1_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CG12,lpuart4 clock (lpuart4_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CG11,gpt1 serial clock (gpt_serial_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CG10,gpt1 bus clock (gpt_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CG9,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CG8,adc1 clock (adc1_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CG7,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CG6,pit clocks (pit_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CG5,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CG4,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CG3,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CG2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,lpspi2 clocks (lpspi2_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,lpspi1 clocks (lpspi1_clk_enable)" "0,1,2,3"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CCGR2,CCM Clock Gating Register 2"
|
|
bitfld.long 0x00 30.--31. "CG15,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CG14,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CG13,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CG12,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CG11,xbar1 clock (xbar1_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CG10,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CG9,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CG8,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CG7,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CG6,OCOTP_CTRL clock (iim_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CG5,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CG4,lpi2c2 clock (lpi2c2_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CG3,lpi2c1 clock (lpi2c1_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CG2,iomuxc_snvs clock (iomuxc_snvs_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,ocram_exsc clock (ocram_exsc_clk_enable)" "0,1,2,3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CCGR3,CCM Clock Gating Register 3"
|
|
bitfld.long 0x00 30.--31. "CG15,iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CG14,The OCRAM clock cannot be turned off when the CM cache is running on this device" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CG13,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CG12,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CG11,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CG10,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CG9,flexram clock (flexram_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CG8,wdog1 clock (wdog1_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CG7,ewm clocks (ewm_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CG6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CG5,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CG4,aoi1 clock (aoi1_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CG3,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CG2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,Reserved" "0,1,2,3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CCGR4,CCM Clock Gating Register 4"
|
|
bitfld.long 0x00 30.--31. "CG15,dma_ps clocks (dma_ps_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CG14,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CG13,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CG12,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CG11,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CG10,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CG9,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CG8,pwm1 clocks (pwm1_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CG7,sim_ems clocks (sim_ems_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CG6,sim_m clocks (sim_m_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CG5,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CG4,sim_m7 clock (sim_m7_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CG3,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CG2,iomuxc gpr clock (iomuxc_gpr_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,iomuxc clock (iomuxc_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,sim_m7_clk_r_enable" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CCGR5,CCM Clock Gating Register 5"
|
|
bitfld.long 0x00 30.--31. "CG15,snvs_lp clock (snvs_lp_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CG14,snvs_hp clock (snvs_hp_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CG13,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CG12,lpuart1 clock (lpuart1_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CG11,sai3 clock (sai3_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CG10,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CG9,sai1 clock (sai1_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CG8,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CG7,spdif clock (spdif_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CG6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CG5,wdog2 clock (wdog2_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CG4,kpp clock (kpp_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CG3,dma clock (dma_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CG2,wdog3 clock (wdog3_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,flexio1 clock (flexio1_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,rom clock (rom_clk_enable)" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CCGR6,CCM Clock Gating Register 6"
|
|
bitfld.long 0x00 30.--31. "CG15,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "CG14,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CG13,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CG12,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CG11,anadig clocks (anadig_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "CG10,sim_per clock (sim_per_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CG9,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "CG8,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CG7,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "CG6,trng clock (trng_clk_enable)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CG5,flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared when flexspi_clk_enable is cleared" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CG4,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CG3,dcdc clocks (dcdc_clk_enable)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "CG2,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CG1,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CG0,usboh3 clock (usboh3_clk_enable)" "0,1,2,3"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CMEOR,CCM Module Enable Overide Register"
|
|
bitfld.long 0x00 9. "MOD_EN_OV_TRNG,Overide clock enable signal from TRNG" "0: don't override module enable signal,1: override module enable signal"
|
|
bitfld.long 0x00 6. "MOD_EN_OV_PIT,Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk'" "0: don't override module enable signal,1: override module enable signal"
|
|
newline
|
|
bitfld.long 0x00 5. "MOD_EN_OV_GPT,Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'" "0: don't override module enable signal,1: override module enable signal"
|
|
tree.end
|
|
tree "ROMC"
|
|
base ad:0x40180000
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "ROMPATCH7D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "ROMPATCH6D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "ROMPATCH5D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "ROMPATCH4D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "ROMPATCH3D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "ROMPATCH2D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "ROMPATCH1D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "ROMPATCH0D,ROMC Data Registers"
|
|
hexmask.long 0x00 0.--31. 1. "DATAX,Data Fix Registers - Stores the data used for 1-word data fix operations"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "ROMPATCHCNTL,ROMC Control Register"
|
|
bitfld.long 0x00 29. "DIS,ROMC Disable -- This bit when set disables all ROMC operations" "0: Does not affect any ROMC functions (default),1: Disable all ROMC functions"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATAFIX,Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "ROMPATCHENH,ROMC Enable Register High"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ROMPATCHENL,ROMC Enable Register Low"
|
|
hexmask.long.word 0x00 0.--15. 1. "ENABLE,Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ROMPATCH0A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ROMPATCH1A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ROMPATCH2A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ROMPATCH3A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ROMPATCH4A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ROMPATCH5A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ROMPATCH6A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "ROMPATCH7A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ROMPATCH8A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ROMPATCH9A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ROMPATCH10A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ROMPATCH11A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ROMPATCH12A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ROMPATCH13A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ROMPATCH14A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ROMPATCH15A,ROMC Address Registers"
|
|
hexmask.long.tbyte 0x00 1.--22. 1. "ADDRX,Address Comparator Registers - Indicates the memory address to be watched"
|
|
bitfld.long 0x00 0. "THUMBX,THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch" "0: Arm patch,1: THUMB patch (ignore if data fix)"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "ROMPATCHSR,ROMC Status Register"
|
|
eventfld.long 0x00 17. "SW,ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred" "0: no event or comparator collisions,1: a collision has occurred"
|
|
rbitfld.long 0x00 0.--5. "SOURCE,ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB" "0: Address Comparator 0 matched,1: Address Comparator 1 matched,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Address Comparator 15 matched,?..."
|
|
tree.end
|
|
tree "LPUART"
|
|
repeat 4. (list 1. 2. 3. 4.) (list ad:0x40184000 ad:0x40188000 ad:0x4018C000 ad:0x40190000)
|
|
tree "LPUART$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from STAT[LBKDIF] flag..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from STAT[RXEDGIF] are..,1: Hardware interrupt is requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive Watermark" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LPSPI"
|
|
repeat 2. (list 1. 2.) (list ad:0x40194000 ad:0x40198000)
|
|
tree "LPSPI$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSNUM,PCS Number"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: LPSPI module is disabled in debug mode,1: LPSPI module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze Mode Enable" "0: LPSPI module is enabled in Doze mode,1: LPSPI module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
eventfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
eventfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
eventfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
eventfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
eventfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
eventfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer of a received word has not yet..,1: Transfer of a received word has completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the Data.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is the LPSPI_HREQ pin,1: Host request input is the input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT is used..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN is used.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: 010b - Match is enabled if 1st data word..,3: 011b - Match is enabled if any data word..,4: 100b - Match is enabled if 1st data word..,5: 101b - Match is enabled if any data word..,6: 110b - Match is enabled if (1st data word AND..,7: 111b - Match is enabled if (any data word AND.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The Peripheral Chip Select pin PCSx is active..,1: The Peripheral Chip Select pin PCSx is active..,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when the transmit FIFO..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation is disabled,1: Automatic PCS generation is enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data is sampled on SCK edge,1: Input data is sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK-to-PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS-to-SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 16.--19. "RXWATER,Receive FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "TXWATER,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--20. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap is disabled,1: Byte swap is enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: 1 bit transfer,1: 2 bit transfer,2: 4 bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LPI2C"
|
|
repeat 2. (list 1. 2.) (list ad:0x401A4000 ad:0x401A8000)
|
|
tree "LPI2C$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
eventfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
eventfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
eventfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without a.."
|
|
eventfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
eventfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK was not detected,1: Unexpected NACK was detected"
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
eventfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data is not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Disabled,1: PLTIE_1"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO,1: Received data is discarded unless the the.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: 2-pin open drain mode,1: 2-pin output only mode (ultra-fast mode),2: 2-pin push-pull mode,3: 4-pin push-pull mode,4: 2-pin open drain mode with separate LPI2C slave,5: 2-pin output only mode (ultra-fast mode) with..,6: 2-pin push-pull mode with separate LPI2C slave,7: 4-pin push-pull mode (inverted outputs)"
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match is enabled (1st data word equals MATCH0..,3: Match is enabled (any data word equals MATCH0..,4: Match is enabled (1st data word equals MATCH0..,5: Match is enabled (any data word equals MATCH0..,6: Match is enabled (1st data word AND MATCH1..,7: Match is enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,IGNACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: AUTOSTOP_0,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave mode logic is not reset,1: Slave mode logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: I2C Slave mode is disabled,1: I2C Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response is disabled or not..,1: SMBus Alert Response is enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received an ADDR1 or ADDR0/ADDR1..,1: Have received an ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received an ADDR0 matching address,1: Have received an ADDR0 matching address"
|
|
newline
|
|
eventfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow was not detected,1: FIFO underflow or overflow was detected"
|
|
eventfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
eventfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Disabled,1: SARIE_1"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: AM0IE_0,1: Disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of HS-mode master code,1: Enables detection of HS-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK is detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the Receive Data register will return..,1: Reading the Receive Data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General Call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: Received Address (RADDR) is valid,1: Received Address (RADDR) is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Write a Transmit ACK for each received word,1: Write a Transmit NACK for each received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FLEXIO"
|
|
base ad:0x401AC000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRIGGER,Trigger Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIN,Pin Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TIMER,Timer Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SHIFTER,Shifter Number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,FlexIO Control Register"
|
|
bitfld.long 0x00 31. "DOZEN,Doze Enable" "0: FlexIO enabled in Doze modes,1: FlexIO disabled in Doze modes"
|
|
bitfld.long 0x00 30. "DBGE,Debug Enable" "0: FlexIO is disabled in debug modes,1: FlexIO is enabled in debug modes"
|
|
newline
|
|
bitfld.long 0x00 2. "FASTACC,Fast Access" "0: Configures for normal register accesses to..,1: Configures for fast register accesses to FlexIO"
|
|
bitfld.long 0x00 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled all FlexIO.."
|
|
newline
|
|
bitfld.long 0x00 0. "FLEXEN,FlexIO Enable" "0: FlexIO module is disabled,1: FlexIO module is enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PIN,Pin State Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Pin Data Input"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSF,Shifter Status Flag"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SHIFTERR,Shifter Error Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEF,Shifter Error Flags"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMSTAT,Timer Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TSF,Timer Status Flags"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSIE,Shifter Status Interrupt Enable"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SHIFTEIEN,Shifter Error Interrupt Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEIE,Shifter Error Interrupt Enable"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TIMIEN,Timer Interrupt Enable Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEIE,Timer Status Interrupt Enable"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSDE,Shifter Status DMA Enable"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHIFTSTATE,Shifter State Register"
|
|
bitfld.long 0x00 0.--2. "STATE,Current State Pointer" "0,1,2,3,4,5,6,7"
|
|
repeat 8. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL[$1],Shifter Control N Register $1"
|
|
bitfld.long 0x00 24.--26. "TIMSEL,Timer Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of Shift clock,1: Shift on negedge of Shift clock"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open drain or bidirectional..,2: Shifter pin bidirectional output data,3: Shifter pin output"
|
|
bitfld.long 0x00 8.--12. "PINSEL,Shifter Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
bitfld.long 0x00 0.--2. "SMOD,Shifter Mode" "0: Disabled,1: Receive mode,2: Transmit mode,?,4: Match Store mode,5: Match Continuous mode,6: State mode,7: Logic mode"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG[$1],Shifter Configuration N Register $1"
|
|
bitfld.long 0x00 16.--20. "PWIDTH,Parallel Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8. "INSRC,Input Source" "0: INSRC_0,1: Shifter N+1 Output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for..,?,2: Transmitter outputs stop bit value 0 on store..,3: Transmitter outputs stop bit value 1 on store.."
|
|
bitfld.long 0x00 0.--1. "SSTART,Shifter Start bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.."
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF[$1],Shifter Buffer N Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUF,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS[$1],Shifter Buffer N Bit Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBIS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS[$1],Shifter Buffer N Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBYS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS[$1],Shifter Buffer N Bit Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "TIMCTL[$1],Timer Control N Register $1"
|
|
bitfld.long 0x00 24.--29. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "TIMCFG[$1],Timer Configuration N Register $1"
|
|
bitfld.long 0x00 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and.."
|
|
bitfld.long 0x00 20.--21. "TIMDEC,Timer Decrement" "0: Decrement counter on FlexIO clock Shift clock..,1: Decrement counter on Trigger input (both..,2: Decrement counter on Pin input (both edges)..,3: Decrement counter on Trigger input (both.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,?,2: Timer reset on Timer Pin equal to Timer Output,3: Timer reset on Timer Trigger equal to Timer..,4: Timer reset on Timer Pin rising edge,?,6: Timer reset on Trigger rising edge,7: Timer reset on Trigger rising or falling edge"
|
|
bitfld.long 0x00 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on Timer compare (upper 8-bits..,3: Timer disabled on Timer compare (upper 8-bits..,4: Timer disabled on Pin rising or falling edge,5: Timer disabled on Pin rising or falling edge..,6: Timer disabled on Trigger falling edge,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger..,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge"
|
|
bitfld.long 0x00 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and.."
|
|
newline
|
|
bitfld.long 0x00 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x500)++0x03
|
|
line.long 0x00 "TIMCMP[$1],Timer Compare N Register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Timer Compare Value"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS[$1],Shifter Buffer N Nibble Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS[$1],Shifter Buffer N Half Word Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFHWS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS[$1],Shifter Buffer N Nibble Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNIS,Shift Buffer"
|
|
repeat.end
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
repeat 3. (list 1. 5. 2.) (list ad:0x401B8000 ad:0x400C0000 ad:0x42000000)
|
|
tree "GPIO$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "DR,GPIO data register"
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hexmask.long 0x00 0.--31. 1. "DR,DR"
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group.long 0x04++0x03
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line.long 0x00 "GDIR,GPIO direction register"
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hexmask.long 0x00 0.--31. 1. "GDIR,GDIR"
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rgroup.long 0x08++0x03
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line.long 0x00 "PSR,GPIO pad status register"
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hexmask.long 0x00 0.--31. 1. "PSR,PSR"
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group.long 0x0C++0x03
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line.long 0x00 "ICR1,GPIO interrupt configuration register1"
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bitfld.long 0x00 30.--31. "ICR15,ICR15" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 28.--29. "ICR14,ICR14" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 26.--27. "ICR13,ICR13" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 24.--25. "ICR12,ICR12" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 22.--23. "ICR11,ICR11" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 20.--21. "ICR10,ICR10" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 18.--19. "ICR9,ICR9" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 16.--17. "ICR8,ICR8" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 14.--15. "ICR7,ICR7" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 12.--13. "ICR6,ICR6" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 10.--11. "ICR5,ICR5" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 8.--9. "ICR4,ICR4" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 6.--7. "ICR3,ICR3" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 4.--5. "ICR2,ICR2" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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newline
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bitfld.long 0x00 2.--3. "ICR1,ICR1" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 0.--1. "ICR0,ICR0" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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group.long 0x10++0x03
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line.long 0x00 "ICR2,GPIO interrupt configuration register2"
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bitfld.long 0x00 30.--31. "ICR31,ICR31" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 28.--29. "ICR30,ICR30" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 26.--27. "ICR29,ICR29" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 24.--25. "ICR28,ICR28" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 22.--23. "ICR27,ICR27" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 20.--21. "ICR26,ICR26" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 18.--19. "ICR25,ICR25" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 16.--17. "ICR24,ICR24" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 14.--15. "ICR23,ICR23" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 12.--13. "ICR22,ICR22" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 10.--11. "ICR21,ICR21" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 8.--9. "ICR20,ICR20" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 6.--7. "ICR19,ICR19" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 4.--5. "ICR18,ICR18" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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newline
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bitfld.long 0x00 2.--3. "ICR17,ICR17" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 0.--1. "ICR16,ICR16" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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group.long 0x14++0x03
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line.long 0x00 "IMR,GPIO interrupt mask register"
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hexmask.long 0x00 0.--31. 1. "IMR,IMR"
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group.long 0x18++0x03
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line.long 0x00 "ISR,GPIO interrupt status register"
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hexmask.long 0x00 0.--31. 1. "ISR,ISR"
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group.long 0x1C++0x03
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line.long 0x00 "EDGE_SEL,GPIO edge select register"
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hexmask.long 0x00 0.--31. 1. "GPIO_EDGE_SEL,GPIO_EDGE_SEL"
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wgroup.long 0x84++0x03
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line.long 0x00 "DR_SET,GPIO data register SET"
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hexmask.long 0x00 0.--31. 1. "DR_SET,DR_SET"
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wgroup.long 0x88++0x03
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line.long 0x00 "DR_CLEAR,GPIO data register CLEAR"
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hexmask.long 0x00 0.--31. 1. "DR_CLEAR,DR_CLEAR"
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wgroup.long 0x8C++0x03
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line.long 0x00 "DR_TOGGLE,GPIO data register TOGGLE"
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hexmask.long 0x00 0.--31. 1. "DR_TOGGLE,DR_TOGGLE"
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tree.end
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repeat.end
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tree.end
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tree "PWM (Pulse-Width Modulator)"
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base ad:0x401CC000
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rgroup.word 0x00++0x01
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line.word 0x00 "SM0CNT,Counter Register"
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hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits"
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group.word 0x02++0x01
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line.word 0x00 "SM0INIT,Initial Count Register"
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hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits"
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group.word 0x04++0x01
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line.word 0x00 "SM0CTRL2,Control 2 Register"
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bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1"
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bitfld.word 0x00 14. "WAITEN,WAIT Enable" "0,1"
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newline
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bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs"
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bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1"
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newline
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bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1"
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bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1"
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newline
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bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization"
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bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled"
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newline
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bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1"
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bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.."
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newline
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bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).."
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bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..."
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group.word 0x06++0x01
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line.word 0x00 "SM0CTRL,Control Register"
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bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities"
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bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled"
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newline
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bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled"
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rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3"
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newline
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bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.."
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bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: PWM clock frequency = fclk,1: PWM clock frequency = fclk/2,2: PWM clock frequency = fclk/4,3: PWM clock frequency = fclk/8,4: PWM clock frequency = fclk/16,5: PWM clock frequency = fclk/32,6: PWM clock frequency = fclk/64,7: PWM clock frequency = fclk/128"
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newline
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bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB"
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bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.."
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newline
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bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled"
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bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled"
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group.word 0x0A++0x01
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line.word 0x00 "SM0VAL0,Value Register 0"
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hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0"
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group.word 0x0C++0x01
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line.word 0x00 "SM0FRACVAL1,Fractional Value Register 1"
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bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x0E++0x01
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line.word 0x00 "SM0VAL1,Value Register 1"
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hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1"
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group.word 0x10++0x01
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line.word 0x00 "SM0FRACVAL2,Fractional Value Register 2"
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bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x12++0x01
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line.word 0x00 "SM0VAL2,Value Register 2"
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hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2"
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group.word 0x14++0x01
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line.word 0x00 "SM0FRACVAL3,Fractional Value Register 3"
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bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x16++0x01
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line.word 0x00 "SM0VAL3,Value Register 3"
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hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3"
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group.word 0x18++0x01
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line.word 0x00 "SM0FRACVAL4,Fractional Value Register 4"
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bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x1A++0x01
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line.word 0x00 "SM0VAL4,Value Register 4"
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hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4"
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group.word 0x1C++0x01
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line.word 0x00 "SM0FRACVAL5,Fractional Value Register 5"
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bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x1E++0x01
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line.word 0x00 "SM0VAL5,Value Register 5"
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hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5"
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group.word 0x20++0x01
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line.word 0x00 "SM0FRCTRL,Fractional Control Register"
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rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1"
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bitfld.word 0x00 8. "FRAC_PU,Fractional Delay Circuit Power Up" "0: Turn off fractional delay logic,1: Power up fractional delay logic"
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newline
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bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B"
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bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A"
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newline
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bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.."
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group.word 0x22++0x01
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line.word 0x00 "SM0OCTRL,Output Control Register"
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rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1"
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rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1"
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newline
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rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1"
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bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted"
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newline
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bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted"
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bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted"
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newline
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bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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newline
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bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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group.word 0x24++0x01
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line.word 0x00 "SM0STS,Status Register"
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rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.."
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eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.."
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newline
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eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing"
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eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1"
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newline
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eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1"
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eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1"
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newline
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eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1"
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eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1"
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newline
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eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1"
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eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..."
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group.word 0x26++0x01
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line.word 0x00 "SM0INTEN,Interrupt Enable Register"
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bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled"
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bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled"
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newline
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bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]"
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bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]"
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newline
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bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]"
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bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]"
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newline
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bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]"
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bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]"
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newline
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bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..."
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group.word 0x28++0x01
|
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line.word 0x00 "SM0DMAEN,DMA Enable Register"
|
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bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: DMA write requests for the VALx and FRACVALx.."
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bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together"
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newline
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bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.."
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bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1"
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group.word 0x2A++0x01
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line.word 0x00 "SM0TCTRL,Output Trigger Control Register"
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bitfld.word 0x00 15. "PWAOT0,Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_OUT_TRIG0 port"
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bitfld.word 0x00 14. "PWBOT1,Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_OUT_TRIG1 port"
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bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.."
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bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "0: PWM_OUT_TRIGx will not set when the counter..,1: PWM_OUT_TRIGx will set when the counter value..,?..."
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group.word 0x2C++0x01
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line.word 0x00 "SM0DISMAP0,Fault Disable Mapping Register 0"
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bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x2E++0x01
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line.word 0x00 "SM0DISMAP1,Fault Disable Mapping Register 1"
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bitfld.word 0x00 8.--11. "DIS1X,PWM_X Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS1B,PWM_B Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DIS1A,PWM_A Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x30++0x01
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line.word 0x00 "SM0DTCNT0,Deadtime Count Register 0"
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hexmask.word 0x00 0.--15. 1. "DTCNT0,DTCNT0"
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group.word 0x32++0x01
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line.word 0x00 "SM0DTCNT1,Deadtime Count Register 1"
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hexmask.word 0x00 0.--15. 1. "DTCNT1,DTCNT1"
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group.word 0x34++0x01
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line.word 0x00 "SM0CAPTCTRLA,Capture Control A Register"
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rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x36++0x01
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line.word 0x00 "SM0CAPTCOMPA,Capture Compare A Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A"
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group.word 0x38++0x01
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line.word 0x00 "SM0CAPTCTRLB,Capture Control B Register"
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rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x3A++0x01
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line.word 0x00 "SM0CAPTCOMPB,Capture Compare B Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B"
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group.word 0x3C++0x01
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line.word 0x00 "SM0CAPTCTRLX,Capture Control X Register"
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rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x3E++0x01
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line.word 0x00 "SM0CAPTCOMPX,Capture Compare X Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X"
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rgroup.word 0x40++0x01
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line.word 0x00 "SM0CVAL0,Capture Value 0 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0"
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rgroup.word 0x42++0x01
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line.word 0x00 "SM0CVAL0CYC,Capture Value 0 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x44++0x01
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line.word 0x00 "SM0CVAL1,Capture Value 1 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1"
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rgroup.word 0x46++0x01
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line.word 0x00 "SM0CVAL1CYC,Capture Value 1 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x48++0x01
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line.word 0x00 "SM0CVAL2,Capture Value 2 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2"
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rgroup.word 0x4A++0x01
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line.word 0x00 "SM0CVAL2CYC,Capture Value 2 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x4C++0x01
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line.word 0x00 "SM0CVAL3,Capture Value 3 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3"
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rgroup.word 0x4E++0x01
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line.word 0x00 "SM0CVAL3CYC,Capture Value 3 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x50++0x01
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line.word 0x00 "SM0CVAL4,Capture Value 4 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4"
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rgroup.word 0x52++0x01
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line.word 0x00 "SM0CVAL4CYC,Capture Value 4 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x54++0x01
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line.word 0x00 "SM0CVAL5,Capture Value 5 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5"
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rgroup.word 0x56++0x01
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line.word 0x00 "SM0CVAL5CYC,Capture Value 5 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x58++0x01
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line.word 0x00 "SM0PHASEDLY,Phase Delay Register"
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hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits"
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rgroup.word 0x60++0x01
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line.word 0x00 "SM1CNT,Counter Register"
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hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits"
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group.word 0x62++0x01
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line.word 0x00 "SM1INIT,Initial Count Register"
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hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits"
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group.word 0x64++0x01
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line.word 0x00 "SM1CTRL2,Control 2 Register"
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bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1"
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bitfld.word 0x00 14. "WAITEN,WAIT Enable" "0,1"
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bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs"
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bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1"
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bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1"
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bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1"
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bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization"
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bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled"
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bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1"
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bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.."
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bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).."
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bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..."
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group.word 0x66++0x01
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line.word 0x00 "SM1CTRL,Control Register"
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bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities"
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bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled"
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bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled"
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|
rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3"
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bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.."
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bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: PWM clock frequency = fclk,1: PWM clock frequency = fclk/2,2: PWM clock frequency = fclk/4,3: PWM clock frequency = fclk/8,4: PWM clock frequency = fclk/16,5: PWM clock frequency = fclk/32,6: PWM clock frequency = fclk/64,7: PWM clock frequency = fclk/128"
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bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB"
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bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.."
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bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled"
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bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled"
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group.word 0x6A++0x01
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line.word 0x00 "SM1VAL0,Value Register 0"
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hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0"
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group.word 0x6C++0x01
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line.word 0x00 "SM1FRACVAL1,Fractional Value Register 1"
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bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.word 0x6E++0x01
|
|
line.word 0x00 "SM1VAL1,Value Register 1"
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|
hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1"
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group.word 0x70++0x01
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line.word 0x00 "SM1FRACVAL2,Fractional Value Register 2"
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bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x72++0x01
|
|
line.word 0x00 "SM1VAL2,Value Register 2"
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|
hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2"
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group.word 0x74++0x01
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line.word 0x00 "SM1FRACVAL3,Fractional Value Register 3"
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bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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group.word 0x76++0x01
|
|
line.word 0x00 "SM1VAL3,Value Register 3"
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|
hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3"
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group.word 0x78++0x01
|
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line.word 0x00 "SM1FRACVAL4,Fractional Value Register 4"
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bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x7A++0x01
|
|
line.word 0x00 "SM1VAL4,Value Register 4"
|
|
hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4"
|
|
group.word 0x7C++0x01
|
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line.word 0x00 "SM1FRACVAL5,Fractional Value Register 5"
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|
bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x7E++0x01
|
|
line.word 0x00 "SM1VAL5,Value Register 5"
|
|
hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5"
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "SM1FRCTRL,Fractional Control Register"
|
|
rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1"
|
|
bitfld.word 0x00 8. "FRAC_PU,Fractional Delay Circuit Power Up" "0: Turn off fractional delay logic,1: Power up fractional delay logic"
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|
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|
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bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B"
|
|
bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A"
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bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.."
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "SM1OCTRL,Output Control Register"
|
|
rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1"
|
|
rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1"
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rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1"
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|
bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted"
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bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted"
|
|
bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted"
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bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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|
bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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group.word 0x84++0x01
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line.word 0x00 "SM1STS,Status Register"
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rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.."
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eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.."
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eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing"
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eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1"
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eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1"
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eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1"
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eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1"
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eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1"
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eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1"
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eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..."
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group.word 0x86++0x01
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line.word 0x00 "SM1INTEN,Interrupt Enable Register"
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bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled"
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bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled"
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bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]"
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bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]"
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bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]"
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bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]"
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bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]"
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bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]"
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bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..."
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group.word 0x88++0x01
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line.word 0x00 "SM1DMAEN,DMA Enable Register"
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bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: DMA write requests for the VALx and FRACVALx.."
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bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together"
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bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.."
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bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1"
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group.word 0x8A++0x01
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line.word 0x00 "SM1TCTRL,Output Trigger Control Register"
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bitfld.word 0x00 15. "PWAOT0,Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_OUT_TRIG0 port"
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bitfld.word 0x00 14. "PWBOT1,Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_OUT_TRIG1 port"
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bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.."
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bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "0: PWM_OUT_TRIGx will not set when the counter..,1: PWM_OUT_TRIGx will set when the counter value..,?..."
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group.word 0x8C++0x01
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line.word 0x00 "SM1DISMAP0,Fault Disable Mapping Register 0"
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bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x8E++0x01
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line.word 0x00 "SM1DISMAP1,Fault Disable Mapping Register 1"
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bitfld.word 0x00 8.--11. "DIS1X,PWM_X Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS1B,PWM_B Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DIS1A,PWM_A Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x90++0x01
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line.word 0x00 "SM1DTCNT0,Deadtime Count Register 0"
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hexmask.word 0x00 0.--15. 1. "DTCNT0,DTCNT0"
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group.word 0x92++0x01
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line.word 0x00 "SM1DTCNT1,Deadtime Count Register 1"
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hexmask.word 0x00 0.--15. 1. "DTCNT1,DTCNT1"
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group.word 0x94++0x01
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line.word 0x00 "SM1CAPTCTRLA,Capture Control A Register"
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rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x96++0x01
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line.word 0x00 "SM1CAPTCOMPA,Capture Compare A Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A"
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group.word 0x98++0x01
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line.word 0x00 "SM1CAPTCTRLB,Capture Control B Register"
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rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x9A++0x01
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line.word 0x00 "SM1CAPTCOMPB,Capture Compare B Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B"
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group.word 0x9C++0x01
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line.word 0x00 "SM1CAPTCTRLX,Capture Control X Register"
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rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: Free running mode is selected,1: One shot mode is selected"
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newline
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bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x9E++0x01
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line.word 0x00 "SM1CAPTCOMPX,Capture Compare X Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X"
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rgroup.word 0xA0++0x01
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line.word 0x00 "SM1CVAL0,Capture Value 0 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0"
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rgroup.word 0xA2++0x01
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line.word 0x00 "SM1CVAL0CYC,Capture Value 0 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0xA4++0x01
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line.word 0x00 "SM1CVAL1,Capture Value 1 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1"
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rgroup.word 0xA6++0x01
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line.word 0x00 "SM1CVAL1CYC,Capture Value 1 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0xA8++0x01
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line.word 0x00 "SM1CVAL2,Capture Value 2 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2"
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rgroup.word 0xAA++0x01
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line.word 0x00 "SM1CVAL2CYC,Capture Value 2 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0xAC++0x01
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line.word 0x00 "SM1CVAL3,Capture Value 3 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3"
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rgroup.word 0xAE++0x01
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line.word 0x00 "SM1CVAL3CYC,Capture Value 3 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0xB0++0x01
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line.word 0x00 "SM1CVAL4,Capture Value 4 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4"
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rgroup.word 0xB2++0x01
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line.word 0x00 "SM1CVAL4CYC,Capture Value 4 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0xB4++0x01
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line.word 0x00 "SM1CVAL5,Capture Value 5 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5"
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rgroup.word 0xB6++0x01
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line.word 0x00 "SM1CVAL5CYC,Capture Value 5 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0xB8++0x01
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line.word 0x00 "SM1PHASEDLY,Phase Delay Register"
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hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits"
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rgroup.word 0xC0++0x01
|
|
line.word 0x00 "SM2CNT,Counter Register"
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|
hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits"
|
|
group.word 0xC2++0x01
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line.word 0x00 "SM2INIT,Initial Count Register"
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hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits"
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group.word 0xC4++0x01
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line.word 0x00 "SM2CTRL2,Control 2 Register"
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|
bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1"
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|
bitfld.word 0x00 14. "WAITEN,WAIT Enable" "0,1"
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bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs"
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bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1"
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bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1"
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bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1"
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bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization"
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bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled"
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|
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bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1"
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bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.."
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bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).."
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|
bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..."
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|
group.word 0xC6++0x01
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|
line.word 0x00 "SM2CTRL,Control Register"
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|
bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities"
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|
bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled"
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|
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|
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bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled"
|
|
rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3"
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bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.."
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|
bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: PWM clock frequency = fclk,1: PWM clock frequency = fclk/2,2: PWM clock frequency = fclk/4,3: PWM clock frequency = fclk/8,4: PWM clock frequency = fclk/16,5: PWM clock frequency = fclk/32,6: PWM clock frequency = fclk/64,7: PWM clock frequency = fclk/128"
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bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB"
|
|
bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.."
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bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled"
|
|
bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled"
|
|
group.word 0xCA++0x01
|
|
line.word 0x00 "SM2VAL0,Value Register 0"
|
|
hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0"
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "SM2FRACVAL1,Fractional Value Register 1"
|
|
bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xCE++0x01
|
|
line.word 0x00 "SM2VAL1,Value Register 1"
|
|
hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1"
|
|
group.word 0xD0++0x01
|
|
line.word 0x00 "SM2FRACVAL2,Fractional Value Register 2"
|
|
bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD2++0x01
|
|
line.word 0x00 "SM2VAL2,Value Register 2"
|
|
hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2"
|
|
group.word 0xD4++0x01
|
|
line.word 0x00 "SM2FRACVAL3,Fractional Value Register 3"
|
|
bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD6++0x01
|
|
line.word 0x00 "SM2VAL3,Value Register 3"
|
|
hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3"
|
|
group.word 0xD8++0x01
|
|
line.word 0x00 "SM2FRACVAL4,Fractional Value Register 4"
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bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDA++0x01
|
|
line.word 0x00 "SM2VAL4,Value Register 4"
|
|
hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4"
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "SM2FRACVAL5,Fractional Value Register 5"
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bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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group.word 0xDE++0x01
|
|
line.word 0x00 "SM2VAL5,Value Register 5"
|
|
hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5"
|
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group.word 0xE0++0x01
|
|
line.word 0x00 "SM2FRCTRL,Fractional Control Register"
|
|
rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1"
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|
bitfld.word 0x00 8. "FRAC_PU,Fractional Delay Circuit Power Up" "0: Turn off fractional delay logic,1: Power up fractional delay logic"
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|
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|
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bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B"
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bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A"
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|
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bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.."
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group.word 0xE2++0x01
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line.word 0x00 "SM2OCTRL,Output Control Register"
|
|
rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1"
|
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rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1"
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rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1"
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|
bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted"
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bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted"
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bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted"
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bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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group.word 0xE4++0x01
|
|
line.word 0x00 "SM2STS,Status Register"
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|
rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.."
|
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eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.."
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|
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|
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eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing"
|
|
eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1"
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|
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eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1"
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eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1"
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|
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|
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eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1"
|
|
eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1"
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|
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eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1"
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|
eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..."
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|
group.word 0xE6++0x01
|
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line.word 0x00 "SM2INTEN,Interrupt Enable Register"
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bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled"
|
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bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled"
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bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]"
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|
bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]"
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|
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bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]"
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|
bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]"
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newline
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bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]"
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bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]"
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bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..."
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|
group.word 0xE8++0x01
|
|
line.word 0x00 "SM2DMAEN,DMA Enable Register"
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|
bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: DMA write requests for the VALx and FRACVALx.."
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|
bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together"
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bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.."
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bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1"
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|
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bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1"
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|
bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1"
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|
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|
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bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1"
|
|
bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1"
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|
newline
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bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1"
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group.word 0xEA++0x01
|
|
line.word 0x00 "SM2TCTRL,Output Trigger Control Register"
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|
bitfld.word 0x00 15. "PWAOT0,Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_OUT_TRIG0 port"
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bitfld.word 0x00 14. "PWBOT1,Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_OUT_TRIG1 port"
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bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.."
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bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "0: PWM_OUT_TRIGx will not set when the counter..,1: PWM_OUT_TRIGx will set when the counter value..,?..."
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group.word 0xEC++0x01
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line.word 0x00 "SM2DISMAP0,Fault Disable Mapping Register 0"
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bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0xEE++0x01
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line.word 0x00 "SM2DISMAP1,Fault Disable Mapping Register 1"
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bitfld.word 0x00 8.--11. "DIS1X,PWM_X Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS1B,PWM_B Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.word 0x00 0.--3. "DIS1A,PWM_A Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0xF0++0x01
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line.word 0x00 "SM2DTCNT0,Deadtime Count Register 0"
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hexmask.word 0x00 0.--15. 1. "DTCNT0,DTCNT0"
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group.word 0xF2++0x01
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line.word 0x00 "SM2DTCNT1,Deadtime Count Register 1"
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hexmask.word 0x00 0.--15. 1. "DTCNT1,DTCNT1"
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group.word 0xF4++0x01
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line.word 0x00 "SM2CAPTCTRLA,Capture Control A Register"
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rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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newline
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bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: Free running mode is selected,1: One shot mode is selected"
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newline
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bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0xF6++0x01
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line.word 0x00 "SM2CAPTCOMPA,Capture Compare A Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A"
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group.word 0xF8++0x01
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line.word 0x00 "SM2CAPTCTRLB,Capture Control B Register"
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rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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newline
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bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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newline
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bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: Free running mode is selected,1: One shot mode is selected"
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newline
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bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0xFA++0x01
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line.word 0x00 "SM2CAPTCOMPB,Capture Compare B Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B"
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group.word 0xFC++0x01
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line.word 0x00 "SM2CAPTCTRLX,Capture Control X Register"
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rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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newline
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bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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newline
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bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: Free running mode is selected,1: One shot mode is selected"
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newline
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bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0xFE++0x01
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line.word 0x00 "SM2CAPTCOMPX,Capture Compare X Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X"
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rgroup.word 0x100++0x01
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line.word 0x00 "SM2CVAL0,Capture Value 0 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0"
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rgroup.word 0x102++0x01
|
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line.word 0x00 "SM2CVAL0CYC,Capture Value 0 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x104++0x01
|
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line.word 0x00 "SM2CVAL1,Capture Value 1 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1"
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rgroup.word 0x106++0x01
|
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line.word 0x00 "SM2CVAL1CYC,Capture Value 1 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x108++0x01
|
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line.word 0x00 "SM2CVAL2,Capture Value 2 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2"
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rgroup.word 0x10A++0x01
|
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line.word 0x00 "SM2CVAL2CYC,Capture Value 2 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x10C++0x01
|
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line.word 0x00 "SM2CVAL3,Capture Value 3 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3"
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rgroup.word 0x10E++0x01
|
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line.word 0x00 "SM2CVAL3CYC,Capture Value 3 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x110++0x01
|
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line.word 0x00 "SM2CVAL4,Capture Value 4 Register"
|
|
hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4"
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rgroup.word 0x112++0x01
|
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line.word 0x00 "SM2CVAL4CYC,Capture Value 4 Cycle Register"
|
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bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x114++0x01
|
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line.word 0x00 "SM2CVAL5,Capture Value 5 Register"
|
|
hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5"
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rgroup.word 0x116++0x01
|
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line.word 0x00 "SM2CVAL5CYC,Capture Value 5 Cycle Register"
|
|
bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word 0x118++0x01
|
|
line.word 0x00 "SM2PHASEDLY,Phase Delay Register"
|
|
hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits"
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "SM3CNT,Counter Register"
|
|
hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits"
|
|
group.word 0x122++0x01
|
|
line.word 0x00 "SM3INIT,Initial Count Register"
|
|
hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits"
|
|
group.word 0x124++0x01
|
|
line.word 0x00 "SM3CTRL2,Control 2 Register"
|
|
bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1"
|
|
bitfld.word 0x00 14. "WAITEN,WAIT Enable" "0,1"
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|
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bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs"
|
|
bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1"
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|
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bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1"
|
|
bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1"
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bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization"
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|
bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled"
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|
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|
|
bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1"
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|
bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.."
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newline
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bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).."
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|
bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..."
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|
group.word 0x126++0x01
|
|
line.word 0x00 "SM3CTRL,Control Register"
|
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bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities"
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bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled"
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bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled"
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rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3"
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|
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bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.."
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bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: PWM clock frequency = fclk,1: PWM clock frequency = fclk/2,2: PWM clock frequency = fclk/4,3: PWM clock frequency = fclk/8,4: PWM clock frequency = fclk/16,5: PWM clock frequency = fclk/32,6: PWM clock frequency = fclk/64,7: PWM clock frequency = fclk/128"
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bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB"
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bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.."
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bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled"
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bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled"
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group.word 0x12A++0x01
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line.word 0x00 "SM3VAL0,Value Register 0"
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hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0"
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group.word 0x12C++0x01
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line.word 0x00 "SM3FRACVAL1,Fractional Value Register 1"
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bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x12E++0x01
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line.word 0x00 "SM3VAL1,Value Register 1"
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hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1"
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group.word 0x130++0x01
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line.word 0x00 "SM3FRACVAL2,Fractional Value Register 2"
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bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x132++0x01
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line.word 0x00 "SM3VAL2,Value Register 2"
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hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2"
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group.word 0x134++0x01
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line.word 0x00 "SM3FRACVAL3,Fractional Value Register 3"
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bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x136++0x01
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line.word 0x00 "SM3VAL3,Value Register 3"
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hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3"
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group.word 0x138++0x01
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line.word 0x00 "SM3FRACVAL4,Fractional Value Register 4"
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bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x13A++0x01
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line.word 0x00 "SM3VAL4,Value Register 4"
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hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4"
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group.word 0x13C++0x01
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line.word 0x00 "SM3FRACVAL5,Fractional Value Register 5"
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bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.word 0x13E++0x01
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line.word 0x00 "SM3VAL5,Value Register 5"
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hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5"
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group.word 0x140++0x01
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line.word 0x00 "SM3FRCTRL,Fractional Control Register"
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rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1"
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bitfld.word 0x00 8. "FRAC_PU,Fractional Delay Circuit Power Up" "0: Turn off fractional delay logic,1: Power up fractional delay logic"
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bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B"
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bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A"
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bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.."
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group.word 0x142++0x01
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line.word 0x00 "SM3OCTRL,Output Control Register"
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rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1"
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rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1"
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rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1"
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bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted"
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bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted"
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bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted"
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bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated"
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group.word 0x144++0x01
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line.word 0x00 "SM3STS,Status Register"
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rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.."
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eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.."
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eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing"
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eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1"
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eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1"
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eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1"
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eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1"
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eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1"
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eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1"
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eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..."
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group.word 0x146++0x01
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line.word 0x00 "SM3INTEN,Interrupt Enable Register"
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bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled"
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bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled"
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bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]"
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bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]"
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bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]"
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bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]"
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bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]"
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bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]"
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bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..."
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group.word 0x148++0x01
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line.word 0x00 "SM3DMAEN,DMA Enable Register"
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bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: DMA write requests for the VALx and FRACVALx.."
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bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together"
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bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.."
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bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1"
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bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1"
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group.word 0x14A++0x01
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line.word 0x00 "SM3TCTRL,Output Trigger Control Register"
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bitfld.word 0x00 15. "PWAOT0,Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_OUT_TRIG0 port"
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bitfld.word 0x00 14. "PWBOT1,Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_OUT_TRIG1 port"
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bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.."
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bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "0: PWM_OUT_TRIGx will not set when the counter..,1: PWM_OUT_TRIGx will set when the counter value..,?..."
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group.word 0x14C++0x01
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line.word 0x00 "SM3DISMAP0,Fault Disable Mapping Register 0"
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bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x14E++0x01
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line.word 0x00 "SM3DISMAP1,Fault Disable Mapping Register 1"
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bitfld.word 0x00 8.--11. "DIS1X,PWM_X Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DIS1B,PWM_B Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DIS1A,PWM_A Fault Disable Mask 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word 0x150++0x01
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line.word 0x00 "SM3DTCNT0,Deadtime Count Register 0"
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hexmask.word 0x00 0.--15. 1. "DTCNT0,DTCNT0"
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group.word 0x152++0x01
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line.word 0x00 "SM3DTCNT1,Deadtime Count Register 1"
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hexmask.word 0x00 0.--15. 1. "DTCNT1,DTCNT1"
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group.word 0x154++0x01
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line.word 0x00 "SM3CAPTCTRLA,Capture Control A Register"
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rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x156++0x01
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line.word 0x00 "SM3CAPTCOMPA,Capture Compare A Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A"
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group.word 0x158++0x01
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line.word 0x00 "SM3CAPTCTRLB,Capture Control B Register"
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rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x15A++0x01
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line.word 0x00 "SM3CAPTCOMPB,Capture Compare B Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B"
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group.word 0x15C++0x01
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line.word 0x00 "SM3CAPTCTRLX,Capture Control X Register"
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rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3"
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bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled"
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bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: Output of edge counter/compare selected as.."
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bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: Disabled,1: Capture falling edges,2: Capture rising edges,3: Capture any edge"
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bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: Free running mode is selected,1: One shot mode is selected"
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bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.."
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group.word 0x15E++0x01
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line.word 0x00 "SM3CAPTCOMPX,Capture Compare X Register"
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hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X"
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hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X"
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rgroup.word 0x160++0x01
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line.word 0x00 "SM3CVAL0,Capture Value 0 Register"
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|
hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0"
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rgroup.word 0x162++0x01
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line.word 0x00 "SM3CVAL0CYC,Capture Value 0 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x164++0x01
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line.word 0x00 "SM3CVAL1,Capture Value 1 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1"
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rgroup.word 0x166++0x01
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line.word 0x00 "SM3CVAL1CYC,Capture Value 1 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x168++0x01
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line.word 0x00 "SM3CVAL2,Capture Value 2 Register"
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hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2"
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rgroup.word 0x16A++0x01
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line.word 0x00 "SM3CVAL2CYC,Capture Value 2 Cycle Register"
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bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x16C++0x01
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line.word 0x00 "SM3CVAL3,Capture Value 3 Register"
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|
hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3"
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rgroup.word 0x16E++0x01
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line.word 0x00 "SM3CVAL3CYC,Capture Value 3 Cycle Register"
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|
bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word 0x170++0x01
|
|
line.word 0x00 "SM3CVAL4,Capture Value 4 Register"
|
|
hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4"
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rgroup.word 0x172++0x01
|
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line.word 0x00 "SM3CVAL4CYC,Capture Value 4 Cycle Register"
|
|
bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x174++0x01
|
|
line.word 0x00 "SM3CVAL5,Capture Value 5 Register"
|
|
hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5"
|
|
rgroup.word 0x176++0x01
|
|
line.word 0x00 "SM3CVAL5CYC,Capture Value 5 Cycle Register"
|
|
bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x178++0x01
|
|
line.word 0x00 "SM3PHASEDLY,Phase Delay Register"
|
|
hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits"
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "OUTEN,Output Enable Register"
|
|
bitfld.word 0x00 8.--11. "PWMA_EN,PWM_A Output Enables" "0: PWM_A output disabled,1: PWM_A output enabled,?..."
|
|
bitfld.word 0x00 4.--7. "PWMB_EN,PWM_B Output Enables" "0: PWM_B output disabled,1: PWM_B output enabled,?..."
|
|
newline
|
|
bitfld.word 0x00 0.--3. "PWMX_EN,PWM_X Output Enables" "0: PWM_X output disabled,1: PWM_X output enabled,?..."
|
|
group.word 0x182++0x01
|
|
line.word 0x00 "MASK,Mask Register"
|
|
bitfld.word 0x00 12.--15. "UPDATE_MASK,Update Mask Bits Immediately" "0: Normal operation,1: Immediate operation,?..."
|
|
bitfld.word 0x00 8.--11. "MASKA,PWM_A Masks" "0: PWM_A output normal,1: PWM_A output masked,?..."
|
|
newline
|
|
bitfld.word 0x00 4.--7. "MASKB,PWM_B Masks" "0: PWM_B output normal,1: PWM_B output masked,?..."
|
|
bitfld.word 0x00 0.--3. "MASKX,PWM_X Masks" "0: PWM_X output normal,1: PWM_X output masked,?..."
|
|
group.word 0x184++0x01
|
|
line.word 0x00 "SWCOUT,Software Controlled Output Register"
|
|
bitfld.word 0x00 7. "SM3OUT23,Submodule 3 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
bitfld.word 0x00 6. "SM3OUT45,Submodule 3 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
newline
|
|
bitfld.word 0x00 5. "SM2OUT23,Submodule 2 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
bitfld.word 0x00 4. "SM2OUT45,Submodule 2 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
newline
|
|
bitfld.word 0x00 3. "SM1OUT23,Submodule 1 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
bitfld.word 0x00 2. "SM1OUT45,Submodule 1 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
newline
|
|
bitfld.word 0x00 1. "SM0OUT23,Submodule 0 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
bitfld.word 0x00 0. "SM0OUT45,Submodule 0 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.."
|
|
group.word 0x186++0x01
|
|
line.word 0x00 "DTSRCSEL,PWM Source Select Register"
|
|
bitfld.word 0x00 14.--15. "SM3SEL23,Submodule 3 PWM23 Control Select" "0: Generated SM3PWM23 signal is used by the..,1: Inverted generated SM3PWM23 signal is used by..,2: SWCOUT[SM3OUT23] is used by the deadtime logic,3: PWM3_EXTA signal is used by the deadtime logic"
|
|
bitfld.word 0x00 12.--13. "SM3SEL45,Submodule 3 PWM45 Control Select" "0: Generated SM3PWM45 signal is used by the..,1: Inverted generated SM3PWM45 signal is used by..,2: SWCOUT[SM3OUT45] is used by the deadtime logic,3: PWM3_EXTB signal is used by the deadtime logic"
|
|
newline
|
|
bitfld.word 0x00 10.--11. "SM2SEL23,Submodule 2 PWM23 Control Select" "0: Generated SM2PWM23 signal is used by the..,1: Inverted generated SM2PWM23 signal is used by..,2: SWCOUT[SM2OUT23] is used by the deadtime logic,3: PWM2_EXTA signal is used by the deadtime logic"
|
|
bitfld.word 0x00 8.--9. "SM2SEL45,Submodule 2 PWM45 Control Select" "0: Generated SM2PWM45 signal is used by the..,1: Inverted generated SM2PWM45 signal is used by..,2: SWCOUT[SM2OUT45] is used by the deadtime logic,3: PWM2_EXTB signal is used by the deadtime logic"
|
|
newline
|
|
bitfld.word 0x00 6.--7. "SM1SEL23,Submodule 1 PWM23 Control Select" "0: Generated SM1PWM23 signal is used by the..,1: Inverted generated SM1PWM23 signal is used by..,2: SWCOUT[SM1OUT23] is used by the deadtime logic,3: PWM1_EXTA signal is used by the deadtime logic"
|
|
bitfld.word 0x00 4.--5. "SM1SEL45,Submodule 1 PWM45 Control Select" "0: Generated SM1PWM45 signal is used by the..,1: Inverted generated SM1PWM45 signal is used by..,2: SWCOUT[SM1OUT45] is used by the deadtime logic,3: PWM1_EXTB signal is used by the deadtime logic"
|
|
newline
|
|
bitfld.word 0x00 2.--3. "SM0SEL23,Submodule 0 PWM23 Control Select" "0: Generated SM0PWM23 signal is used by the..,1: Inverted generated SM0PWM23 signal is used by..,2: SWCOUT[SM0OUT23] is used by the deadtime logic,3: PWM0_EXTA signal is used by the deadtime logic"
|
|
bitfld.word 0x00 0.--1. "SM0SEL45,Submodule 0 PWM45 Control Select" "0: Generated SM0PWM45 signal is used by the..,1: Inverted generated SM0PWM45 signal is used by..,2: SWCOUT[SM0OUT45] is used by the deadtime logic,3: PWM0_EXTB signal is used by the deadtime logic"
|
|
group.word 0x188++0x01
|
|
line.word 0x00 "MCTRL,Master Control Register"
|
|
bitfld.word 0x00 12.--15. "IPOL,Current Polarity" "0: PWM23 is used to generate complementary PWM..,1: PWM45 is used to generate complementary PWM..,?..."
|
|
bitfld.word 0x00 8.--11. "RUN,Run" "0: PWM generator is disabled in the..,1: PWM generator is enabled in the corresponding..,?..."
|
|
newline
|
|
bitfld.word 0x00 4.--7. "CLDOK,Clear Load Okay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. "LDOK,Load Okay" "0: Do not load new values,1: Load prescaler modulus and PWM values of the..,?..."
|
|
group.word 0x18A++0x01
|
|
line.word 0x00 "MCTRL2,Master Control 2 Register"
|
|
bitfld.word 0x00 0.--1. "MONPLL,Monitor PLL State" "0: Not locked,1: Not locked,2: Locked,3: Locked"
|
|
group.word 0x18C++0x01
|
|
line.word 0x00 "FCTRL0,Fault Control Register"
|
|
bitfld.word 0x00 12.--15. "FLVL,Fault Level" "0: A logic 0 on the fault input indicates a..,1: A logic 1 on the fault input indicates a..,?..."
|
|
bitfld.word 0x00 8.--11. "FAUTO,Automatic Fault Clearing" "0: Manual fault clearing,1: Automatic fault clearing,?..."
|
|
newline
|
|
bitfld.word 0x00 4.--7. "FSAFE,Fault Safety Mode" "0: Normal mode,1: Safe mode,?..."
|
|
bitfld.word 0x00 0.--3. "FIE,Fault Interrupt Enables" "0: FAULTx CPU interrupt requests disabled,1: FAULTx CPU interrupt requests enabled,?..."
|
|
group.word 0x18E++0x01
|
|
line.word 0x00 "FSTS0,Fault Status Register"
|
|
bitfld.word 0x00 12.--15. "FHALF,Half Cycle Fault Recovery" "0: PWM outputs are not re-enabled at the start..,1: PWM outputs are re-enabled at the start of a..,?..."
|
|
rbitfld.word 0x00 8.--11. "FFPIN,Filtered Fault Pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 4.--7. "FFULL,Full Cycle" "0: PWM outputs are not re-enabled at the start..,1: PWM outputs are re-enabled at the start of a..,?..."
|
|
bitfld.word 0x00 0.--3. "FFLAG,Fault Flags" "0: No fault on the FAULTx pin,1: Fault on the FAULTx pin,?..."
|
|
group.word 0x190++0x01
|
|
line.word 0x00 "FFILT0,Fault Filter Register"
|
|
bitfld.word 0x00 15. "GSTR,Fault Glitch Stretch Enable" "0: Fault input glitch stretching is disabled,1: Input fault signals will be stretched to at.."
|
|
bitfld.word 0x00 8.--10. "FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "FILT_PER,Fault Filter Period"
|
|
group.word 0x192++0x01
|
|
line.word 0x00 "FTST0,Fault Test Register"
|
|
bitfld.word 0x00 0. "FTEST,Fault Test" "0: No fault,1: Cause a simulated fault"
|
|
group.word 0x194++0x01
|
|
line.word 0x00 "FCTRL20,Fault Control 2 Register"
|
|
bitfld.word 0x00 0.--3. "NOCOMB,No Combinational Path From Fault Input To PWM Output" "0: There is a combinational link from the fault..,1: The direct combinational path from the fault..,?..."
|
|
tree.end
|
|
tree "SPDIF (Sony/Philips Digital Interface)"
|
|
base ad:0x401DC000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCR,SPDIF Configuration Register"
|
|
bitfld.long 0x00 23. "RxFIFO_Ctrl,no description available" "0: Normal operation,1: Always read zero from Rx data register"
|
|
bitfld.long 0x00 22. "RxFIFO_Off_On,no description available" "0: SPDIF Rx FIFO is on,1: SPDIF Rx FIFO is off"
|
|
newline
|
|
bitfld.long 0x00 21. "RxFIFO_Rst,no description available" "0: Normal operation,1: Reset register to 1 sample remaining"
|
|
bitfld.long 0x00 19.--20. "RxFIFOFull_Sel,no description available" "0: Full interrupt if at least 1 sample in Rx..,1: Full interrupt if at least 4 sample in Rx..,2: Full interrupt if at least 8 sample in Rx..,3: Full interrupt if at least 16 sample in Rx.."
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|
newline
|
|
bitfld.long 0x00 18. "RxAutoSync,no description available" "0: Rx FIFO auto sync off,1: RxFIFO auto sync on"
|
|
bitfld.long 0x00 17. "TxAutoSync,no description available" "0: Tx FIFO auto sync off,1: Tx FIFO auto sync on"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TxFIFOEmpty_Sel,no description available" "0: Empty interrupt if 0 sample in Tx left and..,1: Empty interrupt if at most 4 sample in Tx..,2: Empty interrupt if at most 8 sample in Tx..,3: Empty interrupt if at most 12 sample in Tx.."
|
|
bitfld.long 0x00 13. "LOW_POWER,When write 1 to this bit it will cause SPDIF enter low-power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "soft_reset,When write 1 to this bit it will cause SPDIF software reset" "0,1"
|
|
bitfld.long 0x00 10.--11. "TxFIFO_Ctrl,no description available" "0: Send out digital zero on SPDIF Tx,1: Tx Normal operation,2: Reset to 1 sample remaining,?..."
|
|
newline
|
|
bitfld.long 0x00 9. "DMA_Rx_En,DMA Receive Request Enable (RX FIFO full)" "0,1"
|
|
bitfld.long 0x00 8. "DMA_TX_En,DMA Transmit Request Enable (Tx FIFO empty)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ValCtrl,no description available" "0: Outgoing Validity always set,1: Outgoing Validity always clear"
|
|
bitfld.long 0x00 2.--4. "TxSel,no description available" "0: Off and output 0,1: Feed-through SPDIFIN,?,?,?,5: Tx Normal operation,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "USrc_Sel,no description available" "0: No embedded U channel,1: U channel from SPDIF receive block (CD mode),?,3: U channel from on chip transmitter"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SRCD,CDText Control Register"
|
|
bitfld.long 0x00 1. "USyncMode,no description available" "0: USyncMode_0,1: CD user channel subcode"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRPC,PhaseConfig Register"
|
|
bitfld.long 0x00 7.--10. "ClkSrc_Sel,Clock source selection all other settings not shown are reserved" "0: if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K..,1: if (DPLL Locked) SPDIF_RxClk else tx_clk..,?,3: if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK,?,5: REF_CLK_32K (XTALOSC),6: tx_clk (SPDIF0_CLK_ROOT),?,8: SPDIF_EXT_CLK,?..."
|
|
rbitfld.long 0x00 6. "LOCK,LOCK bit to show that the internal DPLL is locked read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "GainSel,Gain selection" "0: 24*(2**10),1: 16*(2**10),2: 12*(2**10),3: GainSel_3,4: GainSel_4,5: GainSel_5,6: GainSel_6,?..."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIE,InterruptEn Register"
|
|
bitfld.long 0x00 20. "Lock,SPDIF receiver's DPLL is locked" "0,1"
|
|
bitfld.long 0x00 19. "TxUnOv,SPDIF Tx FIFO under/overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TxResyn,SPDIF Tx FIFO resync" "0,1"
|
|
bitfld.long 0x00 17. "CNew,SPDIF receive change in value of control channel" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ValNoGood,SPDIF validity flag no good" "0,1"
|
|
bitfld.long 0x00 15. "SymErr,SPDIF receiver found illegal symbol" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BitErr,SPDIF receiver found parity bit error" "0,1"
|
|
bitfld.long 0x00 10. "URxFul,U Channel receive register full can't be cleared with reg" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "URxOv,U Channel receive register overrun" "0,1"
|
|
bitfld.long 0x00 8. "QRxFul,Q Channel receive register full can't be cleared with reg" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "QRxOv,Q Channel receive register overrun" "0,1"
|
|
bitfld.long 0x00 6. "UQSync,U/Q Channel sync found" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "UQErr,U/Q Channel framing error" "0,1"
|
|
bitfld.long 0x00 4. "RxFIFOUnOv,Rx FIFO underrun/overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RxFIFOResyn,Rx FIFO resync" "0,1"
|
|
bitfld.long 0x00 2. "LockLoss,SPDIF receiver loss of lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TxEm,SPDIF Tx FIFO empty can't be cleared with reg" "0,1"
|
|
bitfld.long 0x00 0. "RxFIFOFul,SPDIF Rx FIFO full can't be cleared with reg" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SIC,InterruptClear Register"
|
|
bitfld.long 0x00 20. "Lock,SPDIF receiver's DPLL is locked" "0,1"
|
|
bitfld.long 0x00 19. "TxUnOv,SPDIF Tx FIFO under/overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TxResyn,SPDIF Tx FIFO resync" "0,1"
|
|
bitfld.long 0x00 17. "CNew,SPDIF receive change in value of control channel" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ValNoGood,SPDIF validity flag no good" "0,1"
|
|
bitfld.long 0x00 15. "SymErr,SPDIF receiver found illegal symbol" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BitErr,SPDIF receiver found parity bit error" "0,1"
|
|
bitfld.long 0x00 9. "URxOv,U Channel receive register overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "QRxOv,Q Channel receive register overrun" "0,1"
|
|
bitfld.long 0x00 6. "UQSync,U/Q Channel sync found" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "UQErr,U/Q Channel framing error" "0,1"
|
|
bitfld.long 0x00 4. "RxFIFOUnOv,Rx FIFO underrun/overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RxFIFOResyn,Rx FIFO resync" "0,1"
|
|
bitfld.long 0x00 2. "LockLoss,SPDIF receiver loss of lock" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SIS,InterruptStat Register"
|
|
bitfld.long 0x00 20. "Lock,SPDIF receiver's DPLL is locked" "0,1"
|
|
bitfld.long 0x00 19. "TxUnOv,SPDIF Tx FIFO under/overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TxResyn,SPDIF Tx FIFO resync" "0,1"
|
|
bitfld.long 0x00 17. "CNew,SPDIF receive change in value of control channel" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ValNoGood,SPDIF validity flag no good" "0,1"
|
|
bitfld.long 0x00 15. "SymErr,SPDIF receiver found illegal symbol" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BitErr,SPDIF receiver found parity bit error" "0,1"
|
|
bitfld.long 0x00 10. "URxFul,U Channel receive register full can't be cleared with reg" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "URxOv,U Channel receive register overrun" "0,1"
|
|
bitfld.long 0x00 8. "QRxFul,Q Channel receive register full can't be cleared with reg" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "QRxOv,Q Channel receive register overrun" "0,1"
|
|
bitfld.long 0x00 6. "UQSync,U/Q Channel sync found" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "UQErr,U/Q Channel framing error" "0,1"
|
|
bitfld.long 0x00 4. "RxFIFOUnOv,Rx FIFO underrun/overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RxFIFOResyn,Rx FIFO resync" "0,1"
|
|
bitfld.long 0x00 2. "LockLoss,SPDIF receiver loss of lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TxEm,SPDIF Tx FIFO empty can't be cleared with reg" "0,1"
|
|
bitfld.long 0x00 0. "RxFIFOFul,SPDIF Rx FIFO full can't be cleared with reg" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SRL,SPDIFRxLeft Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxDataLeft,Processor receive SPDIF data left"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SRR,SPDIFRxRight Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxDataRight,Processor receive SPDIF data right"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SRCSH,SPDIFRxCChannel_h Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxCChannel_h,SPDIF receive C channel register contains first 24 bits of C channel without interpretation"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SRCSL,SPDIFRxCChannel_l Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxCChannel_l,SPDIF receive C channel register contains next 24 bits of C channel without interpretation"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SRU,UchannelRx Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxUChannel,SPDIF receive U channel register contains next 3 U channel bytes"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SRQ,QchannelRx Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxQChannel,SPDIF receive Q channel register contains next 3 Q channel bytes"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "STL,SPDIFTxLeft Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxDataLeft,SPDIF transmit left channel data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "STR,SPDIFTxRight Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxDataRight,SPDIF transmit right channel data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "STCSCH,SPDIFTxCChannelCons_h Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxCChannelCons_h,SPDIF transmit Cons"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "STCSCL,SPDIFTxCChannelCons_l Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxCChannelCons_l,SPDIF transmit Cons"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SRFM,FreqMeas Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "FreqMeas,Frequency measurement data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "STC,SPDIFTxClk Register"
|
|
hexmask.long.word 0x00 11.--19. 1. "SYSCLK_DF,system clock divider factor 2~512"
|
|
bitfld.long 0x00 8.--10. "TxClk_Source,no description available" "0: XTALOSC input (XTALOSC clock),1: tx_clk input (from SPDIF0_CLK_ROOT. See CCM.),2: tx_clk1 (from SAI1),3: tx_clk2 SPDIF_EXT_CLK from pads,4: tx_clk3 (from SAI2),5: ipg_clk input (frequency divided),6: tx_clk4 (from SAI3),?..."
|
|
newline
|
|
bitfld.long 0x00 7. "tx_all_clk_en,Spdif transfer clock enable" "0: disable transfer clock,1: enable transfer clock"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TxClk_DF,Divider factor (1-128)"
|
|
tree.end
|
|
tree "I2S (Inter-Integrated Sound Bus Controller)"
|
|
repeat 2. (list 1. 3.) (list ad:0x401E0000 ad:0x401E8000)
|
|
tree "SAI$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 16.--19. "FRAME,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "FIFO,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DATALINE,Number of Datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. "TE,Transmitter Enable" "0: Transmitter is disabled,1: Transmitter is enabled or transmitter has.."
|
|
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Transmitter disabled in Stop mode,1: Transmitter enabled in Stop mode"
|
|
newline
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode"
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled,1: Transmit bit clock is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
newline
|
|
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
newline
|
|
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected,1: Transmit underrun detected"
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty,1: Enabled transmit FIFO is empty"
|
|
newline
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached,1: Transmit FIFO watermark has been reached"
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x00 0.--4. "TFW,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver,?..."
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs..,1: Bit clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. "CFR,Channel FIFO Reset" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "TCE,Transmit Channel Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO reads (from..,2: FIFO combine mode enabled on FIFO writes (by..,3: FIFO combine mode enabled on FIFO reads (from.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
bitfld.long 0x00 16.--20. "FRSZ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. "CHMOD,Channel Mode" "0: TDM mode transmit data pins are tri-stated..,1: Output mode transmit data pins are never.."
|
|
newline
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is transmitted first,1: MSB is transmitted first"
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
newline
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
newline
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave..,1: Frame sync is generated internally in Master.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TDR[$1],SAI Transmit Data Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "TDR,Transmit Data Register"
|
|
repeat.end
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "TFR[$1],SAI Transmit FIFO Register $1"
|
|
bitfld.long 0x00 31. "WCP,Write Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO writes and.."
|
|
bitfld.long 0x00 16.--21. "WFP,Write FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "RFP,Read FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TMR,SAI Transmit Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "TWM,Transmit Word Mask"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled or receiver has been.."
|
|
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Receiver disabled in Stop mode,1: Receiver enabled in Stop mode"
|
|
newline
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode"
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled,1: Receive bit clock is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
newline
|
|
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
newline
|
|
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected,1: Receive overflow detected"
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full,1: Enabled receive FIFO is full"
|
|
newline
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached,1: Receive FIFO watermark has been reached"
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RCR1,SAI Receive Configuration 1 Register"
|
|
bitfld.long 0x00 0.--4. "RFW,Receive FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter,?..."
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit Clock is active high with drive outputs..,1: Bit Clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RCR3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. "CFR,Channel FIFO Reset" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "RCE,Receive Channel Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RCR4,SAI Receive Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO writes..,2: FIFO combine mode enabled on FIFO reads (by..,3: FIFO combine mode enabled on FIFO writes.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
bitfld.long 0x00 16.--20. "FRSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is received first,1: MSB is received first"
|
|
newline
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
newline
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave..,1: Frame Sync is generated internally in Master.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0xA0)++0x03
|
|
line.long 0x00 "RDR[$1],SAI Receive Data Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "RDR,Receive Data Register"
|
|
repeat.end
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "RFR[$1],SAI Receive FIFO Register $1"
|
|
bitfld.long 0x00 16.--21. "WFP,Write FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. "RCP,Receive Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO reads and.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "RFP,Read FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RMR,SAI Receive Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "RWM,Receive Word Mask"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "GPT (General Purpose Timer)"
|
|
repeat 2. (list 1. 2.) (list ad:0x401EC000 ad:0x401F0000)
|
|
tree "GPT$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,GPT Control Register"
|
|
bitfld.long 0x00 31. "FO3,FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)" "0: Writing a 0 has no effect,1: Causes the programmed pin action on the timer.."
|
|
bitfld.long 0x00 30. "FO2,See F03" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "FO1,See F03" "0,1"
|
|
bitfld.long 0x00 26.--28. "OM3,OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode" "0: Output disconnected,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate an active low pulse (that is one..,5: Generate an active low pulse (that is one..,6: Generate an active low pulse (that is one..,7: Generate an active low pulse (that is one.."
|
|
newline
|
|
bitfld.long 0x00 23.--25. "OM2,See OM3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "OM1,See OM3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "IM2,IM2 (bits 19-18 Input Capture Channel 2 operating mode) IM1 (bits 17-16 Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n) which will trigger a capture event" "0: capture disabled,1: capture on rising edge only,2: capture on falling edge only,3: capture on both edges"
|
|
bitfld.long 0x00 16.--17. "IM1,See IM2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 15. "SWR,Software reset" "0: GPT is not in reset state,1: GPT is in reset state"
|
|
bitfld.long 0x00 10. "EN_24M,Enable 24 MHz clock input from crystal" "0: 24M clock disabled,1: 24M clock enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FRR,Free-Run or Restart mode" "0: Restart mode,1: Free-Run mode"
|
|
bitfld.long 0x00 6.--8. "CLKSRC,Clock Source select" "0: CLKSRC_0,1: Peripheral Clock (ipg_clk),2: High Frequency Reference Clock..,3: External Clock,4: Low Frequency Reference Clock (ipg_clk_32k),5: Crystal oscillator as Reference Clock..,?..."
|
|
newline
|
|
bitfld.long 0x00 5. "STOPEN,GPT Stop Mode enable" "0: GPT is disabled in Stop mode,1: GPT is enabled in Stop mode"
|
|
bitfld.long 0x00 4. "DOZEEN,GPT Doze Mode Enable" "0: GPT is disabled in doze mode,1: GPT is enabled in doze mode"
|
|
newline
|
|
bitfld.long 0x00 3. "WAITEN,GPT Wait Mode enable" "0: GPT is disabled in wait mode,1: GPT is enabled in wait mode"
|
|
bitfld.long 0x00 2. "DBGEN,GPT debug mode enable" "0: GPT is disabled in debug mode,1: GPT is enabled in debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "ENMOD,GPT Enable mode" "0: GPT counter will retain its value when it is..,1: GPT counter value is reset to 0 when it is.."
|
|
bitfld.long 0x00 0. "EN,GPT Enable" "0: GPT is disabled,1: GPT is enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PR,GPT Prescaler Register"
|
|
bitfld.long 0x00 12.--15. "PRESCALER24M,Prescaler bits" "0: PRESCALER24M_0,1: PRESCALER24M_1,?,?,?,?,?,?,?,?,?,?,?,?,?,15: PRESCALER24M_15"
|
|
hexmask.long.word 0x00 0.--11. 1. "PRESCALER,Prescaler bits"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,GPT Status Register"
|
|
eventfld.long 0x00 5. "ROV,Rollover Flag" "0: Rollover has not occurred,1: Rollover has occurred"
|
|
eventfld.long 0x00 4. "IF2,IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n" "0: Capture event has not occurred,1: Capture event has occurred"
|
|
newline
|
|
eventfld.long 0x00 3. "IF1,See IF2" "0,1"
|
|
eventfld.long 0x00 2. "OF3,OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
newline
|
|
eventfld.long 0x00 1. "OF2,See OF3" "0,1"
|
|
eventfld.long 0x00 0. "OF1,See OF3" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IR,GPT Interrupt Register"
|
|
bitfld.long 0x00 5. "ROVIE,Rollover Interrupt Enable" "0: Rollover interrupt is disabled,1: Rollover interrupt enabled"
|
|
bitfld.long 0x00 4. "IF2IE,IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable" "0: IF2IE Input Capture n Interrupt Enable is..,1: IF2IE Input Capture n Interrupt Enable is.."
|
|
newline
|
|
bitfld.long 0x00 3. "IF1IE,See IF2IE" "0,1"
|
|
bitfld.long 0x00 2. "OF3IE,OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt" "0: Output Compare Channel n interrupt is disabled,1: Output Compare Channel n interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "OF2IE,See OF3IE" "0,1"
|
|
bitfld.long 0x00 0. "OF1IE,See OF3IE" "0,1"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "OCR$1,GPT Output Compare Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Compare Value"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x1C)++0x03
|
|
line.long 0x00 "ICR$1,GPT Input Capture Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPT,Capture Value"
|
|
repeat.end
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CNT,GPT Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Counter Value"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "OCOTP"
|
|
base ad:0x401F4000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "HW_OCOTP_CTRL,OTP Controller Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
|
|
bitfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
|
|
rbitfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADDR,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HW_OCOTP_CTRL_SET,OTP Controller Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
|
|
bitfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
|
|
rbitfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADDR,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HW_OCOTP_CTRL_CLR,OTP Controller Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
|
|
eventfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
|
|
eventfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0.--5. "ADDR,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HW_OCOTP_CTRL_TOG,OTP Controller Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
|
|
bitfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
|
|
rbitfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADDR,OTP write and read access address register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HW_OCOTP_TIMING,OTP Controller Timing Register"
|
|
bitfld.long 0x00 22.--27. "WAIT,This count value specifies time interval between auto read and write access in one time program" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "STROBE_READ,This count value specifies the strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RELAX,This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "STROBE_PROG,This count value specifies the strobe period in one time write OTP"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "HW_OCOTP_DATA,OTP Controller Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Used to initiate a write to OTP"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HW_OCOTP_READ_CTRL,OTP Controller Write Data Register"
|
|
bitfld.long 0x00 0. "READ_FUSE,Used to initiate a read to OTP" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "HW_OCOTP_READ_FUSE_DATA,OTP Controller Read Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,The data read from OTP"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "HW_OCOTP_SW_STICKY,Sticky bit Register"
|
|
bitfld.long 0x00 2. "FIELD_RETURN_LOCK,Shadow register write and OTP write lock for FIELD_RETURN region" "0,1"
|
|
bitfld.long 0x00 1. "SRK_REVOKE_LOCK,Shadow register write and OTP write lock for SRK_REVOKE region" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "HW_OCOTP_SCS,Software Controllable Signals Register"
|
|
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
|
|
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
|
|
newline
|
|
bitfld.long 0x00 0. "HAB_JDE,HAB JTAG Debug Enable" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "HW_OCOTP_SCS_SET,Software Controllable Signals Register"
|
|
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
|
|
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
|
|
newline
|
|
bitfld.long 0x00 0. "HAB_JDE,HAB JTAG Debug Enable" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "HW_OCOTP_SCS_CLR,Software Controllable Signals Register"
|
|
eventfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
|
|
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
|
|
newline
|
|
eventfld.long 0x00 0. "HAB_JDE,HAB JTAG Debug Enable" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "HW_OCOTP_SCS_TOG,Software Controllable Signals Register"
|
|
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
|
|
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
|
|
newline
|
|
bitfld.long 0x00 0. "HAB_JDE,HAB JTAG Debug Enable" "0,1"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "HW_OCOTP_VERSION,OTP Controller Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR field of the RTL version"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "HW_OCOTP_TIMING2,OTP Controller Timing Register 2"
|
|
hexmask.long.byte 0x00 22.--29. 1. "RELAX1,This count value specifies time interval between auto read and write access in one time program"
|
|
bitfld.long 0x00 16.--21. "RELAX_READ,This count value specifies the strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RELAX_PROG,This count value specifies the strobe period in one time write OTP"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HW_OCOTP_LOCK,Value of OTP Bank0 Word0 (Lock controls)"
|
|
bitfld.long 0x00 28.--31. "FIELD_RETURN,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 26.--27. "GP3,Status of shadow register and OTP write lock for gp3 region" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 23. "SW_GP2_RLOCK,Status of shadow register and OTP read lock for sw_gp2 region" "0,1"
|
|
rbitfld.long 0x00 22. "MISC_CONF,Status of shadow register and OTP write lock for misc_conf region" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 21. "SW_GP2_LOCK,Status of shadow register and OTP write lock for sw_gp2 region" "0,1"
|
|
rbitfld.long 0x00 20. "OTPMK_CRC,Status of shadow register and OTP write lock for otpmk_crc region" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. "ANALOG,Status of shadow register and OTP write lock for analog region" "0,1,2,3"
|
|
rbitfld.long 0x00 17. "OTPMK_LSB,Status of shadow register read and write OTP read and write lock for otpmk region (LSB)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "SW_GP1,Status of shadow register and OTP write lock for sw_gp1 region" "0,1"
|
|
rbitfld.long 0x00 15. "OTPMK_MSB,Status of shadow register read and write OTP read and write lock for otpmk region (MSB)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 12.--13. "GP2,Status of shadow register and OTP write lock for gp2 region" "0,1,2,3"
|
|
rbitfld.long 0x00 10.--11. "GP1,Status of shadow register and OTP write lock for gp1 region" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. "MAC_ADDR,Status of shadow register and OTP write lock for mac_addr region" "0,1,2,3"
|
|
rbitfld.long 0x00 6. "SJC_RESP,Status of shadow register read and write OTP read and write lock for sjc_resp region" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "MEM_TRIM,Status of shadow register and OTP write lock for mem_trim region" "0,1,2,3"
|
|
rbitfld.long 0x00 2.--3. "BOOT_CFG,Status of shadow register and OTP write lock for boot_cfg region" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. "TESTER,Status of shadow register and OTP write lock for tester region" "0,1,2,3"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG0,Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,This register contains 32 bits of the Unique ID and SJC_CHALLENGE field"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG1,Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,This register contains 32 bits of the Unique ID and SJC_CHALLENGE field"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG2,Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 0 word 3 (ADDR = 0x03)"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG3,Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 0 word 4 (ADDR = 0x04)"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG4,Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 0 word 5 (ADDR = 0x05)"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG5,Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 0 word 6 (ADDR = 0x06)"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "HW_OCOTP_CFG6,Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 0 word 7 (ADDR = 0x07)"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "HW_OCOTP_MEM0,Value of OTP Bank1 Word0 (Memory Related Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 0 (ADDR = 0x08)"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "HW_OCOTP_MEM1,Value of OTP Bank1 Word1 (Memory Related Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 1 (ADDR = 0x09)"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "HW_OCOTP_MEM2,Value of OTP Bank1 Word2 (Memory Related Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 2 (ADDR = 0x0A)"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "HW_OCOTP_MEM3,Value of OTP Bank1 Word3 (Memory Related Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 3 (ADDR = 0x0B)"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "HW_OCOTP_MEM4,Value of OTP Bank1 Word4 (Memory Related Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 4 (ADDR = 0x0C)"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "HW_OCOTP_ANA0,Value of OTP Bank1 Word5 (Analog Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 5 (ADDR = 0x0D)"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "HW_OCOTP_ANA1,Value of OTP Bank1 Word6 (Analog Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 6 (ADDR = 0x0E)"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "HW_OCOTP_ANA2,Value of OTP Bank1 Word7 (Analog Info.)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 1 word 7 (ADDR = 0x0F)"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK0,Shadow Register for OTP Bank3 Word0 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3 word 0 (ADDR = 0x1C))"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK1,Shadow Register for OTP Bank3 Word1 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3 word 1 (ADDR = 0x1D))"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK2,Shadow Register for OTP Bank3 Word2 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3 word 2 (ADDR = 0x1E))"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK3,Shadow Register for OTP Bank3 Word3 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3 word 3 (ADDR = 0x1F))"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK4,Shadow Register for OTP Bank3 Word4 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3 word 4 (ADDR = 0x20))"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK5,Shadow Register for OTP Bank3 Word5 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3 word 5 (ADDR = 0x21))"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK6,Shadow Register for OTP Bank3 Word6 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3 word 6 (ADDR = 0x22))"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK7,Shadow Register for OTP Bank3 Word7 (SRK Hash)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3 word 7 (ADDR = 0x23))"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "HW_OCOTP_SJC_RESP0,Value of OTP Bank4 Word0 (Secure JTAG Response Field)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4 word 0 (ADDR = 0x20))"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "HW_OCOTP_SJC_RESP1,Value of OTP Bank4 Word1 (Secure JTAG Response Field)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4 word 1 (ADDR = 0x21))"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "HW_OCOTP_MAC0,Value of OTP Bank4 Word2 (MAC Address)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 4 word 2 (ADDR = 0x22)"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "HW_OCOTP_MAC1,Value of OTP Bank4 Word3 (MAC Address)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 4 word 3 (ADDR = 0x23)"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "HW_OCOTP_GP3,Value of OTP Bank4 Word4 (MAC Address)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 4 word 4 (ADDR = 0x24)"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "HW_OCOTP_GP1,Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 4 word 6 (ADDR = 0x26)"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "HW_OCOTP_GP2,Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 4 word 7 (ADDR = 0x27)"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "HW_OCOTP_SW_GP1,Value of OTP Bank5 Word0 (SW GP1)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 0 (ADDR = 0x28)"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "HW_OCOTP_SW_GP20,Value of OTP Bank5 Word1 (SW GP2)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 1 (ADDR = 0x29)"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "HW_OCOTP_SW_GP21,Value of OTP Bank5 Word2 (SW GP2)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 2 (ADDR = 0x2a)"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "HW_OCOTP_SW_GP22,Value of OTP Bank5 Word3 (SW GP2)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 3 (ADDR = 0x2b)"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "HW_OCOTP_SW_GP23,Value of OTP Bank5 Word4 (SW GP2)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 4 (ADDR = 0x2c)"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "HW_OCOTP_MISC_CONF0,Value of OTP Bank5 Word5 (Misc Conf)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 5 (ADDR = 0x2d)"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "HW_OCOTP_MISC_CONF1,Value of OTP Bank5 Word6 (Misc Conf)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 6 (ADDR = 0x2e)"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "HW_OCOTP_SRK_REVOKE,Value of OTP Bank5 Word7 (SRK Revoke)"
|
|
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 5 word 7 (ADDR = 0x2f)"
|
|
tree.end
|
|
tree "IOMUXC (IOMUX Controller)"
|
|
base ad:0x401F8000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_14,SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_14"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_13,SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_13"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_12,SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_12"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_11,SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_11"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_10,SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_10"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_09,SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_09"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_08,SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_08"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_07,SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_07"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_06,SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_06"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_05,SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_05"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_04,SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_04"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_03,SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_03"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_02,SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_02"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?,7: Select mux mode"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_01,SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_01"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_AD_00,SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_AD_00"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_14,SW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_14"
|
|
bitfld.long 0x00 0. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_13,SW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_13"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_12,SW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_12"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_11,SW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_11"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_10,SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_10"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_09,SW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_09"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_08,SW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_08"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_07,SW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_07"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_06,SW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_06"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_05,SW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_05"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_04,SW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_04"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_03,SW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_03"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_02,SW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_02"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_01,SW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_01"
|
|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
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group.long 0x84++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_SD_00,SW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_SD_00"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
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group.long 0x88++0x03
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|
line.long 0x00 "SW_MUX_CTL_PAD_GPIO_13,SW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register"
|
|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_13"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
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group.long 0x8C++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_12,SW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register"
|
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_12"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
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group.long 0x90++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_11,SW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_11"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,7: Select mux mode"
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group.long 0x94++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_10,SW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_10"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
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group.long 0x98++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_09,SW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_09"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
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group.long 0x9C++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_08,SW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_08"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
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group.long 0xA0++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_07,SW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_07"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
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group.long 0xA4++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_06,SW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_06"
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|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xA8++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_05,SW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_05"
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|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xAC++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_04,SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register"
|
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_04"
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|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xB0++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_03,SW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_03"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xB4++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_02,SW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_02"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xB8++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_01,SW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register"
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bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_01"
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bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xBC++0x03
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line.long 0x00 "SW_MUX_CTL_PAD_GPIO_00,SW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register"
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|
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO_00"
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|
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
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group.long 0xC0++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_14,SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xC4++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_13,SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xC8++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_12,SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
|
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xCC++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_11,SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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|
group.long 0xD0++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_10,SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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|
group.long 0xD4++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_09,SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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|
newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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|
newline
|
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_08,SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register"
|
|
bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
|
bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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|
newline
|
|
bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
|
|
newline
|
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_07,SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register"
|
|
bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
|
newline
|
|
bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xE0++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_06,SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xE4++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_05,SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xE8++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_04,SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xEC++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_03,SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xF0++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_02,SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xF4++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_01,SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xF8++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_AD_00,SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0xFC++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_14,SW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x100++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_13,SW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x104++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_12,SW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x108++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_11,SW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
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group.long 0x10C++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_10,SW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0x110++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_09,SW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x114++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_08,SW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x118++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_07,SW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x11C++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_06,SW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x120++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_05,SW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x124++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_04,SW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x128++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_03,SW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x12C++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_02,SW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x130++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_01,SW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x134++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_SD_00,SW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x138++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_13,SW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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|
group.long 0x13C++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_12,SW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
|
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_GPIO_11,SW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register"
|
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x144++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_10,SW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x148++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_09,SW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x14C++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_08,SW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x150++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_07,SW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x154++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_06,SW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x158++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_05,SW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x15C++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_04,SW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x160++0x03
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_03,SW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x164++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_02,SW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
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bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
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bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
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group.long 0x168++0x03
|
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line.long 0x00 "SW_PAD_CTL_PAD_GPIO_01,SW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register"
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
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bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
|
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
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bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
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group.long 0x16C++0x03
|
|
line.long 0x00 "SW_PAD_CTL_PAD_GPIO_00,SW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register"
|
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bitfld.long 0x00 16. "HYS,Hyst" "0: HYS_0_Hysteresis_Disabled,1: HYS_1_Hysteresis_Enabled"
|
|
bitfld.long 0x00 14.--15. "PUS,Pull Up / Down Config" "0: PUS_0_100K_Ohm_Pull_Down,1: PUS_1_47K_Ohm_Pull_Up,2: PUS_2_100K_Ohm_Pull_Up,3: PUS_3_22K_Ohm_Pull_Up"
|
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newline
|
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bitfld.long 0x00 13. "PUE,Pull / Keep Select Field" "0: PUE_0_Keeper,1: PUE_1_Pull"
|
|
bitfld.long 0x00 12. "PKE,Pull / Keep Enable Field" "0: PKE_0_Pull_Keeper_Disabled,1: PKE_1_Pull_Keeper_Enabled"
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newline
|
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bitfld.long 0x00 11. "ODE,Open Drain Enable Field" "0: ODE_0_Open_Drain_Disabled,1: ODE_1_Open_Drain_Enabled"
|
|
bitfld.long 0x00 6.--7. "SPEED,Speed Field" "0: SPEED_0_low_50MHz,1: SPEED_1_medium_100MHz,2: SPEED_2_fast_150MHz,3: SPEED_3_max_200MHz"
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newline
|
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bitfld.long 0x00 3.--5. "DSE,Drive Strength Field" "0: DSE_0_output_driver_disabled_,1:..,2: DSE_2_R0_2,3: DSE_3_R0_3,4: DSE_4_R0_4,5: DSE_5_R0_5,6: DSE_6_R0_6,7: DSE_7_R0_7"
|
|
bitfld.long 0x00 0. "SRE,Slew Rate Field" "0: SRE_0_Slow_Slew_Rate,1: SRE_1_Fast_Slew_Rate"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "USB_OTG_ID_SELECT_INPUT,USB_OTG_ID_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x174++0x03
|
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line.long 0x00 "FLEXPWM1_PWMA_SELECT_INPUT_0,FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMA_SELECT_INPUT_1,FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMA_SELECT_INPUT_2,FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMA_SELECT_INPUT_3,FLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMB_SELECT_INPUT_0,FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMB_SELECT_INPUT_1,FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMB_SELECT_INPUT_2,FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "FLEXPWM1_PWMB_SELECT_INPUT_3,FLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "FLEXSPI_DQS_FA_SELECT_INPUT,FLEXSPI_DQS_FA_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "FLEXSPI_DQS_FB_SELECT_INPUT,FLEXSPI_DQS_FB_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "KPP_COL_SELECT_INPUT_0,KPP_COL_SELECT_INPUT_0 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "KPP_COL_SELECT_INPUT_1,KPP_COL_SELECT_INPUT_1 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "KPP_COL_SELECT_INPUT_2,KPP_COL_SELECT_INPUT_2 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "KPP_COL_SELECT_INPUT_3,KPP_COL_SELECT_INPUT_3 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "KPP_ROW_SELECT_INPUT_0,KPP_ROW_SELECT_INPUT_0 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "KPP_ROW_SELECT_INPUT_1,KPP_ROW_SELECT_INPUT_1 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "KPP_ROW_SELECT_INPUT_2,KPP_ROW_SELECT_INPUT_2 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "KPP_ROW_SELECT_INPUT_3,KPP_ROW_SELECT_INPUT_3 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "LPI2C1_HREQ_SELECT_INPUT,LPI2C1_HREQ_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "LPI2C1_SCL_SELECT_INPUT,LPI2C1_SCL_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "LPI2C1_SDA_SELECT_INPUT,LPI2C1_SDA_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "LPI2C2_SCL_SELECT_INPUT,LPI2C2_SCL_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "LPI2C2_SDA_SELECT_INPUT,LPI2C2_SDA_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "LPSPI1_PCS_SELECT_INPUT_0,LPSPI1_PCS_SELECT_INPUT_0 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "LPSPI1_SCK_SELECT_INPUT,LPSPI1_SCK_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "LPSPI1_SDI_SELECT_INPUT,LPSPI1_SDI_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "LPSPI1_SDO_SELECT_INPUT,LPSPI1_SDO_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "LPSPI2_PCS_SELECT_INPUT_0,LPSPI2_PCS_SELECT_INPUT_0 DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "LPSPI2_SCK_SELECT_INPUT,LPSPI2_SCK_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "LPSPI2_SDI_SELECT_INPUT,LPSPI2_SDI_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "LPSPI2_SDO_SELECT_INPUT,LPSPI2_SDO_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "LPUART1_RXD_SELECT_INPUT,LPUART1_RXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "LPUART1_TXD_SELECT_INPUT,LPUART1_TXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "LPUART2_RXD_SELECT_INPUT,LPUART2_RXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "LPUART2_TXD_SELECT_INPUT,LPUART2_TXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "LPUART3_RXD_SELECT_INPUT,LPUART3_RXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "LPUART3_TXD_SELECT_INPUT,LPUART3_TXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "LPUART4_RXD_SELECT_INPUT,LPUART4_RXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "LPUART4_TXD_SELECT_INPUT,LPUART4_TXD_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "NMI_GLUE_NMI_SELECT_INPUT,NMI_GLUE_NMI_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "SPDIF_IN1_SELECT_INPUT,SPDIF_IN1_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "SPDIF_TX_CLK2_SELECT_INPUT,SPDIF_TX_CLK2_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "USB_OTG_OC_SELECT_INPUT,USB_OTG_OC_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "XEV_GLUE_RXEV_SELECT_INPUT,XEV_GLUE_RXEV_SELECT_INPUT DAISY Register"
|
|
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
|
|
tree.end
|
|
tree "KPP (KPP Registers)"
|
|
base ad:0x401FC000
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "KPCR,Keypad Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "KCO,Keypad Column Strobe Open-Drain Enable"
|
|
hexmask.word.byte 0x00 0.--7. 1. "KRE,Keypad Row Enable"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "KPSR,Keypad Status Register"
|
|
bitfld.word 0x00 9. "KRIE,Keypad Release Interrupt Enable" "0: No interrupt request is generated when KPKR..,1: An interrupt request is generated when KPKR.."
|
|
bitfld.word 0x00 8. "KDIE,Keypad Key Depress Interrupt Enable" "0: No interrupt request is generated when KPKD..,1: An interrupt request is generated when KPKD.."
|
|
newline
|
|
bitfld.word 0x00 3. "KRSS,Key Release Synchronizer Set" "0: No effect,1: Set bits which sets keypad release.."
|
|
bitfld.word 0x00 2. "KDSC,Key Depress Synchronizer Clear" "0: No effect,1: Set bits that clear the keypad depress.."
|
|
newline
|
|
eventfld.word 0x00 1. "KPKR,Keypad Key Release" "0: No key release detected,1: All keys have been released"
|
|
eventfld.word 0x00 0. "KPKD,Keypad Key Depress" "0: No key presses detected,1: A key has been depressed"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "KDDR,Keypad Data Direction Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "KCDD,Keypad Column Data Direction Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. "KRDD,Keypad Row Data Direction"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "KPDR,Keypad Data Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "KCD,Keypad Column Data"
|
|
hexmask.word.byte 0x00 0.--7. 1. "KRD,Keypad Row Data"
|
|
tree.end
|
|
autoindent.off
|
|
newline
|