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Gen4_R-Car_Trace32/2_Trunk/perepxa.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: Excalibur EXPA (ARM922T) on chip peripherals
; @Props:
; @Author: -
; @Changelog:
; @Manufacturer:
; @Doc:
; @Core:
; @Chiplist: EPXA
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perepxa.per 12685 2020-12-22 12:37:17Z pegold $
config 16. 8.
width 9.
base ad:0
tree "Cache and MMU"
group c15:0x0--0x0 "CP15"
line.long 0x0 "ID,Identity Code"
hexfld.byte 0x3 "IMPL ,Implementor"
hexfld.byte 0x2 " ARCH ,Architecture"
hexmask.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
hexfld.byte 0x0 " REV ,Revision"
group c15:0x100--0x100
line.long 0x0 "CTYPE,Cache Type"
bitfld.long 0x0 25.--28. "CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
textline " "
bitfld.long 0x0 18.--20. "DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k"
bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
textline " "
bitfld.long 0x0 6.--8. "ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k"
bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
group c15:0x1--0x1
line.long 0x0 "CR,Control Register"
bitfld.long 0x0 31. "iA ,Asynchronous Clocking Select" "0,1"
bitfld.long 0x0 30. " nF ,nFastBus Select" "0,1"
bitfld.long 0x0 14. " RR ,Round Robin Replacement" "random,round robin"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "00000000,FFFF0000"
textline " "
bitfld.long 0x0 12. "I ,Instruction Cache Enable" "dis,ena"
bitfld.long 0x0 0x9 "R ,ROM Protection" "off,on"
bitfld.long 0x0 0x8 " S ,System Protection" "off,on"
bitfld.long 0x0 0x7 " B ,Endianism" "little,big"
bitfld.long 0x0 0x2 " C ,Cache" "disable,enable"
bitfld.long 0x0 0x1 " A ,Alignment Fault" "disable,enable"
bitfld.long 0x0 0x0 " M ,MMU" "disable,enable"
;group c15:0x102--0x102
; line.long 0x0 "ITTB,Instruction Translation Table Base Register"
; hexmask.long 0x0 14.--31. 0x4000 "ITTBA ,Instruction Translation Table Base Address"
group c15:0x2--0x2
line.long 0x0 "TTB,Translation Table Base Register"
hexmask.long 0x0 14.--31. 0x4000 "TTBA ,Translation Table Base Address"
;group c15:0x103--0x103
; line.long 0x0 "IDAC,Instruction Domain Access Control Register"
; bitfld.long 0x0 30.--31. "D15 ,Domain Access 15" "no access,client,reserved,manager"
; bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "no access,client,reserved,manager"
; bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "no access,client,reserved,manager"
; bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "no access,client,reserved,manager"
; textline " "
; bitfld.long 0x0 22.--23. "D11 ,Domain Access 11" "no access,client,reserved,manager"
; bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "no access,client,reserved,manager"
; bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "no access,client,reserved,manager"
; bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "no access,client,reserved,manager"
; textline " "
; bitfld.long 0x0 14.--15. "D7 ,Domain Access 7" "no access,client,reserved,manager"
; bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "no access,client,reserved,manager"
; bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "no access,client,reserved,manager"
; bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "no access,client,reserved,manager"
; textline " "
; bitfld.long 0x0 6.--7. "D3 ,Domain Access 3" "no access,client,reserved,manager"
; bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "no access,client,reserved,manager"
; bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "no access,client,reserved,manager"
; bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "no access,client,reserved,manager"
group c15:0x3--0x3
line.long 0x0 "DAC,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15 ,Domain Access 15" "no access,client,reserved,manager"
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "no access,client,reserved,manager"
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "no access,client,reserved,manager"
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "no access,client,reserved,manager"
textline " "
bitfld.long 0x0 22.--23. "D11 ,Domain Access 11" "no access,client,reserved,manager"
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "no access,client,reserved,manager"
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "no access,client,reserved,manager"
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "no access,client,reserved,manager"
textline " "
bitfld.long 0x0 14.--15. "D7 ,Domain Access 7" "no access,client,reserved,manager"
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "no access,client,reserved,manager"
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "no access,client,reserved,manager"
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "no access,client,reserved,manager"
textline " "
bitfld.long 0x0 6.--7. "D3 ,Domain Access 3" "no access,client,reserved,manager"
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "no access,client,reserved,manager"
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "no access,client,reserved,manager"
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "no access,client,reserved,manager"
group c15:0x105--0x105
line.long 0x0 "IFSR,Instruction Fault Status Register"
bitfld.long 0x0 0x4--0x7 "DOM ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0x0--0x3 " STA ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
group c15:0x5--0x5
line.long 0x0 "DFSR,Data Fault Status Register"
bitfld.long 0x0 0x4--0x7 "DOM ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0x0--0x3 " STA ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
group c15:0x106--0x106
line.long 0x0 "IFAR,Instruction Fault Address Register"
group c15:0x6--0x6
line.long 0x0 "DFAR,Data Fault Address Register"
group c15:0x109--0x109
line.long 0x0 "ICACHE,Instruction Cache Lockdown"
group c15:0x9--0x9
line.long 0x0 "DCACHE,Data Cache Lockdown"
group c15:0x0d--0x0d
line.long 0x0 "PID,Process Identifier"
group c15:0x0f--0x0f
line.long 0x0 "TEST,Test State"
tree.end
base ad:0x7fffc000
tree "Reset and Mode Control"
group 0x000++3
line.long 0x0 "BOOT_CR,boot-control register"
bitfld.long 0x0 2. "RE ,Registers enabled" "0,1"
bitfld.long 0x0 1. " HM ,Hold microprocessor" "0,1"
bitfld.long 0x0 0. " BM ,Boot memory mapping" "0,1"
group 0x004++3
line.long 0x0 "RESET_SR,reset status register"
bitfld.long 0x0 3. "ER ,External pin" "0,1"
bitfld.long 0x0 2. " JT ,JTAG" "0,1"
bitfld.long 0x0 1. " CR ,Configuration error" "0,1"
bitfld.long 0x0 0. " WR ,Watchdog" "0,1"
group 0x008++3
line.long 0x0 "IDCODE,identity and version register"
hexmask.long 0x0 0.--31. 0x1 "IDCODE ,Chip ID code"
group 0x020++3
line.long 0x0 "SRAM0_SR,SRAM0 status register"
hexmask.long 0x0 0.--31. 0x1 "SIZE ,Memory block size"
group 0x024++3
line.long 0x0 "SRAM1_SR,SRAM1 status register"
hexmask.long 0x0 0.--31. 0x1 "SIZE ,Memory block size"
group 0x030++3
line.long 0x0 "DPSRAM0,dual-port SRAM0 status register"
hexmask.long 0x0 12.--31. 0x1 "SIZE ,Memory block size"
bitfld.long 0x0 4.--5. " GLBL ,Global dual-port mode" "norm du,deep sing,wide sing,res"
bitfld.long 0x0 0.--3. " M ,MODE" "res,1sing 64kB,1sing 32kB,1sing 16kB,1du 32kB,2sing 32kB,2sing 16kB,?..."
group 0x034++3
line.long 0x0 "AM0_LCR,AM0 lock control register"
hexmask.long 0x0 5.--16. 0x1 "LCKADDR ,Start address"
group 0x038++3
line.long 0x0 "AM1_SR,AM1 status register"
hexmask.long 0x0 12.--31. 0x1 "SIZE ,Memory block size"
bitfld.long 0x0 4.--5. " GLBL ,Global dual-port mode" "norm du,deep sing,wide sing,res"
bitfld.long 0x0 0.--3. " M ,MODE" "res,1sing 64kB,1sing 32kB,1sing 16kB,1du 32kB,2sing 32kB,2sing 16kB,?..."
group 0x03C++3
line.long 0x0 "AM1_LCR,Am1 lock control register"
hexmask.long 0x0 5.--16. 0x1 "LCKADDR ,Start address"
tree.end
tree "I/O Control Registers"
group 0x040++3
line.long 0x0 "SDRAM,SDRAM IO bank control register"
bitfld.long 0x0 5.--6. "IC ,Input control" "2.5,1.8,sstl,res"
bitfld.long 0x0 2.--4. " OC ,Output control" "slow,fast,pci di,pci di,pci di,Op dra,Op dra,Op dra"
bitfld.long 0x0 1. " IO ,Select bank" "Pld,Stripe"
bitfld.long 0x0 0. " LK ," "0,1"
group 0x044++3
line.long 0x0 "EBI,EBI IO bank control register"
bitfld.long 0x0 5.--6. "IC ,Input control" "2.5,1.8,sstl,res"
bitfld.long 0x0 2.--4. " OC ,Output control" "slow,fast,pci di,pci di,pci di,Op dra,Op dra,Op dra"
bitfld.long 0x0 1. " IO ,Select bank" "Pld,Stripe"
bitfld.long 0x0 0. " LK ," "0,1"
group 0x048++3
line.long 0x0 "UART,UART IO bank control register"
bitfld.long 0x0 5.--6. "IC ,Input control" "2.5,1.8,sstl,res"
bitfld.long 0x0 2.--4. " OC ,Output control" "slow,fast,pci di,pci di,pci di,Op dra,Op dra,Op dra"
bitfld.long 0x0 1. " IO ,Select bank" "Pld,Stripe"
bitfld.long 0x0 0. " LK ," "0,1"
group 0x04C++3
line.long 0x0 "TRACE,trace IO bank control register"
bitfld.long 0x0 5.--6. "IC ,Input control" "2.5,1.8,sstl,res"
bitfld.long 0x0 2.--4. " OC ,Output control" "slow,fast,pci di,pci di,pci di,Op dra,Op dra,Op dra"
bitfld.long 0x0 1. " IO ,Select bank" "Pld,Stripe"
bitfld.long 0x0 0. " LK ," "0,1"
tree.end
tree "Memory Map Registers"
group 0x080++3
line.long 0x0 "R,REGISTERS"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x090++3
line.long 0x0 "SRAM0,on-chip SRAM block 0"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x094++3
line.long 0x0 "SRAM1,on-chip SRAM block 1"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0A0++3
line.long 0x0 "DPSRAM0,dual-port SRAM block 0"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0A4++3
line.long 0x0 "DPSRAM1,dual-port SRAM block 1"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0B0++3
line.long 0x0 "SDRAM0,SDRAM block 0"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0B4++3
line.long 0x0 "SDRAM1,SDRAM block 1"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0C0++3
line.long 0x0 "EBI0,EBI block 0"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0C4++3
line.long 0x0 "EBI1,EBI block 1"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0C8++3
line.long 0x0 "EBI2,EBI block 2"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0CC++3
line.long 0x0 "EBI3,EBI block 3"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0D0++3
line.long 0x0 "PLD0,PLD region 0"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0D4++3
line.long 0x0 "PLD1,PLD region 1"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0D8++3
line.long 0x0 "PLD2,PLD region 2"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
group 0x0DC++3
line.long 0x0 "PLD3,PLD region 3"
hexmask.long 0x0 14.--31. 0x4000 "BASE ,base address for this region"
bitfld.long 0x0 7.--11. " SIZE ,log2 region size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x0 1. " NP ,No pre-fetch" "no,yes"
bitfld.long 0x0 0. " EN ,enables the decoding" "no,yes"
tree.end
tree "Bridge-Control and Status Registers"
group 0x100++3
line.long 0x0 "A12BCR,AHB1-2 bridge-control register"
bitfld.long 0x0 1. "NW ,prevents the posting" "no,yes"
bitfld.long 0x0 0. " NP ,prevents the pre-fetching " "no,yes"
group 0x110++3
line.long 0x0 "PLDSB_CR,stripe-to-PLD bridge-control register"
bitfld.long 0x0 6.--8. "HBURST ,The value of the HBURST" "0,1,2,3,?..."
bitfld.long 0x0 3.--5. " HSIZE ,value of the HSIZE" "0,1,2,3,?..."
bitfld.long 0x0 1.--2. " HTRN ,The value of the HTRANS" "0,1,2,3"
bitfld.long 0x0 0. " WF ,error has been received" "no,yes"
group 0x114++3
line.long 0x0 "PLDSB_SR,stripe-to-PLD bridge status register"
bitfld.long 0x0 1. "NW ,prevents the posting" "no,yes"
bitfld.long 0x0 0. " NP ,prevents the pre-fetching " "no,yes"
group 0x118++3
line.long 0x0 "ADDRSR,PLD-to-stripe bridge address status register"
hexmask.long 0x0 0.--31. 0x1 "HADDR ,The value of the HADDR"
group 0x120++3
line.long 0x0 "PLDMB_CR,PLD-to-stripe bridge status register"
bitfld.long 0x0 6.--8. "HBURST ,The value of the HBURST" "0,1,2,3,?..."
bitfld.long 0x0 3.--5. " HSIZE ,value of the HSIZE" "0,1,2,3,?..."
bitfld.long 0x0 1.--2. " HTRN ,The value of the HTRANS" "0,1,2,3"
bitfld.long 0x0 0. " WF ,error has been received" "no,yes"
group 0x800++3
line.long 0x0 "A12B_SR,AHB1-2 bridge-status register"
bitfld.long 0x0 6.--8. "HBURST ,The value of the HBURST" "0,1,2,3,?..."
bitfld.long 0x0 3.--5. " HSIZE ,value of the HSIZE" "0,1,2,3,?..."
bitfld.long 0x0 1.--2. " HTRN ,The value of the HTRANS" "0,1,2,3"
bitfld.long 0x0 0. " WF ,error has been received" "no,yes"
group 0x804++3
line.long 0x0 "A12B_AD,AHB1-2 bridge address status"
hexmask.long 0x0 0.--31. 0x1 "HADDR ,The value of the HADDR"
tree.end
tree "PLD Configuration Registers"
group 0x140++3
line.long 0x0 "CONTROL,configuration control register"
bitfld.long 0x0 5.--7. "ES ,Error source." "res,PLD,Clock,res,exter,res,res,res"
bitfld.long 0x0 4. " E ,Error." "no,yes"
bitfld.long 0x0 3. " PC ,PLD is configured" "no,yes"
textline " "
bitfld.long 0x0 2. " B ,Busy" "ready,not ready"
bitfld.long 0x0 1. " CO ,Configure." "be indic,not indic"
bitfld.long 0x0 0. " LK ,Lock" "no write,write"
group 0x144++3
line.long 0x0 "CLOCK,configuration clock register"
hexmask.long 0x0 0.--15. 0x1 "RATIO ,Half the divide ratio applied to AHB2 clock"
group 0x148++3
line.long 0x0 "DATA,embedded controller data register"
hexmask.long 0x0 0.--15. 0x1 "DATA ,Data written to PLD configuration"
group 0x14C++3
line.long 0x0 "UNLOCK,configuration unlock register"
hexmask.long 0x0 0.--15. 0x1 "MAGIC ,Magic number"
tree.end
tree "Timer Registers"
group 0x200++3 "Timer 0"
line.long 0x0 "CR,timer 0 control register"
bitfld.long 0x0 4. "S ,start timer" "no,yes"
bitfld.long 0x0 3. " CI ,clear pending interrupt" "no,yes"
bitfld.long 0x0 2. " IE ,Interrupt-enable" "no,yes"
bitfld.long 0x0 0.--1. " MODE ,Timer mode" "free,1shot,softwa,res"
group 0x210++3
line.long 0x0 "PRE,timer 0 pre-scaler ratio register"
hexmask.long 0x0 0.--31. 0x1 "PRESCALE ,The amount"
group 0x220++3
line.long 0x0 "LIMIT,timer 0 limit register"
hexmask.long 0x0 0.--31. 0x1 "LIMIT ,The value of the timer limit register"
group 0x230++3
line.long 0x0 "READ,timer 0 read register"
hexmask.long 0x0 0.--31. 0x1 "READ ,The latched value of the timer counter"
group 0x240++3 "Timer 1"
line.long 0x0 "CR,timer 1 control register"
bitfld.long 0x0 4. "S ,start timer" "no,yes"
bitfld.long 0x0 3. " CI ,clear pending interrupt" "no,yes"
bitfld.long 0x0 2. " IE ,Interrupt-enable" "no,yes"
bitfld.long 0x0 0.--1. " MODE ,Timer mode" "free,1shot,softwa,res"
group 0x250++3
line.long 0x0 "PRE,timer 1 pre-scaler ratio register"
hexmask.long 0x0 0.--31. 0x1 "PRESCALE ,The amount"
group 0x260++3
line.long 0x0 "LIMIT,timer 1 limit register"
hexmask.long 0x0 0.--31. 0x1 "LIMIT ,The value of the timer limit register"
group 0x270++3
line.long 0x0 "READ,timer 1 read register"
hexmask.long 0x0 0.--31. 0x1 "READ ,The latched value of the timer counter"
tree.end
tree "UART Registers"
group 0x280++3
line.long 0x0 "RSR,receive status register"
bitfld.long 0x0 0.--1. "RE ,Receive error" "no,yes,?..."
hexmask.long 0x0 0.--4. 0x1 " RX_LEVEL ,The number of bytes in the receive FIFO"
group 0x284++3
line.long 0x0 "RDS,received data status"
bitfld.long 0x0 3. "BI ,Break indicator" "rec,not rec"
bitfld.long 0x0 2. " FE ,Framing error" "no,yes"
bitfld.long 0x0 1. " PE ,Parity error" "no,yes"
bitfld.long 0x0 0. " OE ,Overrun error" "no,yes"
group 0x28C++3
hide.long -0x04 "RD,RX_DATA received data"
in
group 0x28C++3
line.long 0x0 "TSR,transmit status register"
bitfld.long 0x0 7. "TXI ,Transmitter idle" "0,1"
hexmask.long 0x0 0.--4. 0x1 " TX_LEVEL ,Transmit FIFO level"
group 0x290++3
line.long 0x0 "TD,transmit data"
hexmask.long 0x0 0.--7. 0x1 "TX_DATA ,Transmit data"
group 0x294++3
line.long 0x0 "FCR,FIFO control register"
bitfld.long 0x0 5.--7. "RX_THR ,Receive threshold level" "1,2,4,6,8,10,12,14"
bitfld.long 0x0 2.--4. " TX_THR ,Transmit threshold level" "0,2,4,8,10,12,14,15"
bitfld.long 0x0 1. " RC ,Clear receive FIFO." "0,1"
bitfld.long 0x0 0. " TC ,Clear transmit FIFO" "0,1"
group 0x298++3
line.long 0x0 "IES,interrupt-enable set register"
bitfld.long 0x0 3. "ME ,Modem-status-interrupt enable" "no,yes"
bitfld.long 0x0 2. " TIE , Transmit-idle-interrupt enable" "no,yes"
bitfld.long 0x0 1. " TE ,Transmit-interrupt enable" "no,yes"
bitfld.long 0x0 0. " RE ,Receive-interrupt enable" "no,yes"
group 0x29C++3
line.long 0x0 "IEC,interrupt-enable clear register"
bitfld.long 0x0 3. "ME ,Modem-status-interrupt enable" "no,yes"
bitfld.long 0x0 2. " TIE , Transmit-idle-interrupt enable" "no,yes"
bitfld.long 0x0 1. " TE ,Transmit-interrupt enable" "no,yes"
bitfld.long 0x0 0. " RE ,Receive-interrupt enable" "no,yes"
group 0x2A0++3
line.long 0x0 "ISR,interrupt status register"
bitfld.long 0x0 3. "MI ,Modem-status-interrupt " "0,1"
bitfld.long 0x0 2. " TII , Transmit-idle-interrupt " "0,1"
bitfld.long 0x0 1. " TI ,Transmit-interrupt " "0,1"
bitfld.long 0x0 0. " RI ,Receive-interrupt " "0,1"
group 0x2A4++3
line.long 0x0 "IID,interrupt ID register"
bitfld.long 0x0 0.--2. "IID ,Interrupt ID" "res,RI,TI,TII,MI,res,res,res"
group 0x2A8++3
line.long 0x0 "MC,mode-configuration register"
bitfld.long 0x0 6. "OE ,Controls the behavior" "in,out"
bitfld.long 0x0 5. " SP ,Stick parity" "0,1"
bitfld.long 0x0 4. " EP ,Selects between even parity" "0,1"
bitfld.long 0x0 3. " PE ,Parity enable" "trans,rec"
bitfld.long 0x0 2. " ST ,Stop bits" "1-bit,2-bit"
bitfld.long 0x0 0.--1. " CLS ,Selects the number of bits" "5,6,7,8"
group 0x2AC++3
line.long 0x0 "MCR,modem control register"
bitfld.long 0x0 7. "AC ,Auto CTS" "trans,not trans"
bitfld.long 0x0 6. " AR ,Auto RTS" "0,1"
bitfld.long 0x0 5. " BR ,Transmit break" "0,1"
bitfld.long 0x0 4. " LB ,puts the UART into loop-back mode" "no,yes"
bitfld.long 0x0 3. " DCD ,Data carrier detect output" "0,1"
bitfld.long 0x0 2. " RI ,Ring indicator output" "0,1"
bitfld.long 0x0 1. " DTR ,Data terminal ready" "0,1"
bitfld.long 0x0 0. " RTS ,Request to send" "0,1"
group 0x2B0++3
line.long 0x0 "MSR,modem status register"
bitfld.long 0x0 7. "DCD ,Set when the DCD_n pin is at a low value" "no,yes"
bitfld.long 0x0 6. " RI ,Set when the RI_n pin is at a low value" "no,yes"
bitfld.long 0x0 5. " DSR ,Set when the DSR_n pin is at a low value" "no,yes"
bitfld.long 0x0 4. " CTS ,Set when the CTS_n pin is at a low value" "no,yes"
textline " "
bitfld.long 0x0 3. " DDCD ,Set when the DCD_n pin changes state" "no,yes"
bitfld.long 0x0 2. " TERI ,Set when the RI_n pin changes from low to high" "no,yes"
bitfld.long 0x0 1. " DDSR ,Set when the DSR_n pin changes state" "no,yes"
bitfld.long 0x0 0. " DCTS ,Set when the CTS_n pin changes state" "no,yes"
group 0x2B4++3
line.long 0x0 "DIV_LO,divisor register low"
hexmask.long 0x0 0.--7. 0x1 "DIV ,Half of the divisor value"
group 0x2B8++3
line.long 0x0 "DIV_HI,divisor register high"
hexmask.long 0x0 0.--7. 0x1 "DIV ,Half of the divisor value"
tree.end
tree "Clock Control Registers"
group 0x300++3
line.long 0x0 "PL1_NCNT,"
bitfld.long 0x0 18. "CT0 ,1 - Odd multiplication factor for N counter" " no,yes"
bitfld.long 0x0 17. " CT1 ,1 - Even multiplication factor for N counter" " no,yes"
bitfld.long 0x0 16. " CT2 ,1 - Bypass for N counter" " no,yes"
hexmask.long 0x0 8.--10. 0x1 " CP ,CLK_PLL1_NCNT"
hexmask.long 0x0 0.--1. 0x1 " CP ,CLK_PLL1_NCNT"
group 0x304++3
line.long 0x0 "PL1_MCNT,"
bitfld.long 0x0 18. "CT0 ,1 - Odd multiplication factor for M counter" " no,yes"
bitfld.long 0x0 17. " CT1 ,1 - Even multiplication factor for M counter" " no,yes"
bitfld.long 0x0 16. " CT2 ,1 - Bypass for M counter" " no,yes"
hexmask.long 0x0 8.--10. 0x1 " CP ,CLK_PLL1_MCNT"
hexmask.long 0x0 0.--1. 0x1 " CP ,CLK_PLL1_MCNT"
group 0x308++3
line.long 0x0 "PL1_KCNT,"
bitfld.long 0x0 18. "CT0 ,1 - Odd multiplication factor for K counter" " no,yes"
bitfld.long 0x0 17. " CT1 ,1 - Even multiplication factor for K counter" " no,yes"
bitfld.long 0x0 16. " CT2 ,1 - Bypass for K counter" " no,yes"
hexmask.long 0x0 8.--10. 0x1 " CP ,CLK_PLL1_KCNT"
hexmask.long 0x0 0.--1. 0x1 " CP ,CLK_PLL1_KCNT"
group 0x30C++3
line.long 0x0 "PL1_CTRL,"
bitfld.long 0x0 15. "LP ,1 - Low-power mode enabled (EPXA1 only)" "NormalPower,LowPower"
bitfld.long 0x0 4.--6. " RLOCK ,Lock window" "0.1ns,0.25ns,0.5ns,1.0ns,1.5ns,2.5ns,10.0ns,?..."
bitfld.long 0x0 0. " P ,1 - PLL enabled" "PLL disabled,PLL enabled"
group 0x310++3
line.long 0x0 "PL2_NCNT,"
bitfld.long 0x0 18. "CT0 ,1 - Odd multiplication factor for N counter" " no,yes"
bitfld.long 0x0 17. " CT1 ,1 - Even multiplication factor for N counter" " no,yes"
bitfld.long 0x0 16. " CT2 ,1 - Bypass for N counter" " no,yes"
hexmask.long 0x0 8.--10. 0x1 " CP ,CLK_PLL2_NCNT"
hexmask.long 0x0 0.--1. 0x1 " CP ,CLK_PLL2_NCNT"
group 0x314++3
line.long 0x0 "PL2_MCNT,"
bitfld.long 0x0 18. "CT0 ,1 - Odd multiplication factor for M counter" " no,yes"
bitfld.long 0x0 17. " CT1 ,1 - Even multiplication factor for M counter" " no,yes"
bitfld.long 0x0 16. " CT2 ,1 - Bypass for M counter" " no,yes"
hexmask.long 0x0 8.--10. 0x1 " CP ,CLK_PLL2_MCNT"
hexmask.long 0x0 0.--1. 0x1 " CP ,CLK_PLL2_MCNT"
group 0x318++3
line.long 0x0 "PL2_KCNT,"
bitfld.long 0x0 18. "CT0 ,1 - Odd multiplication factor for K counter" " no,yes"
bitfld.long 0x0 17. " CT1 ,1 - Even multiplication factor for K counter" " no,yes"
bitfld.long 0x0 16. " CT2 ,1 - Bypass for K counter" " no,yes"
hexmask.long 0x0 8.--10. 0x1 " CP ,CLK_PLL2_KCNT"
hexmask.long 0x0 0.--1. 0x1 " CP ,CLK_PLL2_KCNT"
group 0x31C++3
line.long 0x0 "PL2_CTRL,"
bitfld.long 0x0 15. "LP ,1 - Low-power mode enabled (EPXA1 only)" "NormalPower,LowPower"
bitfld.long 0x0 4.--6. " RLOCK ,Lock window" "0.1ns,0.25ns,0.5ns,1.0ns,1.5ns,2.5ns,10.0ns,?..."
bitfld.long 0x0 0. " P ,1 - PLL enabled" "PLL disabled,PLL enabled"
group 0x320++3
line.long 0x0 "DERIVE,"
bitfld.long 0x0 12. "BP1 ,1 - Force bypass of PLL1" "no,BypassForced"
bitfld.long 0x0 13. " BP2 ,1 - Force bypass of PLL2" " no,BypassForced"
group 0x324++3
line.long 0x0 "STATUS,"
bitfld.long 0x0 5. "P2 ,1 - PLL2 not bypassed" "bypassed,active"
bitfld.long 0x0 4. " P1 ,1 - PLL1 not bypassed" "bypassed,active"
bitfld.long 0x0 3. " C2 ,1 - PLL2 lock changed" "no,yes"
bitfld.long 0x0 2. " C1 ,1 - PLL1 lock changed" "no,yes"
bitfld.long 0x0 1. " L2 ,PLL2 lock status" "unlocked,locked"
bitfld.long 0x0 0. " L1 ,PLL1 lock status" "unlocked,locked"
group 0x328++3
line.long 0x0 "AC,A1_COUNT"
hexmask.long 0x0 0.--31. 0x1 "CPCSR ,Count of processor cycles since reset"
tree.end
tree "Expansion Bus Interface Registers"
group 0x380++3
line.long 0x0 "CR,control register"
bitfld.long 0x0 19. "CE ,Enables the external clock" "no,yes"
bitfld.long 0x0 18. " TE ,Enables timeouts" "no,yes"
hexmask.long 0x0 10.--17. 0x1 " TC ,TIMEOUT Controls the time delay"
bitfld.long 0x0 6.--9. " CLK_DIV ,Values" "res,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 4. " SP ,1-Split-read enable" "no,yes"
textline " "
bitfld.long 0x0 3. " EO ,Enable chip-select outputs" "no,yes"
bitfld.long 0x0 2. " WP ,Write enable polarity" "low,high"
bitfld.long 0x0 1. " OP ,Output enable polarity" "low,high"
bitfld.long 0x0 0. " BP ,Byte enables polarity" "low,high"
group 0x390++3
line.long 0x0 "BLOCK0,"
bitfld.long 0x0 7. "BE ,turns on byte enables" "no,yes"
bitfld.long 0x0 6. " BH ,Byte- or half-word width select" "half word,byte"
bitfld.long 0x0 5. " CP ,Chip-select polarity" "low,high"
hexmask.long 0x0 1.--4. 0x1 " WAIT ,Block transaction wait states"
bitfld.long 0x0 0. " SA ," "syn,asyn"
group 0x394++3
line.long 0x0 "BLOCK1,"
bitfld.long 0x0 7. "BE ,turns on byte enables" "no,yes"
bitfld.long 0x0 6. " BH ,Byte- or half-word width select" "half word,byte"
bitfld.long 0x0 5. " CP ,Chip-select polarity" "low,high"
hexmask.long 0x0 1.--4. 0x1 " WAIT ,Block transaction wait states"
bitfld.long 0x0 0. " SA ," "syn,asyn"
group 0x398++3
line.long 0x0 "BLOCK2,"
bitfld.long 0x0 7. "BE ,turns on byte enables" "no,yes"
bitfld.long 0x0 6. " BH ,Byte- or half-word width select" "half word,byte"
bitfld.long 0x0 5. " CP ,Chip-select polarity" "low,high"
hexmask.long 0x0 1.--4. 0x1 " WAIT ,Block transaction wait states"
bitfld.long 0x0 0. " SA ," "syn,asyn"
group 0x39C++3
line.long 0x0 "BLOCK3,"
bitfld.long 0x0 7. "BE ,turns on byte enables" "no,yes"
bitfld.long 0x0 6. " BH ,Byte- or half-word width select" "half word,byte"
bitfld.long 0x0 5. " CP ,Chip-select polarity" "low,high"
hexmask.long 0x0 1.--4. 0x1 " WAIT ,Block transaction wait states"
bitfld.long 0x0 0. " SA ," "syn,asyn"
group 0x3A0++3
line.long 0x0 "INT_SR,status register"
bitfld.long 0x0 0. "TOI ,Indicates a timeout interrupt occurred" "no,yes"
group 0x3A4++3
line.long 0x0 "INT_ADD,address"
bitfld.long 0x0 31. "B3 ,1-Timeout occurred for EBI3" "no,yes"
bitfld.long 0x0 30. " B2 ,1-Timeout occurred for EBI2" "no,yes"
bitfld.long 0x0 29. " B1 ,1-Timeout occurred for EBI1" "no,yes"
bitfld.long 0x0 28. " B0 ,1-Timeout occurred for EBI0" "no,yes"
hexmask.long 0x0 0.--24. 0x1 " ADDRESS ,The EBI address at which a timeout occurred"
tree.end
tree "SDRAM Interface Registers"
group 0x400++3
line.long 0x0 "TIMING1,"
bitfld.long 0x0 13.--15. "RCD ,Active to read or write delay" "res,1clock,2clock,3clock,4clock,res,res,res"
bitfld.long 0x0 9.--12. " RAS ,Active to pre-charge command" "res,1clock,2clock,3clock,4clock,5clock,6clock,7clock,8clock,?..."
bitfld.long 0x0 6.--8. " RRD ,Active bank A" "res,1clock,2clock,3clock,4clock,res,res,res"
bitfld.long 0x0 3.--5. " RP ,Pre-charge command period" "res,1clock,2clock,3clock,4clock,res,res,res"
bitfld.long 0x0 0.--2. " WR ,Write recovery time" "res,1clock,2clock,3clock,res,res,res,res"
group 0x404++3
line.long 0x0 "TIMING2,"
bitfld.long 0x0 9.--11. "CL ,CAS latency" "res,res,res,2clock,2.5clock,3.clock,res,res"
bitfld.long 0x0 7.--8. " BL ,SDRAM burst length" "res,res,res,8-words"
bitfld.long 0x0 3.--6. " RFC ,SDRAM auto refresh period" "res,res,res,3clock,4clock,5clock,6clock,7clock,8clock,9clock,10clock,11clock,res,res,res,res"
group 0x408++3
line.long 0x0 "CONFIG,"
bitfld.long 0x0 15. "MT ,SDRAM memory type" "SDR,DDR"
group 0x40C++3
line.long 0x0 "REFRESH,"
hexmask.long 0x0 0.--15. 0x1 "RFSH ,SDRAM hidden refresh period"
group 0x410++3
line.long 0x0 "ADDR,"
bitfld.long 0x0 12.--15. "ROW ,Number of row address bits" "res,res,res,res,res,res,res,res,res,res,11,12,13,res,res,res"
bitfld.long 0x0 8.--11. " COL ,Number of col address bits" "res,res,res,res,res,res,res,8,9,10,11,12,res,res,res,res"
group 0x41C++3
line.long 0x0 "INIT,"
bitfld.long 0x0 15. "EN ,Enable SDRAM controller" "dis,ena"
bitfld.long 0x0 14. " PR ,Perform pre-charge all command" "no,yes"
bitfld.long 0x0 13. " LM ,Perform a load mode register command" "no,yes"
bitfld.long 0x0 12. " LEM ,Perform a load extended mode register" "no,yes"
bitfld.long 0x0 11. " RF ,Perform a refresh command" "no,yes"
bitfld.long 0x0 10. " BS ,performing LM, LEM, or pre-charge commands" "no,yes"
bitfld.long 0x0 9. " SR ,in self-refresh mode" "no,yes"
group 0x420++3
line.long 0x0 "MODE0,"
hexmask.long 0x0 0.--11. 0x1 "VAL ,Holds the value to be loaded"
group 0x424++3
line.long 0x0 "MODE1,"
hexmask.long 0x0 0.--11. 0x1 "VAL ,Holds the value to be loaded"
group 0x07C++3
line.long 0x0 "WIDTH,"
bitfld.long 0x0 1. "W ,Width of SDRAM port defaults to 1" "0,1"
bitfld.long 0x0 0. " LK ,1-Further writes have no effect" "0,1"
tree.end
tree "Watchdog Timer Registers"
group 0xA00++3
line.long 0x0 "CR,control register"
hexmask.long 0x0 4.--29. 0x1 "T ,TRIGGER"
bitfld.long 0x0 0. " LK ," "0,1"
group 0xA04++3
line.long 0x0 "COUNT,"
hexmask.long 0x0 0.--29. 0x1 "COUNT ,Current value of watchdog count register"
group 0xA08++3
line.long 0x0 "RELOAD,"
hexmask.long 0x0 0.--31. 0x1 "MAGIC ,Magic value to reset watchdog"
tree.end
tree "Interrupt Controller Registers"
group 0xC00++3
line.long 0x0 "MASK_SET,"
bitfld.long 0x0 16. "FC ,FAST comms JTAG port within configuration logic" "0,1"
bitfld.long 0x0 15. " CR ,COMMRX line from microprocessor " "0,1"
bitfld.long 0x0 14. " CT ,COMMTX line from microprocessor " "0,1"
bitfld.long 0x0 13. " AE ,AHB1-2 bridge error " "0,1"
bitfld.long 0x0 12. " PE ,Stripe-to-PLD bridge error" "0,1"
textline " "
bitfld.long 0x0 11. " EE ,EBI error " "0,1"
bitfld.long 0x0 10. " PS ,PLL status interrupt line" "0,1"
bitfld.long 0x0 9. " T1 ,Timer 1 interrupt line" "0,1"
bitfld.long 0x0 8. " T0 ,Timer 0 interrupt line" "0,1"
bitfld.long 0x0 7. " UA ,The interrupt line from the UART" "0,1"
textline " "
bitfld.long 0x0 6. " IP ,The external interrupt pin" "0,1"
bitfld.long 0x0 5. " P5 ,The INT_PLD[5] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 4. " P4 ,The INT_PLD[4] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 3. " P3 ,The INT_PLD[3] interrupt line from the PLD" "no,yes"
textline " "
bitfld.long 0x0 2. " P2 ,The INT_PLD[2] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 1. " P1 ,The INT_PLD[1] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 0. " P0 ,The INT_PLD[0] interrupt line from the PLD" "no,yes"
group 0xC04++3
line.long 0x0 "MASK_CL,"
bitfld.long 0x0 16. "FC ,FAST comms JTAG port within configuration logic" "0,1"
bitfld.long 0x0 15. " CR ,COMMRX line from microprocessor " "0,1"
bitfld.long 0x0 14. " CT ,COMMTX line from microprocessor " "0,1"
bitfld.long 0x0 13. " AE ,AHB1-2 bridge error " "0,1"
bitfld.long 0x0 12. " PE ,Stripe-to-PLD bridge error" "0,1"
textline " "
bitfld.long 0x0 11. " PS ,PLL status interrupt line" "0,1"
bitfld.long 0x0 9. " T1 ,Timer 1 interrupt line" "0,1"
bitfld.long 0x0 8. " T0 ,Timer 0 interrupt line" "0,1"
bitfld.long 0x0 7. " UA ,The interrupt line from the UART" "0,1"
textline " "
bitfld.long 0x0 6. " IP ,The external interrupt pin" "0,1"
bitfld.long 0x0 5. " P5 ,The INT_PLD[5] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 4. " P4 ,The INT_PLD[4] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 3. " P3 ,The INT_PLD[3] interrupt line from the PLD" "no,yes"
textline " "
bitfld.long 0x0 2. " P2 ,The INT_PLD[2] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 1. " P1 ,The INT_PLD[1] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 0. " P0 ,The INT_PLD[0] interrupt line from the PLD" "no,yes"
group 0xC08++3
line.long 0x0 "SOURCE,"
bitfld.long 0x0 16. "FC ,FAST comms JTAG port within configuration logic" "0,1"
bitfld.long 0x0 15. " CR ,COMMRX line from microprocessor " "0,1"
bitfld.long 0x0 14. " CT ,COMMTX line from microprocessor " "0,1"
bitfld.long 0x0 13. " AE ,AHB1-2 bridge error " "0,1"
bitfld.long 0x0 12. " PE ,Stripe-to-PLD bridge error" "0,1"
textline " "
bitfld.long 0x0 11. " EE ,EBI error " "0,1"
bitfld.long 0x0 10. " PS ,PLL status interrupt line" "0,1"
bitfld.long 0x0 9. " T1 ,Timer 1 interrupt line" "0,1"
bitfld.long 0x0 8. " T0 ,Timer 0 interrupt line" "0,1"
bitfld.long 0x0 7. " UA ,The interrupt line from the UART" "0,1"
textline " "
bitfld.long 0x0 6. " IP ,The external interrupt pin" "0,1"
bitfld.long 0x0 5. " P5 ,The INT_PLD[5] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 4. " P4 ,The INT_PLD[4] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 3. " P3 ,The INT_PLD[3] interrupt line from the PLD" "no,yes"
textline " "
bitfld.long 0x0 2. " P2 ,The INT_PLD[2] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 1. " P1 ,The INT_PLD[1] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 0. " P0 ,The INT_PLD[0] interrupt line from the PLD" "no,yes"
group 0xC0C++3
line.long 0x0 "REQUEST,"
bitfld.long 0x0 16. "FC ,FAST comms JTAG port within configuration logic" "0,1"
bitfld.long 0x0 15. " CR ,COMMRX line from microprocessor " "0,1"
bitfld.long 0x0 14. " CT ,COMMTX line from microprocessor " "0,1"
bitfld.long 0x0 13. " AE ,AHB1-2 bridge error " "0,1"
bitfld.long 0x0 12. " PE ,Stripe-to-PLD bridge error" "0,1"
textline " "
bitfld.long 0x0 11. " EE ,EBI error " "0,1"
bitfld.long 0x0 10. " PS ,PLL status interrupt line" "0,1"
bitfld.long 0x0 9. " T1 ,Timer 1 interrupt line" "0,1"
bitfld.long 0x0 8. " T0 ,Timer 0 interrupt line" "0,1"
bitfld.long 0x0 7. " UA ,The interrupt line from the UART" "0,1"
textline " "
bitfld.long 0x0 6. " IP ,The external interrupt pin" "0,1"
bitfld.long 0x0 5. " P5 ,The INT_PLD[5] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 4. " P4 ,The INT_PLD[4] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 3. " P3 ,The INT_PLD[3] interrupt line from the PLD" "no,yes"
textline " "
bitfld.long 0x0 2. " P2 ,The INT_PLD[2] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 1. " P1 ,The INT_PLD[1] interrupt line from the PLD" "no,yes"
bitfld.long 0x0 0. " P0 ,The INT_PLD[0] interrupt line from the PLD" "no,yes"
group 0xC10++3
line.long 0x0 "ID,"
hexmask.long 0x0 0.--5. 0x1 "ID ,The priority of the highest priority interrupt"
group 0xC14++3
line.long 0x0 "PLD,PLD interrupt priority"
hexmask.long 0x0 0.--5. 0x1 "PLD_PRI ,The interrupt priority being interrupted by the PLD"
group 0xC18++3
line.long 0x0 "MODE,"
bitfld.long 0x0 0.--1. "MODE ,Interrupt controller operating mode" "6prio,res,5prio,6"
group 0xC80++3
line.long 0x0 "PLD0,"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC84++3
line.long 0x0 "PLD1,"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC88++3
line.long 0x0 "PLD2,"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC8C++3
line.long 0x0 "PLD3,"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC90++3
line.long 0x0 "PLD4,"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC94++3
line.long 0x0 "PLD5,"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC98++3
line.long 0x0 "EXTPIN,INT_EXTPIN_N"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xC9C++3
line.long 0x0 "UART,UART interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCA0++3
line.long 0x0 "TIMER0,timer 0 interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCA4++3
line.long 0x0 "TIMER1,timer 1 interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCA8++3
line.long 0x0 "PLL,PLL status-error interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCAC++3
line.long 0x0 "EBI,EBI-error interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCB0++3
line.long 0x0 "STR-PLD,stripe-to-PLD bridgeerror interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCB4++3
line.long 0x0 "AHB1-2,AHB1-2 bridge-error interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCB8++3
line.long 0x0 "TX,Coprocessor TX space available interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCBC++3
line.long 0x0 "RX,Coprocessor RX data available interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
group 0xCC0++3
line.long 0x0 "FSTCMMS,Fastcomms RX data available interrupt"
bitfld.long.0x0 6. "FQ ,Generate an FIQ interrupt regardless of the priority" "0,1"
hexmask.long 0x0 0.--5. 0x1 " PRI ,Priority of this interrupt relative to others"
tree.end
tree "EmbeddedICE"
group ice:0x0--0x5 "Debug Control"
line.long 0x0 "DBGCTRL,Debug Control Register"
bitfld.long 0x0 0x3 "STEP ,Single Step" "disabled,enabled"
bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
line.long 0x4 "DBGSTAT,Debug Status Register"
bitfld.long 0x4 0x4 "ITBIT ,ITBIT" "0,1"
bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
line.long 0x8 "VECTOR,Vector Catch Register"
bitfld.long 0x8 0x7 "FIQ ,FIQ" "dis,ena"
bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
line.long 0x10 "COMCTRL,Debug Communication Control Register"
bitfld.long 0x10 28.--31. "VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
line.long 0x14 "COMDATA,Debug Communication Data Register"
group ice:0x8--0x0d "Watchpoint 0"
line.long 0x0 "AV,Address Value"
line.long 0x4 "AM,Address Mask"
line.long 0x8 "DV,Data Value"
line.long 0x0c "DM,Data Mask"
line.long 0x10 "CV,Control Value"
bitfld.long 0x10 0x8 "ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
line.long 0x14 "CM,Control Mask"
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
group ice:0x10--0x15 "Watchpoint 1"
line.long 0x0 "AV,Address Value"
line.long 0x4 "AM,Address Mask"
line.long 0x8 "DV,Data Value"
line.long 0x0c "DM,Data Mask"
line.long 0x10 "CV,Control Value"
bitfld.long 0x10 0x8 "ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
line.long 0x14 "CM,Control Mask"
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
tree.end
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