3568 lines
252 KiB
Plaintext
3568 lines
252 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: EM773 On-Chip Peripherals
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; @Props: Released
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; @Author: CIN
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; @Changelog: 2010-12-02 CIN
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: em773.user.manual.pdf Rev. 1 (2010-09-10)
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; @Core: Cortex-M0
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; @Chip: EM773
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perem773.per 12528 2020-11-12 13:57:39Z bschroefel $
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config 16. 8.
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base ad:0x0
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
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line.long 0x18 "INT6,Interrupt Priority Register"
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bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "System Control"
|
|
base ad:0x40048000
|
|
width 15.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "SYSMEMREMAP,System memory remap register"
|
|
bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,User Flash Mode"
|
|
line.long 0x04 "PRESETCTRL,Peripheral reset control register"
|
|
bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset"
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x04 0. " SSP0_RST_N ,SSPI0 reset control" "Reset,No reset"
|
|
else
|
|
bitfld.long 0x04 0. " SSP_RST_N ,SSP reset control" "Reset,No reset"
|
|
endif
|
|
line.long 0x08 "SYSPLLCTRL,System PLL control register"
|
|
bitfld.long 0x08 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
|
|
bitfld.long 0x08 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x0c++0x3
|
|
line.long 0x00 "SYSPLLSTAT,System PLL status register"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "USBPLLCTRL,USB PLL control register"
|
|
bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
|
|
bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "USBPLLSTAT,USB PLL status register"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
|
|
endif
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "SYSOSCCTRL,System oscillator control register"
|
|
bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled"
|
|
line.long 0x04 "WDTOSCCTRL,Watchdog oscillator control register"
|
|
bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency(Fclkana)" "Reserved,0.5 MHz,0.8 MHz,1.1 MHz,1.4 MHz,1.6 MHz,1.8 MHz,2.0 MHz,2.2 MHz,2.4 MHz,2.6 MHz,2.7 MHz,2.9 MHz,3.1 MHz,3.2 MHz,3.4 MHz"
|
|
bitfld.long 0x04 0.--4. " DIVSEL ,BSelect divider for Fclkana." "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
line.long 0x08 "IRCCTRL,Internal resonant crystal control register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TRIM ,Trim value"
|
|
sif cpu()=="EM773"
|
|
rgroup.long 0x30++0x3
|
|
else
|
|
group.long 0x30++0x3
|
|
endif
|
|
line.long 0x00 "SYSRSTSTAT,System reset status register"
|
|
eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset"
|
|
eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset"
|
|
eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset"
|
|
eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset"
|
|
group.long 0x40++0xf
|
|
line.long 0x00 "SYSPLLCLKSEL,System PLL clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,System oscillator,?..."
|
|
line.long 0x04 "SYSPLLUEN,System PLL clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
line.long 0x08 "USBPLLCLKSEL,USB PLL clock source select register"
|
|
bitfld.long 0x08 0.--1. " SEL ,USB PLL clock source" "Reserved,System oscillator,?..."
|
|
line.long 0x0c "USBPLLUEN,USB PLL clock source update enable register"
|
|
bitfld.long 0x0c 0. " ENA ,Enable USB PLL clock source update" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x70++0xb
|
|
line.long 0x00 "MAINCLKSEL,Main clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,Input clock to system PLL,WDT oscillator,System PLL clock out"
|
|
line.long 0x04 "MAINCLKUEN,Main clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled"
|
|
line.long 0x08 "SYSAHBCLKDIV,System AHB clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "SYSAHBCLKCTRL,System AHB clock control register"
|
|
bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 14. " USB_REG ,Clock for USB_REG enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x00 13. " MEC ,Clock for metrology engine enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 13. " ADC ,Clock for ADC enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 12. " UART ,Clock for UART enable" "Disabled,Enabled"
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x00 11. " SSP0 ,Clock for SSPI0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 11. " SSP ,Clock for SSP enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CT32B1 ,Clock for 32-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CT32B0 ,Clock for 32-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x00 8. " MEC ,Clock for metrology engine enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8. " CT16B1 ,Clock for 16-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " CT16B0 ,Clock for 16-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GPIO ,Clock for GPIO enable enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " I2C ,Clock for I2C enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FLASHARRAY ,Clock for flash array access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FLASHREG ,Clock for flash register interface enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RAM ,Clock for RAM enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SYS ,Clock for AHB to APB bridge enable" "Reserved,Enabled"
|
|
group.long 0x94++0x7
|
|
sif cpu()=="EM773"
|
|
line.long 0x00 "SSP0CLKDIV,SSPI0 clock divider register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,SSPI0_PCLK clock divider values"
|
|
else
|
|
line.long 0x00 "SSPCLKDIV,SSP clock divider register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,SSP_PCLK clock divider values"
|
|
endif
|
|
line.long 0x04 "UARTCLKDIV,UART clock divider register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIV ,UART_PCLK clock divider values"
|
|
sif cpu()!="EM773"
|
|
group.long 0xac++0x7
|
|
line.long 0x00 "TRACECLKDIV,TRACECLKDIV clock divider register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,ARM trace clock divider values"
|
|
line.long 0x04 "SYSTICK,SYSTICK clock divider register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIV ,SYSTICK clock divider values"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
group.long 0xc0++0xb
|
|
line.long 0x00 "USBCLKSEL,USB clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,USB clock source" "USB PLL out,Main clock,?..."
|
|
line.long 0x04 "USBCLKUEN,USB clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,USB clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "USBCLKDIV,USB clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,USB clock divider values"
|
|
endif
|
|
endif
|
|
group.long 0xd0++0xb
|
|
line.long 0x00 "WDTCLKSEL,WDT clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,WDT clock source" "IRC oscillator,Main clock,Watchdog oscillator,?..."
|
|
line.long 0x04 "WDTCLKUEN,WDT clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,WDT clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "WDTCLKDIV,WDT clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,WDT clock divider values"
|
|
group.long 0xe0++0xb
|
|
line.long 0x00 "CLKOUTCLKSEL,CLKOUT clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,System oscillator,Watchdog oscillator,Main clock"
|
|
line.long 0x04 "CLKOUTCLKUEN,CLKOUT clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "CLKOUTCLKDIV,CLKOUT clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "PIOPORCAP0,POR captured PIO status register 0"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 24. " CAPPIO2_0 ,Raw reset status input PIO2_0" "No reset,Reset"
|
|
textline " "
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="EM773")
|
|
bitfld.long 0x00 31. " CAPPIO2_7 ,Raw reset status input PIO2_7" "No reset,Reset"
|
|
bitfld.long 0x00 30. " CAPPIO2_6 ,Raw reset status input PIO2_6" "No reset,Reset"
|
|
bitfld.long 0x00 29. " CAPPIO2_5 ,Raw reset status input PIO2_5" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CAPPIO2_4 ,Raw reset status input PIO2_4" "No reset,Reset"
|
|
bitfld.long 0x00 27. " CAPPIO2_3 ,Raw reset status input PIO2_3" "No reset,Reset"
|
|
bitfld.long 0x00 26. " CAPPIO2_2 ,Raw reset status input PIO2_2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CAPPIO2_1 ,Raw reset status input PIO2_1" "No reset,Reset"
|
|
bitfld.long 0x00 24. " CAPPIO2_0 ,Raw reset status input PIO2_0" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " CAPPIO1_11 ,Raw reset status input PIO1_11" "No reset,Reset"
|
|
bitfld.long 0x00 22. " CAPPIO1_10 ,Raw reset status input PIO1_10" "No reset,Reset"
|
|
bitfld.long 0x00 21. " CAPPIO1_9 ,Raw reset status input PIO1_9" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CAPPIO1_8 ,Raw reset status input PIO1_8" "No reset,Reset"
|
|
bitfld.long 0x00 19. " CAPPIO1_7 ,Raw reset status input PIO1_7" "No reset,Reset"
|
|
bitfld.long 0x00 18. " CAPPIO1_6 ,Raw reset status input PIO1_6" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CAPPIO1_5 ,Raw reset status input PIO1_5" "No reset,Reset"
|
|
bitfld.long 0x00 16. " CAPPIO1_4 ,Raw reset status input PIO1_4" "No reset,Reset"
|
|
bitfld.long 0x00 15. " CAPPIO1_3 ,Raw reset status input PIO1_3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CAPPIO1_2 ,Raw reset status input PIO1_2" "No reset,Reset"
|
|
bitfld.long 0x00 13. " CAPPIO1_1 ,Raw reset status input PIO1_1" "No reset,Reset"
|
|
bitfld.long 0x00 12. " CAPPIO1_0 ,Raw reset status input PIO1_0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPPIO0_11 ,Raw reset status input PIO0_11" "No reset,Reset"
|
|
bitfld.long 0x00 10. " CAPPIO0_10 ,Raw reset status input PIO0_10" "No reset,Reset"
|
|
bitfld.long 0x00 9. " CAPPIO0_9 ,Raw reset status input PIO0_9" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAPPIO0_8 ,Raw reset status input PIO0_8" "No reset,Reset"
|
|
bitfld.long 0x00 7. " CAPPIO0_7 ,Raw reset status input PIO0_7" "No reset,Reset"
|
|
bitfld.long 0x00 6. " CAPPIO0_6 ,Raw reset status input PIO0_6" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPPIO0_5 ,Raw reset status input PIO0_5" "No reset,Reset"
|
|
bitfld.long 0x00 4. " CAPPIO0_4 ,Raw reset status input PIO0_4" "No reset,Reset"
|
|
bitfld.long 0x00 3. " CAPPIO0_3 ,Raw reset status input PIO0_3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CAPPIO0_2 ,Raw reset status input PIO0_2" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CAPPIO0_1 ,Raw reset status input PIO0_1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CAPPIO0_0 ,Raw reset status input PIO0_0" "No reset,Reset"
|
|
line.long 0x04 "PIOPORCAP1,POR captured PIO status register 1"
|
|
sif (cpu()=="LPC1311")
|
|
bitfld.long 0x04 9. " CAPPIO3_5 ,Raw reset status input PIO2_5" "No reset,Reset"
|
|
bitfld.long 0x04 8. " CAPPIO3_4 ,Raw reset status input PIO2_4" "No reset,Reset"
|
|
bitfld.long 0x04 6. " CAPPIO3_2 ,Raw reset status input PIO2_2" "No reset,Reset"
|
|
elif (cpu()=="LPC1313"||cpu()=="EM773")
|
|
bitfld.long 0x04 9. " CAPPIO3_5 ,Raw reset status input PIO2_5" "No reset,Reset"
|
|
bitfld.long 0x04 8. " CAPPIO3_4 ,Raw reset status input PIO2_4" "No reset,Reset"
|
|
bitfld.long 0x04 7. " CAPPIO3_3 ,Raw reset status input PIO2_3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 6. " CAPPIO3_2 ,Raw reset status input PIO2_2" "No reset,Reset"
|
|
bitfld.long 0x04 5. " CAPPIO3_1 ,Raw reset status input PIO2_1" "No reset,Reset"
|
|
bitfld.long 0x04 4. " CAPPIO3_0 ,Raw reset status input PIO2_0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CAPPIO2_11 ,Raw reset status input PIO2_11" "No reset,Reset"
|
|
bitfld.long 0x04 2. " CAPPIO2_10 ,Raw reset status input PIO2_10" "No reset,Reset"
|
|
bitfld.long 0x04 1. " CAPPIO2_9 ,Raw reset status input PIO2_9" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CAPPIO2_8 ,Raw reset status input PIO2_8" "No reset,Reset"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x04 6. " CAPPIO3_2 ,Raw reset status input PIO2_2" "No reset,Reset"
|
|
elif (cpu()=="LPC1343")
|
|
bitfld.long 0x04 7. " CAPPIO3_3 ,Raw reset status input PIO2_3" "No reset,Reset"
|
|
bitfld.long 0x04 6. " CAPPIO3_2 ,Raw reset status input PIO2_2" "No reset,Reset"
|
|
bitfld.long 0x04 5. " CAPPIO3_1 ,Raw reset status input PIO2_1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAPPIO3_0 ,Raw reset status input PIO2_0" "No reset,Reset"
|
|
bitfld.long 0x04 3. " CAPPIO2_11 ,Raw reset status input PIO2_11" "No reset,Reset"
|
|
bitfld.long 0x04 2. " CAPPIO2_10 ,Raw reset status input PIO2_10" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CAPPIO2_9 ,Raw reset status input PIO2_9" "No reset,Reset"
|
|
bitfld.long 0x04 0. " CAPPIO2_8 ,Raw reset status input PIO2_8" "No reset,Reset"
|
|
endif
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "BODCTRL,BOD control register"
|
|
bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled"
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" "1.65V/1.80V,2.22V/2.35V,2.52V/2.66V,2.80V/2.90V"
|
|
bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level (assertion/de-assertion)" "1.46V/1.63V,2.06/2.15,2.35/2.43,2.63/2.71"
|
|
else
|
|
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" "1.69V/1.84V,2.29V/2.44V,2.59V/2.74V,2.87V/2.98V"
|
|
bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level (assertion/de-assertion)" "1.49V/1.64V,?..."
|
|
endif
|
|
group.long 0x158++0x3
|
|
line.long 0x00 "SYSTCKCAL,System tick timer calibration register"
|
|
hexmask.long 0x00 0.--25. 1. " CAL ,System tick timer calibration value"
|
|
group.long 0x200++0x7
|
|
line.long 0x00 "STARTAPRP0,Start logic edge control register 0"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 24. " APRPIO2_0 ,Edge select for start logic input PIO2_0" "Falling,Rising"
|
|
textline " "
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 31. " APRPIO2_7 ,Edge select for start logic input PIO2_7" "Falling,Rising"
|
|
bitfld.long 0x00 30. " APRPIO2_6 ,Edge select for start logic input PIO2_6" "Falling,Rising"
|
|
bitfld.long 0x00 29. " APRPIO2_5 ,Edge select for start logic input PIO2_5" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 28. " APRPIO2_4 ,Edge select for start logic input PIO2_4" "Falling,Rising"
|
|
bitfld.long 0x00 27. " APRPIO2_3 ,Edge select for start logic input PIO2_3" "Falling,Rising"
|
|
bitfld.long 0x00 26. " APRPIO2_2 ,Edge select for start logic input PIO2_2" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 25. " APRPIO2_1 ,Edge select for start logic input PIO2_1" "Falling,Rising"
|
|
bitfld.long 0x00 24. " APRPIO2_0 ,Edge select for start logic input PIO2_0" "Falling,Rising"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="EM773"
|
|
bitfld.long 0x00 23. " APRPIO2_11 ,Edge select for start logic input PIO1_11" "Falling,Rising"
|
|
bitfld.long 0x00 22. " APRPIO1_10 ,Edge select for start logic input PIO1_10" "Falling,Rising"
|
|
bitfld.long 0x00 21. " APRPIO1_9 ,Edge select for start logic input PIO1_9" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 20. " APRPIO1_8 ,Edge select for start logic input PIO1_8" "Falling,Rising"
|
|
bitfld.long 0x00 19. " APRPIO1_7 ,Edge select for start logic input PIO1_7" "Falling,Rising"
|
|
bitfld.long 0x00 18. " APRPIO1_6 ,Edge select for start logic input PIO1_6" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 17. " APRPIO1_5 ,Edge select for start logic input PIO1_5" "Falling,Rising"
|
|
bitfld.long 0x00 16. " APRPIO1_4 ,Edge select for start logic input PIO1_4" "Falling,Rising"
|
|
bitfld.long 0x00 15. " APRPIO1_3 ,Edge select for start logic input PIO1_3" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 14. " APRPIO1_2 ,Edge select for start logic input PIO1_2" "Falling,Rising"
|
|
bitfld.long 0x00 13. " APRPIO1_1 ,Edge select for start logic input PIO1_1" "Falling,Rising"
|
|
bitfld.long 0x00 12. " APRPIO1_0 ,Edge select for start logic input PIO1_0" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " APRPIO1_11 ,Edge select for start logic input PIO0_11" "Falling,Rising"
|
|
bitfld.long 0x00 10. " APRPIO0_10 ,Edge select for start logic input PIO0_10" "Falling,Rising"
|
|
bitfld.long 0x00 9. " APRPIO0_9 ,Edge select for start logic input PIO0_9" "Falling,Rising"
|
|
else
|
|
bitfld.long 0x00 10. " APRPIO0_10 ,Edge select for start logic input PIO0_10" "Falling,Rising"
|
|
bitfld.long 0x00 9. " APRPIO0_9 ,Edge select for start logic input PIO0_9" "Falling,Rising"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " APRPIO0_8 ,Edge select for start logic input PIO0_8" "Falling,Rising"
|
|
bitfld.long 0x00 7. " APRPIO0_7 ,Edge select for start logic input PIO0_7" "Falling,Rising"
|
|
bitfld.long 0x00 6. " APRPIO0_6 ,Edge select for start logic input PIO0_6" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 5. " APRPIO0_5 ,Edge select for start logic input PIO0_5" "Falling,Rising"
|
|
bitfld.long 0x00 4. " APRPIO0_4 ,Edge select for start logic input PIO0_4 " "Falling,Rising"
|
|
bitfld.long 0x00 3. " APRPIO0_3 ,Edge select for start logic input PIO0_3" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 2. " APRPIO0_2 ,Edge select for start logic input PIO0_2" "Falling,Rising"
|
|
bitfld.long 0x00 1. " APRPIO0_1 ,Edge select for start logic input PIO0_1" "Falling,Rising"
|
|
bitfld.long 0x00 0. " APRPIO0_0 ,Edge select for start logic input PIO0_0" "Falling,Rising"
|
|
line.long 0x04 "STARTERP0,Start logic signal enable register 0"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x04 24. " ERPIO2_0 ,Start signal for start logic input PIO2_0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x04 31. " ERPIO2_7 ,Start signal for start logic input PIO2_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ERPIO2_6 ,Start signal for start logic input PIO2_6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " ERPIO2_5 ,Start signal for start logic input PIO2_5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " ERPIO2_4 ,Start signal for start logic input PIO2_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " ERPIO2_3 ,Start signal for start logic input PIO2_3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " ERPIO2_2 ,Start signal for start logic input PIO2_2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ERPIO2_1 ,Start signal for start logic input PIO2_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " ERPIO2_0 ,Start signal for start logic input PIO2_0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="EM773"
|
|
bitfld.long 0x04 23. " ERPIO2_11 ,Start signal for start logic input PIO1_11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ERPIO1_10 ,Start signal for start logic input PIO1_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " ERPIO1_9 ,Start signal for start logic input PIO1_9 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ERPIO1_8 ,Start signal for start logic input PIO1_8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " ERPIO1_7 ,Start signal for start logic input PIO1_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ERPIO1_6 ,Start signal for start logic input PIO1_6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " ERPIO1_5 ,Start signal for start logic input PIO1_5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " ERPIO1_4 ,Start signal for start logic input PIO1_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " ERPIO1_3 ,Start signal for start logic input PIO1_3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " ERPIO1_2 ,Start signal for start logic input PIO1_2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " ERPIO1_1 ,Start signal for start logic input PIO1_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " ERPIO1_0 ,Start signal for start logic input PIO1_0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ERPIO1_11 ,Start signal for start logic input PIO0_11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ERPIO0_10 ,Start signal for start logic input PIO0_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ERPIO0_9 ,Start signal for start logic input PIO0_9 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 10. " ERPIO0_10 ,Start signal for start logic input PIO0_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ERPIO0_9 ,Start signal for start logic input PIO0_9 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 8. " ERPIO0_8 ,Start signal for start logic input PIO0_8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " ERPIO0_7 ,Start signal for start logic input PIO0_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ERPIO0_6 ,Start signal for start logic input PIO0_6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERPIO0_5 ,Start signal for start logic input PIO0_5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ERPIO0_4 ,Start signal for start logic input PIO0_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ERPIO0_3 ,Start signal for start logic input PIO0_3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ERPIO0_2 ,Start signal for start logic input PIO0_2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ERPIO0_1 ,Start signal for start logic input PIO0_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ERPIO0_0 ,Start signal for start logic input PIO0_0 enable" "Disabled,Enabled"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x00 "STARTRSRP0CLR,Start logic reset register 0"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 24. " RSRPIO2_0 ,Start signal reset for start logic input PIO2_0" "-,Reset"
|
|
textline " "
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 31. " RSRPIO2_7 ,Start signal reset for start logic input PIO2_7" "-,Reset"
|
|
bitfld.long 0x00 30. " RSRPIO2_6 ,Start signal reset for start logic input PIO2_6" "-,Reset"
|
|
bitfld.long 0x00 29. " RSRPIO2_5 ,Start signal reset for start logic input PIO2_5" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RSRPIO2_4 ,Start signal reset for start logic input PIO2_4" "-,Reset"
|
|
bitfld.long 0x00 27. " RSRPIO2_3 ,Start signal reset for start logic input PIO2_3" "-,Reset"
|
|
bitfld.long 0x00 26. " RSRPIO2_2 ,Start signal reset for start logic input PIO2_2" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSRPIO2_1 ,Start signal reset for start logic input PIO2_1" "-,Reset"
|
|
bitfld.long 0x00 24. " RSRPIO2_0 ,Start signal reset for start logic input PIO2_0" "-,Reset"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="EM773"
|
|
bitfld.long 0x00 23. " RSRPIO2_11 ,Start signal reset for start logic input PIO1_11" "-,Reset"
|
|
bitfld.long 0x00 22. " RSRPIO1_10 ,Start signal reset for start logic input PIO1_10" "-,Reset"
|
|
bitfld.long 0x00 21. " RSRPIO1_9 ,Start signal reset for start logic input PIO1_9" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RSRPIO1_8 ,Start signal reset for start logic input PIO1_8" "-,Reset"
|
|
bitfld.long 0x00 19. " RSRPIO1_7 ,Start signal reset for start logic input PIO1_7" "-,Reset"
|
|
bitfld.long 0x00 18. " RSRPIO1_6 ,Start signal reset for start logic input PIO1_6" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RSRPIO1_5 ,Start signal reset for start logic input PIO1_5" "-,Reset"
|
|
bitfld.long 0x00 16. " RSRPIO1_4 ,Start signal reset for start logic input PIO1_4" "-,Reset"
|
|
bitfld.long 0x00 15. " RSRPIO1_3 ,Start signal reset for start logic input PIO1_3" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RSRPIO1_2 ,Start signal reset for start logic input PIO1_2" "-,Reset"
|
|
bitfld.long 0x00 13. " RSRPIO1_1 ,Start signal reset for start logic input PIO1_1" "-,Reset"
|
|
bitfld.long 0x00 12. " RSRPIO1_0 ,Start signal reset for start logic input PIO1_0" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RSRPIO1_11 ,Start signal reset for start logic input PIO0_11" "-,Reset"
|
|
bitfld.long 0x00 10. " RSRPIO0_10 ,Start signal reset for start logic input PIO0_10" "-,Reset"
|
|
bitfld.long 0x00 9. " RSRPIO0_9 ,Start signal reset for start logic input PIO0_9" "-,Reset"
|
|
else
|
|
bitfld.long 0x00 10. " RSRPIO0_10 ,Start signal reset for start logic input PIO0_10" "-,Reset"
|
|
bitfld.long 0x00 9. " RSRPIO0_9 ,Start signal reset for start logic input PIO0_9" "-,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSRPIO0_8 ,Start signal reset for start logic input PIO0_8" "-,Reset"
|
|
bitfld.long 0x00 7. " RSRPIO0_7 ,Start signal reset for start logic input PIO0_7" "-,Reset"
|
|
bitfld.long 0x00 6. " RSRPIO0_6 ,Start signal reset for start logic input PIO0_6" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RSRPIO0_5 ,Start signal reset for start logic input PIO0_5" "-,Reset"
|
|
bitfld.long 0x00 4. " RSRPIO0_4 ,Start signal reset for start logic input PIO0_4" "-,Reset"
|
|
bitfld.long 0x00 3. " RSRPIO0_3 ,Start signal reset for start logic input PIO0_3" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSRPIO0_2 ,Start signal reset for start logic input PIO0_2" "-,Reset"
|
|
bitfld.long 0x00 1. " RSRPIO0_1 ,Start signal reset for start logic input PIO0_1" "-,Reset"
|
|
bitfld.long 0x00 0. " RSRPIO0_0 ,Start signal reset for start logic input PIO0_0" "-,Reset"
|
|
rgroup.long 0x20c++0x3
|
|
line.long 0x00 "STARTSRP0,Start logic status register 0"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 24. " SRPIO2_0 ,Start signal status for start logic input PIO2_0" "Not started,Started"
|
|
textline " "
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 31. " SRPIO2_7 ,Start signal status for start logic input PIO2_7" "Not started,Started"
|
|
bitfld.long 0x00 30. " SRPIO2_6 ,Start signal status for start logic input PIO2_6" "Not started,Started"
|
|
bitfld.long 0x00 29. " SRPIO2_5 ,Start signal status for start logic input PIO2_5" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SRPIO2_4 ,Start signal status for start logic input PIO2_4" "Not started,Started"
|
|
bitfld.long 0x00 27. " SRPIO2_3 ,Start signal status for start logic input PIO2_3" "Not started,Started"
|
|
bitfld.long 0x00 26. " SRPIO2_2 ,Start signal status for start logic input PIO2_2" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SRPIO2_1 ,Start signal status for start logic input PIO2_1" "Not started,Started"
|
|
bitfld.long 0x00 24. " SRPIO2_0 ,Start signal status for start logic input PIO2_0" "Not started,Started"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="EM773"
|
|
bitfld.long 0x00 23. " SRPIO2_11 ,Start signal status for start logic input PIO1_11" "Not started,Started"
|
|
bitfld.long 0x00 22. " SRPIO1_10 ,Start signal status for start logic input PIO1_10" "Not started,Started"
|
|
bitfld.long 0x00 21. " SRPIO1_9 ,Start signal status for start logic input PIO1_9" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRPIO1_8 ,Start signal status for start logic input PIO1_8" "Not started,Started"
|
|
bitfld.long 0x00 19. " SRPIO1_7 ,Start signal status for start logic input PIO1_7" "Not started,Started"
|
|
bitfld.long 0x00 18. " SRPIO1_6 ,Start signal status for start logic input PIO1_6" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SRPIO1_5 ,Start signal status for start logic input PIO1_5" "Not started,Started"
|
|
bitfld.long 0x00 16. " SRPIO1_4 ,Start signal status for start logic input PIO1_4" "Not started,Started"
|
|
bitfld.long 0x00 15. " SRPIO1_3 ,Start signal status for start logic input PIO1_3" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SRPIO1_2 ,Start signal status for start logic input PIO1_2" "Not started,Started"
|
|
bitfld.long 0x00 13. " SRPIO1_1 ,Start signal status for start logic input PIO1_1" "Not started,Started"
|
|
bitfld.long 0x00 12. " SRPIO1_0 ,Start signal status for start logic input PIO1_0" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SRPIO1_11 ,Start signal status for start logic input PIO0_11" "Not started,Started"
|
|
bitfld.long 0x00 10. " SRPIO0_10 ,Start signal status for start logic input PIO0_10" "Not started,Started"
|
|
bitfld.long 0x00 9. " SRPIO0_9 ,Start signal status for start logic input PIO0_9" "Not started,Started"
|
|
else
|
|
bitfld.long 0x00 10. " SRPIO0_10 ,Start signal status for start logic input PIO0_10" "Not started,Started"
|
|
bitfld.long 0x00 9. " SRPIO0_9 ,Start signal status for start logic input PIO0_9" "Not started,Started"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SRPIO0_8 ,Start signal status for start logic input PIO0_8" "Not started,Started"
|
|
bitfld.long 0x00 7. " SRPIO0_7 ,Start signal status for start logic input PIO0_7" "Not started,Started"
|
|
bitfld.long 0x00 6. " SRPIO0_6 ,Start signal status for start logic input PIO0_6" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRPIO0_5 ,Start signal status for start logic input PIO0_5" "Not started,Started"
|
|
bitfld.long 0x00 4. " SRPIO0_4 ,Start signal status for start logic input PIO0_4" "Not started,Started"
|
|
bitfld.long 0x00 3. " SRPIO0_3 ,Start signal status for start logic input PIO0_3" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRPIO0_2 ,Start signal status for start logic input PIO0_2" "Not started,Started"
|
|
bitfld.long 0x00 1. " SRPIO0_1 ,Start signal status for start logic input PIO0_1" "Not started,Started"
|
|
bitfld.long 0x00 0. " SRPIO0_0 ,Start signal status for start logic input PIO0_0" "Not started,Started"
|
|
sif cpu()!="EM773"
|
|
group.long 0x210++0x7
|
|
line.long 0x00 "STARTAPRP1,Start logic edge control register 1"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 6. " APRPIO3_2 ,Edge select for start logic input PIO2_2" "Falling,Rising"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 7. " APRPIO3_3 ,Edge select for start logic input PIO2_3" "Falling,Rising"
|
|
bitfld.long 0x00 6. " APRPIO3_2 ,Edge select for start logic input PIO2_2" "Falling,Rising"
|
|
bitfld.long 0x00 5. " APRPIO3_1 ,Edge select for start logic input PIO2_1" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " APRPIO3_0 ,Edge select for start logic input PIO2_0" "Falling,Rising"
|
|
bitfld.long 0x00 3. " APRPIO2_11 ,Edge select for start logic input PIO2_11" "Falling,Rising"
|
|
bitfld.long 0x00 2. " APRPIO2_10 ,Edge select for start logic input PIO2_10" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APRPIO2_9 ,Edge select for start logic input PIO2_9" "Falling,Rising"
|
|
bitfld.long 0x00 0. " APRPIO2_8 ,Edge select for start logic input PIO2_8" "Falling,Rising"
|
|
endif
|
|
line.long 0x04 "STARTERP1,Start logic signal enable register 1"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x04 6. " ERPIO3_2 ,Start signal for start logic input PIO2_2" "Disabled,Enabled"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x04 7. " ERPIO3_3 ,Start signal for start logic input PIO2_3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ERPIO3_2 ,Start signal for start logic input PIO2_2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ERPIO3_1 ,Start signal for start logic input PIO2_1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ERPIO3_0 ,Start signal for start logic input PIO2_0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ERPIO2_11 ,Start signal for start logic input PIO2_11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ERPIO2_10 ,Start signal for start logic input PIO2_10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ERPIO2_9 ,Start signal for start logic input PIO2_9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ERPIO2_8 ,Start signal for start logic input PIO2_8 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x218++0x3
|
|
line.long 0x00 "STARTRSRP1CLR,Start logic reset register 1"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 6. " RSRPIO3_2 ,Start signal reset for start logic input PIO2_2" "-,Reset"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 7. " RSRPIO3_3 ,Start signal reset for start logic input PIO2_3" "-,Reset"
|
|
bitfld.long 0x00 6. " RSRPIO3_2 ,Start signal reset for start logic input PIO2_2" "-,Reset"
|
|
bitfld.long 0x00 5. " RSRPIO3_1 ,Start signal reset for start logic input PIO2_1" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RSRPIO3_0 ,Start signal reset for start logic input PIO2_0" "-,Reset"
|
|
bitfld.long 0x00 3. " RSRPIO2_11 ,Start signal reset for start logic input PIO2_11" "-,Reset"
|
|
bitfld.long 0x00 2. " RSRPIO2_10 ,Start signal reset for start logic input PIO2_10" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RSRPIO2_9 ,Start signal reset for start logic input PIO2_9" "-,Reset"
|
|
bitfld.long 0x00 0. " RSRPIO2_8 ,Start signal reset for start logic input PIO2_8" "-,Reset"
|
|
endif
|
|
rgroup.long 0x21c++0x3
|
|
line.long 0x00 "STARTSRP1,Start logic signal status register 1"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342")
|
|
bitfld.long 0x00 6. " SRPIO3_2 ,Start signal status for start logic input PIO2_2" "Not started,Started"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 7. " SRPIO3_3 ,Start signal status for start logic input PIO2_3 enable" "Not started,Started"
|
|
bitfld.long 0x00 6. " SRPIO3_2 ,Start signal status for start logic input PIO2_2 enable" "Not started,Started"
|
|
bitfld.long 0x00 5. " SRPIO3_1 ,Start signal status for start logic input PIO2_1 enable" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRPIO3_0 ,Start signal status for start logic input PIO2_0 enable" "Not started,Started"
|
|
bitfld.long 0x00 3. " SRPIO2_11 ,Start signal status for start logic input PIO2_11 enable" "Not started,Started"
|
|
bitfld.long 0x00 2. " SRPIO2_10 ,Start signal status for start logic input PIO2_10 enable" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRPIO2_9 ,Start signal status for start logic input PIO2_9 enable" "Not started,Started"
|
|
bitfld.long 0x00 0. " SRPIO2_8 ,Start signal status for start logic input PIO2_8 enable" "Not started,Started"
|
|
endif
|
|
endif
|
|
group.long 0x230++0xb
|
|
line.long 0x00 "PDSLEEPCFG,Deep-sleep configuration register"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
bitfld.long 0x00 10. " USBPAD_PD ,USB pad power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 8. " USBPLL_PD ,USB PLL power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 7. " SYSPLL_PD ,System PLL power-down control" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 5. " SYSOSC_PD ,System oscillator power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 4. " ADC_PD ,ADC power-down control" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 2. " FLASH_PD ,Flash power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 1. " IRC_PD ,IRC oscillator power-down control" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRCOUT_PD ,IRC oscillator output power-down control" "Powered,Powered down"
|
|
elif (cpu()=="LPC1311"||cpu()=="LPC1313")
|
|
bitfld.long 0x00 7. " SYSPLL_PD ,System PLL power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 5. " SYSOSC_PD ,System oscillator power-down control" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADC_PD ,ADC power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 2. " FLASH_PD ,Flash power-down control" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRC_PD ,IRC oscillator power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 0. " IRCOUT_PD ,IRC oscillator output power-down control" "Powered,Powered down"
|
|
elif cpu()=="EM773"
|
|
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down"
|
|
endif
|
|
line.long 0x04 "PDAWAKECFG,Wake-up configuration register"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
bitfld.long 0x04 10. " USBPAD_PD ,USB pad wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 8. " USBPLL_PD ,USB PLL wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 1. " IRC_PD ,IRC oscillator wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down"
|
|
elif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="EM773")
|
|
bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x04 4. " METENG_PD ,Metrology Engine wake-up configuration" "Powered,Powered down"
|
|
else
|
|
bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down"
|
|
endif
|
|
bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IRC_PD ,IRC oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down"
|
|
endif
|
|
line.long 0x08 "PDRUNCFG,Power-down configuration register"
|
|
sif (cpu()=="LPC1342"||cpu()=="LPC1343")
|
|
bitfld.long 0x08 10. " USBPAD_PD ,USB pad power-down configuration" "Powered,Powered down"
|
|
bitfld.long 0x08 8. " USBPLL_PD ,USB PLL power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 5. " SYSOSC_PD ,System oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down"
|
|
elif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="EM773")
|
|
bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 5. " SYSOSC_PD ,System oscillator power-down" "Powered,Powered down"
|
|
textline " "
|
|
sif cpu()=="EM773"
|
|
bitfld.long 0x08 4. " METENG_PD ,Metrology Engine power-down" "Powered,Powered down"
|
|
else
|
|
bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down"
|
|
endif
|
|
bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down"
|
|
endif
|
|
rgroup.long 0x3f4++0x3
|
|
line.long 0x00 "DEVICE_ID,Device ID register"
|
|
hexmask.long 0x00 0.--31. 1. " DEVICEID ,Device ID for LPC13xx parts"
|
|
width 0xB
|
|
tree.end
|
|
tree "Power Management Unit (PMU)"
|
|
base ad:0x40038000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCON,Power Control Register"
|
|
eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not entered,Entered"
|
|
sif (cpu()=="EM773"||cpu()=="LPC11D14"||cpu()=="LPC1102LV"||cpu()=="LPC1102"||cpuis("LPC1111*")||cpu()=="LPC1110"||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC1124"||cpu()=="LPC1125"||cpu()=="LPC1126"||cpu()=="LPC1127"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U3*")||cpuis("LPC11U6*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not entered,Entered"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
bitfld.long 0x00 3. " NODPD ,No Deep power-down mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep-power down,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 1. " DPDEN ,Deep power-down mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPREG0,General Purpose Register 0"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPREG2,General Purpose Register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG3,General Purpose Register 3"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DPDCTRL,Deep Power Down Control Register"
|
|
sif (cpuis("LPC82*"))
|
|
hexmask.long 0x00 6.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKECLKPAD_DISABLE ,Disable the external clock input for the self-wake-up time" "No,Yes"
|
|
bitfld.long 0x00 4. " WAKEUPCLKHYS ,External clock input for the self-wake-up timer WKTCLKIN hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
hexmask.long 0x00 4.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " LPOSCDPDEN ,Deep power-down mode low-power oscillator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LPOSCEN ,10 kHz self wake-up timer low-power oscillator use enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DPDCTRL,Deep Power Down Control Register"
|
|
sif (cpuis("LPC84*"))
|
|
bitfld.long 0x00 7. " RESET_DISABLE ,RESET pin disable" "No,Yes"
|
|
bitfld.long 0x00 6. " RESETHYS ,RESET pin hysteresis enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
bitfld.long 0x00 5. " WAKECLKPAD_DISABLE ,Disable the external clock input for the self-wake-up time" "No,Yes"
|
|
bitfld.long 0x00 4. " WAKEUPCLKHYS ,External clock input for the self-wake-up timer WKTCLKIN hysteresis enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " LPOSCDPDEN ,Deep power-down mode low-power oscillator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LPOSCEN ,10 kHz self wake-up timer low-power oscillator use enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("LPC11U6*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register 4"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
elif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register 4"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYSCFG,System Configuration Register"
|
|
bitfld.long 0x00 11.--14. " RTCCLK ,RTC clock source select" "1 Hz clock,delayed 1 Hz clock,,,RTC PCLK,RTC PCLK,RTC PCLK,RTC PCLK,,,1 kHz clock,1 kHz clock,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I/O configuration"
|
|
base ad:0x40044000
|
|
width 25.
|
|
group.long 0x08++0xf
|
|
line.long 0x00 "IOCON_PIO2_0,PIO2_0 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO2_0,/DTR,SSEL1,?..."
|
|
line.long 0x04 "IOCON_nRESET_PIO0_0,PIO0_0 configuration register"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function selection" "/RESET,PIO0_0,?..."
|
|
line.long 0x08 "IOCON_PIO0_1,PIO0_1 configuration register"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Pin function selection" "PIO0_1,CLKOUT,CT32B0_MAT2,?..."
|
|
line.long 0x0c "IOCON_PIO1_8,PIO1_8 configuration register"
|
|
bitfld.long 0x0c 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x0c 0.--2. " FUNC ,Pin function selection" "PIO1_8,?..."
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "IOCON_PIO0_2,PIO0_2 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_2,SSEL0,CT16B0_CAP0,?..."
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "IOCON_PIO0_3,PIO0_3 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_3,?..."
|
|
if ((per.l((ad:0x40044000+0x30))&0x7)==0x0)
|
|
; IOCON_PIO0_4[FUNC] = 000
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "IOCON_PIO0_4,PIO0_4 configuration register"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode" "Standard mode,Standard I/O functionality,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_4,I2C SCL,?..."
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "IOCON_PIO0_4,PIO0_4 configuration register"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode" "Standard mode,Standard I/O functionality,Fast-mode Plus I2C,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_4,I2C SCL,?..."
|
|
endif
|
|
if ((per.l((ad:0x40044000+0x34))&0x7)==0x0)
|
|
; IOCON_PIO0_5[FUNC] = 000
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "IOCON_PIO0_5,PIO0_5 configuration register"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode" "Standard mode,Standard I/O functionality,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_5,I2C SDA,?..."
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "IOCON_PIO0_5,PIO0_5 configuration register"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode" "Standard mode,Standard I/O functionality,Fast-mode Plus I2C,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_5,I2C SDA,?..."
|
|
endif
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "IOCON_PIO1_9,PIO1_9 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO1_9,?..."
|
|
line.long 0x04 "IOCON_PIO3_4,PIO3_4 configuration register"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function selection" "PIO3_4,?..."
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "IOCON_PIO3_5,PIO3_5 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO3_5,?..."
|
|
if ((per.l((ad:0x40044000+0xB0))&0x3)==0x2)
|
|
; IOCON_SCK_LOC[SCKLOC] = 10
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "IOCON_PIO0_6,PIO0_6 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_6,Reserved,SCK,?..."
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "IOCON_PIO0_6,PIO0_6 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_6,?..."
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "IOCON_PIO0_7,PIO0_7 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_7,/CTS,?..."
|
|
group.long 0x60++0x7
|
|
line.long 0x00 "IOCON_PIO0_8,PIO0_8 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "PIO0_8,MISO0,CT16B0_MAT0,?..."
|
|
line.long 0x04 "IOCON_PIO0_9,PIO0_9 configuration register"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function selection" "PIO0_9,MOSI0,CT16B0_MAT1,?..."
|
|
if ((per.l((ad:0x40044000+0xB0))&0x3)==0x0)
|
|
; IOCON_SCK_LOC[SCKLOC] = 00
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "IOCON_SWCLK_PIO0_10,PIO0_10 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "SWCLK,PIO0_10,SCK0,CT16B0_MAT2,?..."
|
|
else
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "IOCON_SWCLK_PIO0_10,PIO0_10 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "SWCLK,PIO0_10,Reserved,CT16B0_MAT2,?..."
|
|
endif
|
|
group.long 0x7C++0x7
|
|
line.long 0x00 "IOCON_R_PIO1_1,PIO1_1 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "Reserved,PIO1_1,Reserved,CT32B1_MAT0,?..."
|
|
line.long 0x04 "IOCON_R_PIO1_2,PIO1_2 configuration register"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function selection" "Reserved,PIO1_2,Reserved,CT32B1_MAT1,?..."
|
|
group.long 0x90++0x1B
|
|
line.long 0x00 "IOCON_SWDIO_PIO1_3,PIO1_3 configuration register"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function selection" "SWDIO,PIO1_3,Reserved,CT32B1_MAT2,?..."
|
|
line.long 0x04 "IOCON_PIO1_4,PIO1_4 configuration register"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function selection" "PIO1_4,Reserved,CT32B1_MAT3,?..."
|
|
line.long 0x08 "IOCON_PIO1_11,PIO1_11 configuration register"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Pin function selection" "PIO1_11,?..."
|
|
line.long 0x0C "IOCON_PIO3_2,PIO3_2 configuration register"
|
|
bitfld.long 0x0C 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Pin function selection" "PIO3_2,/DCD,?..."
|
|
line.long 0x10 "IOCON_PIO1_5,PIO1_5 configuration register"
|
|
bitfld.long 0x10 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Pin function selection" "PIO1_5,/RTS,CT32B0_CAP0,?..."
|
|
line.long 0x14 "IOCON_PIO1_6,PIO1_6 configuration register"
|
|
bitfld.long 0x14 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x14 0.--2. " FUNC ,Pin function selection" "PIO1_6,RXD,CT32B0_MAT0,?..."
|
|
line.long 0x18 "IOCON_PIO1_7,PIO1_7 configuration register"
|
|
bitfld.long 0x18 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 3.--4. " MODE ,Pull-up/pull-down resistor control" "Inactive,Pull-down enabled,Pull-up enabled,Repeater mode"
|
|
bitfld.long 0x18 0.--2. " FUNC ,Pin function selection" "PIO1_7,TXD,CT32B0_MAT1,?..."
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "IOCON_SCKLOC,SCK location register"
|
|
bitfld.long 0x00 0.--1. " SCKLOC ,Pin location for SCK0" "SWCLK/PIO0_10/SCK/CT16B0_MAT2,Reserved,PIO0_6/SCK0,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
tree "Port 0"
|
|
base ad:0x50000000
|
|
width 11.
|
|
group.long 0x3FFC++0x3 "GPIO data registers"
|
|
line.long 0x00 "GPIO0DATA,GPIO 0 data register"
|
|
button "GPIO0DATA" "d ad:0x50000000++0x3fff /long"
|
|
group.long 0x08000++0x3
|
|
line.long 0x00 "GPIO0DIR,GPIO 0 data direction register"
|
|
bitfld.long 0x00 11. " IO[11] ,PIO0_11 direction" "Input,Output"
|
|
bitfld.long 0x00 10. " IO[10] ,PIO0_10 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IO[9] ,PIO0_9 direction" "Input,Output"
|
|
bitfld.long 0x00 8. " IO[8] ,PIO0_8 direction" "Input,Output"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " IO[7] ,PIO0_7 direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " IO[6] ,PIO0_6 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IO[5] ,PIO0_5 direction" "Input,Output"
|
|
bitfld.long 0x00 4. " IO[4] ,PIO0_4 direction" "Input,Output"
|
|
sif (cpu()!="LPC1110")
|
|
textline " "
|
|
bitfld.long 0x00 3. " IO[3] ,PIO0_3 direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO[2] ,PIO0_2 direction" "Input,Output"
|
|
bitfld.long 0x00 1. " IO[1] ,PIO0_1 direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " IO[0] ,PIO0_0 direction" "Input,Output"
|
|
group.long 0x08004++0xf "GPIO 0 interrupt registers"
|
|
line.long 0x00 "GPIO0IS,GPIO 0 interrupt sense register"
|
|
bitfld.long 0x00 11. " ISENSE[11] ,PIO0_11 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 10. " ISENSE[10] ,PIO0_10 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ISENSE[9] ,PIO0_9 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 8. " ISENSE[8] ,PIO0_8 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " ISENSE[7] ,PIO0_7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " ISENSE[6] ,PIO0_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ISENSE[5] ,PIO0_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 4. " ISENSE[4] ,PIO0_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
sif (cpu()!="LPC1110")
|
|
textline " "
|
|
bitfld.long 0x00 3. " ISENSE[3] ,PIO0_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO0_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISENSE[1] ,PIO0_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO0_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x04 "GPIO0IBE,GPIO 0 interrupt both edges sense register"
|
|
bitfld.long 0x04 11. " IBE[11] ,PIO0_11 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " IBE[10] ,PIO0_10 interrupt on both edges" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " IBE[9] ,PIO0_9 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " IBE[8] ,PIO0_8 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x04 7. " IBE[7] ,PIO0_7 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " IBE[6] ,PIO0_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IBE[5] ,PIO0_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " IBE[4] ,PIO0_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1110")
|
|
textline " "
|
|
bitfld.long 0x04 3. " IBE[3] ,PIO0_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO0_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " IBE[1] ,PIO0_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO0_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO0IEV,GPIO 0 interrupt event register"
|
|
bitfld.long 0x08 11. " IEV[11] ,PIO0_11 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 10. " IEV[10] ,PIO0_10 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 9. " IEV[9] ,PIO0_9 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 8. " IEV[8] ,PIO0_8 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x08 7. " IEV[7] ,PIO0_7 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " IEV[6] ,PIO0_6 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IEV[5] ,PIO0_5 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 4. " IEV[4] ,PIO0_4 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x08 3. " IEV[3] ,PIO0_3 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO0_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 1. " IEV[1] ,PIO0_1 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO0_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
line.long 0x0c "GPIO0IE,GPIO 0 interrupt mask register"
|
|
bitfld.long 0x0c 11. " MASK[11] ,PIO0_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 10. " MASK[10] ,PIO0_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " MASK[9] ,PIO0_9 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 8. " MASK[8] ,PIO0_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x0c 7. " MASK[7] ,PIO0_7 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 6. " MASK[6] ,PIO0_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " MASK[5] ,PIO0_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 4. " MASK[4] ,PIO0_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x0c 3. " MASK[3] ,PIO0_3 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO0_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MASK[1] ,PIO0_1 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO0_0 interrupt mask selection" "Masked,Not masked"
|
|
rgroup.long 0x8014++0x7
|
|
line.long 0x00 "GPIO0RIS,GPIO 0 raw interrupt status register"
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt status on PIO0_11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RAWST[10] ,Raw interrupt status on PIO0_10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RAWST[9] ,Raw interrupt status on PIO0_9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RAWST[8] ,Raw interrupt status on PIO0_8" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " RAWST[7] ,Raw interrupt status on PIO0_7" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " RAWST[6] ,Raw interrupt status on PIO0_6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RAWST[5] ,Raw interrupt status on PIO0_5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RAWST[4] ,Raw interrupt status on PIO0_4" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()!="LPC1110")
|
|
textline " "
|
|
bitfld.long 0x00 3. " RAWST[3] ,Raw interrupt status on PIO0_3" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO0_2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RAWST[1] ,Raw interrupt status on PIO0_1" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO0_0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO0MIS,GPIO 0 masked interrupt status register"
|
|
bitfld.long 0x04 11. " MASK[11] ,PIO0_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " MASK[10] ,PIO0_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " MASK[9] ,PIO0_9 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " MASK[8] ,PIO0_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x04 7. " MASK[7] ,PIO0_7 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " MASK[6] ,PIO0_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MASK[5] ,PIO0_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MASK[4] ,PIO0_4 interrupt mask selection" "Masked,Not masked"
|
|
sif (cpu()!="LPC1110")
|
|
textline " "
|
|
bitfld.long 0x04 3. " MASK[3] ,PIO0_3 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO0_2 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " MASK[1] ,PIO0_1 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO0_0 interrupt mask selection" "Masked,Not masked"
|
|
wgroup.long 0x801c++0x3
|
|
line.long 0x00 "GPIO0IC,GPIO 0 interrupt clear register"
|
|
bitfld.long 0x00 11. " CLR[11] ,PIO0_11 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR[10] ,PIO0_10 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLR[9] ,PIO0_9 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 8. " CLR[8] ,PIO0_8 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " CLR[7] ,PIO0_7 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " CLR[6] ,PIO0_6 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLR[5] ,PIO0_5 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 4. " CLR[4] ,PIO0_4 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
sif (cpu()!="LPC1110")
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLR[3] ,PIO0_3 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO0_2 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 1. " CLR[1] ,PIO0_1 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO0_0 interrupt clearing" "-,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "Port 1"
|
|
base ad:0x50010000
|
|
width 11.
|
|
group.long 0x3FFC++0x3 "GPIO data registers"
|
|
line.long 0x00 "GPIO1DATA,GPIO 1 data register"
|
|
button "GPIO1DATA" "d ad:0x50010000++0x3fff /long"
|
|
group.long 0x08000++0x3
|
|
line.long 0x00 "GPIO1DIR,GPIO 1 data direction register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 11. " IO[11] ,PIO1_11 direction" "Input,Output"
|
|
bitfld.long 0x00 10. " IO[10] ,PIO1_10 direction" "Input,Output"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " IO[9] ,PIO1_9 direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " IO[8] ,PIO1_8 direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IO[7] ,PIO1_7 direction" "Input,Output"
|
|
bitfld.long 0x00 6. " IO[6] ,PIO1_6 direction" "Input,Output"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 5. " IO[5] ,PIO1_5 direction" "Input,Output"
|
|
bitfld.long 0x00 4. " IO[4] ,PIO1_4 direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " IO[3] ,PIO1_3 direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO[2] ,PIO1_2 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO[1] ,PIO1_1 direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO[0] ,PIO1_0 direction" "Input,Output"
|
|
group.long 0x08004++0xf "GPIO 1 interrupt registers"
|
|
line.long 0x00 "GPIO1IS,GPIO 1 interrupt sense register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 11. " ISENSE[11] ,PIO1_11 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 10. " ISENSE[10] ,PIO1_10 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " ISENSE[9] ,PIO1_9 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " ISENSE[8] ,PIO1_8 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " ISENSE[7] ,PIO1_7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 6. " ISENSE[6] ,PIO1_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 5. " ISENSE[5] ,PIO1_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 4. " ISENSE[4] ,PIO1_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " ISENSE[3] ,PIO1_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO1_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISENSE[1] ,PIO1_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO1_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x04 "GPIO1IBE,GPIO 1 interrupt both edges sense register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x04 11. " IBE[11] ,PIO1_11 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " IBE[10] ,PIO1_10 interrupt on both edges" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x04 9. " IBE[9] ,PIO1_9 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " IBE[8] ,PIO1_8 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " IBE[7] ,PIO1_7 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " IBE[6] ,PIO1_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
textline " "
|
|
bitfld.long 0x04 5. " IBE[5] ,PIO1_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " IBE[4] ,PIO1_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 3. " IBE[3] ,PIO1_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO1_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IBE[1] ,PIO1_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO1_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO1IEV,GPIO 1 interrupt event register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x08 11. " IEV[11] ,PIO1_11 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 10. " IEV[10] ,PIO1_10 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x08 9. " IEV[9] ,PIO1_9 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 8. " IEV[8] ,PIO1_8 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 7. " IEV[7] ,PIO1_7 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 6. " IEV[6] ,PIO1_6 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x08 5. " IEV[5] ,PIO1_5 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 4. " IEV[4] ,PIO1_4 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " IEV[3] ,PIO1_3 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO1_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IEV[1] ,PIO1_1 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO1_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
line.long 0x0c "GPIO1IE,GPIO 1 interrupt mask register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x0c 11. " MASK[11] ,PIO1_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 10. " MASK[10] ,PIO1_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x0c 9. " MASK[9] ,PIO1_9 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 8. " MASK[8] ,PIO1_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 7. " MASK[7] ,PIO1_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 6. " MASK[6] ,PIO1_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x0c 5. " MASK[5] ,PIO1_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 4. " MASK[4] ,PIO1_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 3. " MASK[3] ,PIO1_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO1_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MASK[1] ,PIO1_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO1_0 interrupt mask selection" "Masked,Not masked"
|
|
rgroup.long 0x8014++0x7
|
|
line.long 0x00 "GPIO1RIS,GPIO 1 raw interrupt status register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt status on PIO1_11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RAWST[10] ,Raw interrupt status on PIO1_10" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " RAWST[9] ,Raw interrupt status on PIO1_9" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RAWST[8] ,Raw interrupt status on PIO1_8" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " RAWST[7] ,Raw interrupt status on PIO1_7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RAWST[6] ,Raw interrupt status on PIO1_6" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 5. " RAWST[5] ,Raw interrupt status on PIO1_5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RAWST[4] ,Raw interrupt status on PIO1_4" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " RAWST[3] ,Raw interrupt status on PIO1_3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO1_2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST[1] ,Raw interrupt status on PIO1_1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO1_0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO1MIS,GPIO 1 masked interrupt status register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x04 11. " MASK[11] ,PIO1_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " MASK[10] ,PIO1_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x04 9. " MASK[9] ,PIO1_9 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " MASK[8] ,PIO1_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " MASK[7] ,PIO1_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " MASK[6] ,PIO1_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
textline " "
|
|
bitfld.long 0x04 5. " MASK[5] ,PIO1_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MASK[4] ,PIO1_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " MASK[3] ,PIO1_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO1_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASK[1] ,PIO1_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO1_0 interrupt mask selection" "Masked,Not masked"
|
|
wgroup.long 0x801c++0x3
|
|
line.long 0x00 "GPIO1IC,GPIO 1 interrupt clear register"
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
bitfld.long 0x00 11. " CLR[11] ,PIO1_11 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR[10] ,PIO1_10 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " CLR[9] ,PIO1_9 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " CLR[8] ,PIO1_8 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " CLR[7] ,PIO1_7 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 6. " CLR[6] ,PIO1_6 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLR[5] ,PIO1_5 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 4. " CLR[4] ,PIO1_4 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " CLR[3] ,PIO1_3 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO1_2 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR[1] ,PIO1_1 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO1_0 interrupt clearing" "-,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "Port 2"
|
|
base ad:0x50020000
|
|
width 11.
|
|
group.long 0x3FFC++0x3 "GPIO data registers"
|
|
line.long 0x00 "GPIO2DATA,GPIO 2 data register"
|
|
button "GPIO2DATA" "d ad:0x50020000++0x3fff /long"
|
|
group.long 0x08000++0x3
|
|
line.long 0x00 "GPIO2DIR,GPIO 2 data direction register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 0. " IO[0] ,PIO2_0 direction" "Input,Output"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 11. " IO[11] ,PIO2_11 direction" "Input,Output"
|
|
bitfld.long 0x00 10. " IO[10] ,PIO2_10 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IO[9] ,PIO2_9 direction" "Input,Output"
|
|
bitfld.long 0x00 8. " IO[8] ,PIO2_8 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IO[7] ,PIO2_7 direction" "Input,Output"
|
|
bitfld.long 0x00 6. " IO[6] ,PIO2_6 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IO[5] ,PIO2_5 direction" "Input,Output"
|
|
bitfld.long 0x00 4. " IO[4] ,PIO2_4 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IO[3] ,PIO2_3 direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO[2] ,PIO2_2 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO[1] ,PIO2_1 direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO[0] ,PIO2_0 direction" "Input,Output"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 11. " IO[11] ,PIO2_11 direction" "Input,Output"
|
|
bitfld.long 0x00 10. " IO[10] ,PIO2_10 direction" "Input,Output"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " IO[9] ,PIO2_9 direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " IO[8] ,PIO2_8 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IO[7] ,PIO2_7 direction" "Input,Output"
|
|
bitfld.long 0x00 6. " IO[6] ,PIO2_6 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IO[3] ,PIO2_3 direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO[2] ,PIO2_2 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO[1] ,PIO2_1 direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO[0] ,PIO2_0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x08004++0xf "GPIO 2 interrupt registers"
|
|
line.long 0x00 "GPIO2IS,GPIO 2 interrupt sense register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO2_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 11. " ISENSE[11] ,PIO2_11 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 10. " ISENSE[10] ,PIO2_10 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ISENSE[9] ,PIO2_9 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 8. " ISENSE[8] ,PIO2_8 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ISENSE[7] ,PIO2_7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 6. " ISENSE[6] ,PIO2_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ISENSE[5] ,PIO2_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 4. " ISENSE[4] ,PIO2_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ISENSE[3] ,PIO2_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO2_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISENSE[1] ,PIO2_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO2_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 11. " ISENSE[11] ,PIO2_11 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 10. " ISENSE[10] ,PIO2_10 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " ISENSE[9] ,PIO2_9 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " ISENSE[8] ,PIO2_8 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ISENSE[7] ,PIO2_7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 6. " ISENSE[6] ,PIO2_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ISENSE[3] ,PIO2_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO2_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISENSE[1] ,PIO2_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO2_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
endif
|
|
line.long 0x04 "GPIO2IBE,GPIO 2 interrupt both edges sense register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO2_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x04 11. " IBE[11] ,PIO2_11 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " IBE[10] ,PIO2_10 interrupt on both edges" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " IBE[9] ,PIO2_9 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " IBE[8] ,PIO2_8 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " IBE[7] ,PIO2_7 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " IBE[6] ,PIO2_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IBE[5] ,PIO2_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " IBE[4] ,PIO2_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IBE[3] ,PIO2_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO2_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IBE[1] ,PIO2_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO2_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x04 11. " IBE[11] ,PIO2_11 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " IBE[10] ,PIO2_10 interrupt on both edges" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x04 9. " IBE[9] ,PIO2_9 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " IBE[8] ,PIO2_8 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " IBE[7] ,PIO2_7 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " IBE[6] ,PIO2_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IBE[3] ,PIO2_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO2_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IBE[1] ,PIO2_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO2_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "GPIO2IEV,GPIO 2 interrupt event register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO2_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x08 11. " IEV[11] ,PIO2_11 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 10. " IEV[10] ,PIO2_10 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 9. " IEV[9] ,PIO2_9 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 8. " IEV[8] ,PIO2_8 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IEV[7] ,PIO2_7 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 6. " IEV[6] ,PIO2_6 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IEV[5] ,PIO2_5 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 4. " IEV[4] ,PIO2_4 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IEV[3] ,PIO2_3 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO2_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IEV[1] ,PIO2_1 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO2_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x08 11. " IEV[11] ,PIO2_11 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 10. " IEV[10] ,PIO2_10 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x08 9. " IEV[9] ,PIO2_9 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
endif
|
|
bitfld.long 0x08 8. " IEV[8] ,PIO2_8 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IEV[7] ,PIO2_7 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 6. " IEV[6] ,PIO2_6 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IEV[3] ,PIO2_3 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO2_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IEV[1] ,PIO2_1 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO2_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
endif
|
|
line.long 0x0c "GPIO2IE,GPIO 2 interrupt mask register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x0c 11. " MASK[11] ,PIO2_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 10. " MASK[10] ,PIO2_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " MASK[9] ,PIO2_9 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 8. " MASK[8] ,PIO2_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " MASK[7] ,PIO2_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 6. " MASK[6] ,PIO2_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " MASK[5] ,PIO2_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 4. " MASK[4] ,PIO2_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " MASK[3] ,PIO2_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO2_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MASK[1] ,PIO2_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x0c 11. " MASK[11] ,PIO2_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 10. " MASK[10] ,PIO2_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x0c 9. " MASK[9] ,PIO2_9 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 8. " MASK[8] ,PIO2_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " MASK[7] ,PIO2_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 6. " MASK[6] ,PIO2_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " MASK[3] ,PIO2_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO2_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MASK[1] ,PIO2_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
rgroup.long 0x8014++0x7
|
|
line.long 0x00 "GPIO2RIS,GPIO 2 raw interrupt status register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO2_0" "No interrupt,Interrupt"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt status on PIO2_11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RAWST[10] ,Raw interrupt status on PIO2_10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RAWST[9] ,Raw interrupt status on PIO2_9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RAWST[8] ,Raw interrupt status on PIO2_8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RAWST[7] ,Raw interrupt status on PIO2_7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RAWST[6] ,Raw interrupt status on PIO2_6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RAWST[5] ,Raw interrupt status on PIO2_5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RAWST[4] ,Raw interrupt status on PIO2_4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RAWST[3] ,Raw interrupt status on PIO2_3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO2_2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST[1] ,Raw interrupt status on PIO2_1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO2_0" "No interrupt,Interrupt"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt status on PIO2_11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RAWST[10] ,Raw interrupt status on PIO2_10" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " RAWST[9] ,Raw interrupt status on PIO2_9" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RAWST[8] ,Raw interrupt status on PIO2_8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RAWST[7] ,Raw interrupt status on PIO2_7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RAWST[6] ,Raw interrupt status on PIO2_6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RAWST[3] ,Raw interrupt status on PIO2_3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO2_2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST[1] ,Raw interrupt status on PIO2_1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO2_0" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x04 "GPIO2MIS,GPIO 2 masked interrupt status register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x04 11. " MASK[11] ,PIO2_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " MASK[10] ,PIO2_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " MASK[9] ,PIO2_9 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " MASK[8] ,PIO2_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MASK[7] ,PIO2_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " MASK[6] ,PIO2_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MASK[5] ,PIO2_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MASK[4] ,PIO2_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MASK[3] ,PIO2_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO2_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASK[1] ,PIO2_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x04 11. " MASK[11] ,PIO2_11 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " MASK[10] ,PIO2_10 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x04 9. " MASK[9] ,PIO2_9 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " MASK[8] ,PIO2_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MASK[7] ,PIO2_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " MASK[6] ,PIO2_6 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MASK[3] ,PIO2_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO2_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASK[1] ,PIO2_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
wgroup.long 0x801c++0x3
|
|
line.long 0x00 "GPIO2IC,GPIO 2 interrupt clear register"
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1342"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO2_0 interrupt clearing" "-,Clear"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 11. " CLR[11] ,PIO2_11 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR[10] ,PIO2_10 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLR[9] ,PIO2_9 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 8. " CLR[8] ,PIO2_8 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLR[7] ,PIO2_7 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 6. " CLR[6] ,PIO2_6 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLR[5] ,PIO2_5 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 4. " CLR[4] ,PIO2_4 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLR[3] ,PIO2_3 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO2_2 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR[1] ,PIO2_1 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO2_0 interrupt clearing" "-,Clear"
|
|
elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 11. " CLR[11] ,PIO2_11 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR[10] ,PIO2_10 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
sif (cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
bitfld.long 0x00 9. " CLR[9] ,PIO2_9 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " CLR[8] ,PIO2_8 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLR[7] ,PIO2_7 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 6. " CLR[6] ,PIO2_6 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLR[3] ,PIO2_3 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO2_2 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR[1] ,PIO2_1 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO2_0 interrupt clearing" "-,Clear"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Port 3"
|
|
base ad:0x50030000
|
|
width 11.
|
|
group.long 0x3FFC++0x3 "GPIO data registers"
|
|
line.long 0x00 "GPIO3DATA,GPIO 3 data register"
|
|
button "GPIO3DATA" "d ad:0x50030000++0x3fff /long"
|
|
group.long 0x08000++0x3
|
|
line.long 0x00 "GPIO3DIR,GPIO 3 data direction register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 5. " IO[5] ,PIO3_5 direction" "Input,Output"
|
|
bitfld.long 0x00 4. " IO[4] ,PIO3_4 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO[2] ,PIO3_2 direction" "Input,Output"
|
|
elif (cpu()=="LPC1313"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x00 5. " IO[5] ,PIO3_5 direction" "Input,Output"
|
|
bitfld.long 0x00 4. " IO[4] ,PIO3_4 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IO[3] ,PIO3_3 direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO[2] ,PIO3_2 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO[1] ,PIO3_1 direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO[0] ,PIO3_0 direction" "Input,Output"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x00 2. " IO[2] ,PIO3_2 direction" "Input,Output"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 3. " IO[3] ,PIO3_3 direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO[2] ,PIO3_2 direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO[1] ,PIO3_1 direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO[0] ,PIO3_0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x08004++0xf "GPIO 3 interrupt registers"
|
|
line.long 0x00 "GPIO3IS,GPIO 3 interrupt sense register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 5. " ISENSE[5] ,PIO3_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 4. " ISENSE[4] ,PIO3_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO3_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x00 5. " ISENSE[5] ,PIO3_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 4. " ISENSE[4] ,PIO3_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ISENSE[3] ,PIO3_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO3_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISENSE[1] ,PIO3_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO3_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO3_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 3. " ISENSE[3] ,PIO3_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " ISENSE[2] ,PIO3_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISENSE[1] ,PIO3_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " ISENSE[0] ,PIO3_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
endif
|
|
line.long 0x04 "GPIO3IBE,GPIO 3 interrupt both edges sense register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x04 5. " IBE[5] ,PIO3_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " IBE[4] ,PIO3_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO3_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x04 5. " IBE[5] ,PIO3_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " IBE[4] ,PIO3_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IBE[3] ,PIO3_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO3_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IBE[1] ,PIO3_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO3_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO3_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x04 3. " IBE[3] ,PIO3_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IBE[2] ,PIO3_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IBE[1] ,PIO3_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IBE[0] ,PIO3_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "GPIO3IEV,GPIO 3 interrupt event register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x08 5. " IEV[5] ,PIO3_5 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 4. " IEV[4] ,PIO3_4 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO3_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x08 5. " IEV[5] ,PIO3_5 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 4. " IEV[4] ,PIO3_4 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IEV[3] ,PIO3_3 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO3_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IEV[1] ,PIO3_1 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO3_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO3_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x08 3. " IEV[3] ,PIO3_3 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 2. " IEV[2] ,PIO3_2 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IEV[1] ,PIO3_1 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
bitfld.long 0x08 0. " IEV[0] ,PIO3_0 interrupt falling/rising edge selection" "Falling/low,Rising/high"
|
|
endif
|
|
line.long 0x0c "GPIO3IE,GPIO 3 interrupt mask register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x0c 5. " MASK[5] ,PIO3_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 4. " MASK[4] ,PIO3_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x0c 5. " MASK[5] ,PIO3_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 4. " MASK[4] ,PIO3_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " MASK[3] ,PIO3_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MASK[1] ,PIO3_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO3_0 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x0c 3. " MASK[3] ,PIO3_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MASK[1] ,PIO3_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x0c 0. " MASK[0] ,PIO3_0 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
rgroup.long 0x8014++0x7
|
|
line.long 0x00 "GPIO3RIS,GPIO 3 raw interrupt status register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 5. " RAWST[5] ,Raw interrupt status on PIO3_5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RAWST[4] ,Raw interrupt status on PIO3_4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO3_2" "No interrupt,Interrupt"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x00 5. " RAWST[5] ,Raw interrupt status on PIO3_5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RAWST[4] ,Raw interrupt status on PIO3_4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RAWST[3] ,Raw interrupt status on PIO3_3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO3_2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST[1] ,Raw interrupt status on PIO3_1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO3_0" "No interrupt,Interrupt"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO3_2" "No interrupt,Interrupt"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 3. " RAWST[3] ,Raw interrupt status on PIO3_3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST[2] ,Raw interrupt status on PIO3_2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST[1] ,Raw interrupt status on PIO3_1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST[0] ,Raw interrupt status on PIO3_0" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x04 "GPIO3MIS,GPIO 3 masked interrupt status register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x04 5. " MASK[5] ,PIO3_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MASK[4] ,PIO3_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x04 5. " MASK[5] ,PIO3_5 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MASK[4] ,PIO3_4 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MASK[3] ,PIO3_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASK[1] ,PIO3_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO3_0 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x04 3. " MASK[3] ,PIO3_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MASK[2] ,PIO3_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASK[1] ,PIO3_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MASK[0] ,PIO3_0 interrupt mask selection" "Masked,Not masked"
|
|
endif
|
|
wgroup.long 0x801c++0x3
|
|
line.long 0x00 "GPIO3IC,GPIO 3 interrupt clear register"
|
|
sif (cpu()=="LPC1311"||cpu()=="EM773"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV")
|
|
bitfld.long 0x00 5. " CLR[5] ,PIO3_5 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 4. " CLR[4] ,PIO3_4 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO3_2 interrupt clearing" "-,Clear"
|
|
elif (cpu()=="LPC1313"||cpu()=="LPC1110"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14")
|
|
bitfld.long 0x00 5. " CLR[5] ,PIO3_5 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 4. " CLR[4] ,PIO3_4 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLR[3] ,PIO3_3 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO3_2 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR[1] ,PIO3_1 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO3_0 interrupt clearing" "-,Clear"
|
|
elif (cpu()=="LPC1342")
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO3_2 interrupt clearing" "-,Clear"
|
|
elif (cpu()=="LPC1343"||cpu()=="LPC11C22"||cpu()=="LPC11C24")
|
|
bitfld.long 0x00 3. " CLR[3] ,PIO3_3 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 2. " CLR[2] ,PIO3_2 interrupt clearing" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR[1] ,PIO3_1 interrupt clearing" "-,Clear"
|
|
bitfld.long 0x00 0. " CLR[0] ,PIO3_0 interrupt clearing" "-,Clear"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x40008000
|
|
width 11.
|
|
if (((per.l((ad:0x40008000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U0RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U0IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U0DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U0DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U0IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U0FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U0MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x40008000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U0LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U0LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U0MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U0LSR,Line Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U0MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U0SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U0ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
if (((per.l((ad:0x40008000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U0ICR,IrDA Control Register"
|
|
sif cpu()=="LPC11U12/201"||cpu()=="LPC11U13/x201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "3/(16 * baud rate),2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk"
|
|
else
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U0ICR,IrDA Control Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U0FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40008000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
width 17.
|
|
if (((per.l((ad:0x40008000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U0FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U0RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
line.long 0x08 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x08 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x08 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x08 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
line.long 0x0C "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x0C 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
width 17.
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
sif (cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "/RTS,/DTR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "U0RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
sif (cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11D14"&&cpu()!="LPC1112LV"&&cpu()!="LPC1114LV")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
width 16.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x40000000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CON,I2C0 Control Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
|
|
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,I2C0 Status Register"
|
|
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
|
|
newline
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "DAT,I2C0 Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
line.long 0x04 "ADR0,I2C0 Slave Address Register 0"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Slave mode address"
|
|
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
line.long 0x08 "SCLH,I2C0 SCL High Duty Cycle Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL HIGH time period selection"
|
|
line.long 0x0C "SCLL,I2C0 SCL Low Duty Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL LOW time period selection"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MMCTRL,I2C0 Monitor Mode Control Register"
|
|
sif cpuis("LPC1311")||cpuis("LPC1313")||cpuis("LPC1342")||cpuis("LPC1343")||cpuis("EM773")||cpuis("LPC11A02")||cpuis("LPC11A04")||cpuis("LPC11A11")||cpuis("LPC11A12")||cpuis("LPC11A13")||cpuis("LPC11A14")
|
|
bitfld.long 0x00 3. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
else
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
endif
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR1,I2C0 Slave Address Register 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADR2,I2C0 Slave Address Register 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADR3,I2C0 Slave Address Register 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
sif cpuis("LPC4072FBD80")||cpuis("LPC4072FET80")||cpuis("LPC4074FBD144")||cpuis("LPC4076FBD144")||cpuis("LPC4076FET180")||cpuis("LPC4078FBD100")||cpuis("LPC4078FBD144")||cpuis("LPC4078FBD208")||cpuis("LPC4078FBD80")||cpuis("LPC4078FET180")||cpuis("LPC4078FET208")||(cpu()=="LPC4088FBD144")||cpuis("LPC4088FBD208")||cpuis("LPC4088FET180")||cpuis("LPC4088FET208")||cpuis("LPC11E*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
elif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
in
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MASK0,I2C0 Mask Register 0"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,I2C0 Mask Register 1"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MASK2,I2C0 Mask Register 2"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK3,I2C0 Mask Register 3"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI0/SSP (Serial Peripheral Interface/Synchronous Serial Port)"
|
|
base ad:0x40040000
|
|
width 11.
|
|
if ((per.l(ad:0x40040000)&0x30)==0x00)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP0CR0,SPI/SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock Out Phase" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " CPOL ,Clock Out Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP0CR0,SPI/SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x04)&0x4)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP0CR1,SPI/SSP0 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave Output Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI/SSP Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SPI/SSP0 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI/SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
endif
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP0DR,SPI/SSP0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SSP0DR,SPI/SSP0 Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP0SR,SPI/SSP0 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Not Full" "Full,Not Full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSP0CPSR,SPI/SSP0 Clock Prescale Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CPSDVSR ,PCLK Divisor (even value between 2 and 254)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSP0IMSC,SPI/SSP0 Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Tx FIFO Half Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIM ,Rx FIFO Half Full Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SSP0RIS,SPI/SSP0 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO Half Empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO Half Full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORRIS ,Frame Received When RxFIFO Full" "Not received,Received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SSP0MIS,SPI/SSP0 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXMIS ,Tx FIFO Half Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXMIS ,Rx FIFO Half Full Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTMIS ,Receive Timeout Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORMIS ,Frame Received When RxFIFO Full Interrupt" "No interrupt,Interrupt"
|
|
sif (cpu()=="EM773"||cpuis("LPC11E*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
wgroup.long 0x20++0x03
|
|
else
|
|
group.long 0x20++0x03
|
|
endif
|
|
line.long 0x00 "SSP0ICR,SPI/SSP0 Interrupt Clear Register"
|
|
bitfld.long 0x0 1. " RTIC ,Receive Timeout Clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RORIC ,Clear Frame Received When RxFIFO Full" "No effect,Clear"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SSP0DMACR,SPI/SSP0 DMA Control Register"
|
|
bitfld.long 0x0 1. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CT16B (16-bit counter/timer)"
|
|
tree "CT16B0"
|
|
base ad:0x4000c000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR16B0IR,CT16B0 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR16B0TCR,CT16B0 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR16B0TC,CT16B0 Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "TMR16B0PR,CT16B0 Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PR ,Prescale max value"
|
|
line.long 0x08 "TMR16B0PC,CT16B0 Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR16B0TC,CT16B0 Timer Counter Register"
|
|
line.long 0x04 "TMR16B0PR,CT16B0 Prescale Register"
|
|
line.long 0x08 "TMR16B0PC,CT16B0 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR16B0MCR,CT16B0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR16B0MR0,CT16B0 Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "TMR16B0MR1,CT16B0 Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "TMR16B0MR2,CT16B0 Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "TMR16B0MR3,CT16B0 Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR16B0MR0,CT16B0 Match Register 0"
|
|
line.long 0x04 "TMR16B0MR1,CT16B0 Match Register 1"
|
|
line.long 0x08 "TMR16B0MR2,CT16B0 Match Register 2"
|
|
line.long 0x0C "TMR16B0MR3,CT16B0 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR16B0CCR,CT16B0 Capture Control Register"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 0 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 0 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 0 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 0 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 0 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 0 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 8. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP1RE ,Capture on CT16B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B0_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B0_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B0_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0xF
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14")
|
|
line.long 0x04 "TMR16B0CR1,CT16B0 Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
line.long 0x08 "TMR16B0CR2,CT16B0 Capture Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x0C "TMR16B0CR3,CT16B0 Capture Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CAP ,Timer counter capture value"
|
|
endif
|
|
endif
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TMR16B0CR1,CT16B0 Capture Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR16B0EMR,CT16B0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x4000c000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16B0_CAP0,CT16B0_CAP1,Comp 0 level output,Comp 0 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16B0_CAP0,Reserved,CT16B0_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR16B0PWMC,CT16B0 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT16B0_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT16B0_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT16B0_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "CT32B (32-bit counter/timer)"
|
|
tree "CT32B0"
|
|
base ad:0x40014000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR32B0IR,CT32B0 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR32B0TCR,CT32B0 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B0TC,CT32B0 Timer Counter Register"
|
|
line.long 0x04 "TMR32B0PR,CT32B0 Prescale Register"
|
|
line.long 0x08 "TMR32B0PC,CT32B0 Prescale Counter Register"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B0TC,CT32B0 Timer Counter Register"
|
|
line.long 0x04 "TMR32B0PR,CT32B0 Prescale Register"
|
|
line.long 0x08 "TMR32B0PC,CT32B0 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR32B0MCR,CT32B0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B0MR0,CT32B0 Match Register 0"
|
|
line.long 0x04 "TMR32B0MR1,CT32B0 Match Register 1"
|
|
line.long 0x08 "TMR32B0MR2,CT32B0 Match Register 2"
|
|
line.long 0x0C "TMR32B0MR3,CT32B0 Match Register 3"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B0MR0,CT32B0 Match Register 0"
|
|
line.long 0x04 "TMR32B0MR1,CT32B0 Match Register 1"
|
|
line.long 0x08 "TMR32B0MR2,CT32B0 Match Register 2"
|
|
line.long 0x0C "TMR32B0MR3,CT32B0 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR32B0CCR,CT32B0 Capture Control Register"
|
|
sif (cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 0 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 0 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 0 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 0 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 0 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 0 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 8. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B0_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B0_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B0_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TMR32B0CR1,CT32B0 Capture Register 1"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR32B0EMR,CT32B0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x40014000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B0_CAP0,CT32B0_CAP1,Comp 0 level output,Comp 0 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B0_CAP0,Reserved,CT32B0_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
if ((per.long(ad:0x40014000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,?..."
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR32B0PWMC,CT32B0 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT32B0_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT32B0_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT32B0_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "CT32B1"
|
|
base ad:0x40018000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR32B1IR,CT32B1 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR32B1TCR,CT32B1 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B1TC,CT32B1 Timer Counter Register"
|
|
line.long 0x04 "TMR32B1PR,CT32B1 Prescale Register"
|
|
line.long 0x08 "TMR32B1PC,CT32B1 Prescale Counter Register"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B1TC,CT32B1 Timer Counter Register"
|
|
line.long 0x04 "TMR32B1PR,CT32B1 Prescale Register"
|
|
line.long 0x08 "TMR32B1PC,CT32B1 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR32B1MCR,CT32B1 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B1MR0,CT32B1 Match Register 0"
|
|
line.long 0x04 "TMR32B1MR1,CT32B1 Match Register 1"
|
|
line.long 0x08 "TMR32B1MR2,CT32B1 Match Register 2"
|
|
line.long 0x0C "TMR32B1MR3,CT32B1 Match Register 3"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B1MR0,CT32B1 Match Register 0"
|
|
line.long 0x04 "TMR32B1MR1,CT32B1 Match Register 1"
|
|
line.long 0x08 "TMR32B1MR2,CT32B1 Match Register 2"
|
|
line.long 0x0C "TMR32B1MR3,CT32B1 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR32B1CCR,CT32B1 Capture Control Register"
|
|
sif (cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 1 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 1 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 1 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 1 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 1 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 1 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B1_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR32B1CCR,CT32B1 Capture Control Register"
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B1_CAP0 rising edge" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x04 "TMR32B1CR1,CT32B1 Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR32B1EMR,CT32B1 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x40018000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B1_CAP0,CT32B1_CAP1,Comp 1 level output,Comp 1 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B1_CAP0,CT32B1_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
if ((per.long(ad:0x40018000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,?..."
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR32B1PWMC,CT32B1 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT32B1_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT32B1_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT32B1_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40004000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WDMOD,Watchdog Mode Register"
|
|
sif cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC11E*")||cpuis("LPC11U6*"))
|
|
bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))
|
|
bitfld.long 0x00 5. " LOCK ,Watchdog oscillator lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 7. " WDLOCKEN ,Watchdog enable and reset lockout" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " WDLOCKDP ,Deep Power-down enable lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")
|
|
eventfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
endif
|
|
bitfld.long 0x00 2. " WDTOF ,Watchdog Time-out flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable" "Disabled,Enabled"
|
|
sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpu()=="LPC11U24"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")||cpu()==("LPC8N04")||cpuis("LPC11D14"))
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value"
|
|
else
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long 0x04 0.--31. 1. " COUNT ,Watchdog time-out interval"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WDFEED,Watchdog Feed Sequence Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value"
|
|
sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*"))||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||(cpu()=="LPC811M001JDH16")||(cpu()=="LPC832M101FDH20")||(cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))||cpu()=="LPC8N04"||cpuis("LPC11D14")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " COUNT ,Counter timer value"
|
|
endif
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&!cpuis("LPC1111*")&&cpu()!="LPC11D14"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857"&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC43*")&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&!cpuis("LPC43S*")&&!cpuis("LPC84*")&&cpu()!="LPC811M001JDH16"&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC8N04"&&!cpuis("LPC802*")&&!cpuis("LPC804*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WDCLKSEL,Watchdog Timer Clock Source Selection Register"
|
|
bitfld.long 0x00 31. " WDLOCK ,Watchdog lock" "Not locked,Locked"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 0.--1. " WDSEL1 ,Select the clock source for the watchdog timer" "Internal RC,Watchdog,?..."
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,Watchdog oscillator"
|
|
else
|
|
bitfld.long 0x00 0.--1. " WDSEL2 ,Select the clock source for the watchdog timer" "RC,APB clock,RTC,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U6*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "WDWARNINT,Watchdog Timer Warning Interrupt Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value"
|
|
line.long 0x04 "WDWINDOW,Watchdog Timer Window Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
; tree "System Tick Timer"
|
|
; base ad:0xe000e010
|
|
; %include em773/stt.ph
|
|
; tree.end
|
|
tree "Flash memory access"
|
|
base ad:0x4003c010
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "FLASHCFG,Flash configuration register"
|
|
bitfld.long 0x00 0.--1. " FLASHTIM ,Flash access time" "1 CPU clock,2 CPU clocks,3 CPU clocks,?..."
|
|
width 0xb
|
|
tree.end
|
|
textline " "
|