29646 lines
2.1 MiB
29646 lines
2.1 MiB
; --------------------------------------------------------------------------------
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; @Title: EFM32GG11 On-Chip Peripherals
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; @Props: Released
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; @Author: BCA, MRO
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; @Changelog: 2018-11-20 MRO
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; @Manufacturer: ENERGYMICRO - Energy Micro AS
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; @Doc: efm32gg11-datasheet.pdf (Rev. 0.6, 2018-03)
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; efm32gg11-rm.pdf (Rev. 0.6, 2018-03)
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; @Core: Cortex-M4
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; @Chip: EFM32GG11B110F, EFM32GG11B120F, EFM32GG11B310F, EFM32GG11B320F,
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; EFM32GG11B420F, EFM32GG11B510F, EFM32GG11B520F, EFM32GG11B810F,
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; EFM32GG11B820F
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perefm32gg11.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; Known problems:
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; MODULE REGISTER DESCRIPTION
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; DBG ALL No base address
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; TRNG STATUS PREIF seems to be R-only but described as RW
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "MABS (Memory and Bus System)"
|
|
base ad:0x0FE081B0
|
|
width 18.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CAL,CRC of DI-Page and Calibration Temperature Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TEMP ,Calibration temperature"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRC ,CRC of DI-page"
|
|
rgroup.long 0x28++0x0F
|
|
line.long 0x00 "EUI48L,EUI48 OUI and Unique Identifier Low Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " OUI48L ,Lower octet of EUI48 organizationally unique identifier"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UNIQUEID ,Unique identifier"
|
|
line.long 0x04 "EUI48H,EUI48 OUI and Unique Identifier High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " OUI48H ,Upper two octets of EUI48 organizationally unique identifier"
|
|
line.long 0x08 "CUSTOMINFO,Custom Information Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " PARTNO ,Custom part identifier"
|
|
line.long 0x0C "MEMINFO,Flash Page Size and Miscellaneous Chip Information Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FLASH_PAGE_SIZE ,Flash page size"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PINCOUNT ,Device pin count"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PKGTYPE ,Package identifier as character"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TEMPGRADE ,Temperature grade of product"
|
|
rgroup.long 0x40++0x17
|
|
line.long 0x00 "UNIQUEL,Low 32 Bits of Device Unique Number Register"
|
|
line.long 0x04 "UNIQUEH,High 32 Bits of Device Unique Number Register"
|
|
line.long 0x08 "MSIZE,Flash and SRAM Memory Size in kB"
|
|
hexmask.long.word 0x08 16.--31. 1. " SRAM ,Ram size"
|
|
hexmask.long.word 0x08 0.--15. 1. " FLASH ,Flash size"
|
|
line.long 0x0C "PART,Part Description Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PROD_REV ,Production revision"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " DEVICE_FAMILY ,Device family"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DEVICE_NUMBER ,Part number"
|
|
line.long 0x10 "DEVINFOREV,Device Information Page Revision Register"
|
|
bitfld.long 0x10 5.--7. " MAJOR ,Major DEVINFO revision" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x10 0.--4. " MINOR ,Minor DEVINFO layout revision" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x14 "EMUTEMP,Emu Temperature Calibration Information"
|
|
hexmask.long.byte 0x14 0.--7. 1. " EMUTEMPROOM ,EMU_TEMP temperature reading at room"
|
|
tree "ADC Calibration Registers"
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "ADC0CAL0,ADC0 Calibration Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GAIN2V5 ,Gain for 2.5V reference"
|
|
hexmask.long.byte 0x00 20.--23. 0x10 " NEGSEOFFSET2V5 ,Negative single ended offset for 2.5V reference"
|
|
hexmask.long.byte 0x00 16.--19. 0x01 " OFFSET2V5 ,Offset for 2.5V reference"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. " GAIN1V25 ,Gain for 1.25V reference"
|
|
hexmask.long.byte 0x00 4.--7. 0x10 " NEGSEOFFSET1V25 ,Negative single ended offset for 1.25V reference"
|
|
hexmask.long.byte 0x00 0.--3. 0x01 " OFFSET1V25 ,Offset for 1.25V reference"
|
|
line.long 0x04 "ADC0CAL1,ADC0 Calibration Register 1"
|
|
hexmask.long.byte 0x04 24.--30. 1. " GAIN5VDIFF ,Gain for 5V differential reference"
|
|
hexmask.long.byte 0x04 20.--23. 0x10 " NEGSEOFFSET5VDIFF ,Negative single ended offset for 5V differential reference"
|
|
hexmask.long.byte 0x04 16.--19. 0x01 " OFFSET5VDIFF ,Offset for 5V differential reference"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--14. 1. " GAINVDD ,Gain for VDD reference"
|
|
hexmask.long.byte 0x04 4.--7. 0x10 " NEGSEOFFSETVDD ,Negative single ended offset for VDD reference"
|
|
hexmask.long.byte 0x04 0.--3. 0x01 " OFFSETVDD ,Offset for VDD reference"
|
|
line.long 0x08 "ADC0CAL2,ADC0 Calibration Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 0x10 " NEGSEOFFSET2XVDD ,Negative single ended offset for 2XVDD reference"
|
|
hexmask.long.byte 0x08 0.--3. 0x01 " OFFSET2XVDD ,Offset for 2XVDD reference"
|
|
line.long 0x0C "ADC0CAL3,ADC0 Calibration Register 3"
|
|
hexmask.long.word 0x0C 4.--15. 1. " TEMPREAD1V25 ,Temperature reading at 1V25 reference"
|
|
rgroup.long 0x70++0x0F
|
|
line.long 0x00 "ADC1CAL0,ADC1 Calibration Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GAIN2V5 ,Gain for 2.5V reference"
|
|
hexmask.long.byte 0x00 20.--23. 0x10 " NEGSEOFFSET2V5 ,Negative single ended offset for 2.5V reference"
|
|
hexmask.long.byte 0x00 16.--19. 0x01 " OFFSET2V5 ,Offset for 2.5V reference"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. " GAIN1V25 ,Gain for 1.25V reference"
|
|
hexmask.long.byte 0x00 4.--7. 0x10 " NEGSEOFFSET1V25 ,Negative single ended offset for 1.25V reference"
|
|
hexmask.long.byte 0x00 0.--3. 0x01 " OFFSET1V25 ,Offset for 1.25V reference"
|
|
line.long 0x04 "ADC1CAL1,ADC1 Calibration Register 1"
|
|
hexmask.long.byte 0x04 24.--30. 1. " GAIN5VDIFF ,Gain for 5V differential reference"
|
|
hexmask.long.byte 0x04 20.--23. 0x10 " NEGSEOFFSET5VDIFF ,Negative single ended offset for 5V differential reference"
|
|
hexmask.long.byte 0x04 16.--19. 0x01 " OFFSET5VDIFF ,Offset for 5V differential reference"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--14. 1. " GAINVDD ,Gain for VDD reference"
|
|
hexmask.long.byte 0x04 4.--7. 0x10 " NEGSEOFFSETVDD ,Negative single ended offset for VDD reference"
|
|
hexmask.long.byte 0x04 0.--3. 0x01 " OFFSETVDD ,Offset for VDD reference"
|
|
line.long 0x08 "ADC1CAL2,ADC1 Calibration Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 0x10 " NEGSEOFFSET2XVDD ,Negative single ended offset for 2XVDD reference"
|
|
hexmask.long.byte 0x08 0.--3. 0x01 " OFFSET2XVDD ,Offset for 2XVDD reference"
|
|
line.long 0x0C "ADC1CAL3,ADC1 Calibration Register 3"
|
|
hexmask.long.word 0x0C 4.--15. 1. " TEMPREAD1V25 ,Temperature reading at 1V25 reference"
|
|
tree.end
|
|
tree "HFRCO Calibration Registers"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "HFRCOCAL0,HFRCO Calibration Register (4 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "HFRCOCAL3,HFRCO Calibration Register (7 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "HFRCOCAL6,HFRCO Calibration Register (13 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "HFRCOCAL7,HFRCO Calibration Register (16 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "HFRCOCAL8,HFRCO Calibration Register (19 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "HFRCOCAL10,HFRCO Calibration Register (26 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "HFRCOCAL11,HFRCO Calibration Register (32 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "HFRCOCAL12,HFRCO Calibration Register (38 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "HFRCOCAL13,HFRCO Calibration Register (48 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "HFRCOCAL14,HFRCO Calibration Register (56 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "HFRCOCAL15,HFRCO Calibration Register (64 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "HFRCOCAL16,HFRCO Calibration Register (72 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,HFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,HFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
tree.end
|
|
tree "AUXHFRCO Calibration Registers"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "AUXHFRCOCAL0,AUXHFRCO Calibration Register (4 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "AUXHFRCOCAL3,AUXHFRCO Calibration Register (7 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "AUXHFRCOCAL6,AUXHFRCO Calibration Register (13 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "AUXHFRCOCAL7,AUXHFRCO Calibration Register (16 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "AUXHFRCOCAL8,AUXHFRCO Calibration Register (19 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "AUXHFRCOCAL10,AUXHFRCO Calibration Register (26 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "AUXHFRCOCAL11,AUXHFRCO Calibration Register (32 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "AUXHFRCOCAL12,AUXHFRCO Calibration Register (38 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "AUXHFRCOCAL13,AUXHFRCO Calibration Register (48 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "AUXHFRCOCAL14,AUXHFRCO Calibration Register (50 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,AUXHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,AUXHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
tree.end
|
|
tree "VMON Calibration Registers"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "VMONCAL0,VMON Calibration Register 0"
|
|
bitfld.long 0x00 28.--31. " ALTAVDD2V98THRESCOARSE ,ALTAVDD 2.98V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ALTAVDD2V98THRESFINE ,ALTAVDD 2.98V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " ALTAVDD1V86THRESCOARSE ,ALTAVDD 1.86V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " ALTAVDD1V86THRESFINE ,ALTAVDD 1.86V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " AVDD2V98THRESCOARSE ,AVDD 2.98V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " AVDD2V98THRESFINE ,AVDD 2.98V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " AVDD1V86THRESCOARSE ,AVDD 1.86V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " AVDD1V86THRESFINE ,AVDD 1.86V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "VMONCAL1,VMON Calibration Register 1"
|
|
bitfld.long 0x00 28.--31. " IO02V98THRESCOARSE ,IO0 2.98V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " IO02V98THRESFINE ,IO0 2.98V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " IO01V86THRESCOARSE ,IO0 1.86V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " IO01V86THRESFINE ,IO0 1.86V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " DVDD2V98THRESCOARSE ,DVDD 2.98V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DVDD2V98THRESFINE ,DVDD 2.98V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DVDD1V86THRESCOARSE ,DVDD 1.86V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DVDD1V86THRESFINE ,DVDD 1.86V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "VMONCAL2,VMON Calibration Register 2"
|
|
bitfld.long 0x00 28.--31. " IO12V98THRESCOARSE ,IO1 2.98V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " IO12V98THRESFINE ,IO1 2.98V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " IO11V86THRESCOARSE ,IO1 1.86V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " IO11V86THRESFINE ,IO1 1.86V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " BUVDD2V98THRESCOARSE ,BUVDD 2.98V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " BUVDD2V98THRESFINE ,BUVDD 2.98V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " BUVDD1V86THRESCOARSE ,BUVDD 1.86V coarse threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " BUVDD1V86THRESFINE ,BUVDD 1.86V fine threshold adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "IDAC Calibration Register"
|
|
rgroup.long 0x158++0x07
|
|
line.long 0x00 "IDAC0CAL0,IDAC0 Calibration Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SOURCERANGE3TUNING ,Calibrated middle step (16) of current source mode range 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SOURCERANGE2TUNING ,Calibrated middle step (16) of current source mode range 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SOURCERANGE1TUNING ,Calibrated middle step (16) of current source mode range 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SOURCERANGE0TUNING ,Calibrated middle step (16) of current source mode range 0"
|
|
line.long 0x04 "IDAC0CAL1,IDAC0 Calibration Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " SKINRANGE3TUNING ,Calibrated middle step (16) of current skin mode range 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SKINRANGE2TUNING ,Calibrated middle step (16) of current skin mode range 2"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " SKINRANGE1TUNING ,Calibrated middle step (16) of current skin mode range 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SKINRANGE0TUNING ,Calibrated middle step (16) of current skin mode range 0"
|
|
tree.end
|
|
tree "DCDC Registers"
|
|
rgroup.long 0x168++0x1B
|
|
line.long 0x00 "DCDCLNVCTRL0,DCDC Low-Noise VREF Trim Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " 3V0LNATT1 ,DCDC LNVREF trim for 3.0V output and LNATT=1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " 1V8LNATT1 ,DCDC LNVREF trim for 1.8V output and LNATT=1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " 1V8LNATT0 ,DCDC LNVREF trim for 1.8V output and LNATT=0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " 1V2LNATT0 ,DCDC LNVREF trim for 1.2V output and LNATT=0"
|
|
line.long 0x04 "DCDCLPVCTRL0,DCDC Low-Power VREF Trim Register 0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " 1V8LPATT0LPCMBIAS1 ,DCDC LPVREF trim for 1.8V output and LPATT=0 and LPCMBIAS=1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " 1V2LPATT0LPCMBIAS1 ,DCDC LPVREF trim for 1.2V output and LPATT=0 and LPCMBIAS=1"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " 1V8LPATT0LPCMBIAS0 ,DCDC LPVREF trim for 1.8V output and LPATT=0 and LPCMBIAS=0"
|
|
hexmask.long.byte 0x04 0.--7. 1. " 1V2LPATT0LPCMBIAS0 ,DCDC LPVREF trim for 1.2V output and LPATT=0 and LPCMBIAS=0"
|
|
line.long 0x08 "DCDCLPVCTRL1,DCDC Low-Power VREF Trim Register 1"
|
|
hexmask.long.byte 0x08 24.--31. 1. " 1V8LPATT0LPCMBIAS3 ,DCDC LPVREF trim for 1.8V output and LPATT=0 and LPCMBIAS=3"
|
|
hexmask.long.byte 0x08 16.--23. 1. " 1V2LPATT0LPCMBIAS3 ,DCDC LPVREF trim for 1.2V output and LPATT=0 and LPCMBIAS=3"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " 1V8LPATT0LPCMBIAS2 ,DCDC LPVREF trim for 1.8V output and LPATT=0 and LPCMBIAS=2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " 1V2LPATT0LPCMBIAS2 ,DCDC LPVREF trim for 1.2V output and LPATT=0 and LPCMBIAS=2"
|
|
line.long 0x0C "DCDCLPVCTRL2,DCDC Low-Power VREF Trim Register 2"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " 3V0LPATT1LPCMBIAS1 ,DCDC LPVREF trim for 3.0V output and LPATT=1 and LPCMBIAS=1"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " 1V8LPATT1LPCMBIAS1 ,DCDC LPVREF trim for 1.8V output and LPATT=1 and LPCMBIAS=1"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " 3V0LPATT1LPCMBIAS0 ,DCDC LPVREF trim for 3.0V output and LPATT=1 and LPCMBIAS=0"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " 1V8LPATT1LPCMBIAS0 ,DCDC LPVREF trim for 1.8V output and LPATT=1 and LPCMBIAS=0"
|
|
line.long 0x10 "DCDCLPVCTRL3,DCDC Low-Power VREF Trim Register 3"
|
|
hexmask.long.byte 0x10 24.--31. 1. " 3V0LPATT1LPCMBIAS3 ,DCDC LPVREF trim for 3.0V output and LPATT=1 and LPCMBIAS=3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " 1V8LPATT1LPCMBIAS3 ,DCDC LPVREF trim for 1.8V output and LPATT=1 and LPCMBIAS=3"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " 3V0LPATT1LPCMBIAS2 ,DCDC LPVREF trim for 3.0V output and LPATT=1 and LPCMBIAS=2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " 1V8LPATT1LPCMBIAS2 ,DCDC LPVREF trim for 1.8V output and LPATT=1 and LPCMBIAS=2"
|
|
line.long 0x14 "DCDCLPCMPHYSSEL0,DCDC LPCMPHYSSEL Trim Register 0"
|
|
hexmask.long.byte 0x14 8.--15. 1. " LPCMPHYSSELLPATT1 ,DCDC LPCMPHYSSEL trim for LPATT=1"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LPCMPHYSSELLPATT0 ,DCDC LPCMPHYSSEL trim for LPATT=0"
|
|
line.long 0x18 "DCDCLPCMPHYSSEL1,DCDC LPCMPHYSSEL Trim Register 1"
|
|
hexmask.long.byte 0x18 24.--31. 1. " LPCMPHYSSELLPCMPBIAS3 ,DCDC LPCMPHYSSEL trim for LPCMPBIAS=3"
|
|
hexmask.long.byte 0x18 16.--23. 1. " LPCMPHYSSELLPCMPBIAS2 ,DCDC LPCMPHYSSEL trim for LPCMPBIAS=2"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. " LPCMPHYSSELLPCMPBIAS1 ,DCDC LPCMPHYSSEL trim for LPCMPBIAS=1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " LPCMPHYSSELLPCMPBIAS0 ,DCDC LPCMPHYSSEL trim for LPCMPBIAS=0"
|
|
tree.end
|
|
tree "VDAC Registers"
|
|
rgroup.long 0x184++0x0B
|
|
line.long 0x00 "VDAC0MAINCAL,VDAC0 Cals for Main Path"
|
|
bitfld.long 0x00 24.--29. " GAINERRTRIMVDDANAEXTPIN ,Gain error trim value for DAC main output using references VDDANA and EXTPIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18.--23. " GAINERRTRIM2V5 ,Gain error trim value for DAC main output using reference 2.50V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 12.--17. " GAINERRTRIM1V25 ,Gain error trim value for DAC main output using reference 1.25V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x00 6.--11. " GAINERRTRIM2V5LN ,Gain error trim value for DAC main output using reference 2.50V LN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAINERRTRIM1V25LN ,Gain error trim value for DAC main output using reference 1.25V LN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
line.long 0x04 "VDAC0ALTCAL,VDAC0 Cals for Alternative Path"
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|
bitfld.long 0x04 24.--29. " GAINERRTRIMVDDANAEXTPINALT ,Gain error trim value for DAC alternative output using references VDDANA and EXTPIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x04 18.--23. " GAINERRTRIM2V5ALT ,Gain error trim value for DAC alternative output using reference 2.50V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x04 12.--17. " GAINERRTRIM1V25ALT ,Gain error trim value for DAC alternative output using reference 1.25V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x04 6.--11. " GAINERRTRIM2V5LNALT ,Gain error trim value for DAC alternative output using reference 2.50V LN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x04 0.--5. " GAINERRTRIM1V25LNALT ,Gain error trim value for DAC alternative output using reference 1.25V LN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
line.long 0x08 "VDAC0CH1CAL,VDAC0 CH1 Error Cal"
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|
bitfld.long 0x08 8.--11. " GAINERRTRIMCH1B ,Gain error trim value for channel 1 main output for references 2V5LN / 2V5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x08 4.--7. " GAINERRTRIMCH1A ,Gain error trim value for channel 1 main output for references 1V25LN / 1V25 / VDDANA / EXTPIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x08 0.--2. " OFFSETTRIM ,Input buffer offset calibration value for all DAC references" "0,1,2,3,4,5,6,7"
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tree.end
|
|
width 10.
|
|
tree "OPA Registers"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "OPA0CAL0,OPA0 Calibration Register for DRIVESTRENGTH=0 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "OPA0CAL1,OPA0 Calibration Register for DRIVESTRENGTH=1 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "OPA0CAL2,OPA0 Calibration Register for DRIVESTRENGTH=2 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "OPA0CAL3,OPA0 Calibration Register for DRIVESTRENGTH=3 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "OPA0CAL4,OPA0 Calibration Register for DRIVESTRENGTH=0 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "OPA0CAL5,OPA0 Calibration Register for DRIVESTRENGTH=1 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
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|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "OPA0CAL6,OPA0 Calibration Register for DRIVESTRENGTH=2 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "OPA0CAL7,OPA0 Calibration Register for DRIVESTRENGTH=3 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "OPA1CAL0,OPA1 Calibration Register for DRIVESTRENGTH=0 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "OPA1CAL1,OPA1 Calibration Register for DRIVESTRENGTH=1 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "OPA1CAL2,OPA1 Calibration Register for DRIVESTRENGTH=2 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "OPA1CAL3,OPA1 Calibration Register for DRIVESTRENGTH=3 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "OPA1CAL4,OPA1 Calibration Register for DRIVESTRENGTH=0 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "OPA1CAL5,OPA1 Calibration Register for DRIVESTRENGTH=1 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "OPA1CAL6,OPA1 Calibration Register for DRIVESTRENGTH=2 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "OPA1CAL7,OPA1 Calibration Register for DRIVESTRENGTH=3 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "OPA2CAL0,OPA2 Calibration Register for DRIVESTRENGTH=0 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "OPA2CAL1,OPA2 Calibration Register for DRIVESTRENGTH=1 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "OPA2CAL2,OPA2 Calibration Register for DRIVESTRENGTH=2 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "OPA2CAL3,OPA2 Calibration Register for DRIVESTRENGTH=3 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "OPA2CAL4,OPA2 Calibration Register for DRIVESTRENGTH=0 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "OPA2CAL5,OPA2 Calibration Register for DRIVESTRENGTH=1 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "OPA2CAL6,OPA2 Calibration Register for DRIVESTRENGTH=2 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "OPA2CAL7,OPA2 Calibration Register for DRIVESTRENGTH=3 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1F0++0x03
|
|
line.long 0x00 "OP30CAL0,OPA3 Calibration Register for DRIVESTRENGTH=0 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1F4++0x03
|
|
line.long 0x00 "OP30CAL1,OPA3 Calibration Register for DRIVESTRENGTH=1 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1F8++0x03
|
|
line.long 0x00 "OP30CAL2,OPA3 Calibration Register for DRIVESTRENGTH=2 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "OP30CAL3,OPA3 Calibration Register for DRIVESTRENGTH=3 and INCBW=1"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "OP30CAL4,OPA3 Calibration Register for DRIVESTRENGTH=0 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "OP30CAL5,OPA3 Calibration Register for DRIVESTRENGTH=1 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "OP30CAL6,OPA3 Calibration Register for DRIVESTRENGTH=2 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "OP30CAL7,OPA3 Calibration Register for DRIVESTRENGTH=3 and INCBW=0"
|
|
hexmask.long.byte 0x00 26.--30. 0x04 " OFFSETN ,OPA inverting input offset configuration value"
|
|
hexmask.long.word 0x00 20.--24. 0x10 " OFFSETP ,OPA non-inverting input offset configuration value"
|
|
bitfld.long 0x00 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x00 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 18.
|
|
tree "Cap Sense Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "CSENGAINCAL,Cap Sense Gain Adjustment Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GAINCAL ,Gain adjustment for cap sense"
|
|
tree.end
|
|
tree "USHFRCO Registers"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "USHFRCOCAL7,USHFRCO Calibration Register (16 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,USHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,USHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,USHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,USHFRCO LDO high power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,USHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,USHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,USHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,USHFRCO tuning value"
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "USHFRCOCAL11,USHFRCO Calibration Register (32 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,USHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,USHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,USHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,USHFRCO LDO high power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,USHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,USHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,USHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,USHFRCO tuning value"
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "USHFRCOCAL13,USHFRCO Calibration Register (48 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,USHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,USHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,USHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,USHFRCO LDO high power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,USHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,USHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,USHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,USHFRCO tuning value"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "USHFRCOCAL14,USHFRCO Calibration Register (50 MHz)"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,USHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,USHFRCO enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,USHFRCO clock output divide" "0,1,2,3"
|
|
bitfld.long 0x00 24. " LDOHP ,USHFRCO LDO high power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,USHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,USHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,USHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,USHFRCO tuning value"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSC (Memory System Controller)"
|
|
base ad:0x40000000
|
|
width 19.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Memory System Control Register"
|
|
bitfld.long 0x00 12. " WAITMODE ,Peripheral access wait mode select" "WS0,WS1"
|
|
bitfld.long 0x00 6. " EBIFAULTEN ,EBI bus fault response enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RAMECCERRFAULTEN ,Two bit ECC error bus fault response enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMEOUTFAULTEN ,Timeout bus fault response enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " IFCREADCLEAR ,IFC read clears IF" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " PWRUPONDEMAND ,Power up on demand during wake up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKDISFAULTEN ,Clock-disabled bus fault response enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADDRFAULTEN ,Invalid address bus fault response enable" "Disabled,Enabled"
|
|
line.long 0x04 "READCTRL,Read Control Register"
|
|
bitfld.long 0x04 28. " SCBTP ,Suppress conditional branch target prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--25. " MODE ,Read wait-states" "Zero,One,Two,Three"
|
|
bitfld.long 0x04 10. " QSPICDIS ,QSPI cache disabled" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 9. " USEHPROT ,AHB_HPROT mode" "Not cacheable,Cacheable"
|
|
bitfld.long 0x04 8. " PREFETCH ,Prefetch mode" "0,1"
|
|
bitfld.long 0x04 6. " EBICDIS ,External bus interface cache disabled" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 5. " ICCDIS ,Interrupt context cache disabled" "No,Yes"
|
|
bitfld.long 0x04 4. " AIDIS ,Automatic invalidate disabled" "No,Yes"
|
|
bitfld.long 0x04 3. " IFCDIS ,Internal flash cache disabled" "No,Yes"
|
|
line.long 0x08 "WRITECTRL,Write Control Register"
|
|
bitfld.long 0x08 5. " RWWEN ,Read-while-write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " IRQERASEABORT ,Abort page erase on interrupt" "No effect,Aborted"
|
|
bitfld.long 0x08 0. " WREN ,Enable write/erase controller" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "WRITECMD,Write Command Register"
|
|
bitfld.long 0x00 12. " CLEARWDATA ,Clear WDATA state" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ERASEMAIN1 ,Mass erase region 1" "No effect,Erase"
|
|
bitfld.long 0x00 8. " ERASEMAIN0 ,Mass erase region 0" "No effect,Erase"
|
|
newline
|
|
bitfld.long 0x00 5. " ERASEABORT ,Abort erase sequence" "No effect,Abort"
|
|
bitfld.long 0x00 4. " WRITETRIG ,Word write sequence trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 3. " WRITEONCE ,Word write-once trigger" "No effect,Trigger"
|
|
newline
|
|
bitfld.long 0x00 2. " WRITEEND ,End write mode" "No effect,End write"
|
|
bitfld.long 0x00 1. " ERASEPAGE ,Erase page" "No effect,Erase"
|
|
bitfld.long 0x00 0. " LADDRIM ,Load ADDRB into ADDR" "No effect,Load"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADDRB,Page Erase/Write Address Buffer"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "WDATA,Write Data Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 28.--31. " PWRUPCKBDFAILCNT ,Flash power up checkerboard pattern check fail count" "0,1,2,3,4,5,6,8,7,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " WDATAVALID ,Write data buffer valid flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " BANKSWITCHED ,Bank switching status" "Region 0,Region 1"
|
|
bitfld.long 0x00 6. " PCRUNNING ,Performance counters running" "Not running,Running"
|
|
newline
|
|
bitfld.long 0x00 5. " ERASEABORTED ,The current flash erase operation aborted" "Not aborted,Aborted"
|
|
bitfld.long 0x00 4. " WORDTIMEOUT ,Flash write word timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 3. " WDATAREADY ,WDATA write ready" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 2. " INVADDR ,Invalid write address or erase page" "Valid,Not valid"
|
|
bitfld.long 0x00 1. " LOCKED ,Access locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " BUSY ,Erase/write busy" "Not busy,Busy"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " RAM1ERR2B ,RAM1 2-bit ECC error interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " RAM1ERR1B ,RAM1 1-bit ECC error interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RAMERR2B ,RAM1 2-bit ECC error interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " RAMERR1B ,RAM1 1-bit ECC error interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " LVEWRITE ,Flash LVE write error flag" "No error,Error"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " WDATAOV ,Flash controller write buffer overflow" "No overflow,Overflow"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ICACHERR ,ICache RAM parity error flag" "No error,Error"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PWRUPF ,Flash power up sequence complete flag" "Not completed,Completed"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CMOF ,Cache misses overflow interrupt flag" "No overflow,Overflow"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CHOF ,Cache hits overflow interrupt flag" "No overflow,Overflow"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WRITE ,Write done interrupt read flag" "Pending,Done"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERASE ,Erase done interrupt read flag" "Pending,Done"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 19. " RAM1ERR2B ,RAM1 2-bit ECC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RAM1ERR1B ,RAM1 1-bit ECC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RAMERR2B ,RAM1 2-bit ECC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RAMERR1B ,RAM1 1-bit ECC interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " LVEWRITE ,Flash LVE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WDATAOV ,Flash controller write buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ICACHERR ,ICache RAM parity interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWRUPF ,Flash power up sequence complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CMOF ,Cache misses overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHOF ,Cache hits overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WRITE ,Write done interrupt read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERASE ,Erase done interrupt read enable" "Disabled,Enabled"
|
|
line.long 0x04 "LOCK,Configuration Lock Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOCKKEY ,Configuration lock"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "CACHECMD,Flash Cache Command Register"
|
|
bitfld.long 0x00 2. " STOPPC ,Stop performance counters" "No effect,Stop"
|
|
bitfld.long 0x00 1. " STARTPC ,Start performance counters" "No effect,Start"
|
|
bitfld.long 0x00 0. " INVCACHE ,Invalidate instruction cache" "No effect,Invalidate"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "CACHEHITS,Cache Hits Performance Counter"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CACHEHITS ,Cache hits since last performance counter start command"
|
|
line.long 0x04 "CACHEMISSES,Cache Misses Performance Counter"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " CACHEMISSES ,Cache misses since last performance counter start command"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MASSLOCK,Mass Erase Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Mass erase lock"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "STARTUP,Startup Control"
|
|
bitfld.long 0x00 28.--30. " STWS ,Startup wait-states" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " STWSAEN ,Startup wait-states always enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " STWSEN ,Startup wait-states enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " ASTWAIT ,Active startup wait enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 12.--21. 1. " STDLY1 ,Startup delay 1"
|
|
hexmask.long.word 0x00 0.--9. 1. " STDLY0 ,Startup delay 0"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BANKSWITCHLOCK,Bank Switching Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Bank switching lock"
|
|
wgroup.long 0x74++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " SWITCHINGBANK ,Bank switching command" "No effect,Switch"
|
|
bitfld.long 0x00 0. " PWRUP ,Flash power up command" "No effect,Power up"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BOOTLOADERCTRL,Bootloader Read and Write Enable"
|
|
bitfld.long 0x00 1. " BLWDIS ,Flash bootloader write/erase disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BLRDIS ,Flash bootloader read disable" "No,Yes"
|
|
wgroup.long 0x94++0x03
|
|
line.long 0x00 "AAPUNLOCKCMD,Software Unlock AAP Command Register"
|
|
bitfld.long 0x00 0. " UNLOCKAAP ,Software unlock AAP command" "No effect,Unlock"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CACHECONFIG0,Cache Configuration Register 0"
|
|
bitfld.long 0x00 0.--1. " CACHELPLEVEL ,Instruction cache low-power level" "Base,Advanced,,MINACTIVITY"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "RAMCTRL,RAM Control Enable Register"
|
|
bitfld.long 0x00 18. " RAM2PREFETCHEN ,RAM2 prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RAM2WSEN ,RAM2 wait-state enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RAM2CACHEEN ,RAM2 cache enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAM1PREFETCHEN ,RAM1 prefetch enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RAM1WSEN ,RAM1 wait-state enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RAMPREFETCHEN ,RAM prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RAMWSEN ,RAM wait-state enable" "Disabled,Enabled"
|
|
line.long 0x04 "ECCCTRL,RAM ECC Control Register"
|
|
bitfld.long 0x04 3. " RAM1ECCCHKEN ,RAM1 ECC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RAM1ECCEWEN ,RAM1 ECC write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RAMECCCHKEN ,RAM ECC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RAMECCEWEN ,RAM ECC write enable" "Disabled,Enabled"
|
|
rgroup.long 0x108++0x07
|
|
line.long 0x00 "RAMECCADDR,RAM ECC Error Address Register"
|
|
line.long 0x04 "RAM1ECCADDR,RAM1 ECC Error Address Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LDMA (Linked DMA Controller)"
|
|
base ad:0x40002000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,DMA Control Register"
|
|
bitfld.long 0x00 24.--28. " NUMFIXED ,Number of fixed priority channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SYNCPRSCLREN[7] ,Synchronization PRS[7] clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [6] ,Synchronization PRS[6] clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [5] ,Synchronization PRS[5] clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [4] ,Synchronization PRS[4] clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,Synchronization PRS[3] clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [2] ,Synchronization PRS[2] clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [1] ,Synchronization PRS[1] clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [0] ,Synchronization PRS[0] clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SYNCPRSCLREN[7] ,Synchronization PRS[7] set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Synchronization PRS[6] set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Synchronization PRS[5] set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Synchronization PRS[4] set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Synchronization PRS[3] set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Synchronization PRS[2] set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Synchronization PRS[1] set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Synchronization PRS[0] set enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,DMA Status Register"
|
|
bitfld.long 0x00 24.--28. " CHNUM ,Number of channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 16.--20. " FIFOLEVEL ,FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " CHERROR ,Errant channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x00 3.--7. " CHGRANT ,Granted channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 1. " ANYREQ ,Any DMA channel request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ANYBUSY ,Any DMA channel busy" "Not busy,Busy"
|
|
newline
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SYNC,DMA Synchronization Trigger Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SYNCTRIG ,Synchronization trigger"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHEN,DMA Channel Enable Register"
|
|
bitfld.long 0x00 23. " CHEN[23] ,Channel [23] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CHBUSY,DMA Channel Busy Register"
|
|
bitfld.long 0x00 23. " BUSY[23] ,Channel [23] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] busy" "Not busy,Busy"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "CHDONE,DMA Channel Done Register"
|
|
bitfld.long 0x00 23. " CHDONE[23] ,DMA channel [23] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 22. " [22] ,DMA channel [22] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 21. " [21] ,DMA channel [21] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 20. " [20] ,DMA channel [20] linking or done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,DMA channel [19] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 18. " [18] ,DMA channel [18] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 17. " [17] ,DMA channel [17] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 16. " [16] ,DMA channel [16] linking or done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,DMA channel [15] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 14. " [14] ,DMA channel [14] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 13. " [13] ,DMA channel [13] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 12. " [12] ,DMA channel [12] linking or done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,DMA channel [11] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 10. " [10] ,DMA channel [10] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 9. " [9] ,DMA channel [9] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 8. " [8] ,DMA channel [8] linking or done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,DMA channel [7] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel [6] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel [5] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel [4] linking or done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,DMA channel [3] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 2. " [2] ,DMA channel [2] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 1. " [1] ,DMA channel [1] linking or done" "Not done,Done"
|
|
bitfld.long 0x00 0. " [0] ,DMA channel [0] linking or done" "Not done,Done"
|
|
line.long 0x04 "DBGHALT,DMA Channel Debug Halt Register"
|
|
bitfld.long 0x04 23. " DBGHALT[23] ,DMA channel [23] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 22. " [22] ,DMA channel [22] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 21. " [21] ,DMA channel [21] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 20. " [20] ,DMA channel [20] halt" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,DMA channel [19] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 18. " [18] ,DMA channel [18] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 17. " [17] ,DMA channel [17] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 16. " [16] ,DMA channel [16] halt" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,DMA channel [15] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 14. " [14] ,DMA channel [14] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 13. " [13] ,DMA channel [13] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 12. " [12] ,DMA channel [12] halt" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,DMA channel [11] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 10. " [10] ,DMA channel [10] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 9. " [9] ,DMA channel [9] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 8. " [8] ,DMA channel [8] halt" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,DMA channel [7] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 6. " [6] ,DMA channel [6] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 5. " [5] ,DMA channel [5] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 4. " [4] ,DMA channel [4] halt" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,DMA channel [3] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 2. " [2] ,DMA channel [2] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 1. " [1] ,DMA channel [1] halt" "Not halted,Halted"
|
|
bitfld.long 0x04 0. " [0] ,DMA channel [0] halt" "Not halted,Halted"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SWREQ,DMA Channel Software Transfer Request Register"
|
|
bitfld.long 0x00 23. " SWREQ[23] ,DMA channel [23] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 22. " [22] ,DMA channel [22] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 21. " [21] ,DMA channel [21] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 20. " [20] ,DMA channel [20] software transfer request" "No action,Request"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,DMA channel [19] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 18. " [18] ,DMA channel [18] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 17. " [17] ,DMA channel [17] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 16. " [16] ,DMA channel [16] software transfer request" "No action,Request"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,DMA channel [15] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 14. " [14] ,DMA channel [14] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 13. " [13] ,DMA channel [13] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 12. " [12] ,DMA channel [12] software transfer request" "No action,Request"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,DMA channel [11] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 10. " [10] ,DMA channel [10] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 9. " [9] ,DMA channel [9] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 8. " [8] ,DMA channel [8] software transfer request" "No action,Request"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,DMA channel [7] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel [6] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel [5] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel [4] software transfer request" "No action,Request"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,DMA channel [3] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 2. " [2] ,DMA channel [2] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 1. " [1] ,DMA channel [1] software transfer request" "No action,Request"
|
|
bitfld.long 0x00 0. " [0] ,DMA channel [0] software transfer request" "No action,Request"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "REQDIS,DMA Channel Request Disable Register"
|
|
bitfld.long 0x00 23. " REQDIS[23] ,DMA channel [23] request disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,DMA channel [22] request disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,DMA channel [21] request disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,DMA channel [20] request disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,DMA channel [19] request disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,DMA channel [18] request disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,DMA channel [17] request disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,DMA channel [16] request disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,DMA channel [15] request disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,DMA channel [14] request disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,DMA channel [13] request disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,DMA channel [12] request disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,DMA channel [11] request disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,DMA channel [10] request disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,DMA channel [9] request disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,DMA channel [8] request disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,DMA channel [7] request disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel [6] request disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel [5] request disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel [4] request disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,DMA channel [3] request disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,DMA channel [2] request disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,DMA channel [1] request disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,DMA channel [0] request disable" "No,Yes"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "REQPEND,DMA Channel Request Pending Register"
|
|
bitfld.long 0x00 23. " REQPEND[23] ,DMA channel [23] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,DMA channel [22] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,DMA channel [21] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,DMA channel [20] request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,DMA channel [19] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,DMA channel [18] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,DMA channel [17] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,DMA channel [16] request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,DMA channel [15] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,DMA channel [14] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,DMA channel [13] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,DMA channel [12] request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,DMA channel [11] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,DMA channel [10] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,DMA channel [9] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,DMA channel [8] request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,DMA channel [7] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel [6] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel [5] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel [4] request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,DMA channel [3] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,DMA channel [2] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,DMA channel [1] request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,DMA channel [0] request pending" "Not pending,Pending"
|
|
wgroup.long 0x3C++0x07
|
|
line.long 0x00 "LINKLOAD,DMA Channel Link Load Register"
|
|
bitfld.long 0x00 23. " LINKLOAD[23] ,DMA channel [23] link load" "No effect,Load"
|
|
bitfld.long 0x00 22. " [22] ,DMA channel [22] link load" "No effect,Load"
|
|
bitfld.long 0x00 21. " [21] ,DMA channel [21] link load" "No effect,Load"
|
|
bitfld.long 0x00 20. " [20] ,DMA channel [20] link load" "No effect,Load"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,DMA channel [19] link load" "No effect,Load"
|
|
bitfld.long 0x00 18. " [18] ,DMA channel [18] link load" "No effect,Load"
|
|
bitfld.long 0x00 17. " [17] ,DMA channel [17] link load" "No effect,Load"
|
|
bitfld.long 0x00 16. " [16] ,DMA channel [16] link load" "No effect,Load"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,DMA channel [15] link load" "No effect,Load"
|
|
bitfld.long 0x00 14. " [14] ,DMA channel [14] link load" "No effect,Load"
|
|
bitfld.long 0x00 13. " [13] ,DMA channel [13] link load" "No effect,Load"
|
|
bitfld.long 0x00 12. " [12] ,DMA channel [12] link load" "No effect,Load"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,DMA channel [11] link load" "No effect,Load"
|
|
bitfld.long 0x00 10. " [10] ,DMA channel [10] link load" "No effect,Load"
|
|
bitfld.long 0x00 9. " [9] ,DMA channel [9] link load" "No effect,Load"
|
|
bitfld.long 0x00 8. " [8] ,DMA channel [8] link load" "No effect,Load"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,DMA channel [7] link load" "No effect,Load"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel [6] link load" "No effect,Load"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel [5] link load" "No effect,Load"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel [4] link load" "No effect,Load"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,DMA channel [3] link load" "No effect,Load"
|
|
bitfld.long 0x00 2. " [2] ,DMA channel [2] link load" "No effect,Load"
|
|
bitfld.long 0x00 1. " [1] ,DMA channel [1] link load" "No effect,Load"
|
|
bitfld.long 0x00 0. " [0] ,DMA channel [0] link load" "No effect,Load"
|
|
line.long 0x04 "REQCLEAR,DMA Channel Request Clear Register"
|
|
bitfld.long 0x04 23. " REQCLEAR[23] ,DMA channel [23] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 22. " [22] ,DMA channel [22] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 21. " [21] ,DMA channel [21] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " [20] ,DMA channel [20] request clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,DMA channel [19] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 18. " [18] ,DMA channel [18] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " [17] ,DMA channel [17] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " [16] ,DMA channel [16] request clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,DMA channel [15] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,DMA channel [14] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 13. " [13] ,DMA channel [13] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,DMA channel [12] request clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,DMA channel [11] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " [10] ,DMA channel [10] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,DMA channel [9] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,DMA channel [8] request clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,DMA channel [7] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,DMA channel [6] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,DMA channel [5] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,DMA channel [4] request clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,DMA channel [3] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,DMA channel [2] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [1] ,DMA channel [1] request clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,DMA channel [0] request clear" "No effect,Clear"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " ERROR ,Transfer error interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " DONE[23] ,DMA channel [23] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,DMA channel [22] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,DMA channel [21] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,DMA channel [20] DONE interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,DMA channel [19] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,DMA channel [18] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,DMA channel [17] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,DMA channel [16] DONE interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,DMA channel [15] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,DMA channel [14] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,DMA channel [13] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,DMA channel [12] DONE interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,DMA channel [11] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,DMA channel [10] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,DMA channel [9] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,DMA channel [8] DONE interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,DMA channel [7] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,DMA channel [6] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,DMA channel [5] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,DMA channel [4] DONE interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,DMA channel [3] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,DMA channel [2] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,DMA channel [1] DONE interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,DMA channel [0] DONE interrupt flag" "No error,Error"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " ERROR ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " DONE[23] ,DMA channel [23] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,DMA channel [22] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,DMA channel [21] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,DMA channel [20] done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,DMA channel [19] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,DMA channel [18] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,DMA channel [17] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,DMA channel [16] done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,DMA channel [15] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,DMA channel [14] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,DMA channel [13] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,DMA channel [12] done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,DMA channel [11] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,DMA channel [10] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,DMA channel [9] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,DMA channel [8] done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,DMA channel [7] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,DMA channel [6] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,DMA channel [5] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,DMA channel [4] done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,DMA channel [3] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,DMA channel [2] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,DMA channel [1] done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,DMA channel [0] done interrupt enable" "Disabled,Enabled"
|
|
tree "Channel 0 Registers"
|
|
group.long 0x80++0x1B
|
|
line.long 0x00 "CH0_REQSEL,Channel 0 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH0_CFG,Channel 0 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH0_LOOP,Channel 0 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH0_CTRL,Channel 0 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH0_SRC,Channel 0 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH0_DST,Channel 0 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH0_LINK,Channel 0 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 1 Registers"
|
|
group.long 0xB0++0x1B
|
|
line.long 0x00 "CH1_REQSEL,Channel 1 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH1_CFG,Channel 1 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH1_LOOP,Channel 1 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH1_CTRL,Channel 1 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH1_SRC,Channel 1 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH1_DST,Channel 1 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH1_LINK,Channel 1 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 2 Registers"
|
|
group.long 0xE0++0x1B
|
|
line.long 0x00 "CH2_REQSEL,Channel 2 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH2_CFG,Channel 2 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH2_LOOP,Channel 2 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH2_CTRL,Channel 2 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH2_SRC,Channel 2 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH2_DST,Channel 2 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH2_LINK,Channel 2 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 3 Registers"
|
|
group.long 0x110++0x1B
|
|
line.long 0x00 "CH3_REQSEL,Channel 3 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH3_CFG,Channel 3 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH3_LOOP,Channel 3 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH3_CTRL,Channel 3 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH3_SRC,Channel 3 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH3_DST,Channel 3 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH3_LINK,Channel 3 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 4 Registers"
|
|
group.long 0x140++0x1B
|
|
line.long 0x00 "CH4_REQSEL,Channel 4 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH4_CFG,Channel 4 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH4_LOOP,Channel 4 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH4_CTRL,Channel 4 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH4_SRC,Channel 4 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH4_DST,Channel 4 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH4_LINK,Channel 4 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 5 Registers"
|
|
group.long 0x170++0x1B
|
|
line.long 0x00 "CH5_REQSEL,Channel 5 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH5_CFG,Channel 5 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH5_LOOP,Channel 5 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH5_CTRL,Channel 5 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH5_SRC,Channel 5 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH5_DST,Channel 5 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH5_LINK,Channel 5 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 6 Registers"
|
|
group.long 0x1A0++0x1B
|
|
line.long 0x00 "CH6_REQSEL,Channel 6 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH6_CFG,Channel 6 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH6_LOOP,Channel 6 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH6_CTRL,Channel 6 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH6_SRC,Channel 6 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH6_DST,Channel 6 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH6_LINK,Channel 6 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 7 Registers"
|
|
group.long 0x1D0++0x1B
|
|
line.long 0x00 "CH7_REQSEL,Channel 7 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH7_CFG,Channel 7 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH7_LOOP,Channel 7 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH7_CTRL,Channel 7 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH7_SRC,Channel 7 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH7_DST,Channel 7 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH7_LINK,Channel 7 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 8 Registers"
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "CH8_REQSEL,Channel 8 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH8_CFG,Channel 8 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH8_LOOP,Channel 8 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH8_CTRL,Channel 8 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH8_SRC,Channel 8 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH8_DST,Channel 8 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH8_LINK,Channel 8 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 9 Registers"
|
|
group.long 0x230++0x1B
|
|
line.long 0x00 "CH9_REQSEL,Channel 9 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH9_CFG,Channel 9 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH9_LOOP,Channel 9 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH9_CTRL,Channel 9 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH9_SRC,Channel 9 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH9_DST,Channel 9 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH9_LINK,Channel 9 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 10 Registers"
|
|
group.long 0x260++0x1B
|
|
line.long 0x00 "CH10_REQSEL,Channel 10 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH10_CFG,Channel 10 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH10_LOOP,Channel 10 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH10_CTRL,Channel 10 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH10_SRC,Channel 10 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH10_DST,Channel 10 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH10_LINK,Channel 10 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 11 Registers"
|
|
group.long 0x290++0x1B
|
|
line.long 0x00 "CH11_REQSEL,Channel 11 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH11_CFG,Channel 11 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH11_LOOP,Channel 11 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH11_CTRL,Channel 11 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH11_SRC,Channel 11 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH11_DST,Channel 11 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH11_LINK,Channel 11 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 12 Registers"
|
|
group.long 0x2C0++0x1B
|
|
line.long 0x00 "CH12_REQSEL,Channel 12 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH12_CFG,Channel 12 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH12_LOOP,Channel 12 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH12_CTRL,Channel 12 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH12_SRC,Channel 12 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH12_DST,Channel 12 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH12_LINK,Channel 12 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 13 Registers"
|
|
group.long 0x2F0++0x1B
|
|
line.long 0x00 "CH13_REQSEL,Channel 13 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH13_CFG,Channel 13 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH13_LOOP,Channel 13 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH13_CTRL,Channel 13 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH13_SRC,Channel 13 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH13_DST,Channel 13 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH13_LINK,Channel 13 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 14 Registers"
|
|
group.long 0x320++0x1B
|
|
line.long 0x00 "CH14_REQSEL,Channel 14 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH14_CFG,Channel 14 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH14_LOOP,Channel 14 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH14_CTRL,Channel 14 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH14_SRC,Channel 14 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH14_DST,Channel 14 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH14_LINK,Channel 14 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 15 Registers"
|
|
group.long 0x350++0x1B
|
|
line.long 0x00 "CH15_REQSEL,Channel 15 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH15_CFG,Channel 15 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH15_LOOP,Channel 15 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH15_CTRL,Channel 15 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH15_SRC,Channel 15 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH15_DST,Channel 15 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH15_LINK,Channel 15 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 16 Registers"
|
|
group.long 0x380++0x1B
|
|
line.long 0x00 "CH16_REQSEL,Channel 16 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH16_CFG,Channel 16 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH16_LOOP,Channel 16 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH16_CTRL,Channel 16 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH16_SRC,Channel 16 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH16_DST,Channel 16 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH16_LINK,Channel 16 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 17 Registers"
|
|
group.long 0x3B0++0x1B
|
|
line.long 0x00 "CH17_REQSEL,Channel 17 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH17_CFG,Channel 17 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH17_LOOP,Channel 17 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH17_CTRL,Channel 17 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH17_SRC,Channel 17 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH17_DST,Channel 17 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH17_LINK,Channel 17 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 18 Registers"
|
|
group.long 0x3E0++0x1B
|
|
line.long 0x00 "CH18_REQSEL,Channel 18 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH18_CFG,Channel 18 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH18_LOOP,Channel 18 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH18_CTRL,Channel 18 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH18_SRC,Channel 18 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH18_DST,Channel 18 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH18_LINK,Channel 18 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 19 Registers"
|
|
group.long 0x410++0x1B
|
|
line.long 0x00 "CH19_REQSEL,Channel 19 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH19_CFG,Channel 19 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH19_LOOP,Channel 19 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH19_CTRL,Channel 19 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH19_SRC,Channel 19 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH19_DST,Channel 19 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH19_LINK,Channel 19 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 20 Registers"
|
|
group.long 0x440++0x1B
|
|
line.long 0x00 "CH20_REQSEL,Channel 20 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH20_CFG,Channel 20 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH20_LOOP,Channel 20 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH20_CTRL,Channel 20 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH20_SRC,Channel 20 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH20_DST,Channel 20 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH20_LINK,Channel 20 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 21 Registers"
|
|
group.long 0x470++0x1B
|
|
line.long 0x00 "CH21_REQSEL,Channel 21 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH21_CFG,Channel 21 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH21_LOOP,Channel 21 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH21_CTRL,Channel 21 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH21_SRC,Channel 21 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH21_DST,Channel 21 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH21_LINK,Channel 21 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 22 Registers"
|
|
group.long 0x4A0++0x1B
|
|
line.long 0x00 "CH22_REQSEL,Channel 22 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH22_CFG,Channel 22 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH22_LOOP,Channel 22 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH22_CTRL,Channel 22 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH22_SRC,Channel 22 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH22_DST,Channel 22 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH22_LINK,Channel 22 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
tree "Channel 23 Registers"
|
|
group.long 0x4D0++0x1B
|
|
line.long 0x00 "CH23_REQSEL,Channel 23 Peripheral Request Select Register"
|
|
bitfld.long 0x00 16.--21. " SOURCESEL ,Source select" "NONE,PRS,,,,,,,ADC0,ADC1,VDAC0,,USART0,USART1,USART2,USART3,USART4,USART5,UART0,UART1,LEUART0,LEUART1,I2C0,I2C1,I2C2,TIMER0,TIMER1,TIMER2,TIMER3,TIMER4,TIMER5,TIMER6,WTIMER0,WTIMER1,WTIMER2,WTIMER3,,,,,,,,,,,,,MSC,CRYPTO0,EBI,,,,,,,,,,,CSEN,LESENSE,?..."
|
|
bitfld.long 0x00 0.--3. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CH23_CFG,Channel 23 Configuration Register"
|
|
bitfld.long 0x04 21. " DSTINCSIGN ,Destination address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 20. " SRCINCSIGN ,Source address increment sign mode select" "Positive,Negative"
|
|
bitfld.long 0x04 16.--17. " ARBSLOTS ,Arbitration slot number select" "One,Two,Four,Eight"
|
|
line.long 0x08 "CH23_LOOP,Channel 23 Loop Counter Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPCNT ,Linked structure sequence loop counter"
|
|
line.long 0x0C "CH23_CTRL,Channel 23 Descriptor Control Word Register"
|
|
rbitfld.long 0x0C 31. " DSTMODE ,Destination addressing mode" "Absolute,Relative"
|
|
rbitfld.long 0x0C 30. " SRCMODE ,Source addressing mode" "Absolute,Relative"
|
|
bitfld.long 0x0C 28.--29. " DSTINC ,Destination address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 26.--27. " SIZE ,Unit data transfer size" "Byte,Halfword,Word,?..."
|
|
newline
|
|
bitfld.long 0x0C 24.--25. " SRCINC ,Source address increment size" "One,Two,Four,None"
|
|
bitfld.long 0x0C 23. " IGNORESREQ ,Ignore single request" "Not ignored,Ignored"
|
|
bitfld.long 0x0C 22. " DECLOOPCNT ,Decrement loop count enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " REQMODE ,DMA request transfer mode select" "Block,All"
|
|
newline
|
|
bitfld.long 0x0C 20. " DONEIFSEN ,DMA operation done interrupt flag set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " BLOCKSIZE ,Block transfer size" "UNIT1,UNIT2,UNIT3,UNIT4,UNIT6,UNIT8,,UNIT16,,UNIT32,UNIT64,UNIT128,UNIT256,UNIT512,UNIT1024,ALL"
|
|
bitfld.long 0x0C 15. " BYTESWAP ,Endian byte swap enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x0C 4.--14. 1. " XFERCNT ,DMA unit data transfer count"
|
|
bitfld.long 0x0C 3. " STRUCTREQ ,Structure DMA transfer request" "No action,Request"
|
|
rbitfld.long 0x0C 0.--1. " STUCTTYPE ,DMA structure type" "Transfer,Synchronize,Write,?..."
|
|
line.long 0x10 "CH23_SRC,Channel 23 Descriptor Source Data Address Register"
|
|
line.long 0x14 "CH23_DST,Channel 23 Descriptor Destination Data Address Register"
|
|
line.long 0x18 "CH23_LINK,Channel 23 Link Structure Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " LINKADDR ,Link structure address"
|
|
bitfld.long 0x18 1. " LINK ,Link next structure" "Not linked,Linked"
|
|
rbitfld.long 0x18 0. " LINKMODE ,Link structure addressing mode" "Absolute,Relative"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "RMU (Reset Management Unit)"
|
|
base ad:0x400e5000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,RMU Control Register"
|
|
bitfld.long 0x00 24.--25. " RESETSTATE ,System software reset state" "0,1,2,3"
|
|
bitfld.long 0x00 12.--14. " PINRMODE ,PIN reset mode select" "Disabled,Limited,Extended,,Full,?..."
|
|
bitfld.long 0x00 8.--10. " SYSRMODE ,Core sysreset reset mode select" "Disabled,Limited,Extended,,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " LOCKUPRMODE ,Core lockup reset mode select" "Disabled,Limited,Extended,,Full,?..."
|
|
bitfld.long 0x00 0.--2. " WDOGRMODE ,WDOG reset mode select" "Disabled,Limited,Extended,,Full,?..."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RSTCAUSE,Reset Cause Register"
|
|
bitfld.long 0x00 16. " EM4RST ,EM4 reset" "Not performed,Performed"
|
|
bitfld.long 0x00 12. " BUMODERST ,Backup mode reset" "Not performed,Performed"
|
|
bitfld.long 0x00 11. " WDOGRST ,Watchdog reset" "Not performed,Performed"
|
|
bitfld.long 0x00 10. " SYSREQRST ,System request reset" "Not performed,Performed"
|
|
newline
|
|
bitfld.long 0x00 9. " LOCKUPRST ,Lockup reset" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " EXTRST ,External pin reset" "Not performed,Performed"
|
|
bitfld.long 0x00 4. " DECBOD ,Brown out detector decouple domain reset" "Not performed,Performed"
|
|
newline
|
|
bitfld.long 0x00 3. " DVDDBOD ,Brown out detector DVDD reset" "Not performed,Performed"
|
|
bitfld.long 0x00 2. " AVDDBOD ,Brown out detector AVDD reset" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " PORST ,Power on reset" "Not performed,Performed"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 0. " RCCLR ,Reset cause clear" "No effect,Clear"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LOCK,Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Configuration lock key"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMU (Energy Management Unit)"
|
|
base ad:0x400e3000
|
|
width 24.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,EMU Control Register"
|
|
bitfld.long 0x00 16.--17. " EM4HVSCALE ,EM4H voltage scale" "VSCALE2,,VSCALE0,RESV"
|
|
bitfld.long 0x00 8.--9. " EM23VSCALE ,EM23 voltage scale" "VSCALE2,,VSCALE0,RESV"
|
|
bitfld.long 0x00 4. " EM23VSCALEAUTOWSEN ,Automatically configures flash and frequency to wakeup from EM or EM3 at low voltage" "Not configured,Configured"
|
|
newline
|
|
bitfld.long 0x00 2. " EM2BODDIS ,Disable BOD in EM2" "No,Yes"
|
|
bitfld.long 0x00 1. " EM2BLOCK ,Energy mode 2 block" "Not blocked,Blocked"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,EMU Status Register"
|
|
bitfld.long 0x00 26. " TEMPACTIVE ,Temperature measurement active" "Not active,Active"
|
|
bitfld.long 0x00 20. " EM4IORET ,IO retention status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " VSCALEBUSY ,System is busy scaling voltage" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " VSCALE ,Current voltage scale value" "VSCALE2,,VSCALE0,RESV"
|
|
bitfld.long 0x00 12. " BURDY ,Backup mode ready" "Not ready,Ready"
|
|
bitfld.long 0x00 7. " VMONBUVDD ,VMON BUVDD channel status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " VMONIO1 ,VMON IOVDD1 channel status" "0,1"
|
|
bitfld.long 0x00 4. " VMONIO0 ,VMON IOVDD0 channel status" "0,1"
|
|
bitfld.long 0x00 3. " VMONDVDD ,VMON DVDD channel status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " VMONALTAVDD ,Alternate VMON AVDD channel status" "0,1"
|
|
bitfld.long 0x00 1. " VMONAVDD ,VMON AVDD channel status" "0,1"
|
|
bitfld.long 0x00 0. " VMONRDY ,VMON ready" "Not ready,Ready"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "LOCK,EMU Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Configuration lock key"
|
|
line.long 0x04 "RAM0CTRL,EMU Memory Control Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RAMPOWERDOWN ,RAM0 blockset power-down"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CMD,EMU Command Register"
|
|
bitfld.long 0x00 6. " EM01VSCALE2 ,EM01 voltage scale command to scale to voltage scale level 2" "No effect,Start"
|
|
bitfld.long 0x00 4. " EM01VSCALE0 ,EM01 voltage scale command to scale to voltage scale level 0" "No effect,Start"
|
|
bitfld.long 0x00 0. " EM4UNLATCH ,EM4 unlatch" "No effect,Execute"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "EM4CTRL,EMU EM4 Control Register"
|
|
bitfld.long 0x00 16.--17. " EM4ENTRY ,Energy mode 4 entry" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " EM4IORETMODE ,EM4 IO retention disable" "Disabled,EM4EXIT,SWUNLATCH,?..."
|
|
bitfld.long 0x00 3. " RETAINULFRCO ,ULFRCO retain during EM4S" "Not retained,Retained"
|
|
newline
|
|
bitfld.long 0x00 2. " RETAINLFXO ,LFXO retain during EM4" "Not retained,Retained"
|
|
bitfld.long 0x00 1. " RETAINLFRCO ,LFRCO retain during EM4" "Not retained,Retained"
|
|
bitfld.long 0x00 0. " EM4STATE ,Energy mode 4 state" "EM4S,EM4H"
|
|
line.long 0x04 "TEMPLIMITS,EMU Temperature Limits for Interrupt Generation"
|
|
bitfld.long 0x04 16. " EM4WUEN ,Enable EM4 wakeup due to low/high temperature" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TEMPHIGH ,Temperature high limit"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TEMPLOW ,Temperature low limit"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TEMP,EMU Value of Last Temperature Measurement"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Temperature measurement"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IF_SET/CLR,EMU Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " TEMPHIGH ,Temperature high limit reached" "Not reached,Reached"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " TEMPLOW ,Temperature low limit reached" "Not reached,Reached"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " TEMP ,New temperature measurement valid" "Not available,Available"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " VSCALEDONE ,Voltage scale steps done IRQ" "Not scaled,Scaled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " EM23WAKEUP ,Wakeup IRQ from EM2 and EM3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " R5VVSINT ,5V regulator voltage update done" "Not updated,Updated"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " BURDY ,Backup functionality ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DCDCINBYPASS ,DCDC is in bypass" "Not bypassed,Bypassed"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " DCDCLNRUNNING ,LN mode is running" "Not running,Running"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " DCDCLPRUNNING ,LP mode is running" "Not running,Running"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " NFETOVERCURRENTLIMIT ,NFET current limit hit" "No hit,Hit"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PFETOVERCURRENTLIMIT ,PFET current limit hit" "No hit,Hit"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " VMONBUVDDRISE ,VMON BUVDD channel rising rise detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " VMONBUVDDFALL ,VMON BUVDD channel falling rise detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " R5VREADY ,5V regulator is ready to use" "Not ready,Ready"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " VMONIO1RISE ,VMON IOVDD1 channel rising edge detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " VMONIO1FALL ,VMON IOVDD1 channel falling edge detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " VMONIO0RISE ,VMON IOVDD0 channel rising edge detect" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " VMONIO0FALL ,VMON IOVDD0 channel falling edge detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " VMONDVDDRISE ,VMON DVDD channel rising edge detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " VMONDVDDFALL ,VMON DVDD channel falling edge detect" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " VMONALTAVDDRISE ,Alternate VMON ADVDD channel rising edge detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " VMONALTAVDDFALL ,Alternate VMON ADVDD channel falling edge detect" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " VMONAVDDRISE ,VMON ADVDD channel rising edge detect" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " VMONAVDDFALL ,VMON ADVDD channel falling edge detect" "Not detected,Detected"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IEN,EMU Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " TEMPHIGH ,Temperature high limit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TEMPLOW ,Temperature low limit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " TEMP ,New temperature measurement interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " VSCALEDONE ,Voltage scale steps done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EM23WAKEUP ,Wakeup IRQ from EM2 and EM3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " R5VVSINT ,5V regulator voltage update done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " BURDY ,Backup functionality ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DCDCINBYPASS ,DCDC is in bypass interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DCDCLNRUNNING ,LN mode is running interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DCDCLPRUNNING ,LP mode is running interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " NFETOVERCURRENTLIMIT ,NFET current limit hit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PFETOVERCURRENTLIMIT ,PFET current limit hit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " VMONBUVDDRISE ,VMON BUVDD channel rise interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " VMONBUVDDFALL ,VMON BUVDD channel fall interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " R5VREADY ,5V regulator is ready to use interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VMONIO1RISE ,VMON IOVDD1 channel rise interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VMONIO1FALL ,VMON IOVDD1 channel fall interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VMONIO0RISE ,VMON IOVDD0 channel rise interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VMONIO0FALL ,VMON IOVDD0 channel fall interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VMONDVDDRISE ,VMON DVDD channel rise interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VMONDVDDFALL ,VMON DVDD channel fall interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " VMONALTAVDDRISE ,Alternate VMON ADVDD channel rise interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VMONALTAVDDFALL ,Alternate VMON ADVDD channel fall interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " VMONAVDDRISE ,VMON ADVDD channel rise interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VMONAVDDFALL ,VMON ADVDD channel fall interrupt enable" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PWRLOCK,EMU Regulator and Supply Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Regulator and supply configuration lock key"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "PWRCTRL,EMU Power Control Register"
|
|
bitfld.long 0x00 13. " IMMEDIATEPWRSWITCH ,Allows immediate switching of ANASW and REGPWRSEL bit-fields" "Not allowed,Allowed"
|
|
bitfld.long 0x00 10. " REGPWRSEL ,This field selects the input supply pin for the digital LDO" "AVDD,DVDD"
|
|
bitfld.long 0x00 5. " ANASW ,Analog switch selection" "AVDD,DVDD"
|
|
line.long 0x04 "DCDCCTRL,EMU DCDC Control Register"
|
|
bitfld.long 0x04 5. " DCDCMODEEM4 ,DCDC mode EM4H" "EM4SW,EM4 low power"
|
|
bitfld.long 0x04 4. " DCDCMODEEM23 ,DCDC mode EM23" "EM23SW,EM23 low power"
|
|
bitfld.long 0x04 0.--1. " DCDCMODE ,Regulator mode" "Bypass,Low noise,Low power,Off"
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "DCDCMISCCTRL,EMU DCDC Miscellaneous Control Register"
|
|
bitfld.long 0x00 28.--29. " LPCMPBIASEM234H ,LP mode comparator bias selection for EM23 or EM4H" "Bias 0,Bias 1,Bias 2,Bias 3"
|
|
bitfld.long 0x00 24.--26. " LNCLIMILIMSEL ,Current limit level selection for current limiter in LN mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " LPCLIMILIMSEL ,Current limit level selection for current limiter in LP mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " BYPLIMSEL ,Current limit in bypass mode" "20 mA,40 mA,60 mA,80 mA,100 mA,120 mA,140 mA,160 mA,180 mA,200 mA,220 mA,240 mA,260 mA,280 mA,300 mA,320 mA"
|
|
bitfld.long 0x00 12.--15. " NFETCNT ,NFET switch number selection" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 8.--11. " PFETCNT ,PFET switch number selection" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
bitfld.long 0x00 5. " LNFORCECCMIMM ,Force DCDC into CCM mode immediately based on LNFORCECCM" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " LNFORCECCM ,Force DCDC into CCM mode in low noise operation" "Zero-crossing,Reverse-current"
|
|
line.long 0x04 "DCDCZDETCTRL,EMU DCDC Power Train NFET Zero Current Detector Control Register"
|
|
bitfld.long 0x04 4.--6. " ZDETILIMSEL ,Reverse current limit level selection for zero detector" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "DCDCCLIMCTRL,EMU DCDC Power Train PFET Current Limiter Control Register"
|
|
bitfld.long 0x08 13. " BYPLIMEN ,Bypass current limit enable" "Disabled,Enabled"
|
|
line.long 0x0C "DCDCLNCOMPCTRL,EMU DCDC Low Noise Compensator Control Register"
|
|
bitfld.long 0x0C 28.--31. " COMPENC3 ,Low noise mode compensator C3 trim value" "0.5 pF,1 pF,1.5 pF,2 pF,2.5 pF,3 pF,3.5 pF,4 pF,4.5 pF,5 pF,5.5 pF,6 pF,6.5 pF,7 pF,7.5 pF,8 pF"
|
|
bitfld.long 0x0C 24.--26. " COMPENC2 ,Low noise mode compensator C2 trim value" "1 pF,2 pF,3 pF,4 pF,5 pF,6 pF,7 pF,8 pF"
|
|
bitfld.long 0x0C 20.--21. " COMPENC1 ,Low noise mode compensator C1 trim value" "0.15 pF,0.30 pF,0.45 pF,0.60 pF"
|
|
newline
|
|
bitfld.long 0x0C 12.--15. " COMPENR3 ,Low noise mode compensator R3 trim value" "5 KOhm,10 KOhm,15 KOhm,20 KOhm,25 KOhm,30 KOhm,35 KOhm,40 KOhm,45 KOhm,50 KOhm,55 KOhm,60 KOhm,65 KOhm,70 KOhm,75 KOhm,80 KOhm"
|
|
bitfld.long 0x0C 4.--8. " COMPENR2 ,Low noise mode compensator R2 trim value" "50 KOhm,100 KOhm,150 KOhm,200 KOhm,250 KOhm,300 KOhm,350 KOhm,400 KOhm,450 KOhm,500 KOhm,550 KOhm,600 KOhm,650 KOhm,700 KOhm,750 KOhm,800 KOhm,850 KOhm,900 KOhm,950 KOhm,1000 KOhm,1050 KOhm,1100 KOhm,1150 KOhm,1200 KOhm,1250 KOhm,1300 KOhm,1350 KOhm,1400 KOhm,1450 KOhm,1500 KOhm,1550 KOhm,1600 KOhm"
|
|
bitfld.long 0x0C 0.--2. " COMPENR1 ,Low noise mode compensator R1 trim value" "500 KOhm,600 KOhm,700 KOhm,800 KOhm,900 KOhm,1000 KOhm,1100 KOhm,1200 KOhm"
|
|
line.long 0x10 "DCDCLNVCTRL,EMU DCDC Low Noise Voltage Register"
|
|
hexmask.long.byte 0x10 8.--14. 1. " LNVREF ,Low noise mode VREF trim"
|
|
bitfld.long 0x10 1. " LNATT ,Low noise mode feedback attenuation" "DIV3,DIV6"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DCDCLPVCTRL,EMU DCDC Low Power Voltage Register"
|
|
hexmask.long.byte 0x00 1.--8. 1. " LPVREF ,LP mode reference selection for EM23 and EM4H"
|
|
bitfld.long 0x00 0. " LPATT ,Low power feedback attenuation" "DIV4,DIV8"
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "DCDCLPCTRL,EMU DCDC Low Power Control Register"
|
|
bitfld.long 0x00 24. " LPVREFDUTYEN ,LP mode duty cycling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " LPCMPHYSSELEM234H ,LP mode hysteresis selection for EM23 and EM4H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "DCDCLNFREQCTRL,EMU DCDC Low Noise Controller Frequency Control"
|
|
bitfld.long 0x04 0.--2. " RCOBAND ,LN mode RCO frequency band selection" "3 MHz,3.85 MHz,4.7 MHz,5.55 MHz,6.4 MHz,7.25 MHz,8.1 MHz,8.95 MHz"
|
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rgroup.long 0x78++0x03
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line.long 0x00 "DCDCSYNC,EMU DCDC Read Status Register"
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|
bitfld.long 0x00 0. " DCDCCTRLBUSY ,DCDC control register transfer busy" "Not busy,Busy"
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group.long 0x90++0x17
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line.long 0x00 "VMONAVDDCTRL,EMU VMON AVDD Channel Control Register"
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bitfld.long 0x00 20.--23. " RISETHRESCOARSE ,Rising threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " RISETHRESFINE ,Rising threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " FALLTHRESCOARSE ,Falling threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--11. " FALLTHRESFINE ,Falling threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. " FALLWU ,Wakeup upon falling edge enable" "Disabled,Enabled"
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|
newline
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bitfld.long 0x00 2. " RISEWU ,Wakeup upon rising edge enable" "Disabled,Enabled"
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|
bitfld.long 0x00 0. " EN ,AVDD VMON enable" "Disabled,Enabled"
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line.long 0x04 "VMONALTAVDDCTRL,EMU Alternate VMON AVDD Channel Control Register"
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bitfld.long 0x04 12.--15. " THRESCOARSE ,Threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 8.--11. " THRESFINE ,Threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 3. " FALLWU ,Wakeup upon falling edge enable" "Disabled,Enabled"
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|
newline
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bitfld.long 0x04 2. " RISEWU ,Wakeup upon rising edge enable" "Disabled,Enabled"
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|
bitfld.long 0x04 0. " EN ,ALTAVDD VMON enable" "Disabled,Enabled"
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line.long 0x08 "VMONDVDDCTRL,EMU VMON DVDD Channel Control Register"
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bitfld.long 0x08 12.--15. " THRESCOARSE ,Threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. " THRESFINE ,Threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 3. " FALLWU ,Wakeup upon falling edge enable" "Disabled,Enabled"
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|
newline
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bitfld.long 0x08 2. " RISEWU ,Wakeup upon rising edge enable" "Disabled,Enabled"
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bitfld.long 0x08 0. " EN ,DVDD VMON enable" "Disabled,Enabled"
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line.long 0x0C "VMONIO0CTRL,EMU VMON IOVDD0 Channel Control Register"
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bitfld.long 0x0C 12.--15. " THRESCOARSE ,Threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. " THRESFINE ,Threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 4. " RETDIS ,EM4 IO0 retention disable" "No,Yes"
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newline
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bitfld.long 0x0C 3. " FALLWU ,Wakeup upon falling edge enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 2. " RISEWU ,Wakeup upon rising edge enable" "Disabled,Enabled"
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bitfld.long 0x0C 0. " EN ,IO0 VMON enable" "Disabled,Enabled"
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line.long 0x10 "VMONIO1CTRL,EMU VMON IOVDD1 Channel Control Register"
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bitfld.long 0x10 12.--15. " THRESCOARSE ,Threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. " THRESFINE ,Threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4. " RETDIS ,EM4 IO1 retention disable" "No,Yes"
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newline
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bitfld.long 0x10 3. " FALLWU ,Wakeup upon falling edge enable" "Disabled,Enabled"
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|
bitfld.long 0x10 2. " RISEWU ,Wakeup upon rising edge enable" "Disabled,Enabled"
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|
bitfld.long 0x10 0. " EN ,IO1 VMON enable" "Disabled,Enabled"
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line.long 0x14 "VMONBUVDDCTRL,EMU VMON BUVDD Channel Control Register"
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bitfld.long 0x14 12.--15. " THRESCOARSE ,Threshold coarse adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. " THRESFINE ,Threshold fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 3. " FALLWU ,Wakeup upon falling edge enable" "Disabled,Enabled"
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newline
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bitfld.long 0x14 2. " RISEWU ,Wakeup upon rising edge enable" "Disabled,Enabled"
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bitfld.long 0x14 0. " EN ,BUVDD VMON enable" "Disabled,Enabled"
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group.long 0xB4++0x0B
|
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line.long 0x00 "RAM1CTRL,EMU Memory 1 Control Register"
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hexmask.long.byte 0x00 0.--7. 1. " RAMPOWERDOWN ,RAM1 blockset power-down"
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line.long 0x04 "RAM2CTRL,EMU Memory 2 Control Register"
|
|
bitfld.long 0x04 0.--3. " RAMPOWERDOWN ,RAM2 blockset power-down" "None,,,,,,,,BLK3,,,,BLK2T03,,BLK1T03,BLK0T03"
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line.long 0x08 "BUCTRL,EMU Backup Power Configuration Register"
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bitfld.long 0x08 31. " DISMAXCOMP ,Disable MAIN-BU comparator" "No,Yes"
|
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bitfld.long 0x08 20.--21. " BUINACTPWRCON ,Power connection configuration when not in backup mode" "None,MAINBU,BUMAIN,NODIODE"
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bitfld.long 0x08 16.--17. " BUACTPWRCON ,Power connection configuration in backup mode" "None,MAINBU,BUMAIN,NODIODE"
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newline
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bitfld.long 0x08 12.--13. " PWRRES ,Power domain resistor select" "RES0,RES1,RES2,RES3"
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|
bitfld.long 0x08 8.--9. " VOUTRES ,BU_VOUT resistor select" "Disabled,WEAK,MED,STRONG"
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|
bitfld.long 0x08 2. " BUVINPROBEEN ,Enable BU_VIN probing" "Disabled,Enabled"
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|
newline
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bitfld.long 0x08 1. " STATEN ,Enable backup mode status export" "Disabled,Enabled"
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bitfld.long 0x08 0. " EN ,Enable backup mode" "Disabled,Enabled"
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group.long 0xC8++0x0B
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line.long 0x00 "R5VCTRL,EMU 5V Regulator Control Register"
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bitfld.long 0x00 8.--9. " INPUTMODE ,5V input mode" "Auto,VBUS,VREGI,?..."
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bitfld.long 0x00 2. " IMOEN ,Enable the regulator current monitor for selected current path to either VREGI or VBUS" "Disabled,Enabled"
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|
newline
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bitfld.long 0x00 1. " EM4WUEN ,Enable EM4 wakeup due to VBUS detection" "Disabled,Enabled"
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bitfld.long 0x00 0. " BYPASS ,5V regulator bypass" "Not bypassed,Bypassed"
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line.long 0x04 "R5VADCCTRL,EMU 5V Regulator Control Register"
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bitfld.long 0x04 12.--15. " AMUXSEL ,ADC mux selection" "VBUSDIV10,VREGIDIV10,VREGODIV6,VREGIMON,VBUSIMON,?..."
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bitfld.long 0x04 0. " ENAMUX ,Enable the 5V subsystem ADC MUX" "Disabled,Enabled"
|
|
line.long 0x08 "R5VOUTLEVEL,EMU 5V Regulator Voltage Select"
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bitfld.long 0x08 0.--3. " OUTLEVEL ,5V regulator voltage" ",2.4 V,2.5 V,2.6 V,2.7 V,2.8 V,2.9 V,3 V,3.1 V,3.2 V,3.3 V,3.4 V,3.5 V,3.6 V,3.7 V,3.8 V"
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group.long 0xDC++0x03
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line.long 0x00 "R5VDETCTRL,EMU 5V Detector Enables Register"
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bitfld.long 0x00 2. " VREGODETDIS ,VREG0 detector disable" "No,Yes"
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bitfld.long 0x00 1. " VBUSDETDIS ,VBUS detector disable" "No,Yes"
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|
bitfld.long 0x00 0. " VREGIDETDIS ,VREGI detector disable" "No,Yes"
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|
group.long 0xEC++0x03
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|
line.long 0x00 "DCDCLPEM01CFG,EMU Configuration Bits for Low Power Mode During EM01 Register"
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|
bitfld.long 0x00 12.--15. " LPCMPHYSSELEM01 ,LP mode hysteresis selection for EM01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--9. " LPCMPBIASEM01 ,LP mode comparator bias selection for EM01" "BIAS0,BIAS1,BIAS2,BIAS3"
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rgroup.long 0xF0++0x03
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line.long 0x00 "R5VSTATUS,EMU 5V Detector Status Register"
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bitfld.long 0x00 5. " COLDSTART ,Regulator is going through cold start" "Not going,Going"
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bitfld.long 0x00 4. " LDODROPOUTDET ,Regulator dropout detection" "Not detected,Detected"
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bitfld.long 0x00 3. " VBUSGTVREGI ,Output of the supply comparator between VBUS and VREGI" "0,1"
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newline
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bitfld.long 0x00 2. " VREGODET ,VREGO detected" "Not detected,Detected"
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bitfld.long 0x00 1. " VBUSDET ,USB VBUS detected" "Not detected,Detected"
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bitfld.long 0x00 0. " VREGIDET ,VREGI detected" "Not detected,Detected"
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rgroup.long 0xF8++0x03
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line.long 0x00 "R5VSYNC,EMU 5V Read Status Register"
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bitfld.long 0x00 0. " OUTLEVELBUSY ,5V regulator voltage register transfer busy" "Not busy,Busy"
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group.long 0x104++0x03
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line.long 0x00 "EM23PERNORETAIN_SETCLR,Peripherals Power Down in EM23 Set/Clear Register"
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setclrfld.long 0x00 24. -0x04 24. 0x04 24. " USBLOCKED ,USB power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 23. -0x04 23. 0x04 23. " RTCLOCKED ,RTC power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 22. -0x04 22. 0x04 22. " ACMP3LOCKED ,ACMP3 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 21. -0x04 21. 0x04 21. " ACMP2LOCKED ,ACMP2 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 20. -0x04 20. 0x04 20. " ADC1LOCKED ,ADC1 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 19. -0x04 19. 0x04 19. " I2C2LOCKED ,I2C2 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 18. -0x04 18. 0x04 18. " LETIMER1LOCKED ,LETIMER1 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 17. -0x04 17. 0x04 17. " LCDLOCKED ,LCD power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 16. -0x04 16. 0x04 16. " LEUART1LOCKED ,LEUART1 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 15. -0x04 15. 0x04 15. " LEUART0LOCKED ,LEUART0 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 14. -0x04 14. 0x04 14. " CSENLOCKED ,CSEN power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 13. -0x04 13. 0x04 13. " LESENSE0LOCKED ,LESENSE0 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 12. -0x04 12. 0x04 12. " WDOG1LOCKED ,WDOG1 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 11. -0x04 11. 0x04 11. " WDOG0LOCKED ,WDOG0 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 10. -0x04 10. 0x04 10. " LETIMER0LOCKED ,LETIMER0 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 9. -0x04 9. 0x04 9. " ADC0LOCKED ,ADC0 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 8. -0x04 8. 0x04 8. " IDAC0LOCKED ,IDAC0 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 7. -0x04 7. 0x04 7. " DAC0LOCKED ,DAC0 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 6. -0x04 6. 0x04 6. " I2C1LOCKED ,I2C1 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 5. -0x04 5. 0x04 5. " I2C0LOCKED ,I2C0 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 4. -0x04 4. 0x04 4. " PCNT2LOCKED ,PCNT2 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 3. -0x04 3. 0x04 3. " PCNT1LOCKED ,PCNT1 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 2. -0x04 2. 0x04 2. " PCNT0LOCKED ,PCNT0 power down during EM23" "Powered up,Powered down"
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newline
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setclrfld.long 0x00 1. -0x04 1. 0x04 1. " ACMP1LOCKED ,ACMP1 power down during EM23" "Powered up,Powered down"
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setclrfld.long 0x00 0. -0x04 0. 0x04 0. " ACMP0LOCKED ,ACMP0 power down during EM23" "Powered up,Powered down"
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width 0x0B
|
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tree.end
|
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tree "CMU (Clock Management Unit)"
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base ad:0x400e4000
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width 21.
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group.long 0x00++0x03
|
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line.long 0x00 "CTRL,CMU Control Register"
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bitfld.long 0x00 20. " HFPERCLKEN ,HFPERCLK enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " WSHFLE ,LE peripherals access allow" "Not allowed,Allowed"
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bitfld.long 0x00 10.--14. " CLKOUTSEL2 ,Clock output select 2" "Disabled,ULFRCO,LFRCO,LFXO,,HFXODIV2Q,HFXO,HFEXPCLK,HFXOX2Q,ULFRCOQ,LFRCOQ,LFXOQ,HFRCOQ,AUXHFRCOQ,HFXOQ,HFSRCCLK,,,USHFRCOQ,?..."
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newline
|
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bitfld.long 0x00 5.--9. " CLKOUTSEL1 ,Clock output select 1" "Disabled,ULFRCO,LFRCO,LFXO,,,HFXO,HFEXPCLK,,ULFRCOQ,LFRCOQ,LFXOQ,HFRCOQ,AUXHFRCOQ,HFXOQ,HFSRCCLK,,,USHFRCOQ,?..."
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bitfld.long 0x00 0.--4. " CLKOUTSEL0 ,Clock output select 0" "Disabled,ULFRCO,LFRCO,LFXO,,,HFXO,HFEXPCLK,,ULFRCOQ,LFRCOQ,LFXOQ,HFRCOQ,AUXHFRCOQ,HFXOQ,HFSRCCLK,,,USHFRCOQ,?..."
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group.long 0x8++0x03
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line.long 0x00 "USHFRCOCTRL,USHFRCO Control Register"
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bitfld.long 0x00 28.--31. " VREFTC ,USHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 27. " FINETUNINGEN ,Enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,Locally divide USHFRCO clock output" "DIV1,DIV2,DIV4,?..."
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bitfld.long 0x00 24. " LDOHP ,USHFRCO LDO high power mode" "Turn off,Turn on"
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newline
|
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bitfld.long 0x00 21.--23. " CMPBIAS ,USHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--20. " FREQRANGE ,USHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--13. " FINETUNING ,USHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,USHFRCO tuning value"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "HFRCOCTRL,HFRCO Control Register"
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|
bitfld.long 0x00 28.--31. " VREFTC ,HFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 27. " FINETUNINGEN ,Enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,Locally divide HFRCO clock output" "DIV1,DIV2,DIV4,?..."
|
|
bitfld.long 0x00 24. " LDOHP ,HFRCO LDO high power mode" "Turn off,Turn on"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,HFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,HFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,HFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,HFRCO tuning value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AUXHFRCOCTRL,AUXHFRCO Control Register"
|
|
bitfld.long 0x00 28.--31. " VREFTC ,AUXHFRCO temperature coefficient trim on comparator reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " FINETUNINGEN ,Enable reference for fine tuning" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " CLKDIV ,Locally divide AUXHFRCO clock output" "DIV1,DIV2,DIV4,?..."
|
|
bitfld.long 0x00 24. " LDOHP ,AUXHFRCO LDO high power mode" "Turn off,Turn on"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " CMPBIAS ,AUXHFRCO comparator bias current" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " FREQRANGE ,AUXHFRCO frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--13. " FINETUNING ,AUXHFRCO fine tuning value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,AUXHFRCO tuning value"
|
|
if (((per.l(ad:0x400e4000+0x90))&0x40)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "LFRCOCTRL,LFRCO Control Register"
|
|
bitfld.long 0x00 28.--31. " GMCCURTUNE ,Tuning of GMC current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--25. " TIMEOUT ,LFRCO timeout" "2 cycles,16 cycles,32 cycles,?..."
|
|
bitfld.long 0x00 20.--21. " VREFUPDATE ,Control vref update rate" "32 cycles,64 cycles,128 cycles,256 cycles"
|
|
bitfld.long 0x00 18. " ENDEM ,Enable dynamic element matching" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " ENCHOP ,Enable comparator chopping" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENVREF ,Enable duty cycling of vref" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " TUNING ,LFRCO tuning value"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "LFRCOCTRL,LFRCO Control Register"
|
|
bitfld.long 0x00 28.--31. " GMCCURTUNE ,Tuning of GMC current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " TIMEOUT ,LFRCO timeout" "2 cycles,16 cycles,32 cycles,?..."
|
|
bitfld.long 0x00 20.--21. " VREFUPDATE ,Control vref update rate" "32 cycles,64 cycles,128 cycles,256 cycles"
|
|
bitfld.long 0x00 18. " ENDEM ,Enable dynamic element matching" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " ENCHOP ,Enable comparator chopping" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENVREF ,Enable duty cycling of vref" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " TUNING ,LFRCO tuning value"
|
|
endif
|
|
if (((per.l(ad:0x400e4000+0x90))&0x04)==0x00)&&(((per.l(ad:0x400e4000+0xF0))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HFXOCTRL,HFXO Control Register"
|
|
bitfld.long 0x00 29. " AUTOSTARTSELEM0EM1 ,Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTOSTARTEM0EM1 ,Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " LFTIMEOUT ,HFXO low frequency timeout" "0 cycles,2 cycles,4 cycles,16 cycles,32 cycles,64 cycles,1024 cycles,4096 cycles"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PEAKDETMODE ,HFXO automatic peak detection mode" "Once CMD,Auto CMD,CMD,Manual"
|
|
bitfld.long 0x00 3. " HFXOX2EN ,Enable double frequency on HFXOX2 clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,HFXO mode" "XTAL,ACBUFEXTCLK,DCBUFEXTCLK,DIGEXTCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HFXOCTRL,HFXO Control Register"
|
|
bitfld.long 0x00 29. " AUTOSTARTSELEM0EM1 ,Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTOSTARTEM0EM1 ,Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--26. " LFTIMEOUT ,HFXO low frequency timeout" "0 cycles,2 cycles,4 cycles,16 cycles,32 cycles,64 cycles,1024 cycles,4096 cycles"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PEAKDETMODE ,HFXO automatic peak detection mode" "Once CMD,Auto CMD,CMD,Manual"
|
|
bitfld.long 0x00 3. " HFXOX2EN ,Enable double frequency on HFXOX2 clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,HFXO mode" "XTAL,ACBUFEXTCLK,DCBUFEXTCLK,DIGEXTCLK"
|
|
endif
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "HFXOCTRL1,HFXO Control 1 Register"
|
|
bitfld.long 0x00 12.--14. " PEAKDETTHR ,Sets the amplitude detection level" "50 mV,75 mV,115 mV,160 mV,220 mV,260 mV,320 mV,320 mV"
|
|
line.long 0x04 "HFXOSTARTUPCTRL,HFXO Startup Control"
|
|
hexmask.long.word 0x04 11.--19. 1. " CTUNE ,Set oscillator tuning capacitance"
|
|
hexmask.long.word 0x04 0.--10. 1. " IBTRIMXOCORE ,Set the startup oscillator core bias current"
|
|
if (((per.l(ad:0x400e4000+0x90))&0x40080)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HFXOSTEADYSTATECTRL,HFXO Steady State Control"
|
|
bitfld.long 0x00 27. " PEAKMONEN ,Automatically perform peak monitoring algorithm on every rising edge of ULFRCO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " PEAKDETEN ,Enables oscillator peak detectors" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 11.--19. 1. " CTUNE ,Sets oscillator tuning capacitance"
|
|
hexmask.long.word 0x00 0.--10. 1. " IBTRIMXOCORE ,Sets the steady state oscillator core bias current"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HFXOSTEADYSTATECTRL,HFXO Steady State Control"
|
|
bitfld.long 0x00 27. " PEAKMONEN ,Automatically perform peak monitoring algorithm on every rising edge of ULFRCO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " PEAKDETEN ,Enables oscillator peak detectors" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 11.--19. 1. " CTUNE ,Sets oscillator tuning capacitance"
|
|
hexmask.long.word 0x00 0.--10. 1. " IBTRIMXOCORE ,Sets the steady state oscillator core bias current"
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HFXOTIMEOUTCTRL,HFXO Timeout Control"
|
|
bitfld.long 0x00 12.--15. " PEAKDETTIMEOUT ,Wait duration in HFXO peak detection wait state" "2 cycles,4 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,?..."
|
|
bitfld.long 0x00 4.--7. " STEADYTIMEOUT ,Wait duration HFXO peak detection wait state" "2 cycles,4 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,?..."
|
|
bitfld.long 0x00 0.--3. " STARTUPTIMEOUT ,Wait duration HFXO startup enable wait state" "2 cycles,4 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,?..."
|
|
if (((per.l(ad:0x400e4000+0x90))&0x100)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "LFXOCTRL,LFXO Control Register"
|
|
bitfld.long 0x00 24.--26. " TIMEOUT ,LFXO timeout" "2 cycles,256 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles"
|
|
bitfld.long 0x00 20. " BUFCUR ,LFXO buffer bias current" "0,1"
|
|
bitfld.long 0x00 16.--17. " CUR ,LFXO current trim" "0,1,2,3"
|
|
bitfld.long 0x00 15. " AGC ,LFXO AGC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " HIGHAMPL ,LFXO high XTAL oscillation amplitude enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--12. " GAIN ,LFXO startup gain" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MODE ,LFXO mode" "XTAL,BUFEXTCLK,DIGEXTCLK,?..."
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,LFXO internal capacitor array tuning value"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "LFXOCTRL,LFXO Control Register"
|
|
rbitfld.long 0x00 24.--26. " TIMEOUT ,LFXO timeout" "2 cycles,256 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles"
|
|
rbitfld.long 0x00 20. " BUFCUR ,LFXO buffer bias current" "0,1"
|
|
rbitfld.long 0x00 16.--17. " CUR ,LFXO current trim" "0,1,2,3"
|
|
rbitfld.long 0x00 15. " AGC ,LFXO AGC enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 14. " HIGHAMPL ,LFXO high XTAL oscillation amplitude enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--12. " GAIN ,LFXO startup gain" "0,1,2,3"
|
|
rbitfld.long 0x00 8.--9. " MODE ,LFXO mode" "XTAL,BUFEXTCLK,DIGEXTCLK,?..."
|
|
hexmask.long.byte 0x00 0.--6. 1. " TUNING ,LFXO internal capacitor array tuning value"
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "DPLLCTRL,DPLL Control Register"
|
|
bitfld.long 0x00 6. " DITHEN ,Dither enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " REFSEL ,Reference clock selection control" "HFXO,LFXO,USHFRCO,CLKIN0"
|
|
bitfld.long 0x00 2. " AUTORECOVER ,Automatic recovery control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " EDGESEL ,Reference edge select" "Fall,Rise"
|
|
bitfld.long 0x00 0. " MODE ,Operating mode control" "FREQLL,PHASELL"
|
|
line.long 0x04 "DPLLCTRL1,DPLL Control 1 Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " N ,Factor N"
|
|
hexmask.long.word 0x04 0.--11. 1. " M ,Factor M"
|
|
if (((per.l(ad:0x400e4000+0x90))&0x10000)==0x10000)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CALCTRL,Calibration Control Register"
|
|
bitfld.long 0x00 24.--28. " PRSDOWNSEL ,PRS select for PRS input when selected in DOWNSEL" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 16.--20. " PRSUPSEL ,PRS select for PRS input when selected in UPSEL" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 8. " CONT ,Continuous calibration enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DOWNSEL ,Calibration down-counter select" "HFCLK,HFXO,LFXO,HFRCO,LFRCO,AUXHFRCO,PRS,USHFRCO,?..."
|
|
bitfld.long 0x00 0.--2. " UPSEL ,Calibration up-counter select" "HFXO,LFXO,HFRCO,LFRCO,AUXHFRCO,PRS,,USHFRCO"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CALCTRL,Calibration Control Register"
|
|
bitfld.long 0x00 24.--28. " PRSDOWNSEL ,PRS select for PRS input when selected in DOWNSEL" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 16.--20. " PRSUPSEL ,PRS select for PRS input when selected in UPSEL" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 8. " CONT ,Continuous calibration enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DOWNSEL ,Calibration down-counter select" "HFCLK,HFXO,LFXO,HFRCO,LFRCO,AUXHFRCO,PRS,USHFRCO,?..."
|
|
bitfld.long 0x00 0.--2. " UPSEL ,Calibration up-counter select" "HFXO,LFXO,HFRCO,LFRCO,AUXHFRCO,PRS,,USHFRCO"
|
|
endif
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CALCNT,Calibration Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CALCNT ,Calibration counter"
|
|
wgroup.long 0x60++0x07
|
|
line.long 0x00 "OSCENCMD,Oscillator Enable/Disable Command Register"
|
|
bitfld.long 0x00 13. " DPLLDIS ,DPLL disable" "No effect,Yes"
|
|
bitfld.long 0x00 12. " DPLLEN ,DPLL enable" "No effect,Enable"
|
|
bitfld.long 0x00 11. " USHFRCODIS ,USHFRCO disable" "No effect,Yes"
|
|
bitfld.long 0x00 10. " USHFRCOEN ,USHFRCO enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 9. " LFXODIS ,LFXO disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " LFXOEN ,LFXO enable" "No effect,Enable"
|
|
bitfld.long 0x00 7. " LFRCODIS ,LFRCO disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " LFRCOEN ,LFRCO enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " AUXHFRCODIS ,AUXHFRC disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " AUXHFRCOEN ,AUXHFRC enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " HFXODIS ,HFXO disable" "No effect,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " HFXOEN ,HFXO enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " HFRCODIS ,HFRCO disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " HFRCOEN ,HFRCO enable" "No effect,Enable"
|
|
line.long 0x04 "CMD,Command Register"
|
|
bitfld.long 0x04 4. " HFXOPEAKDETSTART ,HFXO peak detection start" "No effect,Start"
|
|
bitfld.long 0x04 1. " CALSTOP ,Calibration stop" "No effect,Stop"
|
|
bitfld.long 0x04 0. " CALSTART ,Calibration start" "No effect,Start"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DBGCLKSEL,Debug Trace Clock Select"
|
|
bitfld.long 0x00 0.--1. " DBG ,Debug trace clock" "AUXHFRCO,HFCLK,HFRCODIV2,?..."
|
|
wgroup.long 0x74++0x03
|
|
line.long 0x00 "HFCLKSEL,High Frequency Clock Select Command Register"
|
|
bitfld.long 0x00 0.--2. " HF ,High frequency clock select" ",HFRCO,HFXO,LFRCO,LFXO,HFRCODIV2,USHFRCO,CLKIN0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "LFACLKSEL,Low Frequency A Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " LFA ,Clock select for LFA" "Disabled,LFRCO,LFXO,,ULFRCO,?..."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "LFBCLKSEL,Low Frequency B Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " LFB ,Clock select for LFB" "Disabled,LFRCO,LFXO,HFCLKE,ULFRCO,?..."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "LFECLKSEL,Low Frequency E Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " LFE ,Clock select for LFE" "Disabled,LFRCO,LFXO,,ULFRCO,?..."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "LFCCLKSEL,Low Frequency C Clock Select Register"
|
|
bitfld.long 0x00 0.--2. " LFC ,Clock select for LFC" "Disabled,LFRCO,LFXO,,ULFRCO,?..."
|
|
rgroup.long 0x90++0x07
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 29. " ULFRCOPHASE ,ULFRCO clock phase" "Low,High"
|
|
bitfld.long 0x00 28. " LFRCOPHASE ,LFRCO clock phase" "Low,High"
|
|
bitfld.long 0x00 27. " LFXOPHASE ,LFXO clock phase" "Low,High"
|
|
bitfld.long 0x00 25. " HFXOAMPLOW ,HFXO amplitude tuning value too low" "OK,Too low"
|
|
newline
|
|
bitfld.long 0x00 22. " HFXOPEAKDETRDY ,HFXO peak detection ready" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " QSPI0CLKENS ,QSPI0 clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDIOCLKENS ,SDIO clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CALRDY ,Calibration ready" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 13. " DPLLRDY ,DPLL ready" "Not ready,Ready"
|
|
bitfld.long 0x00 12. " DPLLENS ,DPLL enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " USHFRCORDY ,USHFRCO ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " USHFRCOENS ,USHFRCO enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " LFXORDY ,LFXO ready" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " LFXOENS ,LFXO enable status" "Not ready,Ready"
|
|
bitfld.long 0x00 7. " LFRCORDY ,LFRCO ready" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " LFRCOENS ,LFRCO enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " AUXHFRCRDY ,AUXHFRC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " AUXHFRCENS ,AUXHFRC enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HFXORDY ,HFXO ready" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 2. " HFXOENS ,HFXO enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFRCORDY ,HFRCO ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HFRCOENS ,HFRCO enable status" "Disabled,Enabled"
|
|
line.long 0x04 "HFCLKSTATUS,HFCLK Status Register"
|
|
bitfld.long 0x04 0.--2. " SELECTED ,HFCLK selected" ",HFRCO,HFXO,LFRCO,LFXO,HFRCODIV2,USHFRCO,CLKIN0"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "HFXOTRIMSTATUS,HFXO Trim Status"
|
|
bitfld.long 0x00 31. " MONVALID ,Peak detection algorithm or peak monitoring algorithm found a value for IBTRIMXOCOREMON" "Not found,Found"
|
|
bitfld.long 0x00 30. " VALID ,Peak detection algorithm found a value for IBTRIMXOCORE" "Not found,Found"
|
|
hexmask.long.word 0x00 16.--26. 1. " IBTRIMXOCOREMON ,Value found by automatic HFXO peak detection algorithm or peak monitoring algorithm"
|
|
hexmask.long.word 0x00 0.--10. 1. " IBTRIMXOCORE ,Value found by automatic HFXO peak detection algorithm"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "IF_SETCLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CMUERR ,CMU error interrupt flag" "No error,Error"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ULFRCOEDGE ,ULFRCO clock edge detected interrupt flag" "Not detected,Detected"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " LFRCOEDGE ,LFRCO clock edge detected interrupt flag" "Not detected,Detected"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " LFXOEDGE ,LFXO clock edge detected interrupt flag" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DPLLLOCKFAILHIGH ,DPLL lock failure high interrupt flag" "Not locked,Locked"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DPLLLOCKFAILLOW ,DPLL lock failure low interrupt flag" "Not locked,Locked"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DPLLRDY ,DPLL lock interrupt flag" "Not locked,Locked"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " LFTIMEOUTERR ,Low frequency timeout error interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " HFRCODIS ,HFRCO disabled interrupt flag" "No,Yes"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " HFXOPEAKDETRDY ,HFXO automatic peak detection ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " HFXOAUTOSW ,HFXO automatic switch interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " HFXODISERR ,HFXO disable error interrupt flag" "No error,Error"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " USHFRCORDY ,USHFRCO ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CALOF ,Calibration overflow interrupt flag" "No overflow,Overflow"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CALRDY ,Calibration ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AUXHFRCORDY ,AUXHFRCO ready interrupt flag" "Not ready,Ready"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " LFXORDY ,LFXO ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " LFRCORDY ,LFRCO ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " HFXORDY ,HFXO ready interrupt flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " HFRCORDY ,HFRCO ready interrupt flag" "Not ready,Ready"
|
|
group.long 0xAC++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " CMUERR ,CMU error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ULFRCOEDGE ,ULFRCO clock edge detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " LFRCOEDGE ,LFRCO clock edge detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LFXOEDGE ,LFXO clock edge detected interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " DPLLLOCKFAILHIGH ,DPLL lock failure high interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DPLLLOCKFAILLOW ,DPLL lock failure low interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DPLLRDY ,DPLL lock interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LFTIMEOUTERR ,Low frequency timeout error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " HFRCODIS ,HFRCO disabled interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HFXOPEAKDETRDY ,HFXO automatic peak detection ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HFXOAUTOSW ,HFXO automatic switch interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HFXODISERR ,HFXO disable error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " USHFRCORDY ,USHFRCO ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CALOF ,Calibration overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CALRDY ,Calibration ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AUXHFRCORDY ,AUXHFRCO ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " LFXORDY ,LFXO ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LFRCORDY ,LFRCO ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFXORDY ,HFXO ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HFRCORDY ,HFRCO ready interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "HFBUSCLKEN0,High Frequency Bus Clock Enable Register"
|
|
bitfld.long 0x04 10. " USB ,Universal serial bus interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " QSPI0 ,Quad-SPI clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " GPCRC ,General purpose CRC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " LDMA ,Linked direct memory access controller clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " PRS ,Peripheral reflex system clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " GPIO ,General purpose input/output clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " SDIO ,SDIO controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ETH ,Ethernet controller clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " EBI ,External bus interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CRYPTO0 ,Advanced encryption standard accelerator clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LE ,Low energy peripheral interface clock enable" "Disabled,Enabled"
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "HFPERCLKEN0,High Frequency Peripheral Clock Enable Register 0"
|
|
bitfld.long 0x00 24. " TRNG0 ,True random number generator 0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " IDAC0 ,Current digital to analog converter 0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CRYOTIMER ,CryoTimer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ADC1 ,Analog to digital converter 1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " ADC0 ,Analog to digital converter 0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " I2C2 ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " I2C1 ,I2C 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " I2C0 ,I2C 0 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " ACMP3 ,Analog comparator 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ACMP2 ,Analog comparator 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ACMP1 ,Analog comparator 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ACMP0 ,Analog comparator 0 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " USART5 ,Universal synchronous/asynchronous Rx/Tx 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " USART4 ,Universal synchronous/asynchronous Rx/Tx 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USART3 ,Universal synchronous/asynchronous Rx/Tx 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USART2 ,Universal synchronous/asynchronous Rx/Tx 2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " USART1 ,Universal synchronous/asynchronous Rx/Tx 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " USART0 ,Universal synchronous/asynchronous Rx/Tx 0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMER6 ,Timer 6 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " TIMER5 ,Timer 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMER4 ,Timer 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMER3 ,Timer 3 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TIMER2 ,Timer 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMER1 ,Timer 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMER0 ,Timer 0 clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "HFPERCLKEN1,High Frequency Peripheral Clock Enable Register 1"
|
|
bitfld.long 0x04 9. " CSEN ,Capacitive touch sense module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " VDAC0 ,Digital to analog converter 0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " CAN1 ,CAN 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CAN0 ,CAN 0 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " UART1 ,Universal asynchronous Rx/Tx 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " UART0 ,Universal asynchronous Rx/Tx 0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " WTIMER3 ,Wide timer 3 clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " WTIMER2 ,Wide timer 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " WTIMER1 ,Wide timer 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WTIMER0 ,Wide timer 0 clock enable" "Disabled,Enabled"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "LFACLKEN0,Low Frequency A Clock Enable Register 0"
|
|
bitfld.long 0x00 4. " RTC ,Real-time counter clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " LCD ,Liquid crystal display controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LESENSE ,Low energy sensor interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LETIMER1 ,Low energy timer 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LETIMER0 ,Low energy timer 0 clock enable" "Disabled,Enabled"
|
|
group.long 0xE8++0x0B
|
|
line.long 0x00 "LFBCLKEN0,Low Frequency B Clock Enable Register 0"
|
|
bitfld.long 0x00 3. " CSEN ,Capacitive touch sense module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYSTICK ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LEUART1 ,Low energy UART 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEUART0 ,Low energy UART 0 clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "LFCCLKEN0,Low Frequency C Clock Enable Register 0"
|
|
bitfld.long 0x04 0. " USB ,Universal serial bus interface clock enable" "Disabled,Enabled"
|
|
line.long 0x08 "LFECLKEN0,Low Frequency E Clock Enable Register 0"
|
|
bitfld.long 0x08 0. " RTCC ,Real-time counter and calendar clock enable" "Disabled,Enabled"
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "HFPRESC,High Frequency Clock Prescaler Register"
|
|
bitfld.long 0x00 24.--25. " HFCLKLEPRESC ,HFCLKLE prescaler" "DIV2,DIV4,DIV8,?..."
|
|
bitfld.long 0x00 8.--12. " PRESC ,HFCLK prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x04 "HFBUSPRESC,High Frequency Bus Clock Prescaler Register"
|
|
hexmask.long.word 0x04 8.--16. 1. " PRESC ,HFBUSCLK prescaler"
|
|
line.long 0x08 "HFCOREPRESC,High Frequency Core Clock Prescaler Register"
|
|
hexmask.long.word 0x08 8.--16. 1. " PRESC ,HFBUSCLK prescaler"
|
|
line.long 0x0C "HFPERPRESC,High Frequency Peripheral Clock Prescaler Register"
|
|
hexmask.long.word 0x0C 8.--16. 1. " PRESC ,HFBUSCLK prescaler"
|
|
group.long 0x114++0x0F
|
|
line.long 0x00 "HFEXPPRESC,High Frequency Export Clock Prescaler Register"
|
|
bitfld.long 0x00 8.--12. " PRESC ,HFBUSCLK prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x04 "HFPERPRESCB,High Frequency Peripheral Clock Prescaler B Register"
|
|
hexmask.long.word 0x04 8.--16. 1. " PRESC ,HFBUSCLK prescaler"
|
|
line.long 0x08 "HFPERPRESCC,High Frequency Peripheral Clock Prescaler C Register"
|
|
hexmask.long.word 0x08 8.--16. 1. " PRESC ,HFBUSCLK prescaler"
|
|
line.long 0x0C "LFAPRESC0,Low Frequency a Prescaler Register 0"
|
|
bitfld.long 0x0C 16.--19. " RTC ,Real-time counter prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
bitfld.long 0x0C 12.--14. " LCD ,Liquid crystal display controller prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x0C 8.--9. " LESENSE ,Low energy sensor interface prescaler" "/1,/2,/4,/8"
|
|
newline
|
|
bitfld.long 0x0C 4.--7. " LETIMER1 ,Low energy timer 1 prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
bitfld.long 0x0C 0.--3. " LETIMER0 ,Low energy timer 0 prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "LFBPRESC0,Low Frequency B Prescaler Register 0"
|
|
bitfld.long 0x00 12.--13. " CSEN ,Capacitive touch sense module prescaler" "/16,/32,/64,/128"
|
|
bitfld.long 0x00 8.--11. " SYSTICK ,Configure prescaler" "/1,?..."
|
|
bitfld.long 0x00 4.--5. " LEUART1 ,Low energy UART 1 prescaler" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 0.--1. " LEUART0 ,Low energy UART 0 prescaler" "/1,/2,/4,/8"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "LFEPRESC0,Low Frequency E Prescaler Register 0"
|
|
bitfld.long 0x00 0.--1. " RTCC ,Real-time counter and calendar prescaler" "/1,/2,/4,?..."
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 30. " USHFRCOBSY ,USHFRCO busy" "Not busy,Busy"
|
|
bitfld.long 0x00 29. " LFXOBSY ,LFXO busy" "Not busy,Busy"
|
|
bitfld.long 0x00 28. " HFXOBSY ,HFXO busy" "Not busy,Busy"
|
|
bitfld.long 0x00 27. " LFRCOREFBSY ,LFRCO VREF busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 26. " LFRCOBSY ,LFRCO busy" "Not busy,Busy"
|
|
bitfld.long 0x00 25. " AUXHFRCOBSY ,AUXHFRCO busy" "Not busy,Busy"
|
|
bitfld.long 0x00 24. " HFRCOBSY ,HFRCO busy" "Not busy,Busy"
|
|
bitfld.long 0x00 18. " LFEPRESC0 ,Low frequency E prescaler 0 busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 16. " LFECLKEN0 ,Low frequency E clock enable 0 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " LFCCLKEN0 ,Low frequency C clock enable 0 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " LFBPRESC0 ,Low frequency B prescaler 0 busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 4. " LFBCLKEN0 ,Low frequency B clock enable 0 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " LFAPRESC0 ,Low frequency A prescaler 0 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " LFACLKEN0 ,Low frequency A prescaler enable 0 busy" "Not busy,Busy"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 0. " REGFREEZE ,Register update freeze" "Updated,Freezed"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCNTCTRL,PCNT Control Register"
|
|
bitfld.long 0x00 5. " PCNT2CLKSEL ,PCNT2 clock select" "LFACLK,PCNT2S0"
|
|
bitfld.long 0x00 4. " PCNT2CLKEN ,PCNT2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PCNT1CLKSEL ,PCNT1 clock select" "LFACLK,PCNT1S0"
|
|
newline
|
|
bitfld.long 0x00 2. " PCNT1CLKEN ,PCNT1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PCNT0CLKSEL ,PCNT0 clock select" "LFACLK,PCNT0S0"
|
|
bitfld.long 0x00 0. " PCNT0CLKEN ,PCNT0 clock enable" "Disabled,Enabled"
|
|
group.long 0x15C++0x0B
|
|
line.long 0x00 "ADCCTRL,ADC Control Register"
|
|
bitfld.long 0x00 24. " ADC1CLKINV ,Invert clock selected by ADC1CLKSEL" "Not inverted,Inverted"
|
|
bitfld.long 0x00 20.--21. " ADC1CLKSEL ,ADC1 clock select" "Disabled,AUXHFRCO,HFXO,HFSRCCLK"
|
|
bitfld.long 0x00 16.--17. " ADC1CLKDIV ,ADC1 clock prescaler" "/1,/2,/3,/4"
|
|
newline
|
|
bitfld.long 0x00 8. " ADC0CLKINV ,Invert clock selected by ADC0CLKSEL" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4.--5. " ADC0CLKSEL ,ADC0 clock select" "Disabled,AUXHFRCO,HFXO,HFSRCCLK"
|
|
bitfld.long 0x00 0.--1. " ADC0CLKDIV ,ADC0 clock prescaler" "/1,/2,/3,/4"
|
|
line.long 0x04 "SDIOCTRL,SDIO Control Register"
|
|
bitfld.long 0x04 7. " SDIOCLKDIS ,SDIO reference clock disable" "No,Yes"
|
|
bitfld.long 0x04 0.--1. " SDIOCLKSEL ,SDIO reference clock select" "HFRCO,HFXO,AUXHFRCO,USHFRCO"
|
|
line.long 0x08 "QSPICTRL,QSPI Control Register"
|
|
bitfld.long 0x08 7. " QSPI0CLKDIS ,QSPI0 reference clock disable" "No,Yes"
|
|
bitfld.long 0x08 0.--1. " QSPI0CLKSEL ,QSPI0 reference clock select" "HFRCO,HFXO,AUXHFRCO,USHFRCO"
|
|
group.long 0x170++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 28. " CLKIN0PEN ,CLKIN0 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CLKOUT2PEN ,CLKOUT2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKOUT1PEN ,CLKOUT1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CLKOUT0PEN ,CLKOUT0 pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 16.--21. " CLKOUT2LOC ,Clock out 2 location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x04 8.--13. " CLKOUT1LOC ,Clock out 1 location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x04 0.--5. " CLKOUT0LOC ,Clock out 0 location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 0.--5. " CLKIN0LOC ,Clock out 0 location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "LOCK,Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Configuration lock key"
|
|
line.long 0x04 "HFRCOSS,HFRCO Spread Spectrum Register"
|
|
bitfld.long 0x04 8.--12. " SSINV ,Spread spectrum update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--2. " SSAMP ,Spread spectrum amplitude" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "USBCTRL,USB Control Register"
|
|
bitfld.long 0x00 7. " USBCLKEN ,USB rate clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " USBCLKSEL ,USB rate clock select" "USHFRCO,HFXO,HFXOX2,HFRCO,LFXO,LFRCO,?..."
|
|
line.long 0x04 "USBCRCTRL,USB Clock Recovery Control"
|
|
bitfld.long 0x04 1. " USBLSCRMD ,Low speed clock recovery mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " USBCREN ,Clock recovery enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMU (Security Management Unit)"
|
|
base ad:0x40020000
|
|
width 11.
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PPUPRIV ,PPU privilege interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " PPUPRIV ,PPU privilege interrupt enable" "Disabled,Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PPUCTRL,PPU Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Checking of peripheral access enable" "Disabled,Enabled"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "PPUPATD0,PPU Privilege Access Type Descriptor 0"
|
|
bitfld.long 0x00 31. " LEUART1 ,Low energy UART 1 access control bit" "No access,Access"
|
|
bitfld.long 0x00 30. " LEUART0 ,Low energy UART 0 access control bit" "No access,Access"
|
|
bitfld.long 0x00 29. " LETIMER1 ,Low energy timer 1 access control bit" "No access,Access"
|
|
bitfld.long 0x00 28. " LETIMER0 ,Low energy timer 0 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 27. " LESENSE ,Low energy sensor interface access control bit" "No access,Access"
|
|
bitfld.long 0x00 26. " LDMA ,Linked direct memory access controller access control bit" "No access,Access"
|
|
bitfld.long 0x00 25. " LCD ,Liquid crystal display controller access control bit" "No access,Access"
|
|
bitfld.long 0x00 24. " MSC ,Memory system controller access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 23. " IDAC0 ,Current digital to analog converter 0 access control bit" "No access,Access"
|
|
bitfld.long 0x00 22. " I2C2 ,I2C 2 access control bit" "No access,Access"
|
|
bitfld.long 0x00 21. " I2C1 ,I2C 1 access control bit" "No access,Access"
|
|
bitfld.long 0x00 20. " I2C0 ,I2C 0 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO ,General purpose Input/Output access control bit" "No access,Access"
|
|
bitfld.long 0x00 18. " GPCRC ,General purpose CRC access control bit" "No access,Access"
|
|
bitfld.long 0x00 17. " FPUEH ,FPU exception handler access control bit" "No access,Access"
|
|
bitfld.long 0x00 16. " ETH ,Ethernet controller access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 15. " EMU ,Energy management unit access control bit" "No access,Access"
|
|
bitfld.long 0x00 14. " EBI ,External bus interface access control bit" "No access,Access"
|
|
bitfld.long 0x00 13. " PRS ,Peripheral reflex system access control bit" "No access,Access"
|
|
bitfld.long 0x00 12. " VDAC0 ,Digital to analog converter 0 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 11. " CSEN ,Capacitive touch sense module access control bit" "No access,Access"
|
|
bitfld.long 0x00 10. " CRYPTO0 ,Advanced encryption standard accelerator access control bit" "No access,Access"
|
|
bitfld.long 0x00 9. " CRYOTIMER ,CryoTimer access control bit" "No access,Access"
|
|
bitfld.long 0x00 8. " CMU ,Clock management unit access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 7. " CAN1 ,CAN 1 access control bit" "No access,Access"
|
|
bitfld.long 0x00 6. " CAN0 ,CAN 0 access control bit" "No access,Access"
|
|
bitfld.long 0x00 5. " ADC1 ,Analog to digital converter 1 access control bit" "No access,Access"
|
|
bitfld.long 0x00 4. " ADC0 ,Analog to digital converter 0 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 3. " ACMP3 ,Analog comparator 3 access control bit" "No access,Access"
|
|
bitfld.long 0x00 2. " ACMP2 ,Analog comparator 2 access control bit" "No access,Access"
|
|
bitfld.long 0x00 1. " ACMP1 ,Analog comparator 1 access control bit" "No access,Access"
|
|
bitfld.long 0x00 0. " ACMP0 ,Analog comparator 0 access control bit" "No access,Access"
|
|
line.long 0x04 "PPUPATD1,PPU Privilege Access Type Descriptor 1"
|
|
bitfld.long 0x04 31. " WTIMER3 ,Wide timer 3 access control bit" "No access,Access"
|
|
bitfld.long 0x04 30. " WTIMER2 ,Wide timer 2 access control bit" "No access,Access"
|
|
bitfld.long 0x04 29. " WTIMER1 ,Wide timer 1 access control bit" "No access,Access"
|
|
bitfld.long 0x04 28. " WTIMER0 ,Wide timer 0 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 27. " WDOG1 ,Watchdog 1 access control bit" "No access,Access"
|
|
bitfld.long 0x04 26. " WDOG0 ,Watchdog 0 access control bit" "No access,Access"
|
|
bitfld.long 0x04 25. " USB ,Universal serial bus interface access control bit" "No access,Access"
|
|
bitfld.long 0x04 24. " USART5 ,Universal synchronous/asynchronous Rx/Tx 5 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 23. " USART4 ,Universal synchronous/asynchronous Rx/Tx 4 access control bit" "No access,Access"
|
|
bitfld.long 0x04 22. " USART3 ,Universal synchronous/asynchronous Rx/Tx 3 access control bit" "No access,Access"
|
|
bitfld.long 0x04 21. " USART2 ,Universal synchronous/asynchronous Rx/Tx 2 access control bit" "No access,Access"
|
|
bitfld.long 0x04 20. " USART1 ,Universal synchronous/asynchronous Rx/Tx 1 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 19. " USART0 ,Universal synchronous/asynchronous Rx/Tx 0 access control bit" "No access,Access"
|
|
bitfld.long 0x04 18. " UART1 ,Universal synchronous Rx/Tx 1 access control bit" "No access,Access"
|
|
bitfld.long 0x04 17. " UART0 ,Universal synchronous Rx/Tx 0 access control bit" "No access,Access"
|
|
bitfld.long 0x04 16. " TRNG0 ,True random number generator 0 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 15. " TIMER6 ,Timer 6 access control bit" "No access,Access"
|
|
bitfld.long 0x04 14. " TIMER5 ,Timer 5 access control bit" "No access,Access"
|
|
bitfld.long 0x04 13. " TIMER4 ,Timer 4 access control bit" "No access,Access"
|
|
bitfld.long 0x04 12. " TIMER3 ,Timer 3 access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 11. " TIMER2 ,Timer 2 access control bit" "No access,Access"
|
|
bitfld.long 0x04 10. " TIMER1 ,Timer 1 access control bit" "No access,Access"
|
|
bitfld.long 0x04 9. " TIMER0 ,Timer 0 access control bit" "No access,Access"
|
|
bitfld.long 0x04 8. " SMU ,Security management unit access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 7. " SDIO ,SDIO controller access control bit" "No access,Access"
|
|
bitfld.long 0x04 6. " RTCC ,Real-time counter and calendar access control bit" "No access,Access"
|
|
bitfld.long 0x04 5. " RTC ,Real-time counter access control bit" "No access,Access"
|
|
bitfld.long 0x04 4. " RMU ,Reset management unit access control bit" "No access,Access"
|
|
newline
|
|
bitfld.long 0x04 3. " QSPI0 ,Quad-SPI access control bit" "No access,Access"
|
|
bitfld.long 0x04 2. " PCNT2 ,Pulse counter 2 access control bit" "No access,Access"
|
|
bitfld.long 0x04 1. " PCNT1 ,Pulse counter 1 access control bit" "No access,Access"
|
|
bitfld.long 0x04 0. " PCNT0 ,Pulse counter 0 access control bit" "No access,Access"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "PPUPATD2,PPU Privilege Access Type Descriptor 2"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PPUFS,PPU Fault Status Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PERIPHID ,Peripheral ID of the first peripheral that was accessed resulting in an access fault"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTCC (Real Time Counter and Calendar)"
|
|
base ad:0x40062000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 17. " LYEARCORRDIS ,Leap year correction disable" "No,Yes"
|
|
bitfld.long 0x00 16. " CNTMODE ,Main counter mode" "Normal,Calendar"
|
|
bitfld.long 0x00 15. " OSCFDETEN ,Oscillator failure detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BUMODETSEN ,Backup mode timestamp enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " CNTTICK ,Counter prescaler mode" "PRESC,CCV0MATCH"
|
|
bitfld.long 0x00 8.--11. " CNTPRESC ,Counter prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
bitfld.long 0x00 5. " CCV1TOP ,CCV1 top value enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " PRECCV0TOP ,Pre-counter CCV0 top value enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DEBUGRUN ,Debug mode run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,RTCC enable" "Disabled,Enabled"
|
|
line.long 0x04 "PRECNT,Pre-Counter Value Register"
|
|
hexmask.long.word 0x04 0.--14. 1. " PRECNT ,Pre-counter value"
|
|
if (((per.l(ad:0x40062000+0x00))&0x10000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter Value Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "CNT,Counter Value Register"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "COMBCNT,Combined Pre-Counter and Counter Value Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. " CNTLSB ,Counter value"
|
|
hexmask.long.word 0x00 0.--14. 1. " PRECNT ,Pre-counter value"
|
|
if (((per.l(ad:0x40062000+0x00))&0x10000)==0x10000)
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "TIME,Time of Day Register"
|
|
bitfld.long 0x00 20.--21. " HOURT ,Hours - tens" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HOURU ,Hours - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MINT ,Minutes - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. " MINU ,Minutes - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " SECT ,Seconds - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SECU ,Seconds - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
line.long 0x04 "DATE,Date Register"
|
|
bitfld.long 0x04 24.--26. " DAYOW ,Day of week" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 20.--23. " YEART ,Year - tens" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x04 16.--19. " YEARU ,Year - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x04 12. " MONTHT ,Month tens" "0,1"
|
|
bitfld.long 0x04 8.--11. " MONTHU ,Month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " DAYOMT ,Day of month - tens" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " DAYOMU ,Day of month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
hgroup.long 0x10++0x07
|
|
hide.long 0x00 "TIME,Time of Day Register"
|
|
hide.long 0x04 "DATE,Date Register"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IF_SETCLR,RTCC Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MONTHTICK ,Month tick" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DAYOWOF ,Day of week overflow" "No overflow,Overflow"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DAYTICK ,Day tick" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " HOURTICK ,Hour tick" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " MINTICK ,Minute tick" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CNTTICK ,Main counter tick" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " OSCFAIL ,Oscillator failure interrupt flag" "Not failed,Failed"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CC2 ,Channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CC1 ,Channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CC0 ,Channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No overflow,Overflow"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IEN,RTCC Interrupt Enable Register"
|
|
bitfld.long 0x00 10. " MONTHTICK ,Month tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DAYOWOF ,Day of week overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DAYTICK ,Day tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HOURTICK ,Hour tick interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " MINTICK ,Minute tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CNTTICK ,Main counter tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OSCFAIL ,Oscillator failure interrupt flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CC2 ,Channel 2 interrupt flag interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1 ,Channel 1 interrupt flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CC0 ,Channel 0 interrupt flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt flag interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " BUMODETS ,Timestamp for backup mode entry stored" "Not stored,Stored"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 0. " CLRSTATUS ,Clear STATUS register" "No effect,Clear"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 5. " CMD ,CMD register busy" "Not busy,Busy"
|
|
if (((per.l(ad:0x40062000+0x34))&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "POWERDOWN,Retention RAM Power-Down Register"
|
|
bitfld.long 0x00 0. " RAM ,Retention RAM power-down" "Powered up,Powered down"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "POWERDOWN,Retention RAM Power-Down Register"
|
|
rbitfld.long 0x00 0. " RAM ,Retention RAM power-down" "Powered up,Powered down"
|
|
endif
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "LOCK,Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,Configuration lock key"
|
|
line.long 0x04 "EM4WUEN,Wake Up Enable Register"
|
|
bitfld.long 0x04 0. " EM4WU ,EM4 wake-up enable" "Disabled,Enabled"
|
|
tree "Capture/Compare 0 Registers"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CC0_CTRL,CC 0 Channel Control Register"
|
|
bitfld.long 0x00 17. " DAYCC ,Day capture/compare selection" "Month,Week"
|
|
bitfld.long 0x00 12.--16. " COMPMASK ,Capture compare channel comparison mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11. " COMPBASE ,Capture compare channel comparison base" "CNT,PRECNT"
|
|
bitfld.long 0x00 6.--10. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
bitfld.long 0x00 2.--3. " CMOA ,Compare match output action" "Pulse,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "OFF,Input capture,Output compare,?..."
|
|
if (((per.l(ad:0x40062000+0x00))&0x10000)==0x00)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CC0_CCV,Capture/Compare Value Register"
|
|
hgroup.long (0x40+0x08)++0x07
|
|
hide.long 0x00 "CC0_TIME,Capture/Compare Time Register"
|
|
hide.long 0x04 "CC0_DATE,Capture/Compare Date Register"
|
|
else
|
|
hgroup.long (0x40+0x04)++0x03
|
|
hide.long 0x00 "CC0_CCV,Capture/Compare Value Register"
|
|
group.long (0x40+0x08)++0x07
|
|
line.long 0x00 "CC0_TIME,Capture/Compare Time Register"
|
|
bitfld.long 0x00 20.--21. " HOURT ,Hours - tens" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HOURU ,Hours - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MINT ,Minutes - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. " MINU ,Minutes - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " SECT ,Seconds - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SECU ,Seconds - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
line.long 0x04 "CC0_DATE,Capture/Compare Date Register"
|
|
bitfld.long 0x04 12. " MONTHT ,Month tens" "0,1"
|
|
bitfld.long 0x04 8.--11. " MONTHU ,Month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " DAYT ,Day of month - tens" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " DAYU ,Day of month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
tree.end
|
|
tree "Capture/Compare 1 Registers"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CC1_CTRL,CC 1 Channel Control Register"
|
|
bitfld.long 0x00 17. " DAYCC ,Day capture/compare selection" "Month,Week"
|
|
bitfld.long 0x00 12.--16. " COMPMASK ,Capture compare channel comparison mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11. " COMPBASE ,Capture compare channel comparison base" "CNT,PRECNT"
|
|
bitfld.long 0x00 6.--10. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
bitfld.long 0x00 2.--3. " CMOA ,Compare match output action" "Pulse,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "OFF,Input capture,Output compare,?..."
|
|
if (((per.l(ad:0x40062000+0x00))&0x10000)==0x00)
|
|
group.long (0x50+0x04)++0x03
|
|
line.long 0x00 "CC1_CCV,Capture/Compare Value Register"
|
|
hgroup.long (0x50+0x08)++0x07
|
|
hide.long 0x00 "CC1_TIME,Capture/Compare Time Register"
|
|
hide.long 0x04 "CC1_DATE,Capture/Compare Date Register"
|
|
else
|
|
hgroup.long (0x50+0x04)++0x03
|
|
hide.long 0x00 "CC1_CCV,Capture/Compare Value Register"
|
|
group.long (0x50+0x08)++0x07
|
|
line.long 0x00 "CC1_TIME,Capture/Compare Time Register"
|
|
bitfld.long 0x00 20.--21. " HOURT ,Hours - tens" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HOURU ,Hours - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MINT ,Minutes - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. " MINU ,Minutes - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " SECT ,Seconds - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SECU ,Seconds - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
line.long 0x04 "CC1_DATE,Capture/Compare Date Register"
|
|
bitfld.long 0x04 12. " MONTHT ,Month tens" "0,1"
|
|
bitfld.long 0x04 8.--11. " MONTHU ,Month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " DAYT ,Day of month - tens" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " DAYU ,Day of month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
tree.end
|
|
tree "Capture/Compare 2 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CC2_CTRL,CC 2 Channel Control Register"
|
|
bitfld.long 0x00 17. " DAYCC ,Day capture/compare selection" "Month,Week"
|
|
bitfld.long 0x00 12.--16. " COMPMASK ,Capture compare channel comparison mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11. " COMPBASE ,Capture compare channel comparison base" "CNT,PRECNT"
|
|
bitfld.long 0x00 6.--10. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
bitfld.long 0x00 2.--3. " CMOA ,Compare match output action" "Pulse,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "OFF,Input capture,Output compare,?..."
|
|
if (((per.l(ad:0x40062000+0x00))&0x10000)==0x00)
|
|
group.long (0x60+0x04)++0x03
|
|
line.long 0x00 "CC2_CCV,Capture/Compare Value Register"
|
|
hgroup.long (0x60+0x08)++0x07
|
|
hide.long 0x00 "CC2_TIME,Capture/Compare Time Register"
|
|
hide.long 0x04 "CC2_DATE,Capture/Compare Date Register"
|
|
else
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CC2_CCV,Capture/Compare Value Register"
|
|
group.long (0x60+0x08)++0x07
|
|
line.long 0x00 "CC2_TIME,Capture/Compare Time Register"
|
|
bitfld.long 0x00 20.--21. " HOURT ,Hours - tens" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HOURU ,Hours - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MINT ,Minutes - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. " MINU ,Minutes - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " SECT ,Seconds - tens" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SECU ,Seconds - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
line.long 0x04 "CC2_DATE,Capture/Compare Date Register"
|
|
bitfld.long 0x04 12. " MONTHT ,Month tens" "0,1"
|
|
bitfld.long 0x04 8.--11. " MONTHU ,Month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " DAYT ,Day of month - tens" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " DAYU ,Day of month - units" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
tree.end
|
|
tree "Retention Registers"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "RET0_REG,Retention Register 0"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "RET1_REG,Retention Register 1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RET2_REG,Retention Register 2"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "RET3_REG,Retention Register 3"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "RET4_REG,Retention Register 4"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "RET5_REG,Retention Register 5"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "RET6_REG,Retention Register 6"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "RET7_REG,Retention Register 7"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "RET8_REG,Retention Register 8"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "RET9_REG,Retention Register 9"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "RET10_REG,Retention Register 10"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "RET11_REG,Retention Register 11"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "RET12_REG,Retention Register 12"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "RET13_REG,Retention Register 13"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "RET14_REG,Retention Register 14"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RET15_REG,Retention Register 15"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "RET16_REG,Retention Register 16"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "RET17_REG,Retention Register 17"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "RET18_REG,Retention Register 18"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "RET19_REG,Retention Register 19"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "RET20_REG,Retention Register 20"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "RET21_REG,Retention Register 21"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "RET22_REG,Retention Register 22"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "RET23_REG,Retention Register 23"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "RET24_REG,Retention Register 24"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "RET25_REG,Retention Register 25"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "RET26_REG,Retention Register 26"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "RET27_REG,Retention Register 27"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "RET28_REG,Retention Register 28"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "RET29_REG,Retention Register 29"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "RET30_REG,Retention Register 30"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "RET31_REG,Retention Register 31"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real Time Counter)"
|
|
base ad:0x40060000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 2. " COMP0TOP ,Compare channel 0 is top value" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DEBUGRUN ,Debug mode run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,RTC enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT,Counter Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CNT ,Counter value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " COMP[F] ,Compare match [F] interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [E] ,Compare match [E] interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [D] ,Compare match [D] interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [C] ,Compare match [C] interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [B] ,Compare match [B] interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [A] ,Compare match [A] interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " COMP[F] ,Clear compare match [F] interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [E] ,Clear compare match [E] interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [D] ,Clear compare match [D] interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [C] ,Clear compare match [C] interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [B] ,Clear compare match [B] interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [A] ,Clear compare match [A] interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " OF ,Clear overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMPA,Compare Value Register A"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COMP[A] ,Compare value [A]"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "COMPB,Compare Value Register B"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COMP[B] ,Compare value [B]"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMPC,Compare Value Register C"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COMP[C] ,Compare value [C]"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "COMPD,Compare Value Register D"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COMP[D] ,Compare value [D]"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMPE,Compare Value Register E"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COMP[E] ,Compare value [E]"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "COMPF,Compare Value Register F"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COMP[F] ,Compare value [F]"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "WDOG (Watchdog Timer)"
|
|
tree "WDOG0"
|
|
base ad:0x40052000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Watchdog Control Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 31. " WDOGRSTDIS ,Watchdog reset disable" "No,Yes"
|
|
bitfld.long 0x00 30. " CLRSRC ,Watchdog clear source" "SW,PCH0"
|
|
bitfld.long 0x00 24.--26. " WINSEL ,Watchdog illegal windows select" "Disabled,12.5%,25%,37.5%,50%,62.5%,75%,87.5%"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " WARNSEL ,Watchdog timeout period select" "Disabled,25%,50%,75%"
|
|
bitfld.long 0x00 12.--13. " CLKSEL ,Watchdog clock select" "ULFRCO,LFRCO,LFXO,HFCORECLK"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 12.--13. " CLKSEL ,Watchdog clock select" "ULFRCO,LFRCO,LFXO,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--11. " PERSEL ,Watchdog timeout period select" "9 cycles,17 cycles,33 cycles,65 cycles,129 cycles,257 cycles,513 cycles,1k cycles,2k cycles,4k cycles,8k cycles,16k cycles,32k cycles,64k cycles,128k cycles,256k cycles"
|
|
bitfld.long 0x00 6. " SWOSCBLOCK ,Software oscillator disable block" "No,Yes"
|
|
bitfld.long 0x00 5. " EM4BLOCK ,Energy mode 4 block" "Not blocked,Blocked"
|
|
newline
|
|
bitfld.long 0x00 4. " LOCK ,Configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " EM3RUN ,Energy mode 3 run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EM2RUN ,Energy mode 2 run enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DEBUGRUN ,Debug mode run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Watchdog timer enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Watchdog Command Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Watchdog timer clear" "No effect,Clear"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SYNCBUSY,Watchdog Synchronization Busy Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 3. " PCH1_PRSCTRL ,PCH1_PRSCTRL register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " PCH0_PRSCTRL ,PCH0_PRSCTRL register busy" "Not busy,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PCH0_PRSCTRL,PRS Control Register 0"
|
|
bitfld.long 0x00 8. " PRSMISSRSTEN ,PRS missing event will trigger a watchdog reset" "No reset,Reset"
|
|
bitfld.long 0x00 0.--4. " PRSSEL ,PRS channel PRS select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCH1_PRSCTRL,PRS Control Register 1"
|
|
bitfld.long 0x00 8. " PRSMISSRSTEN ,PRS missing event will trigger a watchdog reset" "No reset,Reset"
|
|
bitfld.long 0x00 0.--4. " PRSSEL ,PRS channel PRS select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IF_SET/CLEAR,Watchdog Interrupt Flags Set/Clear Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PEM1 ,PRS channel one event missing interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PEM0 ,PRS channel zero event missing interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " WIN ,Watchdog window interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WARN ,Watchdog warning timeout interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TOUT ,Watchdog timeout interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IEN,Watchdog Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " PEM1 ,PRS channel one event missing interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PEM0 ,PRS channel zero event missing interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WIN ,Watchdog window interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " WARN ,Watchdog warning timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOUT ,Watchdog timeout interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDOG1"
|
|
base ad:0x40052400
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Watchdog Control Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 31. " WDOGRSTDIS ,Watchdog reset disable" "No,Yes"
|
|
bitfld.long 0x00 30. " CLRSRC ,Watchdog clear source" "SW,PCH0"
|
|
bitfld.long 0x00 24.--26. " WINSEL ,Watchdog illegal windows select" "Disabled,12.5%,25%,37.5%,50%,62.5%,75%,87.5%"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " WARNSEL ,Watchdog timeout period select" "Disabled,25%,50%,75%"
|
|
bitfld.long 0x00 12.--13. " CLKSEL ,Watchdog clock select" "ULFRCO,LFRCO,LFXO,HFCORECLK"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 12.--13. " CLKSEL ,Watchdog clock select" "ULFRCO,LFRCO,LFXO,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--11. " PERSEL ,Watchdog timeout period select" "9 cycles,17 cycles,33 cycles,65 cycles,129 cycles,257 cycles,513 cycles,1k cycles,2k cycles,4k cycles,8k cycles,16k cycles,32k cycles,64k cycles,128k cycles,256k cycles"
|
|
bitfld.long 0x00 6. " SWOSCBLOCK ,Software oscillator disable block" "No,Yes"
|
|
bitfld.long 0x00 5. " EM4BLOCK ,Energy mode 4 block" "Not blocked,Blocked"
|
|
newline
|
|
bitfld.long 0x00 4. " LOCK ,Configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " EM3RUN ,Energy mode 3 run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EM2RUN ,Energy mode 2 run enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DEBUGRUN ,Debug mode run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Watchdog timer enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Watchdog Command Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Watchdog timer clear" "No effect,Clear"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SYNCBUSY,Watchdog Synchronization Busy Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 3. " PCH1_PRSCTRL ,PCH1_PRSCTRL register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " PCH0_PRSCTRL ,PCH0_PRSCTRL register busy" "Not busy,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PCH0_PRSCTRL,PRS Control Register 0"
|
|
bitfld.long 0x00 8. " PRSMISSRSTEN ,PRS missing event will trigger a watchdog reset" "No reset,Reset"
|
|
bitfld.long 0x00 0.--4. " PRSSEL ,PRS channel PRS select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCH1_PRSCTRL,PRS Control Register 1"
|
|
bitfld.long 0x00 8. " PRSMISSRSTEN ,PRS missing event will trigger a watchdog reset" "No reset,Reset"
|
|
bitfld.long 0x00 0.--4. " PRSSEL ,PRS channel PRS select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IF_SET/CLEAR,Watchdog Interrupt Flags Set/Clear Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PEM1 ,PRS channel one event missing interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PEM0 ,PRS channel zero event missing interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " WIN ,Watchdog window interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WARN ,Watchdog warning timeout interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TOUT ,Watchdog timeout interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IEN,Watchdog Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " PEM1 ,PRS channel one event missing interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PEM0 ,PRS channel zero event missing interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WIN ,Watchdog window interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " WARN ,Watchdog warning timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOUT ,Watchdog timeout interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PRS (Peripheral Reflex System)"
|
|
base ad:0x400E6000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SWPULSE,Software Pulse Register"
|
|
bitfld.long 0x00 23. " CH[23]PULSE ,Channel [23] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] pulse generation" "No effect,Generate"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] pulse generation" "No effect,Generate"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] pulse generation" "No effect,Generate"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] pulse generation" "No effect,Generate"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] pulse generation" "No effect,Generate"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] pulse generation" "No effect,Generate"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] pulse generation" "No effect,Generate"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "SWLEVEL,Software Level Register"
|
|
bitfld.long 0x00 23. " CH[23]LEVEL ,Channel [23] software level" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] software level" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] software level" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] software level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] software level" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] software level" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] software level" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] software level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] software level" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] software level" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] software level" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] software level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] software level" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] software level" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] software level" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] software level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] software level" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] software level" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] software level" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] software level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] software level" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] software level" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] software level" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] software level" "Low,High"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 23. " CH[23]PEN ,Channel [23] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Channel [22] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,Channel [21] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Channel [20] pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Channel [19] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Channel [18] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Channel [17] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [16] ,Channel [16] pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Channel [15] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Channel [14] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,Channel [13] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Channel [12] pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Channel [11] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Channel [10] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Channel [9] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Channel [8] pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Channel [7] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Channel [6] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Channel [5] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Channel [4] pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Channel [3] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Channel [2] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Channel [1] pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Channel [0] pin enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ROUTELOC0,I/O Routing Location 0 Register"
|
|
bitfld.long 0x00 24.--29. " CH[3 ]LOC ,Channel [3 ] I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x00 16.--21. " [2 ] ,Channel [2 ] I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x00 8.--13. " [1 ] ,Channel [1 ] I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x00 0.--5. " [0 ] ,Channel [0 ] I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ROUTELOC1,I/O Routing Location 1 Register"
|
|
bitfld.long 0x00 24.--29. " CH[7 ]LOC ,Channel [7 ] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 16.--21. " [6 ] ,Channel [6 ] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 8.--13. " [5 ] ,Channel [5 ] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 0.--5. " [4 ] ,Channel [4 ] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location 2 Register"
|
|
bitfld.long 0x00 24.--29. " CH[11]LOC ,Channel [11] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 16.--21. " [10] ,Channel [10] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 8.--13. " [9 ] ,Channel [9 ] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 0.--5. " [8 ] ,Channel [8 ] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ROUTELOC3,I/O Routing Location 3 Register"
|
|
bitfld.long 0x00 24.--29. " CH[15]LOC ,Channel [15] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 16.--21. " [14] ,Channel [14] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 8.--13. " [13] ,Channel [13] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 0.--5. " [12] ,Channel [12] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ROUTELOC4,I/O Routing Location 4 Register"
|
|
bitfld.long 0x00 24.--29. " CH[19]LOC ,Channel [19] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 16.--21. " [18] ,Channel [18] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 8.--13. " [17] ,Channel [17] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 0.--5. " [16] ,Channel [16] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ROUTELOC5,I/O Routing Location 5 Register"
|
|
bitfld.long 0x00 24.--29. " CH[23]LOC ,Channel [23] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 16.--21. " [22] ,Channel [22] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 8.--13. " [21] ,Channel [21] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x00 0.--5. " [20] ,Channel [20] I/O location" "LOC0,LOC1,LOC2,?..."
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 1.--5. " SEVONPRSSEL ,SEVONPRS PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 0. " SEVONPRS ,Set event on PRS" "Not set,Set"
|
|
line.long 0x04 "DMAREQ0,DMA Request 0 Register"
|
|
bitfld.long 0x04 6.--10. " PRSSEL ,DMA request 0 PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x08 "DMAREQ1,DMA Request 1 Register"
|
|
bitfld.long 0x08 6.--10. " PRSSEL ,DMA request 1 PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PEEK,PRS Channel Values"
|
|
bitfld.long 0x00 23. " CH[23]VAL ,Channel [23] current value" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] current value" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] current value" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] current value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] current value" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] current value" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] current value" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] current value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] current value" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] current value" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] current value" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] current value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] current value" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] current value" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] current value" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] current value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] current value" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] current value" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] current value" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] current value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] current value" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] current value" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] current value" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] current value" "Low,High"
|
|
tree "Control Registers"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH0_CTRL,Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1_CTRL,Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH2_CTRL,Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH3_CTRL,Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CH4_CTRL,Channel 4 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CH5_CTRL,Channel 5 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH6_CTRL,Channel 6 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH7_CTRL,Channel 7 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH8_CTRL,Channel 8 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH9_CTRL,Channel 9 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CH10_CTRL,Channel 10 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CH11_CTRL,Channel 11 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH12_CTRL,Channel 12 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH13_CTRL,Channel 13 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH14_CTRL,Channel 14 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH15_CTRL,Channel 15 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH16_CTRL,Channel 16 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH17_CTRL,Channel 17 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH18_CTRL,Channel 18 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH19_CTRL,Channel 19 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH20_CTRL,Channel 20 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH21_CTRL,Channel 21 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH22_CTRL,Channel 22 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH23_CTRL,Channel 23 Control Register"
|
|
bitfld.long 0x00 30. " ASYNC ,Asynchronous reflex" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ANDNEXT ,And next enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ORVPREV ,Or previous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INV ,Invert channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " STRETCH ,Stretch channel output" "Not stretched,Stretched"
|
|
bitfld.long 0x00 20.--21. " EDSEL ,Edge detect select" "Off,Positive edge,Negative edge,Both edges"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SOURCESEL ,Source select"
|
|
bitfld.long 0x00 0.--2. " SIGSEL ,Signal select" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("EFM32GG11B110*")&&!cpuis("EFM32GG11B120*")
|
|
tree "LCD (Liquid Crystal Display Driver)"
|
|
base ad:0x40054000
|
|
width 12.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 23. " DSC ,Direct segment control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " UDCTRL ,Update data control" "Regular,FCEVENT,FRAMESTART,?..."
|
|
bitfld.long 0x00 0. " EN ,LCD enable" "Disabled,Enabled"
|
|
line.long 0x04 "DISPCTRL,Display Control Register"
|
|
bitfld.long 0x04 28.--29. " MODE ,Mode setting" "NOEXTCAP,STEPDOWN,CPINTOSC,?..."
|
|
bitfld.long 0x04 24.--25. " BIAS ,Bias configuration" "STATIC,1/2 bias,1/3 bias,1/4 bias"
|
|
bitfld.long 0x04 20.--22. " CHGRDST ,Charge redistribution cycles" "Disabled,One,Two,Three,Four,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " CONTRAST ,Contrast control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4. " WAVE ,Waveform selection" "Low power,Normal"
|
|
bitfld.long 0x04 0.--2. " MUX ,Mux configuration" "Static,DUPLEX,TRIPLEX,QUADRUPLEX,,SEXTAPLEX,,OCTAPLEX"
|
|
line.long 0x08 "SEGEN,Segment Enable Register"
|
|
bitfld.long 0x08 31. " SEGEN[31] ,Segment [31] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Segment [30] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Segment [29] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [28] ,Segment [28] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " SEGEN[27] ,Segment [27] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Segment [26] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [25] ,Segment [25] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Segment [24] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " SEGEN[23] ,Segment [23] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [22] ,Segment [22] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Segment [21] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Segment [20] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " SEGEN[19] ,Segment [19] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Segment [18] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Segment [17] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [16] ,Segment [16] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " SEGEN[15] ,Segment [15] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Segment [14] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [13] ,Segment [13] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Segment [12] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " SEGEN[11] ,Segment [11] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Segment [10] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Segment [9] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Segment [8] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " SEGEN[7] ,Segment [7] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Segment [6] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Segment [5] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Segment [4] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " SEGEN[3] ,Segment [3] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Segment [2] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Segment [1] enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Segment [0] enable" "Disabled,Enabled"
|
|
line.long 0x0C "BACTRL,Blink and Animation Control Register"
|
|
bitfld.long 0x0C 28. " ALOC ,Animation location" "SEG0TO7,SEG8TO15"
|
|
bitfld.long 0x0C 18.--23. " FCTOP ,Frame counter top value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 16.--17. " FCPRESC ,Frame counter prescaler" "DIV1,DIV2,DIV4,DIV8"
|
|
newline
|
|
bitfld.long 0x0C 8. " FCEN ,Frame counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " ALOGSEL ,Animate logic function select" "AND,OR"
|
|
bitfld.long 0x0C 5.--6. " AREGBSC ,Animate register B shift control" "No shift,Shift left,Shift right,?..."
|
|
newline
|
|
bitfld.long 0x0C 3.--4. " AREGASC ,Animate register A shift control" "No shift,Shift left,Shift right,?..."
|
|
bitfld.long 0x0C 2. " AEN ,Animation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " BLANK ,Blank display" "Not blanked,Blanked"
|
|
bitfld.long 0x0C 0. " BLINKEN ,Blink enable" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 8. " BLINK ,Blink state" "On,Off"
|
|
bitfld.long 0x00 0.--3. " ASTATE ,Current animation state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x13
|
|
line.long 0x00 "AREGA,Animation Register A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AREGA ,Animation register A data"
|
|
line.long 0x04 "AREGB,Animation Register B"
|
|
hexmask.long.byte 0x04 0.--7. 1. " AREGB ,Animation register B data"
|
|
line.long 0x08 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " FC ,Frame counter interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " FC ,Frame Counter Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BIASCTRL,Analog BIAS Control"
|
|
bitfld.long 0x00 10.--12. " BUFBIAS ,Buffer bias setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--7. " BUFDRV ,Buffer drive strength" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " SPEED ,Speed adjustment" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SEGD0L,Segment Data Low Register 0"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SEGD1L,Segment Data Low Register 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SEGD2L,Segment Data Low Register 2"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SEGD3L,Segment Data Low Register 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SEGD0H,Segment Data High Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD0H ,COM0 segment data high"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SEGD1H,Segment Data High Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD1H ,COM1 segment data high"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SEGD2H,Segment Data High Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD2H ,COM2 segment data high"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SEGD3H,Segment Data High Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD3H ,COM3 segment data high"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SEGD4L,Segment Data Low Register 4"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SEGD5L,Segment Data Low Register 5"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SEGD6L,Segment Data Low Register 6"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SEGD7L,Segment Data Low Register 7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "SEGD4H,Segment Data High Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD4H ,COM4 segment data high"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SEGD5H,Segment Data High Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD5H ,COM5 segment data high"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SEGD6H,Segment Data High Register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD6H ,COM6 segment data high"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "SEGD7H,Segment Data High Register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEGD7H ,COM7 segment data high"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 1. " LCDGATE ,LCD gate" "Ungated,Gated"
|
|
bitfld.long 0x00 0. " REGFREEZE ,RegistEr Update Freeze" "Update,Freeze"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 19. " SEGD7H ,SEGD7H register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 18. " SEGD6H ,SEGD6H register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 17. " SEGD5H ,SEGD5H register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " SEGD4H ,SEGD4H register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " SEGD7L ,SEGD7L register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " SEGD6L ,SEGD6L register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 13. " SEGD5L ,SEGD5L register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 12. " SEGD4L ,SEGD4L register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 11. " SEGD3H ,SEGD3H register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 10. " SEGD2H ,SEGD2H register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 9. " SEGD1H ,SEGD1H register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " SEGD0H ,SEGD0H register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 7. " SEGD3L ,SEGD3L register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " SEGD2L ,SEGD2L register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " SEGD1L ,SEGD1L register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " SEGD0L ,SEGD0L register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " AREGB ,AREGB register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " AREGA ,AREGA register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " BACTRL ,BACTRL register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
group.long 0xF0++0x07
|
|
line.long 0x00 "FRAMERATE,Frame Rate Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " FRDIV ,Frame rate divider"
|
|
line.long 0x04 "SEGEN2,Segment Enable Register 2"
|
|
bitfld.long 0x04 7. " SEGEN[39] ,Segment [39] enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [34] ,Segment [34] enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [33] ,Segment [33] enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [32] ,Segment [32] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " SEGEN[35] ,Segment [35] enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Segment [34] enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Segment [33] enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Segment [32] enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "PCNT (Pulse Counter)"
|
|
tree "PCNT0"
|
|
base ad:0x4006E000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " TOPBHFSEL ,TOPB high frequency value select" "Not selected,Selected"
|
|
bitfld.long 0x00 26.--30. " .TCCPRSSEL ,TCC PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 25. " TCCPRSPOL ,TCC PRS polarity select" "Rising,Falling"
|
|
bitfld.long 0x00 24. " PRSGATEEN ,PRS gate enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " TCCCOMP ,Triggered compare and clear compare mode" "LTOE,GTOE,Range,?..."
|
|
bitfld.long 0x00 19.--20. " TCCPRESC ,Set the LFA prescaler for triggered compare and clear" "DIV1,DIV2,DIV4,DIV8"
|
|
bitfld.long 0x00 16.--17. " TCCMODE ,Sets the mode for triggered compare and clear" "Disabled,LFA,PRS,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " EDGE ,Edge select" "POS,NEG"
|
|
bitfld.long 0x00 14. " CNTDIR ,Non-quadrature mode counter direction control" "Up,Down"
|
|
bitfld.long 0x00 12.--13. " AUXCNTEV ,Controls when the auxiliary counter counts" "None,Up,Down,Both"
|
|
bitfld.long 0x00 10.--11. " CNTEV ,Controls when the counter counts" "Both,Up,Down,None"
|
|
newline
|
|
bitfld.long 0x00 9. " S1CDIR ,Count direction determined by S1" "Opposite,CNTDIR"
|
|
bitfld.long 0x00 8. " HYST ,Enable hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DEBUGHALT ,Debug mode halt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AUXCNTRSTEN ,Enable AUXCNT reset" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CNTRSTEN ,Enable PCNT clock domain reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RSTEN ,Enable PCNT reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FILT ,Enable digital pulse width filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " MODE ,Mode select" "Disable,OVSSINGLE,EXTCLKSINGLE,EXTCLKQUAD,OVSQUAD1X,OVSQUAD2X,OVSQUAD4X,?..."
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " LTOPBIM ,Load TOPB immediately" "No effect,Load"
|
|
bitfld.long 0x00 0. " LCNTIM ,Load CNT immediately" "No effect,Load"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " DIR ,Current counter direction" "Up,Down"
|
|
line.long 0x04 "CNT,Counter Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter value"
|
|
line.long 0x08 "TOP,Top Value Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TOP ,Counter top value"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TOPB,Top Value Buffer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOPB ,Counter top buffer"
|
|
line.long 0x04 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " OQSTERR ,Oversampling quadrature state error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " TCC ,Triggered compare interrupt read flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " AUXOF ,Auxiliary overflow interrupt read flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " DIRCNG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " OF ,Overflow interrupt read flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " UF ,Underflow interrupt read flag" "No interrupt,Interrupt"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " OQSTERR ,Oversampling quadrature state error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TCC ,Triggered compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AUXOF ,Auxiliary overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCNG ,Direction change detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ROUTELOC0,I/O Routing Location 0 Register"
|
|
bitfld.long 0x00 8.--13. " S1INLOC ,I/O S1IN location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x00 0.--5. " S0INLOC ,I/O S0IN location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 0. " REGFREEZE ,Register update freeze" "Update,Freeze"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 3. " OVSCFG ,OVSCFG register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " TOPB ,TOPB register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "AUXCNT,Auxiliary Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " AUXCNT ,Auxiliary counter value"
|
|
group.long 0x68++0x07
|
|
line.long 0x00 "INPUT,PCNT Input Register"
|
|
bitfld.long 0x00 11. " S1PRSEN ,S1IN PRS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--10. " S1PRSSEL ,S1IN PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 5. " S0PRSEN ,S0IN PRS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " S0PRSSEL ,S0IN PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "OVSCFG,Oversampling Config Register"
|
|
bitfld.long 0x04 12. " FLUTTERRM ,Flutter remove" "Not removed,Removed"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FILTLEN ,Filter length for inputs S0IN and S1IN"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCNT1"
|
|
base ad:0x4006E400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " TOPBHFSEL ,TOPB high frequency value select" "Not selected,Selected"
|
|
bitfld.long 0x00 26.--30. " .TCCPRSSEL ,TCC PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 25. " TCCPRSPOL ,TCC PRS polarity select" "Rising,Falling"
|
|
bitfld.long 0x00 24. " PRSGATEEN ,PRS gate enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " TCCCOMP ,Triggered compare and clear compare mode" "LTOE,GTOE,Range,?..."
|
|
bitfld.long 0x00 19.--20. " TCCPRESC ,Set the LFA prescaler for triggered compare and clear" "DIV1,DIV2,DIV4,DIV8"
|
|
bitfld.long 0x00 16.--17. " TCCMODE ,Sets the mode for triggered compare and clear" "Disabled,LFA,PRS,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " EDGE ,Edge select" "POS,NEG"
|
|
bitfld.long 0x00 14. " CNTDIR ,Non-quadrature mode counter direction control" "Up,Down"
|
|
bitfld.long 0x00 12.--13. " AUXCNTEV ,Controls when the auxiliary counter counts" "None,Up,Down,Both"
|
|
bitfld.long 0x00 10.--11. " CNTEV ,Controls when the counter counts" "Both,Up,Down,None"
|
|
newline
|
|
bitfld.long 0x00 9. " S1CDIR ,Count direction determined by S1" "Opposite,CNTDIR"
|
|
bitfld.long 0x00 8. " HYST ,Enable hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DEBUGHALT ,Debug mode halt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AUXCNTRSTEN ,Enable AUXCNT reset" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CNTRSTEN ,Enable PCNT clock domain reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RSTEN ,Enable PCNT reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FILT ,Enable digital pulse width filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " MODE ,Mode select" "Disable,OVSSINGLE,EXTCLKSINGLE,EXTCLKQUAD,OVSQUAD1X,OVSQUAD2X,OVSQUAD4X,?..."
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " LTOPBIM ,Load TOPB immediately" "No effect,Load"
|
|
bitfld.long 0x00 0. " LCNTIM ,Load CNT immediately" "No effect,Load"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " DIR ,Current counter direction" "Up,Down"
|
|
line.long 0x04 "CNT,Counter Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter value"
|
|
line.long 0x08 "TOP,Top Value Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TOP ,Counter top value"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TOPB,Top Value Buffer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOPB ,Counter top buffer"
|
|
line.long 0x04 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " OQSTERR ,Oversampling quadrature state error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " TCC ,Triggered compare interrupt read flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " AUXOF ,Auxiliary overflow interrupt read flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " DIRCNG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " OF ,Overflow interrupt read flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " UF ,Underflow interrupt read flag" "No interrupt,Interrupt"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " OQSTERR ,Oversampling quadrature state error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TCC ,Triggered compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AUXOF ,Auxiliary overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCNG ,Direction change detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ROUTELOC0,I/O Routing Location 0 Register"
|
|
bitfld.long 0x00 8.--13. " S1INLOC ,I/O S1IN location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x00 0.--5. " S0INLOC ,I/O S0IN location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 0. " REGFREEZE ,Register update freeze" "Update,Freeze"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 3. " OVSCFG ,OVSCFG register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " TOPB ,TOPB register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "AUXCNT,Auxiliary Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " AUXCNT ,Auxiliary counter value"
|
|
group.long 0x68++0x07
|
|
line.long 0x00 "INPUT,PCNT Input Register"
|
|
bitfld.long 0x00 11. " S1PRSEN ,S1IN PRS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--10. " S1PRSSEL ,S1IN PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 5. " S0PRSEN ,S0IN PRS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " S0PRSSEL ,S0IN PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "OVSCFG,Oversampling Config Register"
|
|
bitfld.long 0x04 12. " FLUTTERRM ,Flutter remove" "Not removed,Removed"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FILTLEN ,Filter length for inputs S0IN and S1IN"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCNT2"
|
|
base ad:0x4006E800
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " TOPBHFSEL ,TOPB high frequency value select" "Not selected,Selected"
|
|
bitfld.long 0x00 26.--30. " .TCCPRSSEL ,TCC PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 25. " TCCPRSPOL ,TCC PRS polarity select" "Rising,Falling"
|
|
bitfld.long 0x00 24. " PRSGATEEN ,PRS gate enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " TCCCOMP ,Triggered compare and clear compare mode" "LTOE,GTOE,Range,?..."
|
|
bitfld.long 0x00 19.--20. " TCCPRESC ,Set the LFA prescaler for triggered compare and clear" "DIV1,DIV2,DIV4,DIV8"
|
|
bitfld.long 0x00 16.--17. " TCCMODE ,Sets the mode for triggered compare and clear" "Disabled,LFA,PRS,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " EDGE ,Edge select" "POS,NEG"
|
|
bitfld.long 0x00 14. " CNTDIR ,Non-quadrature mode counter direction control" "Up,Down"
|
|
bitfld.long 0x00 12.--13. " AUXCNTEV ,Controls when the auxiliary counter counts" "None,Up,Down,Both"
|
|
bitfld.long 0x00 10.--11. " CNTEV ,Controls when the counter counts" "Both,Up,Down,None"
|
|
newline
|
|
bitfld.long 0x00 9. " S1CDIR ,Count direction determined by S1" "Opposite,CNTDIR"
|
|
bitfld.long 0x00 8. " HYST ,Enable hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DEBUGHALT ,Debug mode halt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AUXCNTRSTEN ,Enable AUXCNT reset" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CNTRSTEN ,Enable PCNT clock domain reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RSTEN ,Enable PCNT reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FILT ,Enable digital pulse width filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " MODE ,Mode select" "Disable,OVSSINGLE,EXTCLKSINGLE,EXTCLKQUAD,OVSQUAD1X,OVSQUAD2X,OVSQUAD4X,?..."
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " LTOPBIM ,Load TOPB immediately" "No effect,Load"
|
|
bitfld.long 0x00 0. " LCNTIM ,Load CNT immediately" "No effect,Load"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " DIR ,Current counter direction" "Up,Down"
|
|
line.long 0x04 "CNT,Counter Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter value"
|
|
line.long 0x08 "TOP,Top Value Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TOP ,Counter top value"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TOPB,Top Value Buffer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOPB ,Counter top buffer"
|
|
line.long 0x04 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " OQSTERR ,Oversampling quadrature state error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " TCC ,Triggered compare interrupt read flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " AUXOF ,Auxiliary overflow interrupt read flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " DIRCNG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " OF ,Overflow interrupt read flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " UF ,Underflow interrupt read flag" "No interrupt,Interrupt"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " OQSTERR ,Oversampling quadrature state error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TCC ,Triggered compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AUXOF ,Auxiliary overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCNG ,Direction change detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ROUTELOC0,I/O Routing Location 0 Register"
|
|
bitfld.long 0x00 8.--13. " S1INLOC ,I/O S1IN location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x00 0.--5. " S0INLOC ,I/O S0IN location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 0. " REGFREEZE ,Register update freeze" "Update,Freeze"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 3. " OVSCFG ,OVSCFG register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " TOPB ,TOPB register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "AUXCNT,Auxiliary Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " AUXCNT ,Auxiliary counter value"
|
|
group.long 0x68++0x07
|
|
line.long 0x00 "INPUT,PCNT Input Register"
|
|
bitfld.long 0x00 11. " S1PRSEN ,S1IN PRS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--10. " S1PRSSEL ,S1IN PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 5. " S0PRSEN ,S0IN PRS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " S0PRSSEL ,S0IN PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "OVSCFG,Oversampling Config Register"
|
|
bitfld.long 0x04 12. " FLUTTERRM ,Flutter remove" "Not removed,Removed"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FILTLEN ,Filter length for inputs S0IN and S1IN"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit Interface)"
|
|
tree "I2C 0"
|
|
base ad:0x40089000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 16.--18. " CLTO ,Clock low timeout" "Off,40PCC,80PCC,160PCC,320PPC,1024PPC,?..."
|
|
bitfld.long 0x00 15. " GIBITO ,Go idle on bus idle timeout" "No effect,Idle"
|
|
bitfld.long 0x00 12.--13. " BITO ,Bus idle timeout" "Off,40PCC,80PCC,160PCC"
|
|
bitfld.long 0x00 8.--9. " CLHR ,Clock low high ratio" "Standard,Asymmetric,Fast,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " TXBIL ,TX buffer interrupt level" "Empty,Half full"
|
|
bitfld.long 0x00 6. " GCAMEN ,General call address match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ARBDIS ,Arbitration disable" "No,Yes"
|
|
bitfld.long 0x00 4. " AUTOSN ,Automatic STOP on NACK" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " AUTOSE ,Automatic STOP when empty" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOACK ,Automatic acknowledge" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLAVE ,Addressable as slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,I2C enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 7. " CLEARPC ,Clear pending commands" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEARTX ,Clear transmit buffer" "No effect,Clear"
|
|
bitfld.long 0x00 5. " ABORT ,Abort transmission" "No effect,Abort"
|
|
newline
|
|
bitfld.long 0x00 4. " CONT ,Continue transmission" "No effect,Continue"
|
|
bitfld.long 0x00 3. " NACK ,Send NACK" "No effect,NACK"
|
|
bitfld.long 0x00 2. " ACK ,Send ACK" "No effect,ACK"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Send stop condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send start condition" "No effect,START"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "STATE,State Register"
|
|
bitfld.long 0x00 5.--7. " STATE ,Transmission state" "Idle,Wait,Start,Addr,Addrack,Data,Dataack,?..."
|
|
bitfld.long 0x00 4. " BUSHOLD ,Bus held" "Not held,Held"
|
|
bitfld.long 0x00 3. " NACKED ,NACK received" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x00 2. " TRANSMITTER ,Transmitter" "Receiver,Transmitter"
|
|
bitfld.long 0x00 1. " MASTER ,Master" "Slave,Master"
|
|
bitfld.long 0x00 0. " BUSY ,Bus busy" "Not busy,Busy"
|
|
line.long 0x04 "STATUS,Status Register"
|
|
bitfld.long 0x04 9. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 8. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
bitfld.long 0x04 7. " TXBL ,TX buffer level" "Full,Empty"
|
|
newline
|
|
bitfld.long 0x04 6. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x04 5. " PABORT ,Pending abort" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " PCONT ,Pending continue" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x04 3. " PNACK ,Pending NACK" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " PACK ,Pending ACK" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x04 1. " PSTOP ,Pending STOP" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " PSTART ,Pending START" "Not pending,Pending"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CLKDIV,Clock Division Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " DIV ,Clock divider"
|
|
line.long 0x04 "SADDR,Slave Address Register"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDR ,Slave address"
|
|
line.long 0x08 "SADDRMASK,Slave Address Mask Register"
|
|
hexmask.long.byte 0x08 1.--7. 0x02 " MASK ,Slave address mask"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,Receive Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLE,Receive Buffer Double Data Register"
|
|
in
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "RXDATAP,Receive Buffer Data Peek Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATAP ,RX data peek"
|
|
line.long 0x04 "RXDOUBLEP,Receive Buffer Double Data Peek Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXDATAP1 ,RX data 1 peek"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RXDATAP0 ,RX data 0 peek"
|
|
wgroup.long 0x2C++0x07
|
|
line.long 0x00 "TXDATA,Transmit Buffer Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,TX data"
|
|
line.long 0x04 "TXDOUBLE,Transmit Buffer Double Data Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TXDATAP1 ,TX data 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAP0 ,TX data 0"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " CLERR_SET/CLR ,Clock low error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RXFULL_SET/CLR ,Receive buffer full interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SSTOP_SET/CLR ,Slave STOP condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CLTO_SET/CLR ,Clock low timeout interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " BITO_SET/CLR ,Bus idle timeout interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " RXUF_SET/CLR ,Receive buffer underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TXOF_SET/CLR ,Transmit buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " BUSHOLD_SET/CLR ,Bus held interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " BUSERR_SET/CLR ,Bus error" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ARBLOST_SET/CLR ,Arbitration lost flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " MSTOP_SET/CLR ,Master STOP condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " NACK_SET/CLR ,Not acknowledge received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ACK_SET/CLR ,Acknowledge received interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " RXDATAV ,Receive data valid interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 4. " TXBL ,Transmit buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TXC_SET/CLR ,Transfer completed interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ADDR_SET/CLR ,Address interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RSTART_SET/CLR ,Repeated START condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " START_SET/CLR ,START condition interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 18. " CLERR ,Clock low error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RXFULL ,Receive buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSTOP ,Slave STOP condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CLTO ,Clock low interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " BITO ,Bus idle timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RXUF ,Receive buffer underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TXOF ,Transmit buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUSHOLD ,Bus held interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " BUSERR ,Bus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ARBLOST ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MSTOP ,Master STOP condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " NACK ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " ACK ,Acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXDATAV ,Receive data valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TXBL ,Transmit buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TXC ,Transfer completed interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " ADDR ,Address interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSTART ,Repeated START condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " START ,START condition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 1. " SCLPEN ,SCL pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SDAPEN ,SDA pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x08 8.--13. " SCLLOC ,I2C SCL pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " SDALOC ,I2C SDA pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C 1"
|
|
base ad:0x40089400
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 16.--18. " CLTO ,Clock low timeout" "Off,40PCC,80PCC,160PCC,320PPC,1024PPC,?..."
|
|
bitfld.long 0x00 15. " GIBITO ,Go idle on bus idle timeout" "No effect,Idle"
|
|
bitfld.long 0x00 12.--13. " BITO ,Bus idle timeout" "Off,40PCC,80PCC,160PCC"
|
|
bitfld.long 0x00 8.--9. " CLHR ,Clock low high ratio" "Standard,Asymmetric,Fast,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " TXBIL ,TX buffer interrupt level" "Empty,Half full"
|
|
bitfld.long 0x00 6. " GCAMEN ,General call address match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ARBDIS ,Arbitration disable" "No,Yes"
|
|
bitfld.long 0x00 4. " AUTOSN ,Automatic STOP on NACK" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " AUTOSE ,Automatic STOP when empty" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOACK ,Automatic acknowledge" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLAVE ,Addressable as slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,I2C enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 7. " CLEARPC ,Clear pending commands" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEARTX ,Clear transmit buffer" "No effect,Clear"
|
|
bitfld.long 0x00 5. " ABORT ,Abort transmission" "No effect,Abort"
|
|
newline
|
|
bitfld.long 0x00 4. " CONT ,Continue transmission" "No effect,Continue"
|
|
bitfld.long 0x00 3. " NACK ,Send NACK" "No effect,NACK"
|
|
bitfld.long 0x00 2. " ACK ,Send ACK" "No effect,ACK"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Send stop condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send start condition" "No effect,START"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "STATE,State Register"
|
|
bitfld.long 0x00 5.--7. " STATE ,Transmission state" "Idle,Wait,Start,Addr,Addrack,Data,Dataack,?..."
|
|
bitfld.long 0x00 4. " BUSHOLD ,Bus held" "Not held,Held"
|
|
bitfld.long 0x00 3. " NACKED ,NACK received" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x00 2. " TRANSMITTER ,Transmitter" "Receiver,Transmitter"
|
|
bitfld.long 0x00 1. " MASTER ,Master" "Slave,Master"
|
|
bitfld.long 0x00 0. " BUSY ,Bus busy" "Not busy,Busy"
|
|
line.long 0x04 "STATUS,Status Register"
|
|
bitfld.long 0x04 9. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 8. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
bitfld.long 0x04 7. " TXBL ,TX buffer level" "Full,Empty"
|
|
newline
|
|
bitfld.long 0x04 6. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x04 5. " PABORT ,Pending abort" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " PCONT ,Pending continue" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x04 3. " PNACK ,Pending NACK" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " PACK ,Pending ACK" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x04 1. " PSTOP ,Pending STOP" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " PSTART ,Pending START" "Not pending,Pending"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CLKDIV,Clock Division Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " DIV ,Clock divider"
|
|
line.long 0x04 "SADDR,Slave Address Register"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDR ,Slave address"
|
|
line.long 0x08 "SADDRMASK,Slave Address Mask Register"
|
|
hexmask.long.byte 0x08 1.--7. 0x02 " MASK ,Slave address mask"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,Receive Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLE,Receive Buffer Double Data Register"
|
|
in
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "RXDATAP,Receive Buffer Data Peek Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATAP ,RX data peek"
|
|
line.long 0x04 "RXDOUBLEP,Receive Buffer Double Data Peek Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXDATAP1 ,RX data 1 peek"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RXDATAP0 ,RX data 0 peek"
|
|
wgroup.long 0x2C++0x07
|
|
line.long 0x00 "TXDATA,Transmit Buffer Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,TX data"
|
|
line.long 0x04 "TXDOUBLE,Transmit Buffer Double Data Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TXDATAP1 ,TX data 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAP0 ,TX data 0"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " CLERR_SET/CLR ,Clock low error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RXFULL_SET/CLR ,Receive buffer full interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SSTOP_SET/CLR ,Slave STOP condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CLTO_SET/CLR ,Clock low timeout interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " BITO_SET/CLR ,Bus idle timeout interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " RXUF_SET/CLR ,Receive buffer underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TXOF_SET/CLR ,Transmit buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " BUSHOLD_SET/CLR ,Bus held interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " BUSERR_SET/CLR ,Bus error" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ARBLOST_SET/CLR ,Arbitration lost flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " MSTOP_SET/CLR ,Master STOP condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " NACK_SET/CLR ,Not acknowledge received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ACK_SET/CLR ,Acknowledge received interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " RXDATAV ,Receive data valid interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 4. " TXBL ,Transmit buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TXC_SET/CLR ,Transfer completed interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ADDR_SET/CLR ,Address interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RSTART_SET/CLR ,Repeated START condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " START_SET/CLR ,START condition interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 18. " CLERR ,Clock low error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RXFULL ,Receive buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSTOP ,Slave STOP condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CLTO ,Clock low interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " BITO ,Bus idle timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RXUF ,Receive buffer underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TXOF ,Transmit buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUSHOLD ,Bus held interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " BUSERR ,Bus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ARBLOST ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MSTOP ,Master STOP condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " NACK ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " ACK ,Acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXDATAV ,Receive data valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TXBL ,Transmit buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TXC ,Transfer completed interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " ADDR ,Address interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSTART ,Repeated START condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " START ,START condition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 1. " SCLPEN ,SCL pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SDAPEN ,SDA pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x08 8.--13. " SCLLOC ,I2C SCL pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " SDALOC ,I2C SDA pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C 2"
|
|
base ad:0x40089800
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 16.--18. " CLTO ,Clock low timeout" "Off,40PCC,80PCC,160PCC,320PPC,1024PPC,?..."
|
|
bitfld.long 0x00 15. " GIBITO ,Go idle on bus idle timeout" "No effect,Idle"
|
|
bitfld.long 0x00 12.--13. " BITO ,Bus idle timeout" "Off,40PCC,80PCC,160PCC"
|
|
bitfld.long 0x00 8.--9. " CLHR ,Clock low high ratio" "Standard,Asymmetric,Fast,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " TXBIL ,TX buffer interrupt level" "Empty,Half full"
|
|
bitfld.long 0x00 6. " GCAMEN ,General call address match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ARBDIS ,Arbitration disable" "No,Yes"
|
|
bitfld.long 0x00 4. " AUTOSN ,Automatic STOP on NACK" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " AUTOSE ,Automatic STOP when empty" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AUTOACK ,Automatic acknowledge" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLAVE ,Addressable as slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,I2C enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 7. " CLEARPC ,Clear pending commands" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEARTX ,Clear transmit buffer" "No effect,Clear"
|
|
bitfld.long 0x00 5. " ABORT ,Abort transmission" "No effect,Abort"
|
|
newline
|
|
bitfld.long 0x00 4. " CONT ,Continue transmission" "No effect,Continue"
|
|
bitfld.long 0x00 3. " NACK ,Send NACK" "No effect,NACK"
|
|
bitfld.long 0x00 2. " ACK ,Send ACK" "No effect,ACK"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Send stop condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send start condition" "No effect,START"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "STATE,State Register"
|
|
bitfld.long 0x00 5.--7. " STATE ,Transmission state" "Idle,Wait,Start,Addr,Addrack,Data,Dataack,?..."
|
|
bitfld.long 0x00 4. " BUSHOLD ,Bus held" "Not held,Held"
|
|
bitfld.long 0x00 3. " NACKED ,NACK received" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x00 2. " TRANSMITTER ,Transmitter" "Receiver,Transmitter"
|
|
bitfld.long 0x00 1. " MASTER ,Master" "Slave,Master"
|
|
bitfld.long 0x00 0. " BUSY ,Bus busy" "Not busy,Busy"
|
|
line.long 0x04 "STATUS,Status Register"
|
|
bitfld.long 0x04 9. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 8. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
bitfld.long 0x04 7. " TXBL ,TX buffer level" "Full,Empty"
|
|
newline
|
|
bitfld.long 0x04 6. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x04 5. " PABORT ,Pending abort" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " PCONT ,Pending continue" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x04 3. " PNACK ,Pending NACK" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " PACK ,Pending ACK" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x04 1. " PSTOP ,Pending STOP" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " PSTART ,Pending START" "Not pending,Pending"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CLKDIV,Clock Division Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " DIV ,Clock divider"
|
|
line.long 0x04 "SADDR,Slave Address Register"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDR ,Slave address"
|
|
line.long 0x08 "SADDRMASK,Slave Address Mask Register"
|
|
hexmask.long.byte 0x08 1.--7. 0x02 " MASK ,Slave address mask"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,Receive Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLE,Receive Buffer Double Data Register"
|
|
in
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "RXDATAP,Receive Buffer Data Peek Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATAP ,RX data peek"
|
|
line.long 0x04 "RXDOUBLEP,Receive Buffer Double Data Peek Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXDATAP1 ,RX data 1 peek"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RXDATAP0 ,RX data 0 peek"
|
|
wgroup.long 0x2C++0x07
|
|
line.long 0x00 "TXDATA,Transmit Buffer Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,TX data"
|
|
line.long 0x04 "TXDOUBLE,Transmit Buffer Double Data Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TXDATAP1 ,TX data 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAP0 ,TX data 0"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " CLERR_SET/CLR ,Clock low error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RXFULL_SET/CLR ,Receive buffer full interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SSTOP_SET/CLR ,Slave STOP condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CLTO_SET/CLR ,Clock low timeout interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " BITO_SET/CLR ,Bus idle timeout interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " RXUF_SET/CLR ,Receive buffer underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TXOF_SET/CLR ,Transmit buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " BUSHOLD_SET/CLR ,Bus held interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " BUSERR_SET/CLR ,Bus error" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ARBLOST_SET/CLR ,Arbitration lost flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " MSTOP_SET/CLR ,Master STOP condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " NACK_SET/CLR ,Not acknowledge received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ACK_SET/CLR ,Acknowledge received interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " RXDATAV ,Receive data valid interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 4. " TXBL ,Transmit buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TXC_SET/CLR ,Transfer completed interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ADDR_SET/CLR ,Address interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RSTART_SET/CLR ,Repeated START condition interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " START_SET/CLR ,START condition interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 18. " CLERR ,Clock low error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RXFULL ,Receive buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSTOP ,Slave STOP condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CLTO ,Clock low interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " BITO ,Bus idle timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RXUF ,Receive buffer underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TXOF ,Transmit buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUSHOLD ,Bus held interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " BUSERR ,Bus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ARBLOST ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MSTOP ,Master STOP condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " NACK ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " ACK ,Acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXDATAV ,Receive data valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TXBL ,Transmit buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TXC ,Transfer completed interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " ADDR ,Address interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSTART ,Repeated START condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " START ,START condition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 1. " SCLPEN ,SCL pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SDAPEN ,SDA pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x08 8.--13. " SCLLOC ,I2C SCL pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " SDALOC ,I2C SDA pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver/Transmitter)"
|
|
tree "USART 0"
|
|
base ad:0x40010000
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " SMSDELAY ,Synchronous master sample delay" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MVDIS ,Majority vote disable" "No,Yes"
|
|
bitfld.long 0x00 29. " AUTOTX ,Always transmit when RX not full" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BYTESWAP ,Byte-swap in double accesses" "Normal,Swapped"
|
|
bitfld.long 0x00 25. " SSSEARLY ,Synchronous slave setup early" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERRSTX ,Disable TX on error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " ERRSRX ,Disable RX on error" "No,Yes"
|
|
bitfld.long 0x00 22. " ERRSDMA ,Halt DMA on error" "Not halted,Halted"
|
|
bitfld.long 0x00 21. " BIT8DV ,Bit 8 default value" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SKIPPERRF ,Skip parity error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SCRETRANS ,SmartCard retransmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCMODE ,SmartCard mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AUTOTRI ,Automatic TX tristate" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AUTOCS ,Automatic chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSINV ,Chip select invert" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 14. " TXINV ,Transmitter output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " RXINV ,Receiver input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TXBIL ,TX buffer interrupt level" "Empty,Half-full"
|
|
newline
|
|
bitfld.long 0x00 11. " CSMA ,Action on slave-select in master mode" "No action,Go to slave mode"
|
|
bitfld.long 0x00 10. " MSBF ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLKPHA ,Clock edge for setup/sample" "Leading,Trailing"
|
|
newline
|
|
bitfld.long 0x00 8. " CLKPOL ,Clock polarity" "Idle low,Idle high"
|
|
bitfld.long 0x00 5.--6. " OVS ,Oversampling" "X16,X8,X6,X4"
|
|
bitfld.long 0x00 4. " MPAB ,Multi-processor address-bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2. " CCEN ,Collision check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
bitfld.long 0x00 0. " SYNC ,USART synchronous mode" "Asynchronous,Synchronous"
|
|
line.long 0x04 "FRAME,USART Frame Format Register"
|
|
bitfld.long 0x04 12.--13. " STOPBITS ,Stop-bit mode" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 8.--9. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x04 0.--3. " DATABITS ,Data-bit mode" ",4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
line.long 0x08 "TRIGCTRL,USART Trigger Control Register"
|
|
bitfld.long 0x08 16.--20. " TSEL ,Trigger PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 12. " RXATX2EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL2 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RXATX1EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL1 baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " RXATX0EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL0 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TXARX2EN ,Enable Tx trigger after Rx end of frame plus TCMP2VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TXARX1EN ,Enable Tx trigger after Rx end of frame plus TCMP1VAL baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " TXARX0EN ,Enable Tx trigger after Rx end of frame plus TCMP0VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " AUTOTXTEN ,AUTOTX trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TXTEN ,Transmit trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RXTEN ,Receive trigger enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " TXTRIDIS ,Transmitter tristate disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " TXTRIEN ,Transmitter tristate enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 7. " RXBLOCKDIS ,Receiver block disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " RXBLOCKEN ,Receiver block enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " MASTERDIS ,Master disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " MASTEREN ,Master enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,USART Status Register"
|
|
bitfld.long 0x00 16.--17. " TXBUFCNT ,TX buffer count" "0,1,2,3"
|
|
bitfld.long 0x00 14. " TIMERRESTARTED ,The USART timer restarted itself" "Not restarted,Restarted"
|
|
bitfld.long 0x00 13. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
bitfld.long 0x00 12. " RXFULLRIGHT ,RX Full of right data" "Not full,Full"
|
|
bitfld.long 0x00 11. " RXDATAVRIGHT ,RX data right" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXBSRIGHT ,TX buffer expects single right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TXBDRIGHT ,TX buffer expects double right data" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 7. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " TXBL ,TX buffer level" "Low level,High level"
|
|
bitfld.long 0x00 5. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " TXTRI ,Transmitter tristated" "Output,Tri-State"
|
|
newline
|
|
bitfld.long 0x00 3. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MASTER ,SPI master mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
bitfld.long 0x00 31. " AUTOBAUDEN ,Autobaud detection enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 3.--22. 1. " DIV ,Fractional clock divider"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,RX Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,RX Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLEX,RX Buffer Double Data Extended Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDOUBLE,RX FIFO Double Data Register"
|
|
in
|
|
if (((per.l(ad:0x40010000))&0x01)==0x00)
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
bitfld.long 0x04 30. " PERRP1 ,Data parity error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
bitfld.long 0x04 14. " PERRP0 ,Data parity error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
endif
|
|
wgroup.long 0x30++0x0F
|
|
line.long 0x00 "TXDATAX,TX Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x00 12. " TXTRIAT ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x00 11. " UBRXAT ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATAX ,Tx data"
|
|
line.long 0x04 "TXDATA,TX Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAX ,Tx data"
|
|
line.long 0x08 "TXDOUBLEX,TX Buffer Double Data Extended Register"
|
|
bitfld.long 0x08 31. " RXENAT1 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 30. " TXDISAT1 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 29. " TXBREAK1 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 28. " TXTRIAT1 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 27. " UBRXAT1 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 16.--24. 1. " TXDATA1 ,Tx data"
|
|
newline
|
|
bitfld.long 0x08 15. " RXENAT0 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 14. " TXDISAT0 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 13. " TXBREAK0 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 12. " TXTRIAT0 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 11. " UBRXAT0 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 0.--8. 1. " TXDATA0 ,Tx data"
|
|
line.long 0x0C "TXDOUBLE,TX Buffer Double Data Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TXDATA1 ,Tx data"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXDATA0 ,Tx data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TCMP2_SET/CLR ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TCMP1_SET/CLR ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TCMP0_SET/CLR ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TXIDLE_SET/CLR ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CCF_SET/CLR ,Collision check fail interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SSM_SET/CLR ,Slave-select in master mode interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TXUF_SET/CLR ,TX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXFULL_SET/CLR ,RX buffer full interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " TCMP2 ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TCMP1 ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TCMP0 ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TXIDLE ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CCF ,Collision check fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSM ,Slave-select in master mode interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXUF ,TX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXFULL ,RX buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRCTRL,IrDA Control Register"
|
|
bitfld.long 0x04 8.--12. " IRPRSSEL ,IrDA PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 7. " IRPRSEN ,IrDA PRS channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IRFILT ,IrDA RX filter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1.--2. " IRPW ,IrDA TX pulse width" "One,Two,Three,Four"
|
|
bitfld.long 0x04 0. " IREN ,Enable IrDA module" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "INPUT,USART Input Register"
|
|
bitfld.long 0x00 15. " CLKPRS ,PRS CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " CLKPRSSEL ,CLK PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "I2SCTRL,I2S Control Register"
|
|
bitfld.long 0x04 8.--10. " FORMAT ,I2S word format" "W32D32,W32D24M,W32D24,W32D16,W32D8,W16D16,W16D8,W8D8"
|
|
bitfld.long 0x04 4. " DELAY ,Delay on I2S data" "No delay,Delay"
|
|
bitfld.long 0x04 3. " DMASPLIT ,Separate DMA request for left/right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " JUSTIFY ,Justification of I2S data" "Left,Right"
|
|
bitfld.long 0x04 1. " MONO ,Stereo or mono" "Stereo,Mono"
|
|
bitfld.long 0x04 0. " EN ,Enable I2S mode" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "TIMING,Timing Register"
|
|
bitfld.long 0x00 28.--30. " CSHOLD ,Chip select hold" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 24.--26. " ICS ,Inter-character spacing" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
newline
|
|
bitfld.long 0x00 20.--22. " CSSETUP ,Chip select setup" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 16.--18. " TXDELAY ,TX frame start delay" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
line.long 0x04 "CTRLX,Control Register Extended"
|
|
bitfld.long 0x04 3. " RTSINV ,RTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 2. " CTSEN ,CTS function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CTSINV ,CTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMECMP0,Generate Interrupts and Various Delays Register 0"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 0" "TCMP0,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 0"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMECMP1,Generate Interrupts and Various Delays Register 1"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 1" "TCMP1,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMECMP2,Generate Interrupts and Various Delays Register 2"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 2" "TCMP2,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 2"
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 5. " RTSPEN ,RTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTSPEN ,CTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKPEN ,CLK pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CSPEN ,CS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 24.--29. " CLKLOC ,USART CLK pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 16.--21. " CSLOC ,USART CS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 8.--13. " RTSLOC ,USART RTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x08 0.--5. " CTSLOC ,USART CTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 1"
|
|
base ad:0x40010400
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " SMSDELAY ,Synchronous master sample delay" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MVDIS ,Majority vote disable" "No,Yes"
|
|
bitfld.long 0x00 29. " AUTOTX ,Always transmit when RX not full" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BYTESWAP ,Byte-swap in double accesses" "Normal,Swapped"
|
|
bitfld.long 0x00 25. " SSSEARLY ,Synchronous slave setup early" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERRSTX ,Disable TX on error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " ERRSRX ,Disable RX on error" "No,Yes"
|
|
bitfld.long 0x00 22. " ERRSDMA ,Halt DMA on error" "Not halted,Halted"
|
|
bitfld.long 0x00 21. " BIT8DV ,Bit 8 default value" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SKIPPERRF ,Skip parity error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SCRETRANS ,SmartCard retransmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCMODE ,SmartCard mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AUTOTRI ,Automatic TX tristate" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AUTOCS ,Automatic chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSINV ,Chip select invert" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 14. " TXINV ,Transmitter output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " RXINV ,Receiver input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TXBIL ,TX buffer interrupt level" "Empty,Half-full"
|
|
newline
|
|
bitfld.long 0x00 11. " CSMA ,Action on slave-select in master mode" "No action,Go to slave mode"
|
|
bitfld.long 0x00 10. " MSBF ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLKPHA ,Clock edge for setup/sample" "Leading,Trailing"
|
|
newline
|
|
bitfld.long 0x00 8. " CLKPOL ,Clock polarity" "Idle low,Idle high"
|
|
bitfld.long 0x00 5.--6. " OVS ,Oversampling" "X16,X8,X6,X4"
|
|
bitfld.long 0x00 4. " MPAB ,Multi-processor address-bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2. " CCEN ,Collision check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
bitfld.long 0x00 0. " SYNC ,USART synchronous mode" "Asynchronous,Synchronous"
|
|
line.long 0x04 "FRAME,USART Frame Format Register"
|
|
bitfld.long 0x04 12.--13. " STOPBITS ,Stop-bit mode" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 8.--9. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x04 0.--3. " DATABITS ,Data-bit mode" ",4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
line.long 0x08 "TRIGCTRL,USART Trigger Control Register"
|
|
bitfld.long 0x08 16.--20. " TSEL ,Trigger PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 12. " RXATX2EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL2 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RXATX1EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL1 baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " RXATX0EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL0 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TXARX2EN ,Enable Tx trigger after Rx end of frame plus TCMP2VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TXARX1EN ,Enable Tx trigger after Rx end of frame plus TCMP1VAL baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " TXARX0EN ,Enable Tx trigger after Rx end of frame plus TCMP0VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " AUTOTXTEN ,AUTOTX trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TXTEN ,Transmit trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RXTEN ,Receive trigger enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " TXTRIDIS ,Transmitter tristate disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " TXTRIEN ,Transmitter tristate enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 7. " RXBLOCKDIS ,Receiver block disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " RXBLOCKEN ,Receiver block enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " MASTERDIS ,Master disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " MASTEREN ,Master enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,USART Status Register"
|
|
bitfld.long 0x00 16.--17. " TXBUFCNT ,TX buffer count" "0,1,2,3"
|
|
bitfld.long 0x00 14. " TIMERRESTARTED ,The USART timer restarted itself" "Not restarted,Restarted"
|
|
bitfld.long 0x00 13. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
bitfld.long 0x00 12. " RXFULLRIGHT ,RX Full of right data" "Not full,Full"
|
|
bitfld.long 0x00 11. " RXDATAVRIGHT ,RX data right" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXBSRIGHT ,TX buffer expects single right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TXBDRIGHT ,TX buffer expects double right data" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 7. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " TXBL ,TX buffer level" "Low level,High level"
|
|
bitfld.long 0x00 5. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " TXTRI ,Transmitter tristated" "Output,Tri-State"
|
|
newline
|
|
bitfld.long 0x00 3. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MASTER ,SPI master mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
bitfld.long 0x00 31. " AUTOBAUDEN ,Autobaud detection enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 3.--22. 1. " DIV ,Fractional clock divider"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,RX Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,RX Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLEX,RX Buffer Double Data Extended Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDOUBLE,RX FIFO Double Data Register"
|
|
in
|
|
if (((per.l(ad:0x40010400))&0x01)==0x00)
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
bitfld.long 0x04 30. " PERRP1 ,Data parity error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
bitfld.long 0x04 14. " PERRP0 ,Data parity error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
endif
|
|
wgroup.long 0x30++0x0F
|
|
line.long 0x00 "TXDATAX,TX Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x00 12. " TXTRIAT ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x00 11. " UBRXAT ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATAX ,Tx data"
|
|
line.long 0x04 "TXDATA,TX Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAX ,Tx data"
|
|
line.long 0x08 "TXDOUBLEX,TX Buffer Double Data Extended Register"
|
|
bitfld.long 0x08 31. " RXENAT1 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 30. " TXDISAT1 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 29. " TXBREAK1 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 28. " TXTRIAT1 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 27. " UBRXAT1 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 16.--24. 1. " TXDATA1 ,Tx data"
|
|
newline
|
|
bitfld.long 0x08 15. " RXENAT0 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 14. " TXDISAT0 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 13. " TXBREAK0 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 12. " TXTRIAT0 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 11. " UBRXAT0 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 0.--8. 1. " TXDATA0 ,Tx data"
|
|
line.long 0x0C "TXDOUBLE,TX Buffer Double Data Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TXDATA1 ,Tx data"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXDATA0 ,Tx data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TCMP2_SET/CLR ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TCMP1_SET/CLR ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TCMP0_SET/CLR ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TXIDLE_SET/CLR ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CCF_SET/CLR ,Collision check fail interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SSM_SET/CLR ,Slave-select in master mode interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TXUF_SET/CLR ,TX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXFULL_SET/CLR ,RX buffer full interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " TCMP2 ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TCMP1 ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TCMP0 ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TXIDLE ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CCF ,Collision check fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSM ,Slave-select in master mode interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXUF ,TX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXFULL ,RX buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRCTRL,IrDA Control Register"
|
|
bitfld.long 0x04 8.--12. " IRPRSSEL ,IrDA PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 7. " IRPRSEN ,IrDA PRS channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IRFILT ,IrDA RX filter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1.--2. " IRPW ,IrDA TX pulse width" "One,Two,Three,Four"
|
|
bitfld.long 0x04 0. " IREN ,Enable IrDA module" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "INPUT,USART Input Register"
|
|
bitfld.long 0x00 15. " CLKPRS ,PRS CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " CLKPRSSEL ,CLK PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "I2SCTRL,I2S Control Register"
|
|
bitfld.long 0x04 8.--10. " FORMAT ,I2S word format" "W32D32,W32D24M,W32D24,W32D16,W32D8,W16D16,W16D8,W8D8"
|
|
bitfld.long 0x04 4. " DELAY ,Delay on I2S data" "No delay,Delay"
|
|
bitfld.long 0x04 3. " DMASPLIT ,Separate DMA request for left/right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " JUSTIFY ,Justification of I2S data" "Left,Right"
|
|
bitfld.long 0x04 1. " MONO ,Stereo or mono" "Stereo,Mono"
|
|
bitfld.long 0x04 0. " EN ,Enable I2S mode" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "TIMING,Timing Register"
|
|
bitfld.long 0x00 28.--30. " CSHOLD ,Chip select hold" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 24.--26. " ICS ,Inter-character spacing" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
newline
|
|
bitfld.long 0x00 20.--22. " CSSETUP ,Chip select setup" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 16.--18. " TXDELAY ,TX frame start delay" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
line.long 0x04 "CTRLX,Control Register Extended"
|
|
bitfld.long 0x04 3. " RTSINV ,RTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 2. " CTSEN ,CTS function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CTSINV ,CTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMECMP0,Generate Interrupts and Various Delays Register 0"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 0" "TCMP0,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 0"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMECMP1,Generate Interrupts and Various Delays Register 1"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 1" "TCMP1,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMECMP2,Generate Interrupts and Various Delays Register 2"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 2" "TCMP2,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 2"
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 5. " RTSPEN ,RTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTSPEN ,CTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKPEN ,CLK pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CSPEN ,CS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 24.--29. " CLKLOC ,USART CLK pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 16.--21. " CSLOC ,USART CS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 8.--13. " RTSLOC ,USART RTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x08 0.--5. " CTSLOC ,USART CTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x40010800
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " SMSDELAY ,Synchronous master sample delay" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MVDIS ,Majority vote disable" "No,Yes"
|
|
bitfld.long 0x00 29. " AUTOTX ,Always transmit when RX not full" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BYTESWAP ,Byte-swap in double accesses" "Normal,Swapped"
|
|
bitfld.long 0x00 25. " SSSEARLY ,Synchronous slave setup early" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERRSTX ,Disable TX on error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " ERRSRX ,Disable RX on error" "No,Yes"
|
|
bitfld.long 0x00 22. " ERRSDMA ,Halt DMA on error" "Not halted,Halted"
|
|
bitfld.long 0x00 21. " BIT8DV ,Bit 8 default value" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SKIPPERRF ,Skip parity error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SCRETRANS ,SmartCard retransmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCMODE ,SmartCard mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AUTOTRI ,Automatic TX tristate" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AUTOCS ,Automatic chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSINV ,Chip select invert" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 14. " TXINV ,Transmitter output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " RXINV ,Receiver input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TXBIL ,TX buffer interrupt level" "Empty,Half-full"
|
|
newline
|
|
bitfld.long 0x00 11. " CSMA ,Action on slave-select in master mode" "No action,Go to slave mode"
|
|
bitfld.long 0x00 10. " MSBF ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLKPHA ,Clock edge for setup/sample" "Leading,Trailing"
|
|
newline
|
|
bitfld.long 0x00 8. " CLKPOL ,Clock polarity" "Idle low,Idle high"
|
|
bitfld.long 0x00 5.--6. " OVS ,Oversampling" "X16,X8,X6,X4"
|
|
bitfld.long 0x00 4. " MPAB ,Multi-processor address-bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2. " CCEN ,Collision check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
bitfld.long 0x00 0. " SYNC ,USART synchronous mode" "Asynchronous,Synchronous"
|
|
line.long 0x04 "FRAME,USART Frame Format Register"
|
|
bitfld.long 0x04 12.--13. " STOPBITS ,Stop-bit mode" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 8.--9. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x04 0.--3. " DATABITS ,Data-bit mode" ",4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
line.long 0x08 "TRIGCTRL,USART Trigger Control Register"
|
|
bitfld.long 0x08 16.--20. " TSEL ,Trigger PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 12. " RXATX2EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL2 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RXATX1EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL1 baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " RXATX0EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL0 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TXARX2EN ,Enable Tx trigger after Rx end of frame plus TCMP2VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TXARX1EN ,Enable Tx trigger after Rx end of frame plus TCMP1VAL baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " TXARX0EN ,Enable Tx trigger after Rx end of frame plus TCMP0VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " AUTOTXTEN ,AUTOTX trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TXTEN ,Transmit trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RXTEN ,Receive trigger enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " TXTRIDIS ,Transmitter tristate disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " TXTRIEN ,Transmitter tristate enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 7. " RXBLOCKDIS ,Receiver block disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " RXBLOCKEN ,Receiver block enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " MASTERDIS ,Master disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " MASTEREN ,Master enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,USART Status Register"
|
|
bitfld.long 0x00 16.--17. " TXBUFCNT ,TX buffer count" "0,1,2,3"
|
|
bitfld.long 0x00 14. " TIMERRESTARTED ,The USART timer restarted itself" "Not restarted,Restarted"
|
|
bitfld.long 0x00 13. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
bitfld.long 0x00 12. " RXFULLRIGHT ,RX Full of right data" "Not full,Full"
|
|
bitfld.long 0x00 11. " RXDATAVRIGHT ,RX data right" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXBSRIGHT ,TX buffer expects single right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TXBDRIGHT ,TX buffer expects double right data" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 7. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " TXBL ,TX buffer level" "Low level,High level"
|
|
bitfld.long 0x00 5. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " TXTRI ,Transmitter tristated" "Output,Tri-State"
|
|
newline
|
|
bitfld.long 0x00 3. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MASTER ,SPI master mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
bitfld.long 0x00 31. " AUTOBAUDEN ,Autobaud detection enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 3.--22. 1. " DIV ,Fractional clock divider"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,RX Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,RX Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLEX,RX Buffer Double Data Extended Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDOUBLE,RX FIFO Double Data Register"
|
|
in
|
|
if (((per.l(ad:0x40010800))&0x01)==0x00)
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
bitfld.long 0x04 30. " PERRP1 ,Data parity error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
bitfld.long 0x04 14. " PERRP0 ,Data parity error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
endif
|
|
wgroup.long 0x30++0x0F
|
|
line.long 0x00 "TXDATAX,TX Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x00 12. " TXTRIAT ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x00 11. " UBRXAT ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATAX ,Tx data"
|
|
line.long 0x04 "TXDATA,TX Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAX ,Tx data"
|
|
line.long 0x08 "TXDOUBLEX,TX Buffer Double Data Extended Register"
|
|
bitfld.long 0x08 31. " RXENAT1 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 30. " TXDISAT1 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 29. " TXBREAK1 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 28. " TXTRIAT1 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 27. " UBRXAT1 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 16.--24. 1. " TXDATA1 ,Tx data"
|
|
newline
|
|
bitfld.long 0x08 15. " RXENAT0 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 14. " TXDISAT0 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 13. " TXBREAK0 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 12. " TXTRIAT0 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 11. " UBRXAT0 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 0.--8. 1. " TXDATA0 ,Tx data"
|
|
line.long 0x0C "TXDOUBLE,TX Buffer Double Data Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TXDATA1 ,Tx data"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXDATA0 ,Tx data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TCMP2_SET/CLR ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TCMP1_SET/CLR ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TCMP0_SET/CLR ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TXIDLE_SET/CLR ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CCF_SET/CLR ,Collision check fail interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SSM_SET/CLR ,Slave-select in master mode interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TXUF_SET/CLR ,TX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXFULL_SET/CLR ,RX buffer full interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " TCMP2 ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TCMP1 ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TCMP0 ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TXIDLE ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CCF ,Collision check fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSM ,Slave-select in master mode interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXUF ,TX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXFULL ,RX buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRCTRL,IrDA Control Register"
|
|
bitfld.long 0x04 8.--12. " IRPRSSEL ,IrDA PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 7. " IRPRSEN ,IrDA PRS channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IRFILT ,IrDA RX filter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1.--2. " IRPW ,IrDA TX pulse width" "One,Two,Three,Four"
|
|
bitfld.long 0x04 0. " IREN ,Enable IrDA module" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "INPUT,USART Input Register"
|
|
bitfld.long 0x00 15. " CLKPRS ,PRS CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " CLKPRSSEL ,CLK PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "I2SCTRL,I2S Control Register"
|
|
bitfld.long 0x04 8.--10. " FORMAT ,I2S word format" "W32D32,W32D24M,W32D24,W32D16,W32D8,W16D16,W16D8,W8D8"
|
|
bitfld.long 0x04 4. " DELAY ,Delay on I2S data" "No delay,Delay"
|
|
bitfld.long 0x04 3. " DMASPLIT ,Separate DMA request for left/right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " JUSTIFY ,Justification of I2S data" "Left,Right"
|
|
bitfld.long 0x04 1. " MONO ,Stereo or mono" "Stereo,Mono"
|
|
bitfld.long 0x04 0. " EN ,Enable I2S mode" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "TIMING,Timing Register"
|
|
bitfld.long 0x00 28.--30. " CSHOLD ,Chip select hold" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 24.--26. " ICS ,Inter-character spacing" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
newline
|
|
bitfld.long 0x00 20.--22. " CSSETUP ,Chip select setup" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 16.--18. " TXDELAY ,TX frame start delay" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
line.long 0x04 "CTRLX,Control Register Extended"
|
|
bitfld.long 0x04 3. " RTSINV ,RTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 2. " CTSEN ,CTS function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CTSINV ,CTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMECMP0,Generate Interrupts and Various Delays Register 0"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 0" "TCMP0,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 0"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMECMP1,Generate Interrupts and Various Delays Register 1"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 1" "TCMP1,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMECMP2,Generate Interrupts and Various Delays Register 2"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 2" "TCMP2,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 2"
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 5. " RTSPEN ,RTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTSPEN ,CTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKPEN ,CLK pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CSPEN ,CS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 24.--29. " CLKLOC ,USART CLK pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 16.--21. " CSLOC ,USART CS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 8.--13. " RTSLOC ,USART RTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x08 0.--5. " CTSLOC ,USART CTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 3"
|
|
base ad:0x40010C00
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " SMSDELAY ,Synchronous master sample delay" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MVDIS ,Majority vote disable" "No,Yes"
|
|
bitfld.long 0x00 29. " AUTOTX ,Always transmit when RX not full" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BYTESWAP ,Byte-swap in double accesses" "Normal,Swapped"
|
|
bitfld.long 0x00 25. " SSSEARLY ,Synchronous slave setup early" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERRSTX ,Disable TX on error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " ERRSRX ,Disable RX on error" "No,Yes"
|
|
bitfld.long 0x00 22. " ERRSDMA ,Halt DMA on error" "Not halted,Halted"
|
|
bitfld.long 0x00 21. " BIT8DV ,Bit 8 default value" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SKIPPERRF ,Skip parity error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SCRETRANS ,SmartCard retransmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCMODE ,SmartCard mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AUTOTRI ,Automatic TX tristate" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AUTOCS ,Automatic chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSINV ,Chip select invert" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 14. " TXINV ,Transmitter output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " RXINV ,Receiver input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TXBIL ,TX buffer interrupt level" "Empty,Half-full"
|
|
newline
|
|
bitfld.long 0x00 11. " CSMA ,Action on slave-select in master mode" "No action,Go to slave mode"
|
|
bitfld.long 0x00 10. " MSBF ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLKPHA ,Clock edge for setup/sample" "Leading,Trailing"
|
|
newline
|
|
bitfld.long 0x00 8. " CLKPOL ,Clock polarity" "Idle low,Idle high"
|
|
bitfld.long 0x00 5.--6. " OVS ,Oversampling" "X16,X8,X6,X4"
|
|
bitfld.long 0x00 4. " MPAB ,Multi-processor address-bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2. " CCEN ,Collision check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
bitfld.long 0x00 0. " SYNC ,USART synchronous mode" "Asynchronous,Synchronous"
|
|
line.long 0x04 "FRAME,USART Frame Format Register"
|
|
bitfld.long 0x04 12.--13. " STOPBITS ,Stop-bit mode" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 8.--9. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x04 0.--3. " DATABITS ,Data-bit mode" ",4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
line.long 0x08 "TRIGCTRL,USART Trigger Control Register"
|
|
bitfld.long 0x08 16.--20. " TSEL ,Trigger PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 12. " RXATX2EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL2 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RXATX1EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL1 baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " RXATX0EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL0 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TXARX2EN ,Enable Tx trigger after Rx end of frame plus TCMP2VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TXARX1EN ,Enable Tx trigger after Rx end of frame plus TCMP1VAL baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " TXARX0EN ,Enable Tx trigger after Rx end of frame plus TCMP0VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " AUTOTXTEN ,AUTOTX trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TXTEN ,Transmit trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RXTEN ,Receive trigger enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " TXTRIDIS ,Transmitter tristate disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " TXTRIEN ,Transmitter tristate enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 7. " RXBLOCKDIS ,Receiver block disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " RXBLOCKEN ,Receiver block enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " MASTERDIS ,Master disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " MASTEREN ,Master enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,USART Status Register"
|
|
bitfld.long 0x00 16.--17. " TXBUFCNT ,TX buffer count" "0,1,2,3"
|
|
bitfld.long 0x00 14. " TIMERRESTARTED ,The USART timer restarted itself" "Not restarted,Restarted"
|
|
bitfld.long 0x00 13. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
bitfld.long 0x00 12. " RXFULLRIGHT ,RX Full of right data" "Not full,Full"
|
|
bitfld.long 0x00 11. " RXDATAVRIGHT ,RX data right" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXBSRIGHT ,TX buffer expects single right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TXBDRIGHT ,TX buffer expects double right data" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 7. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " TXBL ,TX buffer level" "Low level,High level"
|
|
bitfld.long 0x00 5. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " TXTRI ,Transmitter tristated" "Output,Tri-State"
|
|
newline
|
|
bitfld.long 0x00 3. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MASTER ,SPI master mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
bitfld.long 0x00 31. " AUTOBAUDEN ,Autobaud detection enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 3.--22. 1. " DIV ,Fractional clock divider"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,RX Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,RX Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLEX,RX Buffer Double Data Extended Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDOUBLE,RX FIFO Double Data Register"
|
|
in
|
|
if (((per.l(ad:0x40010C00))&0x01)==0x00)
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
bitfld.long 0x04 30. " PERRP1 ,Data parity error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
bitfld.long 0x04 14. " PERRP0 ,Data parity error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
endif
|
|
wgroup.long 0x30++0x0F
|
|
line.long 0x00 "TXDATAX,TX Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x00 12. " TXTRIAT ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x00 11. " UBRXAT ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATAX ,Tx data"
|
|
line.long 0x04 "TXDATA,TX Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAX ,Tx data"
|
|
line.long 0x08 "TXDOUBLEX,TX Buffer Double Data Extended Register"
|
|
bitfld.long 0x08 31. " RXENAT1 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 30. " TXDISAT1 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 29. " TXBREAK1 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 28. " TXTRIAT1 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 27. " UBRXAT1 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 16.--24. 1. " TXDATA1 ,Tx data"
|
|
newline
|
|
bitfld.long 0x08 15. " RXENAT0 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 14. " TXDISAT0 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 13. " TXBREAK0 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 12. " TXTRIAT0 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 11. " UBRXAT0 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 0.--8. 1. " TXDATA0 ,Tx data"
|
|
line.long 0x0C "TXDOUBLE,TX Buffer Double Data Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TXDATA1 ,Tx data"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXDATA0 ,Tx data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TCMP2_SET/CLR ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TCMP1_SET/CLR ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TCMP0_SET/CLR ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TXIDLE_SET/CLR ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CCF_SET/CLR ,Collision check fail interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SSM_SET/CLR ,Slave-select in master mode interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TXUF_SET/CLR ,TX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXFULL_SET/CLR ,RX buffer full interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " TCMP2 ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TCMP1 ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TCMP0 ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TXIDLE ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CCF ,Collision check fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSM ,Slave-select in master mode interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXUF ,TX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXFULL ,RX buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRCTRL,IrDA Control Register"
|
|
bitfld.long 0x04 8.--12. " IRPRSSEL ,IrDA PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 7. " IRPRSEN ,IrDA PRS channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IRFILT ,IrDA RX filter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1.--2. " IRPW ,IrDA TX pulse width" "One,Two,Three,Four"
|
|
bitfld.long 0x04 0. " IREN ,Enable IrDA module" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "INPUT,USART Input Register"
|
|
bitfld.long 0x00 15. " CLKPRS ,PRS CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " CLKPRSSEL ,CLK PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "I2SCTRL,I2S Control Register"
|
|
bitfld.long 0x04 8.--10. " FORMAT ,I2S word format" "W32D32,W32D24M,W32D24,W32D16,W32D8,W16D16,W16D8,W8D8"
|
|
bitfld.long 0x04 4. " DELAY ,Delay on I2S data" "No delay,Delay"
|
|
bitfld.long 0x04 3. " DMASPLIT ,Separate DMA request for left/right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " JUSTIFY ,Justification of I2S data" "Left,Right"
|
|
bitfld.long 0x04 1. " MONO ,Stereo or mono" "Stereo,Mono"
|
|
bitfld.long 0x04 0. " EN ,Enable I2S mode" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "TIMING,Timing Register"
|
|
bitfld.long 0x00 28.--30. " CSHOLD ,Chip select hold" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 24.--26. " ICS ,Inter-character spacing" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
newline
|
|
bitfld.long 0x00 20.--22. " CSSETUP ,Chip select setup" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 16.--18. " TXDELAY ,TX frame start delay" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
line.long 0x04 "CTRLX,Control Register Extended"
|
|
bitfld.long 0x04 3. " RTSINV ,RTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 2. " CTSEN ,CTS function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CTSINV ,CTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMECMP0,Generate Interrupts and Various Delays Register 0"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 0" "TCMP0,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 0"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMECMP1,Generate Interrupts and Various Delays Register 1"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 1" "TCMP1,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMECMP2,Generate Interrupts and Various Delays Register 2"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 2" "TCMP2,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 2"
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 5. " RTSPEN ,RTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTSPEN ,CTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKPEN ,CLK pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CSPEN ,CS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 24.--29. " CLKLOC ,USART CLK pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 16.--21. " CSLOC ,USART CS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 8.--13. " RTSLOC ,USART RTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x08 0.--5. " CTSLOC ,USART CTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 4"
|
|
base ad:0x40011000
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " SMSDELAY ,Synchronous master sample delay" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MVDIS ,Majority vote disable" "No,Yes"
|
|
bitfld.long 0x00 29. " AUTOTX ,Always transmit when RX not full" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BYTESWAP ,Byte-swap in double accesses" "Normal,Swapped"
|
|
bitfld.long 0x00 25. " SSSEARLY ,Synchronous slave setup early" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERRSTX ,Disable TX on error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " ERRSRX ,Disable RX on error" "No,Yes"
|
|
bitfld.long 0x00 22. " ERRSDMA ,Halt DMA on error" "Not halted,Halted"
|
|
bitfld.long 0x00 21. " BIT8DV ,Bit 8 default value" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SKIPPERRF ,Skip parity error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SCRETRANS ,SmartCard retransmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCMODE ,SmartCard mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AUTOTRI ,Automatic TX tristate" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AUTOCS ,Automatic chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSINV ,Chip select invert" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 14. " TXINV ,Transmitter output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " RXINV ,Receiver input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TXBIL ,TX buffer interrupt level" "Empty,Half-full"
|
|
newline
|
|
bitfld.long 0x00 11. " CSMA ,Action on slave-select in master mode" "No action,Go to slave mode"
|
|
bitfld.long 0x00 10. " MSBF ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLKPHA ,Clock edge for setup/sample" "Leading,Trailing"
|
|
newline
|
|
bitfld.long 0x00 8. " CLKPOL ,Clock polarity" "Idle low,Idle high"
|
|
bitfld.long 0x00 5.--6. " OVS ,Oversampling" "X16,X8,X6,X4"
|
|
bitfld.long 0x00 4. " MPAB ,Multi-processor address-bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2. " CCEN ,Collision check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
bitfld.long 0x00 0. " SYNC ,USART synchronous mode" "Asynchronous,Synchronous"
|
|
line.long 0x04 "FRAME,USART Frame Format Register"
|
|
bitfld.long 0x04 12.--13. " STOPBITS ,Stop-bit mode" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 8.--9. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x04 0.--3. " DATABITS ,Data-bit mode" ",4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
line.long 0x08 "TRIGCTRL,USART Trigger Control Register"
|
|
bitfld.long 0x08 16.--20. " TSEL ,Trigger PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 12. " RXATX2EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL2 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RXATX1EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL1 baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " RXATX0EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL0 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TXARX2EN ,Enable Tx trigger after Rx end of frame plus TCMP2VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TXARX1EN ,Enable Tx trigger after Rx end of frame plus TCMP1VAL baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " TXARX0EN ,Enable Tx trigger after Rx end of frame plus TCMP0VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " AUTOTXTEN ,AUTOTX trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TXTEN ,Transmit trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RXTEN ,Receive trigger enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " TXTRIDIS ,Transmitter tristate disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " TXTRIEN ,Transmitter tristate enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 7. " RXBLOCKDIS ,Receiver block disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " RXBLOCKEN ,Receiver block enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " MASTERDIS ,Master disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " MASTEREN ,Master enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,USART Status Register"
|
|
bitfld.long 0x00 16.--17. " TXBUFCNT ,TX buffer count" "0,1,2,3"
|
|
bitfld.long 0x00 14. " TIMERRESTARTED ,The USART timer restarted itself" "Not restarted,Restarted"
|
|
bitfld.long 0x00 13. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
bitfld.long 0x00 12. " RXFULLRIGHT ,RX Full of right data" "Not full,Full"
|
|
bitfld.long 0x00 11. " RXDATAVRIGHT ,RX data right" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXBSRIGHT ,TX buffer expects single right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TXBDRIGHT ,TX buffer expects double right data" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 7. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " TXBL ,TX buffer level" "Low level,High level"
|
|
bitfld.long 0x00 5. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " TXTRI ,Transmitter tristated" "Output,Tri-State"
|
|
newline
|
|
bitfld.long 0x00 3. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MASTER ,SPI master mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
bitfld.long 0x00 31. " AUTOBAUDEN ,Autobaud detection enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 3.--22. 1. " DIV ,Fractional clock divider"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,RX Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,RX Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLEX,RX Buffer Double Data Extended Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDOUBLE,RX FIFO Double Data Register"
|
|
in
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
bitfld.long 0x04 30. " PERRP1 ,Data parity error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
bitfld.long 0x04 14. " PERRP0 ,Data parity error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
endif
|
|
wgroup.long 0x30++0x0F
|
|
line.long 0x00 "TXDATAX,TX Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x00 12. " TXTRIAT ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x00 11. " UBRXAT ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATAX ,Tx data"
|
|
line.long 0x04 "TXDATA,TX Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAX ,Tx data"
|
|
line.long 0x08 "TXDOUBLEX,TX Buffer Double Data Extended Register"
|
|
bitfld.long 0x08 31. " RXENAT1 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 30. " TXDISAT1 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 29. " TXBREAK1 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 28. " TXTRIAT1 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 27. " UBRXAT1 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 16.--24. 1. " TXDATA1 ,Tx data"
|
|
newline
|
|
bitfld.long 0x08 15. " RXENAT0 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 14. " TXDISAT0 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 13. " TXBREAK0 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 12. " TXTRIAT0 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 11. " UBRXAT0 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 0.--8. 1. " TXDATA0 ,Tx data"
|
|
line.long 0x0C "TXDOUBLE,TX Buffer Double Data Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TXDATA1 ,Tx data"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXDATA0 ,Tx data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TCMP2_SET/CLR ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TCMP1_SET/CLR ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TCMP0_SET/CLR ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TXIDLE_SET/CLR ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CCF_SET/CLR ,Collision check fail interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SSM_SET/CLR ,Slave-select in master mode interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TXUF_SET/CLR ,TX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXFULL_SET/CLR ,RX buffer full interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " TCMP2 ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TCMP1 ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TCMP0 ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TXIDLE ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CCF ,Collision check fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSM ,Slave-select in master mode interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXUF ,TX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXFULL ,RX buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRCTRL,IrDA Control Register"
|
|
bitfld.long 0x04 8.--12. " IRPRSSEL ,IrDA PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 7. " IRPRSEN ,IrDA PRS channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IRFILT ,IrDA RX filter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1.--2. " IRPW ,IrDA TX pulse width" "One,Two,Three,Four"
|
|
bitfld.long 0x04 0. " IREN ,Enable IrDA module" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "INPUT,USART Input Register"
|
|
bitfld.long 0x00 15. " CLKPRS ,PRS CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " CLKPRSSEL ,CLK PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "I2SCTRL,I2S Control Register"
|
|
bitfld.long 0x04 8.--10. " FORMAT ,I2S word format" "W32D32,W32D24M,W32D24,W32D16,W32D8,W16D16,W16D8,W8D8"
|
|
bitfld.long 0x04 4. " DELAY ,Delay on I2S data" "No delay,Delay"
|
|
bitfld.long 0x04 3. " DMASPLIT ,Separate DMA request for left/right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " JUSTIFY ,Justification of I2S data" "Left,Right"
|
|
bitfld.long 0x04 1. " MONO ,Stereo or mono" "Stereo,Mono"
|
|
bitfld.long 0x04 0. " EN ,Enable I2S mode" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "TIMING,Timing Register"
|
|
bitfld.long 0x00 28.--30. " CSHOLD ,Chip select hold" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 24.--26. " ICS ,Inter-character spacing" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
newline
|
|
bitfld.long 0x00 20.--22. " CSSETUP ,Chip select setup" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 16.--18. " TXDELAY ,TX frame start delay" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
line.long 0x04 "CTRLX,Control Register Extended"
|
|
bitfld.long 0x04 3. " RTSINV ,RTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 2. " CTSEN ,CTS function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CTSINV ,CTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMECMP0,Generate Interrupts and Various Delays Register 0"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 0" "TCMP0,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 0"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMECMP1,Generate Interrupts and Various Delays Register 1"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 1" "TCMP1,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMECMP2,Generate Interrupts and Various Delays Register 2"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 2" "TCMP2,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 2"
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 5. " RTSPEN ,RTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTSPEN ,CTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKPEN ,CLK pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CSPEN ,CS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 24.--29. " CLKLOC ,USART CLK pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 16.--21. " CSLOC ,USART CS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 8.--13. " RTSLOC ,USART RTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x08 0.--5. " CTSLOC ,USART CTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 5"
|
|
base ad:0x40011400
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " SMSDELAY ,Synchronous master sample delay" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MVDIS ,Majority vote disable" "No,Yes"
|
|
bitfld.long 0x00 29. " AUTOTX ,Always transmit when RX not full" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BYTESWAP ,Byte-swap in double accesses" "Normal,Swapped"
|
|
bitfld.long 0x00 25. " SSSEARLY ,Synchronous slave setup early" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERRSTX ,Disable TX on error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " ERRSRX ,Disable RX on error" "No,Yes"
|
|
bitfld.long 0x00 22. " ERRSDMA ,Halt DMA on error" "Not halted,Halted"
|
|
bitfld.long 0x00 21. " BIT8DV ,Bit 8 default value" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SKIPPERRF ,Skip parity error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SCRETRANS ,SmartCard retransmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCMODE ,SmartCard mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AUTOTRI ,Automatic TX tristate" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AUTOCS ,Automatic chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSINV ,Chip select invert" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 14. " TXINV ,Transmitter output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " RXINV ,Receiver input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TXBIL ,TX buffer interrupt level" "Empty,Half-full"
|
|
newline
|
|
bitfld.long 0x00 11. " CSMA ,Action on slave-select in master mode" "No action,Go to slave mode"
|
|
bitfld.long 0x00 10. " MSBF ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLKPHA ,Clock edge for setup/sample" "Leading,Trailing"
|
|
newline
|
|
bitfld.long 0x00 8. " CLKPOL ,Clock polarity" "Idle low,Idle high"
|
|
bitfld.long 0x00 5.--6. " OVS ,Oversampling" "X16,X8,X6,X4"
|
|
bitfld.long 0x00 4. " MPAB ,Multi-processor address-bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2. " CCEN ,Collision check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
bitfld.long 0x00 0. " SYNC ,USART synchronous mode" "Asynchronous,Synchronous"
|
|
line.long 0x04 "FRAME,USART Frame Format Register"
|
|
bitfld.long 0x04 12.--13. " STOPBITS ,Stop-bit mode" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 8.--9. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x04 0.--3. " DATABITS ,Data-bit mode" ",4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
line.long 0x08 "TRIGCTRL,USART Trigger Control Register"
|
|
bitfld.long 0x08 16.--20. " TSEL ,Trigger PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 12. " RXATX2EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL2 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RXATX1EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL1 baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " RXATX0EN ,Enable Rx trigger after Tx end of frame plus TCMPVAL0 baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TXARX2EN ,Enable Tx trigger after Rx end of frame plus TCMP2VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TXARX1EN ,Enable Tx trigger after Rx end of frame plus TCMP1VAL baud-times" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " TXARX0EN ,Enable Tx trigger after Rx end of frame plus TCMP0VAL baud-times" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " AUTOTXTEN ,AUTOTX trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TXTEN ,Transmit trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RXTEN ,Receive trigger enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " TXTRIDIS ,Transmitter tristate disable" "No effect,Yes"
|
|
bitfld.long 0x00 8. " TXTRIEN ,Transmitter tristate enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 7. " RXBLOCKDIS ,Receiver block disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " RXBLOCKEN ,Receiver block enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " MASTERDIS ,Master disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " MASTEREN ,Master enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,USART Status Register"
|
|
bitfld.long 0x00 16.--17. " TXBUFCNT ,TX buffer count" "0,1,2,3"
|
|
bitfld.long 0x00 14. " TIMERRESTARTED ,The USART timer restarted itself" "Not restarted,Restarted"
|
|
bitfld.long 0x00 13. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
bitfld.long 0x00 12. " RXFULLRIGHT ,RX Full of right data" "Not full,Full"
|
|
bitfld.long 0x00 11. " RXDATAVRIGHT ,RX data right" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXBSRIGHT ,TX buffer expects single right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TXBDRIGHT ,TX buffer expects double right data" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RXFULL ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 7. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " TXBL ,TX buffer level" "Low level,High level"
|
|
bitfld.long 0x00 5. " TXC ,TX complete" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " TXTRI ,Transmitter tristated" "Output,Tri-State"
|
|
newline
|
|
bitfld.long 0x00 3. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MASTER ,SPI master mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
bitfld.long 0x00 31. " AUTOBAUDEN ,Autobaud detection enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 3.--22. 1. " DIV ,Fractional clock divider"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,RX Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,RX Buffer Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RXDOUBLEX,RX Buffer Double Data Extended Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDOUBLE,RX FIFO Double Data Register"
|
|
in
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
bitfld.long 0x04 30. " PERRP1 ,Data parity error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
bitfld.long 0x04 14. " PERRP0 ,Data parity error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "RXDATAXP,RX Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Data framing error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
line.long 0x04 "RXDOUBLEXP,RX Buffer Double Data Extended Peek Register"
|
|
bitfld.long 0x04 31. " FERRP1 ,Data framing error 1 peek" "No error,Error"
|
|
hexmask.long.word 0x04 16.--24. 1. " RXDATAP1 ,Rx data 1 peek"
|
|
newline
|
|
bitfld.long 0x04 15. " FERRP0 ,Data framing error 0 peek" "No error,Error"
|
|
hexmask.long.word 0x04 0.--8. 1. " RXDATAP0 ,Rx data 0 peek"
|
|
endif
|
|
wgroup.long 0x30++0x0F
|
|
line.long 0x00 "TXDATAX,TX Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x00 12. " TXTRIAT ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x00 11. " UBRXAT ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATAX ,Tx data"
|
|
line.long 0x04 "TXDATA,TX Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATAX ,Tx data"
|
|
line.long 0x08 "TXDOUBLEX,TX Buffer Double Data Extended Register"
|
|
bitfld.long 0x08 31. " RXENAT1 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 30. " TXDISAT1 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 29. " TXBREAK1 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 28. " TXTRIAT1 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 27. " UBRXAT1 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 16.--24. 1. " TXDATA1 ,Tx data"
|
|
newline
|
|
bitfld.long 0x08 15. " RXENAT0 ,Enable RX after transmission" "No effect,Enable"
|
|
bitfld.long 0x08 14. " TXDISAT0 ,Clear TXEN after transmission" "No effect,Clear"
|
|
bitfld.long 0x08 13. " TXBREAK0 ,Transmit data as break" "No effect,Transmit"
|
|
newline
|
|
bitfld.long 0x08 12. " TXTRIAT0 ,Set TXTRI after transmission" "No effect,Tri-State"
|
|
bitfld.long 0x08 11. " UBRXAT0 ,Unblock RX after transmission" "No effect,Unblock"
|
|
hexmask.long.word 0x08 0.--8. 1. " TXDATA0 ,Tx data"
|
|
line.long 0x0C "TXDOUBLE,TX Buffer Double Data Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TXDATA1 ,Tx data"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXDATA0 ,Tx data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TCMP2_SET/CLR ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TCMP1_SET/CLR ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TCMP0_SET/CLR ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TXIDLE_SET/CLR ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CCF_SET/CLR ,Collision check fail interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SSM_SET/CLR ,Slave-select in master mode interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TXUF_SET/CLR ,TX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXFULL_SET/CLR ,RX buffer full interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " TCMP2 ,Timer comparator 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TCMP1 ,Timer comparator 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TCMP0 ,Timer comparator 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TXIDLE ,Tx idle interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " CCF ,Collision check fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSM ,Slave-select in master mode interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXUF ,TX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXFULL ,RX buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRCTRL,IrDA Control Register"
|
|
bitfld.long 0x04 8.--12. " IRPRSSEL ,IrDA PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 7. " IRPRSEN ,IrDA PRS channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IRFILT ,IrDA RX filter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1.--2. " IRPW ,IrDA TX pulse width" "One,Two,Three,Four"
|
|
bitfld.long 0x04 0. " IREN ,Enable IrDA module" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "INPUT,USART Input Register"
|
|
bitfld.long 0x00 15. " CLKPRS ,PRS CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " CLKPRSSEL ,CLK PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x04 "I2SCTRL,I2S Control Register"
|
|
bitfld.long 0x04 8.--10. " FORMAT ,I2S word format" "W32D32,W32D24M,W32D24,W32D16,W32D8,W16D16,W16D8,W8D8"
|
|
bitfld.long 0x04 4. " DELAY ,Delay on I2S data" "No delay,Delay"
|
|
bitfld.long 0x04 3. " DMASPLIT ,Separate DMA request for left/right data" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " JUSTIFY ,Justification of I2S data" "Left,Right"
|
|
bitfld.long 0x04 1. " MONO ,Stereo or mono" "Stereo,Mono"
|
|
bitfld.long 0x04 0. " EN ,Enable I2S mode" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "TIMING,Timing Register"
|
|
bitfld.long 0x00 28.--30. " CSHOLD ,Chip select hold" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 24.--26. " ICS ,Inter-character spacing" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
newline
|
|
bitfld.long 0x00 20.--22. " CSSETUP ,Chip select setup" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
bitfld.long 0x00 16.--18. " TXDELAY ,TX frame start delay" "Zero,One,Two,Three,Seven,TCMP0,TCMP1,TCMP2"
|
|
line.long 0x04 "CTRLX,Control Register Extended"
|
|
bitfld.long 0x04 3. " RTSINV ,RTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 2. " CTSEN ,CTS function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CTSINV ,CTS pin inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMECMP0,Generate Interrupts and Various Delays Register 0"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 0" "TCMP0,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 0"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMECMP1,Generate Interrupts and Various Delays Register 1"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 1" "TCMP1,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMECMP2,Generate Interrupts and Various Delays Register 2"
|
|
bitfld.long 0x00 24. " RESTARTEN ,Restart timer on TCMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " TSTOP ,Source used to disable comparator 2" "TCMP2,TXST,RXACT,RXACTIN,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TSTART ,Timer start source" "Disabled,TXEOF,TXC,RXACT,RXEOF,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCMPVAL ,Timer comparator 2"
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 5. " RTSPEN ,RTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTSPEN ,CTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKPEN ,CLK pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CSPEN ,CS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x04 24.--29. " CLKLOC ,USART CLK pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 16.--21. " CSLOC ,USART CS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x04 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
line.long 0x08 "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x08 8.--13. " RTSLOC ,USART RTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
bitfld.long 0x08 0.--5. " CTSLOC ,USART CTS pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "LEUART (Low Energy Universal Asynchronous Receiver/Transmitter)"
|
|
tree "LEUART 0"
|
|
base ad:0x4006A000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 14.--15. " TXDELAY ,TX delay transmission" "None,Single,Double,Triple"
|
|
bitfld.long 0x00 13. " TXDMAWU ,TX DMA wakeup" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " RXDMAWU ,RX DMA wakeup" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " BIT8DV ,Bit 8 default value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAB ,Multi-processor address-bit" "0,1"
|
|
bitfld.long 0x00 9. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 8. " SFUBRX ,Start-frame unblock RX" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
newline
|
|
bitfld.long 0x00 6. " ERRSDMA ,Clear RX DMA on error" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " INV ,Invert input and output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " STOPBITS ,Stop-bit mode" "1 bit,2 bits"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x00 1. " DATABITS ,Data-bit mode" "8 bits,9 bits"
|
|
bitfld.long 0x00 0. " AUTOTRI ,Automatic transmitter tristate" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 7. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
bitfld.long 0x00 5. " RXBLOCKDIS ,Receiver block disable" "No,Yes"
|
|
bitfld.long 0x00 4. " RXBLOCKEN ,Receiver block enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disable,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "Disable,Enable"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 6. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " TXBL ,TX buffer level" "Full,Empty"
|
|
bitfld.long 0x00 3. " TXC ,TX complete" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 2. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
hexmask.long.word 0x00 3.--16. 1. " DIV ,Fractional clock divider"
|
|
else
|
|
hexmask.long.word 0x00 3.--14. 1. " DIV ,Fractional clock divider"
|
|
endif
|
|
line.long 0x04 "STARTFRAME,Start Frame Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " STARTFRAME ,Start frame"
|
|
line.long 0x08 "SIGFRAME,Signal Frame Register"
|
|
hexmask.long.word 0x08 0.--8. 1. " SIGFRAME ,Signal frame"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,Receive Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,Receive Buffer Data Register"
|
|
in
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RXDATAXP,Receive Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Receive data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Receive data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
wgroup.long 0x24++0x07
|
|
line.long 0x00 "TXDATAX,Transmit Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "Disable,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Disable TX after transmission" "No,Yes"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Tx data"
|
|
line.long 0x04 "TXDATA,Transmit Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATA ,Tx data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIGF_SET/CLR ,Signal frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " STARTF_SET/CLR ,Start frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x38++0x0B
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 10. " SIGF ,Signal frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " STARTF ,Start frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "PULSECTRL,Pulse Control Register"
|
|
bitfld.long 0x04 5. " PULSEFILT ,Pulse filter" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PULSEEN ,Pulse generator/extender enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " PULSEW ,Pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "FREEZE,Freeze Register"
|
|
bitfld.long 0x08 0. " REGFREEZE ,Register update freeze" "Updated,Freeze"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SYNBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 7. " PULSECTRL ,PULSECTRL register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " TXDATA ,TXDATA register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " TXDATAX ,TXDATAX register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " SIGFRAME ,SIGFRAME register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " STARTFRAME ,STARTFRAME register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " CLKDIV ,CLKDIV register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ROUTE,I/O Routing Register"
|
|
sif (cpuis("EFM32TG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
elif (cpuis("EFM32LG*")||cpuis("EFM32GG*")||cpuis("EFM32WG*")||cpuis("EFM32ZG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
elif (cpuis("EFM32HG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x00 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x00 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INPUT,LEUART Input Register"
|
|
bitfld.long 0x00 5. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
endif
|
|
sif (cpuis("EFM32GG*")||cpuis("EFM32TG*")||cpuis("EFM32LG*")||cpuis("EFM32WG*")||cpuis("EFM32ZG*"))||(cpuis("EFM32HG"))
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "INPUT,LEUART Input Register"
|
|
bitfld.long 0x00 4. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("EFM32GG*")||cpuis("EFM32LG*")||cpuis("EFM32WG*"))
|
|
bitfld.long 0x00 0.--3. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,?..."
|
|
elif (cpuis("EFM32ZG*"))
|
|
bitfld.long 0x00 0.--1. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3"
|
|
elif (cpuis("EFM32HG*"))
|
|
bitfld.long 0x00 0.--2. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,?..."
|
|
else
|
|
bitfld.long 0x00 0.--2. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LEUART 1"
|
|
base ad:0x4006A400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 14.--15. " TXDELAY ,TX delay transmission" "None,Single,Double,Triple"
|
|
bitfld.long 0x00 13. " TXDMAWU ,TX DMA wakeup" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " RXDMAWU ,RX DMA wakeup" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " BIT8DV ,Bit 8 default value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " MPAB ,Multi-processor address-bit" "0,1"
|
|
bitfld.long 0x00 9. " MPM ,Multi-processor mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 8. " SFUBRX ,Start-frame unblock RX" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " LOOPBK ,Loopback enable" "RX connected,TX connected"
|
|
newline
|
|
bitfld.long 0x00 6. " ERRSDMA ,Clear RX DMA on error" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " INV ,Invert input and output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " STOPBITS ,Stop-bit mode" "1 bit,2 bits"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " PARITY ,Parity-bit mode" "None,,Even,Odd"
|
|
bitfld.long 0x00 1. " DATABITS ,Data-bit mode" "8 bits,9 bits"
|
|
bitfld.long 0x00 0. " AUTOTRI ,Automatic transmitter tristate" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 7. " CLEARRX ,Clear RX" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEARTX ,Clear TX" "No effect,Clear"
|
|
bitfld.long 0x00 5. " RXBLOCKDIS ,Receiver block disable" "No,Yes"
|
|
bitfld.long 0x00 4. " RXBLOCKEN ,Receiver block enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " TXDIS ,Transmitter disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TXEN ,Transmitter enable" "Disable,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No,Yes"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "Disable,Enable"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 6. " TXIDLE ,TX idle" "Busy,Idle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " RXDATAV ,RX data valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " TXBL ,TX buffer level" "Full,Empty"
|
|
bitfld.long 0x00 3. " TXC ,TX complete" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 2. " RXBLOCK ,Block incoming data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXENS ,Transmitter enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXENS ,Receiver enable status" "Disabled,Enabled"
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "CLKDIV,Clock Control Register"
|
|
sif cpuis("EFM32GG11B*")
|
|
hexmask.long.word 0x00 3.--16. 1. " DIV ,Fractional clock divider"
|
|
else
|
|
hexmask.long.word 0x00 3.--14. 1. " DIV ,Fractional clock divider"
|
|
endif
|
|
line.long 0x04 "STARTFRAME,Start Frame Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " STARTFRAME ,Start frame"
|
|
line.long 0x08 "SIGFRAME,Signal Frame Register"
|
|
hexmask.long.word 0x08 0.--8. 1. " SIGFRAME ,Signal frame"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATAX,Receive Buffer Data Extended Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RXDATA,Receive Buffer Data Register"
|
|
in
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RXDATAXP,Receive Buffer Data Extended Peek Register"
|
|
bitfld.long 0x00 15. " FERRP ,Receive data framing error peek" "No error,Error"
|
|
bitfld.long 0x00 14. " PERRP ,Receive data parity error peek" "No error,Error"
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATAP ,Rx data peek"
|
|
wgroup.long 0x24++0x07
|
|
line.long 0x00 "TXDATAX,Transmit Buffer Data Extended Register"
|
|
bitfld.long 0x00 15. " RXENAT ,Enable RX after transmission" "Disable,Enable"
|
|
bitfld.long 0x00 14. " TXDISAT ,Disable TX after transmission" "No,Yes"
|
|
bitfld.long 0x00 13. " TXBREAK ,Transmit data as break" "No effect,Transmit"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Tx data"
|
|
line.long 0x04 "TXDATA,Transmit Buffer Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXDATA ,Tx data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIGF_SET/CLR ,Signal frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " STARTF_SET/CLR ,Start frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " MPAF_SET/CLR ,Multi-processor address frame interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " FERR_SET/CLR ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PERR_SET/CLR ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TXOF_SET/CLR ,TX overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RXUF_SET/CLR ,RX underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RXOF_SET/CLR ,RX overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TXBL ,TX buffer level interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXC_SET/CLR ,TX complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x38++0x0B
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 10. " SIGF ,Signal frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " STARTF ,Start frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MPAF ,Multi-processor address frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FERR ,Framing error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " PERR ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXOF ,TX overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXUF ,RX underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RXOF ,RX overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RXDATAV ,RX data valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXBL ,TX buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXC ,TX complete interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "PULSECTRL,Pulse Control Register"
|
|
bitfld.long 0x04 5. " PULSEFILT ,Pulse filter" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PULSEEN ,Pulse generator/extender enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " PULSEW ,Pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "FREEZE,Freeze Register"
|
|
bitfld.long 0x08 0. " REGFREEZE ,Register update freeze" "Updated,Freeze"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SYNBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 7. " PULSECTRL ,PULSECTRL register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " TXDATA ,TXDATA register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " TXDATAX ,TXDATAX register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " SIGFRAME ,SIGFRAME register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " STARTFRAME ,STARTFRAME register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " CLKDIV ,CLKDIV register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ROUTE,I/O Routing Register"
|
|
sif (cpuis("EFM32TG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
elif (cpuis("EFM32LG*")||cpuis("EFM32GG*")||cpuis("EFM32WG*")||cpuis("EFM32ZG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
elif (cpuis("EFM32HG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXPEN ,RX pin enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x00 8.--13. " TXLOC ,USART TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x00 0.--5. " RXLOC ,USART RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INPUT,LEUART Input Register"
|
|
bitfld.long 0x00 5. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
endif
|
|
sif (cpuis("EFM32GG*")||cpuis("EFM32TG*")||cpuis("EFM32LG*")||cpuis("EFM32WG*")||cpuis("EFM32ZG*"))||(cpuis("EFM32HG"))
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "INPUT,LEUART Input Register"
|
|
bitfld.long 0x00 4. " RXPRS ,PRS RX enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("EFM32GG*")||cpuis("EFM32LG*")||cpuis("EFM32WG*"))
|
|
bitfld.long 0x00 0.--3. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,?..."
|
|
elif (cpuis("EFM32ZG*"))
|
|
bitfld.long 0x00 0.--1. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3"
|
|
elif (cpuis("EFM32HG*"))
|
|
bitfld.long 0x00 0.--2. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,?..."
|
|
else
|
|
bitfld.long 0x00 0.--2. " RXPRSSEL ,RX PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TIMER (Timer/Counter Registers)"
|
|
tree "TIMER 0"
|
|
base ad:0x40018000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIMER 1"
|
|
base ad:0x40018400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIMER 2"
|
|
base ad:0x40018800
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIMER 3"
|
|
base ad:0x40018C00
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIMER 4"
|
|
base ad:0x40019000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIMER 5"
|
|
base ad:0x40019400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIMER 6"
|
|
base ad:0x40019800
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "WTIMER (Timer/Counter Registers)"
|
|
tree "WTIMER 0"
|
|
base ad:0x4001A000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "WTIMER 1"
|
|
base ad:0x4001A400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "WTIMER 2"
|
|
base ad:0x4001A800
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "WTIMER 3"
|
|
base ad:0x4001AC00
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 29. " RSSCOIST ,Reload-start sets compare output initial state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ATI ,Always track inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x00 16.--17. " CLKSEL ,Clock source select" "PRESCHFPERCLK,CC1,TIMEROUF,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " DISSYNCOUT ,Disable timer from start/stop/reload other synchronized timers" "No,Yes"
|
|
bitfld.long 0x00 13. " X2CNT ,2x count mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " FALLA ,Timer falling input edge action" "None,Start,Stop,Reload start"
|
|
bitfld.long 0x00 8.--9. " RISEA ,Timer rising input edge action" "None,Start,Stop,Reload start"
|
|
newline
|
|
bitfld.long 0x00 7. " DMACLRACT ,DMA request clear on active" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
bitfld.long 0x00 5. " QDM ,Quadrature decoder mode selection" "X2,X4"
|
|
newline
|
|
bitfld.long 0x00 4. " OSMEN ,One-shot mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SYNC ,Timer start/stop/reload synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,Timer mode" "Up,Down,Up-down,QDEC"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOP ,Stop timer" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start timer" "No effect,Start"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 27. " CCPOL3 ,CC3 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 26. " CCPOL2 ,CC2 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 25. " CCPOL1 ,CC1 polarity" "Low-rise,High-fall"
|
|
bitfld.long 0x00 24. " CCPOL0 ,CC0 polarity" "Low-rise,High-fall"
|
|
newline
|
|
bitfld.long 0x00 19. " ICV3 ,CC3 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " ICV2 ,CC2 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " ICV1 ,CC1 input capture valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " ICV0 ,CC0 input capture valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " CCVBV3 ,CC3 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " CCVBV2 ,CC2 CCVB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " CCVBV1 ,CC1 CCVB valid" "Not Valid,Valid"
|
|
bitfld.long 0x00 8. " CCVBV0 ,CC0 CCVB valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 2. " TOPBV ,TOPB valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Up,Down"
|
|
bitfld.long 0x00 0. " RUNNING ,Running" "Not running,Running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CC3 ,CC channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CC2 ,CC channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CC1 ,CC channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CC0 ,CC channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DIRCHG ,Direction change detect interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OF ,Overflow interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ICBOF3 ,CC channel 3 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ICBOF2 ,CC channel 2 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ICBOF1 ,CC channel 1 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ICBOF0 ,CC channel 0 input capture buffer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CC3 ,CC channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CC2 ,CC channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CC1 ,CC channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CC0 ,CC channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DIRCHG ,Direction change detect interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OF ,Overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TOP,Counter Top Value Register"
|
|
line.long 0x04 "TOPB,Counter Top Value Buffer Register"
|
|
line.long 0x08 "CNT,Counter Value Register"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "LOCK,Timer Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERLOCKKEY ,Timer lock key"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x04 10. " CDTI2PEN ,CC channel 2 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CDTI1PEN ,CC channel 1 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CDTI0PEN ,CC channel 0 complementary dead-time insertion pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CC3PEN ,CC channel 3 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " CC2PEN ,CC channel 2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CC1PEN ,CC channel 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CC0PEN ,CC channel 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " CC3LOC ,CC3 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 16.--21. " CC2LOC ,CC2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 8.--13. " CC1LOC ,CC1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x08 0.--5. " CC0LOC ,CC0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ROUTELOC2,I/O Routing Location Register 2"
|
|
bitfld.long 0x00 16.--21. " CD2LOC ,CD2 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 8.--13. " CD1LOC ,CD1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x00 0.--5. " CD0LOC ,CD0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
tree "Compare/Capture Channel 0 Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,CC Channel 0 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x60+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 0 Value Register"
|
|
in
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 0 Value Peek Register"
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 0 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 1 Registers"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTRL,CC Channel 1 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x70+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 1 Value Register"
|
|
in
|
|
rgroup.long (0x70+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 1 Value Peek Register"
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 1 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 2 Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTRL,CC Channel 2 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x80+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 2 Value Register"
|
|
in
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 2 Value Peek Register"
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 2 Buffer Register"
|
|
tree.end
|
|
tree "Compare/Capture Channel 3 Registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,CC Channel 3 Control Register"
|
|
bitfld.long 0x00 30. " FILT ,Digital filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INSEL ,Input selection" "PIN,PRS"
|
|
bitfld.long 0x00 28. " PRSCONF ,PRS configuration" "Pulse,Level"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " ICEVCTRL ,Input capture event control" "Every edge,Every second edge,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " ICEDGE ,Input capture edge select" "Rising,Falling,Both,None"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " PRSSEL ,Compare/capture channel PRS input channel selection" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 12.--13. " CUFOA ,Counter underflow output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 10.--11. " COFOA ,Counter overflow output action" "None,Toggle,Clear,Set"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CMOA ,Compare match output action" "None,Toggle,Clear,Set"
|
|
bitfld.long 0x00 4. " COIST ,Compare output initial state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " OUTINV ,Output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " MODE ,CC channel mode" "Off,Input capture,Output compare,PWM"
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "CCV,CC Channel 3 Value Register"
|
|
in
|
|
rgroup.long (0x90+0x08)++0x03
|
|
line.long 0x00 "CCVP,CC Channel 3 Value Peek Register"
|
|
group.long (0x90+0x0C)++0x03
|
|
line.long 0x00 "CCVB,CC Channel 3 Buffer Register"
|
|
tree.end
|
|
tree "DTI Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "DTCTRL,DTI Control Register"
|
|
bitfld.long 0x00 24. " DTPRSEN ,DTI PRS source enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTFATS ,DTI fault action on timer stop" "0,1"
|
|
bitfld.long 0x00 9. " DTAR ,DTI always run" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " DTPRSSEL ,DTI PRS source channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " DTCINV ,DTI complementary output invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " DTIPOL ,DTI inactive polarity" "Not set,Set"
|
|
bitfld.long 0x00 1. " DTDAS ,DTI automatic start-up functionality" "No restart,Restart"
|
|
bitfld.long 0x00 0. " DTEN ,DTI enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTTIME,DTI Time Control Register"
|
|
bitfld.long 0x04 16.--21. " DTFALLT ,DTI fall-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 8.--13. " DTRISET ,DTI rise-time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x04 0.--3. " DTPRESC ,DTI prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
line.long 0x08 "DTFC,DTI Fault Configuration Register"
|
|
bitfld.long 0x08 27. " DTLOCKUPFEN ,DTI lockup fault enable" "Disabled,Lock-up"
|
|
bitfld.long 0x08 26. " DTDBGFEN ,DTI debugger fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DTPRS1FEN ,DTI PRS 1 fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DTPRS0FEN ,DTI PRS 0 fault enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--17. " DTFA ,DTI fault action" "None,Inactive,Clear,Tristate"
|
|
bitfld.long 0x08 8.--12. " DTPRSFSEL1 ,DTI PRS fault source 1 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x08 0.--4. " DTPRSFSEL0 ,DTI PRS fault source 0 select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
line.long 0x0C "DTOGEN,DTI Output Generation Enable Register"
|
|
bitfld.long 0x0C 5. " DTOGCDTI2EN ,DTI CDTI2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DTOGCDTI1EN ,DTI CDTI1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DTOGCDTI0EN ,DTI CDTI0 output generation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " DTOGCC2EN ,DTI CC2 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DTOGCC1EN ,DTI CC1 output generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DTOGCC0EN ,DTI CC0 output generation enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DTFAULT,DTI Fault Register"
|
|
bitfld.long 0x00 3. " DTLOCKUPF ,DTI lockup fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " DTDBGF ,DTI debugger fault" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1F ,DTI PRS 1 fault" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " DTPRS0F ,DTI PRS 0 fault" "Not occurred,Occurred"
|
|
wgroup.long 0xB4++0x03
|
|
line.long 0x00 "DTFAULTC,DTI Fault Clear Register"
|
|
bitfld.long 0x00 3. " TLOCKUPFC ,DTI lockup fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DTDBGFC ,DTI debugger fault clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " DTPRS1FC ,DTI PRS1 fault clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTPRS0FC ,DTI PRS0 fault clear" "No effect,Clear"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DTLOCK,DTI Configuration Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCKKEY ,DTI lock key"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "LETIMER (Low Energy Timer)"
|
|
tree "LETIMER 0"
|
|
base ad:0x40066000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 12. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
newline
|
|
sif !cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 11. " RTCC1TEN ,RTC compare 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RTCC0TEN ,RTC compare 0 trigger enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " COMP0TOP ,Compare value 0 is top value" "65535,COMP0"
|
|
bitfld.long 0x00 8. " BUFTOP ,Buffered top" "Not loaded,Loaded"
|
|
bitfld.long 0x00 7. " OPOL1 ,Output 1 polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " OPOL0 ,Output 0 polarity" "Low,High"
|
|
bitfld.long 0x00 4.--5. " UFOA1 ,Underflow output action 1" "None,Toggle,Pulse,PWM"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " UFOA0 ,Underflow output action 0" "None,Toggle,Pulse,PWM"
|
|
bitfld.long 0x00 0.--1. " REPMODE ,Repeat mode" "Free,One-shot,Buffered,Double"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 4. " CTO1 ,Clear toggle output 1" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CTO0 ,Clear toggle output 0" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLEAR ,Clear LETIMER" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Stop LETIMER" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start LETIMER" "No effect,Start"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " RUNNING ,LETIMER running" "Not running,Running"
|
|
line.long 0x04 "CNT,Counter Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter value"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "COMP0,Compare Value Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMP0 ,Compare value 0"
|
|
line.long 0x04 "COMP1,Compare Value Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " COMP1 ,Compare value 1"
|
|
line.long 0x08 "REP0,Repeat Counter Register 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REP0 ,Repeat counter 0"
|
|
line.long 0x0C "REP1,Repeat Counter Register 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REP1 ,Repeat counter 1"
|
|
line.long 0x10 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x10 4. 0x14 4. 0x18 4. " REP1 ,Repeat counter 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 3. 0x14 3. 0x18 3. " REP0 ,Repeat counter 0 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 2. 0x14 2. 0x18 2. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x14 1. 0x18 1. " COMP1 ,Compare match 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 0. 0x04 0. 0x18 0. " COMP0 ,Compare match 0 interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " REP ,Repeat counter 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REP0 ,Repeat counter 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " COMP1 ,Compare match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0 ,Compare match 0 interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("EFM32GG11B*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 0. " REGFREEZE ,Register update freeze" "UPDATE,FREEZE"
|
|
endif
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
sif !cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 5. " REP1 ,REP1 register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " REP0 ,REP0 register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " COMP1 ,COMP1 register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " COMP0 ,COMP0 register busy" "Not busy,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
sif !cpuis("EFM32GG11B*")
|
|
newline
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
endif
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 1. " OUT1PEN ,Output 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OUT0PEN ,Output 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 8.--13. " OUT1LOC ,LETIMER OUT1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x04 0.--5. " OUT0LOC ,LETIMER OUT0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PRSSEL,PRS Input Select Register"
|
|
bitfld.long 0x00 26.--27. " PRSCLEARMODE ,PRS clear mode" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 22.--23. " PRSSTOPMODE ,PRS stop mode" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 18.--19. " PRSSTARTMODE ,PRS start mode" "None,Rising,Falling,Both"
|
|
newline
|
|
bitfld.long 0x00 12.--16. " PRSCLEARSEL ,PRS clear select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 6.--10. " PRSSTOPSEL ,PRS stop select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 0.--4. " PRSSTARTSEL ,PRS start select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ROUTE,I/O Routing Register"
|
|
sif (cpuis("EFM32GG*")||cpuis("EFM32TG*")||cpuis("EFM32WG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " OUT1PEN ,Output 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OUT0PEN ,Output 0 pin enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LETIMER 1"
|
|
base ad:0x40066400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 12. " DEBUGRUN ,Debug mode run enable" "Frozen,Running"
|
|
newline
|
|
sif !cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 11. " RTCC1TEN ,RTC compare 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RTCC0TEN ,RTC compare 0 trigger enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " COMP0TOP ,Compare value 0 is top value" "65535,COMP0"
|
|
bitfld.long 0x00 8. " BUFTOP ,Buffered top" "Not loaded,Loaded"
|
|
bitfld.long 0x00 7. " OPOL1 ,Output 1 polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " OPOL0 ,Output 0 polarity" "Low,High"
|
|
bitfld.long 0x00 4.--5. " UFOA1 ,Underflow output action 1" "None,Toggle,Pulse,PWM"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " UFOA0 ,Underflow output action 0" "None,Toggle,Pulse,PWM"
|
|
bitfld.long 0x00 0.--1. " REPMODE ,Repeat mode" "Free,One-shot,Buffered,Double"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 4. " CTO1 ,Clear toggle output 1" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CTO0 ,Clear toggle output 0" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLEAR ,Clear LETIMER" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Stop LETIMER" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start LETIMER" "No effect,Start"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " RUNNING ,LETIMER running" "Not running,Running"
|
|
line.long 0x04 "CNT,Counter Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter value"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "COMP0,Compare Value Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMP0 ,Compare value 0"
|
|
line.long 0x04 "COMP1,Compare Value Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " COMP1 ,Compare value 1"
|
|
line.long 0x08 "REP0,Repeat Counter Register 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REP0 ,Repeat counter 0"
|
|
line.long 0x0C "REP1,Repeat Counter Register 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REP1 ,Repeat counter 1"
|
|
line.long 0x10 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x10 4. 0x14 4. 0x18 4. " REP1 ,Repeat counter 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 3. 0x14 3. 0x18 3. " REP0 ,Repeat counter 0 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 2. 0x14 2. 0x18 2. " UF ,Underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x14 1. 0x18 1. " COMP1 ,Compare match 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x10 0. 0x04 0. 0x18 0. " COMP0 ,Compare match 0 interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " REP ,Repeat counter 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REP0 ,Repeat counter 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UF ,Underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " COMP1 ,Compare match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0 ,Compare match 0 interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("EFM32GG11B*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FREEZE,Freeze Register"
|
|
bitfld.long 0x00 0. " REGFREEZE ,Register update freeze" "UPDATE,FREEZE"
|
|
endif
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
sif !cpuis("EFM32GG11B*")
|
|
bitfld.long 0x00 5. " REP1 ,REP1 register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " REP0 ,REP0 register busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " COMP1 ,COMP1 register busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " COMP0 ,COMP0 register busy" "Not busy,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CMD ,CMD register busy" "Not busy,Busy"
|
|
sif !cpuis("EFM32GG11B*")
|
|
newline
|
|
bitfld.long 0x00 0. " CTRL ,CTRL register busy" "Not busy,Busy"
|
|
endif
|
|
sif cpuis("EFM32GG11B*")
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 1. " OUT1PEN ,Output 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OUT0PEN ,Output 0 pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 8.--13. " OUT1LOC ,LETIMER OUT1 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x04 0.--5. " OUT0LOC ,LETIMER OUT0 pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PRSSEL,PRS Input Select Register"
|
|
bitfld.long 0x00 26.--27. " PRSCLEARMODE ,PRS clear mode" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 22.--23. " PRSSTOPMODE ,PRS stop mode" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 18.--19. " PRSSTARTMODE ,PRS start mode" "None,Rising,Falling,Both"
|
|
newline
|
|
bitfld.long 0x00 12.--16. " PRSCLEARSEL ,PRS clear select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 6.--10. " PRSSTOPSEL ,PRS stop select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 0.--4. " PRSSTARTSEL ,PRS start select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ROUTE,I/O Routing Register"
|
|
sif (cpuis("EFM32GG*")||cpuis("EFM32TG*")||cpuis("EFM32WG*"))
|
|
bitfld.long 0x00 8.--10. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " LOCATION ,I/O location" "LOC0,LOC1,LOC2,LOC3"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " OUT1PEN ,Output 1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OUT0PEN ,Output 0 pin enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CRYOTIMER (Ultra Low Energy Timer/Counter)"
|
|
base ad:0x4008F000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 5.--7. " PRESC ,Prescaler setting" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 2.--3. " OSCSEL ,Select low frequency oscillator" "Disabled,LFRCO,LFXO,ULFRCO"
|
|
newline
|
|
bitfld.long 0x00 1. " DEBUGRUN ,Debug mode run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable CRYOTIMER" "Disabled,Enabled"
|
|
line.long 0x04 "PERIODSEL,Interrupt Duration"
|
|
bitfld.long 0x04 0.--5. " PERIODSEL ,Interrupt/wakeup events period setting" "Every clock cycle,2 clock cycles,4 clock cycles,8 clock cycles,16 clock cycles,32 clock cycles,64 clock cycles,128 clock cycles,256 clock cycles,512 clock cycles,1k clock cycles,2k clock cycles,4k clock cycles,8k clock cycles,16k clock cycles,32k clock cycles,64k clock cycles,128k clock cycles,256k clock cycles,512k clock cycles,1M clock cycles,2M clock cycles,4M clock cycles,8M clock cycles,16M clock cycles,32M clock cycles,64M clock cycles,128M clock cycles,256M clock cycles,512M clock cycles,1024M clock cycles,2048M clock cycles,4096M clock cycles,?..."
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter Value"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "EM4WUEN,Wake Up Enable"
|
|
bitfld.long 0x00 0. " EM4WU ,EM4 wake-up enable" "Disabled,Enabled"
|
|
line.long 0x04 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " PERIOD ,Wakeup event/interrupt" "No interrupt,Interrupt"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " PERIOD ,PERIOD interrupt enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "VDAC (Digital to Analog Converter)"
|
|
base ad:0x40086000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " DACCLKMODE ,Clock mode" "Sync,Async"
|
|
bitfld.long 0x00 28. " WARMUPMODE ,Warm-up mode" "Normal,Keep in standby"
|
|
bitfld.long 0x00 24.--25. " REFRESHPERIOD ,Refresh period" "8 cycles,16 cycles,32 cycles,64 cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. " PRESC ,Prescaler setting for DAC clock"
|
|
bitfld.long 0x00 8.--10. " REFSEL ,Reference selection" "1V25LN,2V5LN,1V25,2V5,VDD,,EXT,?..."
|
|
bitfld.long 0x00 6. " CH0PRESCRST ,Channel 0 start reset prescaler" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 5. " OUTENPRS ,PRS controlled output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SINEMODE ,Sine mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DIFF ,Differential mode" "Single ended,Differential"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 31. " OPA3OUTVALID ,OPA3 output valid status" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " OPA2OUTVALID ,OPA2 output valid status" "Not valid,Valid"
|
|
bitfld.long 0x00 29. " OPA1OUTVALID ,OPA1 output valid status" "Not valid,Valid"
|
|
bitfld.long 0x00 28. " OPA0OUTVALID ,OPA0 output valid status" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 27. " OPA3WARM ,OPA3 warm status" "Not warmed,Warmed"
|
|
bitfld.long 0x00 26. " OPA2WARM ,OPA2 warm status" "Not warmed,Warmed"
|
|
bitfld.long 0x00 25. " OPA1WARM ,OPA1 warm status" "Not warmed,Warmed"
|
|
bitfld.long 0x00 24. " OPA0WARM ,OPA0 warm status" "Not warmed,Warmed"
|
|
newline
|
|
bitfld.long 0x00 23. " OPA3ENS ,OPA3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " OPA2ENS ,OPA2 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " OPA1ENS ,OPA1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " OPA0ENS ,OPA0 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " OPA3PORTCONFLICT ,OPA3 bus conflict output" "Not conflicted,Conflicted"
|
|
bitfld.long 0x00 18. " OPA2PORTCONFLICT ,OPA2 bus conflict output" "Not conflicted,Conflicted"
|
|
bitfld.long 0x00 17. " OPA1PORTCONFLICT ,OPA1 bus conflict output" "Not conflicted,Conflicted"
|
|
bitfld.long 0x00 16. " OPA0PORTCONFLICT ,OPA0 bus conflict output" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x00 5. " CH1WARM ,Channel 1 warm" "Not warmed,Warmed"
|
|
bitfld.long 0x00 4. " CH0WARM ,Channel 0 warm" "Not warmed,Warmed"
|
|
newline
|
|
bitfld.long 0x00 3. " CH1BL ,Channel 1 buffer level" "Low,High"
|
|
bitfld.long 0x00 2. " CH0BL ,Channel 0 buffer level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " CH1ENS ,Channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0ENS ,Channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CH0CTRL,Channel 0 Control Register"
|
|
bitfld.long 0x00 12.--16. " PRSSEL ,PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 8. " PRASYNC ,Channel 0 PRS asynchronous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " TRIGMODE ,Channel 0 trigger mode" "SW,PRS,Refresh,SWPRS,SW refresh,LESENSE,?..."
|
|
bitfld.long 0x00 0. " CONVMODE ,Conversion mode" "Continuous,Sample off"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CH1CTRL,Channel 1 Control Register"
|
|
bitfld.long 0x00 12.--16. " PRSSEL ,PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 8. " PRASYNC ,Channel 1 PRS asynchronous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " TRIGMODE ,Channel 1 trigger mode" "SW,PRS,Refresh,SWPRS,SW refresh,LESENSE,?..."
|
|
bitfld.long 0x00 0. " CONVMODE ,Conversion mode" "Continuous,Sample off"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 23. " OPA3DIS ,OPA3 disable" "No effect,Yes"
|
|
bitfld.long 0x00 22. " OPA3EN ,OPA3 enable" "No effect,Enable"
|
|
bitfld.long 0x00 21. " OPA2DIS ,OPA2 disable" "No effect,Yes"
|
|
bitfld.long 0x00 20. " OPA2EN ,OPA2 enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 19. " OPA1DIS ,OPA1 disable" "No effect,Yes"
|
|
bitfld.long 0x00 18. " OPA1EN ,OPA1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 17. " OPA0DIS ,OPA0 disable" "No effect,Yes"
|
|
bitfld.long 0x00 16. " OPA0EN ,OPA0 enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " CH1DIS ,CH1 disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " CH1EN ,CH1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " CH0DIS ,CH0 disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CH0EN ,CH0 enable" "No effect,Enable"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " OPA3OUTVALID_set/clr ,OPA3 output valid interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " OPA2OUTVALID_set/clr ,OPA2 output valid interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " OPA1OUTVALID_set/clr ,OPA1 output valid interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " OPA0OUTVALID_set/clr ,OPA0 output valid interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " OPA3PRSTIMEDERR_set/clr ,OPA3 PRS trigger mode error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " OPA2PRSTIMEDERR_set/clr ,OPA2 PRS trigger mode error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " OPA1PRSTIMEDERR_set/clr ,OPA1 PRS trigger mode error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " OPA0PRSTIMEDERR_set/clr ,OPA0 PRS trigger mode error interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OPA3APORTCONFLICT_set/clr ,OPA3 bus conflict output interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " OPA2APORTCONFLICT_set/clr ,OPA2 bus conflict output interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " OPA1APORTCONFLICT_set/clr ,OPA1 bus conflict output interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " OPA0APORTCONFLICT_set/clr ,OPA0 bus conflict output interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " EM23ERR_set/clr ,EM2/3 entry error flag" "No error,Error"
|
|
bitfld.long 0x00 7. " CH1BL ,Channel 1 buffer level interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " CH0BL ,Channel 0 buffer level interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CH1UF_set/clr ,Channel 1 data underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CH0UF_set/clr ,Channel 0 data underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CH1OF_set/clr ,Channel 1 data overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CH0OF_set/clr ,Channel 0 data overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CH1CD_set/clr ,Channel 1 conversion done interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CH0CD_set/clr ,Channel 0 conversion done interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " OPA3OUTVALID ,OPA3 output valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " OPA2OUTVALID ,OPA2 output valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " OPA1OUTVALID ,OPA1 output valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " OPA0OUTVALID ,OPA0 output valid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " OPA3PRSTIMEDERR ,OPA3 PRS trigger mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " OPA2PRSTIMEDERR ,OPA2 PRS trigger mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " OPA1PRSTIMEDERR ,OPA1 PRS trigger mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " OPA0PRSTIMEDERR ,OPA0 PRS trigger mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " OPA3APORTCONFLICT ,OPA3 bus conflict output interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OPA2APORTCONFLICT ,OPA2 bus conflict output interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPA1APORTCONFLICT ,OPA1 bus conflict output interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " OPA0APORTCONFLICT ,OPA0 bus conflict output interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " EM23ERR ,EM23ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CH1BL ,Channel 1 buffer level interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CH0BL ,Channel 0 buffer level interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CH1UF ,Channel 1 data underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0UF ,Channel 0 data underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CH1OF ,Channel 1 data overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH0OF ,Channel 0 data overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CH1CD ,Channel 1 conversion done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0CD ,Channel 0 conversion done interrupt enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DATA,Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Channel 0 data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH1DATA,Channel 1 Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Channel 1 data"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "COMBDATA,Combined Data Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " CH1DATA ,Channel 1 data"
|
|
hexmask.long.word 0x00 0.--11. 1. " CH0DATA ,Channel 0 data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CAL,Calibration Register"
|
|
bitfld.long 0x00 16.--19. " GAINERRTRIMCH1 ,Gain error trim value for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--13. " GAINERRTRIM ,Gain error trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " OFFSETTRIM ,Input buffer offset calibration value" "0,1,2,3,4,5,6,7"
|
|
tree "Operational Amplifier 0 Registers"
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long (0xA0+0x08)++0x13
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 21. " APORTYMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 20. " APORTXMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PRSOUTMODE ,PRS output select" "Warm,Out valid"
|
|
newline
|
|
bitfld.long 0x00 10.--14. " PRSSEL ,PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 9. " PRSMODE ,PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x00 8. " PRSEN ,PRS trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " OUTSCALE ,Scale output driving strength" "Full,Half"
|
|
bitfld.long 0x00 3. " HCMDIS ,High common mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " INCBW ,Unity gain bandwidth scale" "Not scaled,Scaled"
|
|
bitfld.long 0x00 0.--1. " DRIVESTRENGTH ,Operation mode (accuracy / drive strength)" "Lower / Low,Low / Low,High / High,Higher / High"
|
|
line.long 0x04 "TIMER,Timer Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " SETLETTIME ,Output settling timeout value"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WARMUPTIME ,Warm-up time count value"
|
|
bitfld.long 0x04 0.--5. " STARTUPDLY ,Start-up delay count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "MUX,Mux Configuration Register"
|
|
bitfld.long 0x08 24.--26. " RESSEL ,Resistor ladder select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x08 20. " GAIN3X ,Dedicated 3x gain resistor ladder" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " RESINMUX ,Resistor ladder input mux" "Disabled,OPANEXT,NEGPAD,POSPAD,COMPAD,CENTER,VSS,?..."
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " NEGSEL ,Inverting input mux"
|
|
hexmask.long.byte 0x08 0.--7. 1. " POSSEL ,Non-inverting input mux"
|
|
line.long 0x0C "OUT,Output Configuration Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " APORTOUTSEL ,APORT output"
|
|
newline
|
|
bitfld.long 0x0C 8. " ALTOUTPADEN[4] ,Alternate output 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [3] ,Alternate output 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [2] ,Alternate output 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [1] ,Alternate output 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [0] ,Alternate output 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " SHORT ,Main and alternative output short" "Not shorted,Shorted"
|
|
bitfld.long 0x0C 2. " APORTOUTEN ,Aport output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ALTOUTEN ,Alternative output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " MAINOUTEN ,Main output enable" "Disabled,Enabled"
|
|
line.long 0x10 "CAL,Calibration Register"
|
|
bitfld.long 0x10 26.--30. " OFFSETN ,Inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 20.--24. " OFFSETP ,Non-inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Operational Amplifier 1 Registers"
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long (0xC0+0x08)++0x13
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 21. " APORTYMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 20. " APORTXMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PRSOUTMODE ,PRS output select" "Warm,Out valid"
|
|
newline
|
|
bitfld.long 0x00 10.--14. " PRSSEL ,PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 9. " PRSMODE ,PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x00 8. " PRSEN ,PRS trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " OUTSCALE ,Scale output driving strength" "Full,Half"
|
|
bitfld.long 0x00 3. " HCMDIS ,High common mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " INCBW ,Unity gain bandwidth scale" "Not scaled,Scaled"
|
|
bitfld.long 0x00 0.--1. " DRIVESTRENGTH ,Operation mode (accuracy / drive strength)" "Lower / Low,Low / Low,High / High,Higher / High"
|
|
line.long 0x04 "TIMER,Timer Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " SETLETTIME ,Output settling timeout value"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WARMUPTIME ,Warm-up time count value"
|
|
bitfld.long 0x04 0.--5. " STARTUPDLY ,Start-up delay count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "MUX,Mux Configuration Register"
|
|
bitfld.long 0x08 24.--26. " RESSEL ,Resistor ladder select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x08 20. " GAIN3X ,Dedicated 3x gain resistor ladder" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " RESINMUX ,Resistor ladder input mux" "Disabled,OPANEXT,NEGPAD,POSPAD,COMPAD,CENTER,VSS,?..."
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " NEGSEL ,Inverting input mux"
|
|
hexmask.long.byte 0x08 0.--7. 1. " POSSEL ,Non-inverting input mux"
|
|
line.long 0x0C "OUT,Output Configuration Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " APORTOUTSEL ,APORT output"
|
|
newline
|
|
bitfld.long 0x0C 8. " ALTOUTPADEN[4] ,Alternate output 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [3] ,Alternate output 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [2] ,Alternate output 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [1] ,Alternate output 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [0] ,Alternate output 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " SHORT ,Main and alternative output short" "Not shorted,Shorted"
|
|
bitfld.long 0x0C 2. " APORTOUTEN ,Aport output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ALTOUTEN ,Alternative output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " MAINOUTEN ,Main output enable" "Disabled,Enabled"
|
|
line.long 0x10 "CAL,Calibration Register"
|
|
bitfld.long 0x10 26.--30. " OFFSETN ,Inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 20.--24. " OFFSETP ,Non-inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Operational Amplifier 2 Registers"
|
|
rgroup.long 0xE0++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long (0xE0+0x08)++0x13
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 21. " APORTYMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 20. " APORTXMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PRSOUTMODE ,PRS output select" "Warm,Out valid"
|
|
newline
|
|
bitfld.long 0x00 10.--14. " PRSSEL ,PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 9. " PRSMODE ,PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x00 8. " PRSEN ,PRS trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " OUTSCALE ,Scale output driving strength" "Full,Half"
|
|
bitfld.long 0x00 3. " HCMDIS ,High common mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " INCBW ,Unity gain bandwidth scale" "Not scaled,Scaled"
|
|
bitfld.long 0x00 0.--1. " DRIVESTRENGTH ,Operation mode (accuracy / drive strength)" "Lower / Low,Low / Low,High / High,Higher / High"
|
|
line.long 0x04 "TIMER,Timer Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " SETLETTIME ,Output settling timeout value"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WARMUPTIME ,Warm-up time count value"
|
|
bitfld.long 0x04 0.--5. " STARTUPDLY ,Start-up delay count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "MUX,Mux Configuration Register"
|
|
bitfld.long 0x08 24.--26. " RESSEL ,Resistor ladder select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x08 20. " GAIN3X ,Dedicated 3x gain resistor ladder" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " RESINMUX ,Resistor ladder input mux" "Disabled,OPANEXT,NEGPAD,POSPAD,COMPAD,CENTER,VSS,?..."
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " NEGSEL ,Inverting input mux"
|
|
hexmask.long.byte 0x08 0.--7. 1. " POSSEL ,Non-inverting input mux"
|
|
line.long 0x0C "OUT,Output Configuration Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " APORTOUTSEL ,APORT output"
|
|
newline
|
|
bitfld.long 0x0C 8. " ALTOUTPADEN[4] ,Alternate output 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [3] ,Alternate output 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [2] ,Alternate output 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [1] ,Alternate output 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [0] ,Alternate output 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " SHORT ,Main and alternative output short" "Not shorted,Shorted"
|
|
bitfld.long 0x0C 2. " APORTOUTEN ,Aport output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ALTOUTEN ,Alternative output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " MAINOUTEN ,Main output enable" "Disabled,Enabled"
|
|
line.long 0x10 "CAL,Calibration Register"
|
|
bitfld.long 0x10 26.--30. " OFFSETN ,Inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 20.--24. " OFFSETP ,Non-inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Operational Amplifier 3 Registers"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long (0x100+0x08)++0x13
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 21. " APORTYMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 20. " APORTXMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PRSOUTMODE ,PRS output select" "Warm,Out valid"
|
|
newline
|
|
bitfld.long 0x00 10.--14. " PRSSEL ,PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 9. " PRSMODE ,PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x00 8. " PRSEN ,PRS trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " OUTSCALE ,Scale output driving strength" "Full,Half"
|
|
bitfld.long 0x00 3. " HCMDIS ,High common mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " INCBW ,Unity gain bandwidth scale" "Not scaled,Scaled"
|
|
bitfld.long 0x00 0.--1. " DRIVESTRENGTH ,Operation mode (accuracy / drive strength)" "Lower / Low,Low / Low,High / High,Higher / High"
|
|
line.long 0x04 "TIMER,Timer Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " SETLETTIME ,Output settling timeout value"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WARMUPTIME ,Warm-up time count value"
|
|
bitfld.long 0x04 0.--5. " STARTUPDLY ,Start-up delay count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "MUX,Mux Configuration Register"
|
|
bitfld.long 0x08 24.--26. " RESSEL ,Resistor ladder select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x08 20. " GAIN3X ,Dedicated 3x gain resistor ladder" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " RESINMUX ,Resistor ladder input mux" "Disabled,OPANEXT,NEGPAD,POSPAD,COMPAD,CENTER,VSS,?..."
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " NEGSEL ,Inverting input mux"
|
|
hexmask.long.byte 0x08 0.--7. 1. " POSSEL ,Non-inverting input mux"
|
|
line.long 0x0C "OUT,Output Configuration Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " APORTOUTSEL ,APORT output"
|
|
newline
|
|
bitfld.long 0x0C 8. " ALTOUTPADEN[4] ,Alternate output 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [3] ,Alternate output 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [2] ,Alternate output 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [1] ,Alternate output 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [0] ,Alternate output 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " SHORT ,Main and alternative output short" "Not shorted,Shorted"
|
|
bitfld.long 0x0C 2. " APORTOUTEN ,Aport output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ALTOUTEN ,Alternative output enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " MAINOUTEN ,Main output enable" "Disabled,Enabled"
|
|
line.long 0x10 "CAL,Calibration Register"
|
|
bitfld.long 0x10 26.--30. " OFFSETN ,Inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 20.--24. " OFFSETP ,Non-inverting input offset configuration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 17.--18. " GM3 ,GM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 13.--15. " GM ,GM trim value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 10.--11. " CM3 ,Compensation cap CM3 trim value" "0,1,2,3"
|
|
bitfld.long 0x10 5.--8. " CM2 ,Compensation cap CM2 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " CM1 ,Compensation cap CM1 trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "ACMP (Analog Comparator)"
|
|
tree "ACMP 0"
|
|
base ad:0x40080000
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " FULLBIAS ,Full bias current" "Not full,Full"
|
|
bitfld.long 0x00 24.--29. " BIASPROG ,Bias configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 21. " IFALL ,Falling edge interrupt sense" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " IRISE ,Rising edge interrupt sense" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " INPUTRANGE ,Input range" "Full,GTVDDDIV2,LTVDDDIV2,?..."
|
|
bitfld.long 0x00 15. " ACCURACY ,ACMP accuracy mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " PWRSEL ,Power select" "AVDD,DVDD,IOVDD0,,IOVDD1,?..."
|
|
bitfld.long 0x00 10. " APORTVMASTERDIS ,APORT bus master disable for bus selected by VASEL" "No,Yes"
|
|
bitfld.long 0x00 9. " APORTYMASTERDIS ,APORT bus Y master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 8. " APORTXMASTERDIS ,APORT bus X master disable" "No,Yes"
|
|
bitfld.long 0x00 3. " GPIOINV ,Comparator GPIO output invert" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 2. " INACTVAL ,Inactive value" "Low,High"
|
|
bitfld.long 0x00 0. " EN ,Analog comparator enable" "Disabled,Enabled"
|
|
line.long 0x04 "INPUTSEL,Input Selection Register"
|
|
bitfld.long 0x04 28.--30. " CSRESSEL ,Capacitive sense mode internal resistor select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x04 26. " CSRESEN ,Capacitive sense mode internal resistor enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " VLPSEL ,Low-power sampled voltage selection" "VADIV,VBDIV"
|
|
newline
|
|
bitfld.long 0x04 22. " VBSEL ,VB selection" "1.25V,2.5V"
|
|
bitfld.long 0x04 16.--21. " VASEL ,VA selection" "VDD,APORT2YCH0,,APORT2YCH2,,APORT2YCH4,,APORT2YCH6,,APORT2YCH8,,APORT2YCH10,,APORT2YCH12,,APORT2YCH14,,APORT2YCH16,,APORT2YCH18,,APORT2YCH20,,APORT2YCH22,,APORT2YCH24,,APORT2YCH26,,APORT2YCH28,,APORT2YCH30,APORT1XCH0,APORT1YCH1,APORT1XCH2,APORT1YCH3,APORT1XCH4,APORT1YCH5,APORT1XCH6,APORT1YCH7,APORT1XCH8,APORT1YCH9,APORT1XCH10,APORT1YCH11,APORT1XCH12,APORT1YCH13,APORT1XCH14,APORT1YCH15,APORT1XCH16,APORT1YCH17,APORT1XCH18,APORT1YCH19,APORT1XCH20,APORT1YCH21,APORT1XCH22,APORT1YCH23,APORT1XCH24,APORT1YCH25,APORT1XCH26,APORT1YCH27,APORT1XCH28,APORT1YCH29,APORT1XCH30,APORT1YCH31"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " NEGSEL ,Negative input select"
|
|
hexmask.long.byte 0x04 0.--7. 1. " POSSEL ,Positive input select"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 3. " EXTIFACT ,External override interface active" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict output" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x00 1. " ACMPOUT ,Analog comparator output" "0,1"
|
|
bitfld.long 0x00 0. " ACMPACT ,Analog comparator active" "Inactive,Active"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " APORTCONFLICT ,APORT conflict interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WARMUP ,Warm-up interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EDGE ,Edge triggered interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WARMUP ,Warm-up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDGE ,Edge triggered interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " APORT0YREQ ,Bus connected to APORT0Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " APORT0XREQ ,Bus connected to APORT0X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 1. " APORT0YCONFLICT ,Bus connected to APORT0Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 0. " APORT0XCONFLICT ,Bus connected to APORT0X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pine Enable Register"
|
|
bitfld.long 0x00 0. " OUTPEN ,ACMP output enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 0.--5. " OUTLOC ,OUT pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
line.long 0x08 "EXTIFCTRL,External Override Interface Control"
|
|
bitfld.long 0x08 4.--7. " APORTSEL ,APORT selection for external interface" "APORT0X,APORT0Y,APORT1X,APORT1Y,APORT1XY,APORT2X,APORT2Y,APORT2YX,APORT3X,APORT3Y,APORT3XY,APORT4X,APORT4Y,?..."
|
|
bitfld.long 0x08 0. " EN ,Enable external interface" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACMP 1"
|
|
base ad:0x40080400
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " FULLBIAS ,Full bias current" "Not full,Full"
|
|
bitfld.long 0x00 24.--29. " BIASPROG ,Bias configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 21. " IFALL ,Falling edge interrupt sense" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " IRISE ,Rising edge interrupt sense" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " INPUTRANGE ,Input range" "Full,GTVDDDIV2,LTVDDDIV2,?..."
|
|
bitfld.long 0x00 15. " ACCURACY ,ACMP accuracy mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " PWRSEL ,Power select" "AVDD,DVDD,IOVDD0,,IOVDD1,?..."
|
|
bitfld.long 0x00 10. " APORTVMASTERDIS ,APORT bus master disable for bus selected by VASEL" "No,Yes"
|
|
bitfld.long 0x00 9. " APORTYMASTERDIS ,APORT bus Y master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 8. " APORTXMASTERDIS ,APORT bus X master disable" "No,Yes"
|
|
bitfld.long 0x00 3. " GPIOINV ,Comparator GPIO output invert" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 2. " INACTVAL ,Inactive value" "Low,High"
|
|
bitfld.long 0x00 0. " EN ,Analog comparator enable" "Disabled,Enabled"
|
|
line.long 0x04 "INPUTSEL,Input Selection Register"
|
|
bitfld.long 0x04 28.--30. " CSRESSEL ,Capacitive sense mode internal resistor select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x04 26. " CSRESEN ,Capacitive sense mode internal resistor enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " VLPSEL ,Low-power sampled voltage selection" "VADIV,VBDIV"
|
|
newline
|
|
bitfld.long 0x04 22. " VBSEL ,VB selection" "1.25V,2.5V"
|
|
bitfld.long 0x04 16.--21. " VASEL ,VA selection" "VDD,APORT2YCH0,,APORT2YCH2,,APORT2YCH4,,APORT2YCH6,,APORT2YCH8,,APORT2YCH10,,APORT2YCH12,,APORT2YCH14,,APORT2YCH16,,APORT2YCH18,,APORT2YCH20,,APORT2YCH22,,APORT2YCH24,,APORT2YCH26,,APORT2YCH28,,APORT2YCH30,APORT1XCH0,APORT1YCH1,APORT1XCH2,APORT1YCH3,APORT1XCH4,APORT1YCH5,APORT1XCH6,APORT1YCH7,APORT1XCH8,APORT1YCH9,APORT1XCH10,APORT1YCH11,APORT1XCH12,APORT1YCH13,APORT1XCH14,APORT1YCH15,APORT1XCH16,APORT1YCH17,APORT1XCH18,APORT1YCH19,APORT1XCH20,APORT1YCH21,APORT1XCH22,APORT1YCH23,APORT1XCH24,APORT1YCH25,APORT1XCH26,APORT1YCH27,APORT1XCH28,APORT1YCH29,APORT1XCH30,APORT1YCH31"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " NEGSEL ,Negative input select"
|
|
hexmask.long.byte 0x04 0.--7. 1. " POSSEL ,Positive input select"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 3. " EXTIFACT ,External override interface active" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict output" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x00 1. " ACMPOUT ,Analog comparator output" "0,1"
|
|
bitfld.long 0x00 0. " ACMPACT ,Analog comparator active" "Inactive,Active"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " APORTCONFLICT ,APORT conflict interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WARMUP ,Warm-up interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EDGE ,Edge triggered interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WARMUP ,Warm-up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDGE ,Edge triggered interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " APORT0YREQ ,Bus connected to APORT0Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " APORT0XREQ ,Bus connected to APORT0X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 1. " APORT0YCONFLICT ,Bus connected to APORT0Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 0. " APORT0XCONFLICT ,Bus connected to APORT0X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pine Enable Register"
|
|
bitfld.long 0x00 0. " OUTPEN ,ACMP output enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 0.--5. " OUTLOC ,OUT pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
line.long 0x08 "EXTIFCTRL,External Override Interface Control"
|
|
bitfld.long 0x08 4.--7. " APORTSEL ,APORT selection for external interface" "APORT0X,APORT0Y,APORT1X,APORT1Y,APORT1XY,APORT2X,APORT2Y,APORT2YX,APORT3X,APORT3Y,APORT3XY,APORT4X,APORT4Y,?..."
|
|
bitfld.long 0x08 0. " EN ,Enable external interface" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACMP 2"
|
|
base ad:0x40080800
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " FULLBIAS ,Full bias current" "Not full,Full"
|
|
bitfld.long 0x00 24.--29. " BIASPROG ,Bias configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 21. " IFALL ,Falling edge interrupt sense" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " IRISE ,Rising edge interrupt sense" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " INPUTRANGE ,Input range" "Full,GTVDDDIV2,LTVDDDIV2,?..."
|
|
bitfld.long 0x00 15. " ACCURACY ,ACMP accuracy mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " PWRSEL ,Power select" "AVDD,DVDD,IOVDD0,,IOVDD1,?..."
|
|
bitfld.long 0x00 10. " APORTVMASTERDIS ,APORT bus master disable for bus selected by VASEL" "No,Yes"
|
|
bitfld.long 0x00 9. " APORTYMASTERDIS ,APORT bus Y master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 8. " APORTXMASTERDIS ,APORT bus X master disable" "No,Yes"
|
|
bitfld.long 0x00 3. " GPIOINV ,Comparator GPIO output invert" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 2. " INACTVAL ,Inactive value" "Low,High"
|
|
bitfld.long 0x00 0. " EN ,Analog comparator enable" "Disabled,Enabled"
|
|
line.long 0x04 "INPUTSEL,Input Selection Register"
|
|
bitfld.long 0x04 28.--30. " CSRESSEL ,Capacitive sense mode internal resistor select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x04 26. " CSRESEN ,Capacitive sense mode internal resistor enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " VLPSEL ,Low-power sampled voltage selection" "VADIV,VBDIV"
|
|
newline
|
|
bitfld.long 0x04 22. " VBSEL ,VB selection" "1.25V,2.5V"
|
|
bitfld.long 0x04 16.--21. " VASEL ,VA selection" "VDD,APORT2YCH0,,APORT2YCH2,,APORT2YCH4,,APORT2YCH6,,APORT2YCH8,,APORT2YCH10,,APORT2YCH12,,APORT2YCH14,,APORT2YCH16,,APORT2YCH18,,APORT2YCH20,,APORT2YCH22,,APORT2YCH24,,APORT2YCH26,,APORT2YCH28,,APORT2YCH30,APORT1XCH0,APORT1YCH1,APORT1XCH2,APORT1YCH3,APORT1XCH4,APORT1YCH5,APORT1XCH6,APORT1YCH7,APORT1XCH8,APORT1YCH9,APORT1XCH10,APORT1YCH11,APORT1XCH12,APORT1YCH13,APORT1XCH14,APORT1YCH15,APORT1XCH16,APORT1YCH17,APORT1XCH18,APORT1YCH19,APORT1XCH20,APORT1YCH21,APORT1XCH22,APORT1YCH23,APORT1XCH24,APORT1YCH25,APORT1XCH26,APORT1YCH27,APORT1XCH28,APORT1YCH29,APORT1XCH30,APORT1YCH31"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " NEGSEL ,Negative input select"
|
|
hexmask.long.byte 0x04 0.--7. 1. " POSSEL ,Positive input select"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 3. " EXTIFACT ,External override interface active" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict output" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x00 1. " ACMPOUT ,Analog comparator output" "0,1"
|
|
bitfld.long 0x00 0. " ACMPACT ,Analog comparator active" "Inactive,Active"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " APORTCONFLICT ,APORT conflict interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WARMUP ,Warm-up interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EDGE ,Edge triggered interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WARMUP ,Warm-up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDGE ,Edge triggered interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " APORT0YREQ ,Bus connected to APORT0Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " APORT0XREQ ,Bus connected to APORT0X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 1. " APORT0YCONFLICT ,Bus connected to APORT0Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 0. " APORT0XCONFLICT ,Bus connected to APORT0X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pine Enable Register"
|
|
bitfld.long 0x00 0. " OUTPEN ,ACMP output enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 0.--5. " OUTLOC ,OUT pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
line.long 0x08 "EXTIFCTRL,External Override Interface Control"
|
|
bitfld.long 0x08 4.--7. " APORTSEL ,APORT selection for external interface" "APORT0X,APORT0Y,APORT1X,APORT1Y,APORT1XY,APORT2X,APORT2Y,APORT2YX,APORT3X,APORT3Y,APORT3XY,APORT4X,APORT4Y,?..."
|
|
bitfld.long 0x08 0. " EN ,Enable external interface" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACMP 3"
|
|
base ad:0x40080C00
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " FULLBIAS ,Full bias current" "Not full,Full"
|
|
bitfld.long 0x00 24.--29. " BIASPROG ,Bias configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 21. " IFALL ,Falling edge interrupt sense" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " IRISE ,Rising edge interrupt sense" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " INPUTRANGE ,Input range" "Full,GTVDDDIV2,LTVDDDIV2,?..."
|
|
bitfld.long 0x00 15. " ACCURACY ,ACMP accuracy mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " PWRSEL ,Power select" "AVDD,DVDD,IOVDD0,,IOVDD1,?..."
|
|
bitfld.long 0x00 10. " APORTVMASTERDIS ,APORT bus master disable for bus selected by VASEL" "No,Yes"
|
|
bitfld.long 0x00 9. " APORTYMASTERDIS ,APORT bus Y master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 8. " APORTXMASTERDIS ,APORT bus X master disable" "No,Yes"
|
|
bitfld.long 0x00 3. " GPIOINV ,Comparator GPIO output invert" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 2. " INACTVAL ,Inactive value" "Low,High"
|
|
bitfld.long 0x00 0. " EN ,Analog comparator enable" "Disabled,Enabled"
|
|
line.long 0x04 "INPUTSEL,Input Selection Register"
|
|
bitfld.long 0x04 28.--30. " CSRESSEL ,Capacitive sense mode internal resistor select" "RES0,RES1,RES2,RES3,RES4,RES5,RES6,RES7"
|
|
bitfld.long 0x04 26. " CSRESEN ,Capacitive sense mode internal resistor enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " VLPSEL ,Low-power sampled voltage selection" "VADIV,VBDIV"
|
|
newline
|
|
bitfld.long 0x04 22. " VBSEL ,VB selection" "1.25V,2.5V"
|
|
bitfld.long 0x04 16.--21. " VASEL ,VA selection" "VDD,APORT2YCH0,,APORT2YCH2,,APORT2YCH4,,APORT2YCH6,,APORT2YCH8,,APORT2YCH10,,APORT2YCH12,,APORT2YCH14,,APORT2YCH16,,APORT2YCH18,,APORT2YCH20,,APORT2YCH22,,APORT2YCH24,,APORT2YCH26,,APORT2YCH28,,APORT2YCH30,APORT1XCH0,APORT1YCH1,APORT1XCH2,APORT1YCH3,APORT1XCH4,APORT1YCH5,APORT1XCH6,APORT1YCH7,APORT1XCH8,APORT1YCH9,APORT1XCH10,APORT1YCH11,APORT1XCH12,APORT1YCH13,APORT1XCH14,APORT1YCH15,APORT1XCH16,APORT1YCH17,APORT1XCH18,APORT1YCH19,APORT1XCH20,APORT1YCH21,APORT1XCH22,APORT1YCH23,APORT1XCH24,APORT1YCH25,APORT1XCH26,APORT1YCH27,APORT1XCH28,APORT1YCH29,APORT1XCH30,APORT1YCH31"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " NEGSEL ,Negative input select"
|
|
hexmask.long.byte 0x04 0.--7. 1. " POSSEL ,Positive input select"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 3. " EXTIFACT ,External override interface active" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict output" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x00 1. " ACMPOUT ,Analog comparator output" "0,1"
|
|
bitfld.long 0x00 0. " ACMPACT ,Analog comparator active" "Inactive,Active"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " APORTCONFLICT ,APORT conflict interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WARMUP ,Warm-up interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EDGE ,Edge triggered interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " APORTCONFLICT ,APORT conflict interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WARMUP ,Warm-up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDGE ,Edge triggered interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " APORT0YREQ ,Bus connected to APORT0Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " APORT0XREQ ,Bus connected to APORT0X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 1. " APORT0YCONFLICT ,Bus connected to APORT0Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 0. " APORT0XCONFLICT ,Bus connected to APORT0X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HYSTERESIS$2,Hysteresis $2 Register"
|
|
bitfld.long 0x00 24.--29. " DIVVB ,Divider for VB voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " DIVVA ,Divider for VA voltage when ACMPOUT=$2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " HYST ,Hysteresis select when AMPOUT=$2" "No hysteresis,14 mV,25 mV,30 mV,35 mV,39 mV,42 mV,45 mV,No hysteresis,-14 mV,-25 mV,-30 mV,-35 mV,-39 mV,-42 mV,-45 mV"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pine Enable Register"
|
|
bitfld.long 0x00 0. " OUTPEN ,ACMP output enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 0.--5. " OUTLOC ,OUT pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
line.long 0x08 "EXTIFCTRL,External Override Interface Control"
|
|
bitfld.long 0x08 4.--7. " APORTSEL ,APORT selection for external interface" "APORT0X,APORT0Y,APORT1X,APORT1Y,APORT1XY,APORT2X,APORT2Y,APORT2YX,APORT3X,APORT3Y,APORT3XY,APORT4X,APORT4Y,?..."
|
|
bitfld.long 0x08 0. " EN ,Enable external interface" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "ADC (Analog to Digital Converter)"
|
|
tree "ADC 0"
|
|
base ad:0x40082000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 30.--31. " CHCONREFWARMIDLE ,Channel connect and reference warm sel when ADC is IDLE" "PREFSCAN,PREFSINGLE,KEEPPREV,?..."
|
|
bitfld.long 0x00 29. " CHCONMODE ,Channel connect mode" "MAXSETTLE,MAXRESP"
|
|
bitfld.long 0x00 28. " DBGHALT ,Debug mode halt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " OVSRSEL ,Oversample ratio select" "X2,X4,X8,X16,X32,X64,X128,X256,X512,X1024,X2048,X4096,?..."
|
|
hexmask.long.byte 0x00 16.--22. 1. " TIMEBASE ,Time base"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESC ,Prescaler setting"
|
|
newline
|
|
bitfld.long 0x00 7. " ADCCLKMODE ,ADC clock mode" "Sync,Async"
|
|
bitfld.long 0x00 6. " ASYNCCLKEN ,Select ASYNC CLK enable mode when ADCCLKMODE=1" "As needed,Always on"
|
|
bitfld.long 0x00 4. " TAILGATE ,Conversion tailgating" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " SCANDMAWU ,SCANFIFO DMA wakeup occur " "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " SINGLEDMAWU ,SINGLEFIFO DMA wakeup occur" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--1. " WARMUPMODE ,Select Warm-up mode for ADC" "Normal,Stand-by,Slow ACC,ADC warm"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 3. " SCANSTOP ,Scan sequence stop" "No effect,Stop"
|
|
bitfld.long 0x00 2. " SCANSTART ,Scan sequence start" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 1. " SINGLESTOP ,Single conversion stop" "No effect,Stop"
|
|
bitfld.long 0x00 0. " SINGLESTART ,Single conversion start" "No effect,Start"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 17. " SCANDV ,Scan data valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " SINGLEDV ,Single sample data valid" "Not valid,Valid"
|
|
bitfld.long 0x00 12. " WARM ,ADC warmed up" "Not warmed,Warmed"
|
|
newline
|
|
bitfld.long 0x00 11. " PROGERR[1] ,Programming NEGSELCONF error status" "No error,Error"
|
|
bitfld.long 0x00 10. " PROGERR[0] ,Programming BUSCONF error status" "No error,Error"
|
|
bitfld.long 0x00 9. " SCANREFWARM ,Scan reference warmed up" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " SINGLEREFWARM ,Single reference warmed up" "Not warmed,Warmed"
|
|
bitfld.long 0x00 2. " SCANPENDING ,Scan conversion pending" "Idle,Pending"
|
|
newline
|
|
bitfld.long 0x00 1. " SCANACT ,Scan conversion active" "Not active,Active"
|
|
bitfld.long 0x00 0. " SINGLEACT ,Single conversion active" "Not active,Active"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SINGLECTRL,Single Channel Control Register 0"
|
|
bitfld.long 0x00 31. " CMPEN ,Compare logic enable for single channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRSEN ,Single sample PRS trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " AT ,Single sample acquisition time" "1 cycle,2 cycles,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " NEGSEL ,Single channel negative input selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POSSEL ,Single channel positive input selection"
|
|
bitfld.long 0x00 5.--7. " REF ,Single channel reference selection" "1.25 V,2.5 V,VDD,5 V,Ext single,2XEXTDIFF,2XVDD,CONF"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " RES ,Single sample resolution select" "12BIT,8BIT,6BIT,OVS"
|
|
bitfld.long 0x00 2. " ADJ ,Single sample result adjustment" "Right,Left"
|
|
newline
|
|
bitfld.long 0x00 1. " DIFF ,Single sample differential mode" "Single ended,Differential"
|
|
bitfld.long 0x00 0. " REP ,Single sample repetitive mode" "Disabled,Enabled"
|
|
line.long 0x04 "SINGLECTRLX,Single Channel Control Register 1"
|
|
bitfld.long 0x04 29.--31. " REPDELAY ,DEPDELAY select for SINGLE REP mode" "No delay,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
|
|
bitfld.long 0x04 27. " CONVSTARTDELAYEN ,Enable delaying next conversion start" "Disabled,Enabled"
|
|
bitfld.long 0x04 22.--26. " CONVSTARTDELAY ,Delay value for next conversion start if CONVSTARTDELAYEN is set" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us,16 us,17 us,18 us,19 us,20 us,21 us,22 us,23 us,24 us,25 us,26 us,27 us,28 us,29 us,30 us,31 us,32 us"
|
|
newline
|
|
bitfld.long 0x04 17.--21. " PRSSEL ,Single channel PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 16. " PRSMODE ,Single channel PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x04 14. " FIFOOFACT ,Single channel FIFO overflow action" "Discard,Overwrite"
|
|
newline
|
|
bitfld.long 0x04 12.--13. " DVL ,Single channel DV level select" "1,2,3,4"
|
|
bitfld.long 0x04 8.--11. " VINATT ,Code for VIN attenuation factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " VREFATT ,Code for VREF attenuation factor when VREFSEL is 1,2 or 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 3. " VREFATTFIX ,Enable fixed scaling on VREF" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " VREFSEL ,Single channel reference selection" "VBGR,VDDXWATT,VREFPWATT,VREFP,VENTROPY,VREFPNWATT,VREFPN,VBGRLOW"
|
|
group.long 0x18++0x23
|
|
line.long 0x00 "SCANCTRL,Scan Control Register 0"
|
|
bitfld.long 0x00 31. " CMPEN ,Compare logic enable for scan" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRSEN ,Scan sequence PRS trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " AT ,Scan sample acquisition time" "1 cycle,2 cycles,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,?..."
|
|
newline
|
|
bitfld.long 0x00 5.--7. " REF ,Single channel reference selection" "1.25 V,2.5 V,VDD,5 V,Ext single,2XEXTDIFF,2XVDD,CONF"
|
|
bitfld.long 0x00 3.--4. " RES ,Scan sequence resolution select" "12BIT,8BIT,6BIT,OVS"
|
|
bitfld.long 0x00 2. " ADJ ,Scan sequence result adjustment" "Right,Left"
|
|
newline
|
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bitfld.long 0x00 1. " DIFF ,Scan sequence differential mode" "Single ended,Differential"
|
|
bitfld.long 0x00 0. " REP ,Scan sequence repetitive mode" "Disabled,Enabled"
|
|
line.long 0x04 "SCANCTRLX,Scan Control Register 1"
|
|
bitfld.long 0x04 29.--31. " REPDELAY ,DEPDELAY select for SINGLE REP mode" "No delay,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
|
|
bitfld.long 0x04 27. " CONVSTARTDELAYEN ,Enable delaying next conversion start" "Disabled,Enabled"
|
|
bitfld.long 0x04 22.--26. " CONVSTARTDELAY ,Delay value for next conversion start if CONVSTARTDELAYEN is set" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us,16 us,17 us,18 us,19 us,20 us,21 us,22 us,23 us,24 us,25 us,26 us,27 us,28 us,29 us,30 us,31 us,32 us"
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|
newline
|
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bitfld.long 0x04 17.--21. " PRSSEL ,Single channel PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x04 16. " PRSMODE ,Single channel PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x04 14. " FIFOOFACT ,Single channel FIFO overflow action" "Discard,Overwrite"
|
|
newline
|
|
bitfld.long 0x04 12.--13. " DVL ,Single channel DV level select" "1,2,3,4"
|
|
bitfld.long 0x04 8.--11. " VINATT ,Code for VIN attenuation factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " VREFATT ,Code for VREF attenuation factor when VREFSEL is 1,2 or 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x04 3. " VREFATTFIX ,Enable fixed scaling on VREF" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " VREFSEL ,Single channel reference selection" "VBGR,VDDXWATT,VREFPWATT,VREFP,VENTROPY,VREFPNWATT,VREFPN,VBGRLOW"
|
|
newline
|
|
line.long 0x08 "SCANMASK,Scan Sequence Input Mask Register"
|
|
bitfld.long 0x08 31. " SCANINPUTEN ,Scan sequence input mask [31]" "0,1"
|
|
bitfld.long 0x08 30. ",Scan sequence input mask [30]" "0,1"
|
|
bitfld.long 0x08 29. ",Scan sequence input mask [29]" "0,1"
|
|
bitfld.long 0x08 28. ",Scan sequence input mask [28]" "0,1"
|
|
bitfld.long 0x08 27. ",Scan sequence input mask [27]" "0,1"
|
|
bitfld.long 0x08 26. ",Scan sequence input mask [26]" "0,1"
|
|
bitfld.long 0x08 25. ",Scan sequence input mask [25]" "0,1"
|
|
bitfld.long 0x08 24. ",Scan sequence input mask [24]" "0,1"
|
|
bitfld.long 0x08 23. ",Scan sequence input mask [23]" "0,1"
|
|
bitfld.long 0x08 22. ",Scan sequence input mask [22]" "0,1"
|
|
bitfld.long 0x08 21. ",Scan sequence input mask [21]" "0,1"
|
|
bitfld.long 0x08 20. ",Scan sequence input mask [20]" "0,1"
|
|
bitfld.long 0x08 19. ",Scan sequence input mask [19]" "0,1"
|
|
bitfld.long 0x08 18. ",Scan sequence input mask [18]" "0,1"
|
|
bitfld.long 0x08 17. ",Scan sequence input mask [17]" "0,1"
|
|
bitfld.long 0x08 16. ",Scan sequence input mask [16]" "0,1"
|
|
bitfld.long 0x08 15. ",Scan sequence input mask [15]" "0,1"
|
|
bitfld.long 0x08 14. ",Scan sequence input mask [14]" "0,1"
|
|
bitfld.long 0x08 13. ",Scan sequence input mask [13]" "0,1"
|
|
bitfld.long 0x08 12. ",Scan sequence input mask [12]" "0,1"
|
|
bitfld.long 0x08 11. ",Scan sequence input mask [11]" "0,1"
|
|
bitfld.long 0x08 10. ",Scan sequence input mask [10]" "0,1"
|
|
bitfld.long 0x08 9. ",Scan sequence input mask [9]" "0,1"
|
|
bitfld.long 0x08 8. ",Scan sequence input mask [8]" "0,1"
|
|
bitfld.long 0x08 7. ",Scan sequence input mask [7]" "0,1"
|
|
bitfld.long 0x08 6. ",Scan sequence input mask [6]" "0,1"
|
|
bitfld.long 0x08 5. ",Scan sequence input mask [5]" "0,1"
|
|
bitfld.long 0x08 4. ",Scan sequence input mask [4]" "0,1"
|
|
bitfld.long 0x08 3. ",Scan sequence input mask [3]" "0,1"
|
|
bitfld.long 0x08 2. ",Scan sequence input mask [2]" "0,1"
|
|
bitfld.long 0x08 1. ",Scan sequence input mask [1]" "0,1"
|
|
bitfld.long 0x08 0. ",Scan sequence input mask [0]" "0,1"
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|
newline
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line.long 0x0C "SCANINPUTSEL,Input Selection Register for Scan Mode"
|
|
bitfld.long 0x0C 24.--28. " INPUT24TO31SEL ,Inputs chosen for INPUT[24:31] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
|
|
bitfld.long 0x0C 16.--20. " INPUT16TO23SEL ,Inputs chosen for INPUT[16:23] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
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|
newline
|
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bitfld.long 0x0C 8.--12. " INPUT8TO15SEL ,Inputs chosen for INPUT[8:15] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
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|
bitfld.long 0x0C 0.--4. " INPUT0TO7SEL ,Inputs chosen for INPUT[0:7] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
|
|
line.long 0x10 "SCANNEGSEL,Negative Input Select Register for Scan"
|
|
bitfld.long 0x10 14.--15. " INPUT15NEGSEL ,Negative input select register for INPUT15 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
|
|
bitfld.long 0x10 12.--13. " INPUT13NEGSEL ,Negative input select register for INPUT13 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
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|
newline
|
|
bitfld.long 0x10 10.--11. " INPUT11NEGSEL ,Negative input select register for INPUT11 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
|
|
bitfld.long 0x10 8.--9. " INPUT9NEGSEL ,Negative input select register for INPUT9 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
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|
newline
|
|
bitfld.long 0x10 6.--7. " INPUT6NEGSEL ,Negative input select register for INPUT6 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
bitfld.long 0x10 4.--5. " INPUT4NEGSEL ,Negative input select register for INPUT4 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
newline
|
|
bitfld.long 0x10 2.--3. " INPUT2NEGSEL ,Negative input select register for INPUT2 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
bitfld.long 0x10 0.--1. " INPUT0NEGSEL ,Negative input select register for INPUT0 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
line.long 0x14 "CMPTHR,Compare Threshold Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ADGT ,Greater than compare threshold"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADLT ,Less than compare threshold"
|
|
line.long 0x18 "BIASPROG,Bias Programming Register for Various Analog Blocks Used in ADC Operation"
|
|
bitfld.long 0x18 16. " GPBIASACC ,Accuracy setting for system bias during ADC operation" "High accuracy,Low accuracy"
|
|
bitfld.long 0x18 12. " VFAULTCLR ,Clear VREFOF flag" "Not cleared,Cleared"
|
|
bitfld.long 0x18 0.--3. " ADCBIASPROG ,Bias programming value of analog ADC block" "Normal,,,,1/2,,,,1/4,,,,1/8,,1/16,1/32"
|
|
line.long 0x1C "CAL,Calibration Register"
|
|
bitfld.long 0x1C 31. " CALEN ,Calibration mode enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " SCANGAIN ,Scan mode gain calibration value"
|
|
hexmask.long.byte 0x1C 20.--23. 0x10 " SCANOFFSETINV ,Scan mode offset calibration value for negative single-ended mode"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--19. 0x01 " SCANOFFSET ,Scan mode offset calibration value for differential or positive single-ended mode"
|
|
bitfld.long 0x1C 15. " OFFSETINVMODE ,Negative single-ended offset calibration enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C 8.--14. 1. " SINGLEGAIN ,Single mode gain calibration value"
|
|
newline
|
|
hexmask.long.byte 0x1C 4.--7. 0x10 " SINGLEOFFSETINV ,Single mode offset calibration value for negative single-ended mode"
|
|
hexmask.long.byte 0x1C 0.--3. 0x01 " SINGLEOFFSET ,Single mode offset calibration value for differential or positive single-ended mode"
|
|
line.long 0x20 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x20 29. 0x24 29. 0x28 29. " EM23ERR_SET/CLR ,EM23 entry error flag" "No error,Error"
|
|
setclrfld.long 0x20 28. 0x24 28. 0x28 28. " PRSTIMEDERR_SET/CLR ,PRS timed mode error flag" "No error,Error"
|
|
setclrfld.long 0x20 27. 0x24 27. 0x28 27. " SCANPEND_SET/CLR ,Scan trigger pending flag" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x20 26. 0x24 26. 0x28 26. " SCANEXTPEND_SET/CLR ,External scan trigger pending flag" "Not pending,Pending"
|
|
setclrfld.long 0x20 25. 0x24 25. 0x28 25. " PROGERR_SET/CLR ,Programming error interrupt flag" "No error,Error"
|
|
setclrfld.long 0x20 24. 0x24 24. 0x28 24. " VREFOV_SET/CLR ,VREF over voltage interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x20 17. 0x24 17. 0x28 17. " SCANCMP_SET/CLR ,Scan result compare match interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 16. 0x24 16. 0x28 16. " SINGLECMP_SET/CLR ,Single result compare match interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 11. 0x24 11. 0x28 11. " SCANUF_SET/CLR ,Scan FIFO underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x20 10. 0x24 10. 0x28 10. " SINGLEUF_SET/CLR ,Single FIFO underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 9. 0x24 9. 0x28 9. " SCANOF_SET/CLR ,Scan FIFO overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 8. 0x24 8. 0x28 8. " SINGLEOF_SET/CLR ,Single FIFO overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x20 1. " SCAN ,Scan conversion complete interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 0. " SINGLE ,Single conversion complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 29. " EM23ERR ,EM23 entry error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PRSTIMEDERR ,PRS timed mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SCANPEND ,Scan trigger pending interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " SCANEXTPEND ,External scan trigger pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PROGERR ,Programming error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " VREFOV ,VREF over voltage interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " SCANCMP ,Scan result compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SINGLECMP ,Single result compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SCANUF ,Scan FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SINGLEUF ,Single FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SCANOF ,Scan FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SINGLEOF ,Single FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SCAN ,Scan conversion complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SINGLE ,Single conversion complete interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "SINGLEDATA,Single Conversion Result Data Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SCANDATA,Scan Conversion Result Data Register"
|
|
in
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "SINGLEDATAP,Scan Conversion Result Data Peek Register"
|
|
line.long 0x04 "SCANDATAP,Scan Sequence Result Data Peek Register"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "SCANDATAX,Scan Sequence Result Data + Data Source Register"
|
|
in
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "SCANDATAXP,Scan Sequence Result Data + Data Source Peek Register"
|
|
bitfld.long 0x00 16.--20. " SCANINPUTIDPEEK ,Scan conversion data source peek" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATAP ,Scan conversion result data peek"
|
|
rgroup.long 0x7C++0x0F
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " APORT0YREQ ,Bus connected to APORT0Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " APORT0XREQ ,Bus connected to APORT0X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 1. " APORT0YCONFLICT ,Bus connected to APORT0Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 0. " APORT0XCONFLICT ,Bus connected to APORT0X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
line.long 0x08 "SINGLEFIFOCOUNT,Single FIFO Count Register"
|
|
bitfld.long 0x08 0.--2. " SINGLEDC ,Single data count" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "SCANFIFOCOUNT,Scan FIFO Count Register"
|
|
bitfld.long 0x0C 0.--2. " SCANDC ,Scan data count" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x07
|
|
line.long 0x00 "SINGLEFIFOCLEAR,Single FIFO Clear Register"
|
|
bitfld.long 0x00 0. " SINGLEFIFOCLEAR ,Clear single FIFO content" "No effect,Clear"
|
|
line.long 0x04 "SCANFIFOCLEAR,Scan FIFO Clear Register"
|
|
bitfld.long 0x04 0. " SCANFIFOCLEAR ,Clear scan FIFO content" "No effect,Clear"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "APORTMASTERDIS,APORT Bus Master Disable Register"
|
|
bitfld.long 0x00 9. " APORT4YMASTERDIS ,APORT4Y master disable" "No,Yes"
|
|
bitfld.long 0x00 8. " APORT4XMASTERDIS ,APORT4X master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YMASTERDIS ,APORT3Y master disable" "No,Yes"
|
|
bitfld.long 0x00 6. " APORT3XMASTERDIS ,APORT3X master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YMASTERDIS ,APORT2Y master disable" "No,Yes"
|
|
bitfld.long 0x00 4. " APORT2XMASTERDIS ,APORT2X master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YMASTERDIS ,APORT1Y master disable" "No,Yes"
|
|
bitfld.long 0x00 2. " APORT1XMASTERDIS ,APORT1X master disable" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC 1"
|
|
base ad:0x40082400
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 30.--31. " CHCONREFWARMIDLE ,Channel connect and reference warm sel when ADC is IDLE" "PREFSCAN,PREFSINGLE,KEEPPREV,?..."
|
|
bitfld.long 0x00 29. " CHCONMODE ,Channel connect mode" "MAXSETTLE,MAXRESP"
|
|
bitfld.long 0x00 28. " DBGHALT ,Debug mode halt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " OVSRSEL ,Oversample ratio select" "X2,X4,X8,X16,X32,X64,X128,X256,X512,X1024,X2048,X4096,?..."
|
|
hexmask.long.byte 0x00 16.--22. 1. " TIMEBASE ,Time base"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESC ,Prescaler setting"
|
|
newline
|
|
bitfld.long 0x00 7. " ADCCLKMODE ,ADC clock mode" "Sync,Async"
|
|
bitfld.long 0x00 6. " ASYNCCLKEN ,Select ASYNC CLK enable mode when ADCCLKMODE=1" "As needed,Always on"
|
|
bitfld.long 0x00 4. " TAILGATE ,Conversion tailgating" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " SCANDMAWU ,SCANFIFO DMA wakeup occur " "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " SINGLEDMAWU ,SINGLEFIFO DMA wakeup occur" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--1. " WARMUPMODE ,Select Warm-up mode for ADC" "Normal,Stand-by,Slow ACC,ADC warm"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
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bitfld.long 0x00 3. " SCANSTOP ,Scan sequence stop" "No effect,Stop"
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|
bitfld.long 0x00 2. " SCANSTART ,Scan sequence start" "No effect,Start"
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newline
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bitfld.long 0x00 1. " SINGLESTOP ,Single conversion stop" "No effect,Stop"
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|
bitfld.long 0x00 0. " SINGLESTART ,Single conversion start" "No effect,Start"
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|
rgroup.long 0x0C++0x03
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line.long 0x00 "STATUS,Status Register"
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|
bitfld.long 0x00 17. " SCANDV ,Scan data valid" "Not valid,Valid"
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bitfld.long 0x00 16. " SINGLEDV ,Single sample data valid" "Not valid,Valid"
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bitfld.long 0x00 12. " WARM ,ADC warmed up" "Not warmed,Warmed"
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newline
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bitfld.long 0x00 11. " PROGERR[1] ,Programming NEGSELCONF error status" "No error,Error"
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|
bitfld.long 0x00 10. " PROGERR[0] ,Programming BUSCONF error status" "No error,Error"
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bitfld.long 0x00 9. " SCANREFWARM ,Scan reference warmed up" "Disabled,Enabled"
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newline
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bitfld.long 0x00 8. " SINGLEREFWARM ,Single reference warmed up" "Not warmed,Warmed"
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bitfld.long 0x00 2. " SCANPENDING ,Scan conversion pending" "Idle,Pending"
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newline
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bitfld.long 0x00 1. " SCANACT ,Scan conversion active" "Not active,Active"
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|
bitfld.long 0x00 0. " SINGLEACT ,Single conversion active" "Not active,Active"
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group.long 0x10++0x07
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line.long 0x00 "SINGLECTRL,Single Channel Control Register 0"
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bitfld.long 0x00 31. " CMPEN ,Compare logic enable for single channel" "Disabled,Enabled"
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bitfld.long 0x00 29. " PRSEN ,Single sample PRS trigger enable" "Disabled,Enabled"
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bitfld.long 0x00 24.--27. " AT ,Single sample acquisition time" "1 cycle,2 cycles,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,?..."
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newline
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hexmask.long.byte 0x00 16.--23. 1. " NEGSEL ,Single channel negative input selection"
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hexmask.long.byte 0x00 8.--15. 1. " POSSEL ,Single channel positive input selection"
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bitfld.long 0x00 5.--7. " REF ,Single channel reference selection" "1.25 V,2.5 V,VDD,5 V,Ext single,2XEXTDIFF,2XVDD,CONF"
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newline
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bitfld.long 0x00 3.--4. " RES ,Single sample resolution select" "12BIT,8BIT,6BIT,OVS"
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bitfld.long 0x00 2. " ADJ ,Single sample result adjustment" "Right,Left"
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newline
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bitfld.long 0x00 1. " DIFF ,Single sample differential mode" "Single ended,Differential"
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bitfld.long 0x00 0. " REP ,Single sample repetitive mode" "Disabled,Enabled"
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line.long 0x04 "SINGLECTRLX,Single Channel Control Register 1"
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bitfld.long 0x04 29.--31. " REPDELAY ,DEPDELAY select for SINGLE REP mode" "No delay,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
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bitfld.long 0x04 27. " CONVSTARTDELAYEN ,Enable delaying next conversion start" "Disabled,Enabled"
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bitfld.long 0x04 22.--26. " CONVSTARTDELAY ,Delay value for next conversion start if CONVSTARTDELAYEN is set" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us,16 us,17 us,18 us,19 us,20 us,21 us,22 us,23 us,24 us,25 us,26 us,27 us,28 us,29 us,30 us,31 us,32 us"
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newline
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bitfld.long 0x04 17.--21. " PRSSEL ,Single channel PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
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bitfld.long 0x04 16. " PRSMODE ,Single channel PRS trigger mode" "Pulsed,Timed"
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bitfld.long 0x04 14. " FIFOOFACT ,Single channel FIFO overflow action" "Discard,Overwrite"
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newline
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bitfld.long 0x04 12.--13. " DVL ,Single channel DV level select" "1,2,3,4"
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bitfld.long 0x04 8.--11. " VINATT ,Code for VIN attenuation factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. " VREFATT ,Code for VREF attenuation factor when VREFSEL is 1,2 or 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 3. " VREFATTFIX ,Enable fixed scaling on VREF" "Disabled,Enabled"
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bitfld.long 0x04 0.--2. " VREFSEL ,Single channel reference selection" "VBGR,VDDXWATT,VREFPWATT,VREFP,VENTROPY,VREFPNWATT,VREFPN,VBGRLOW"
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group.long 0x18++0x23
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line.long 0x00 "SCANCTRL,Scan Control Register 0"
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|
bitfld.long 0x00 31. " CMPEN ,Compare logic enable for scan" "Disabled,Enabled"
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bitfld.long 0x00 29. " PRSEN ,Scan sequence PRS trigger enable" "Disabled,Enabled"
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bitfld.long 0x00 24.--27. " AT ,Scan sample acquisition time" "1 cycle,2 cycles,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,?..."
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|
newline
|
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bitfld.long 0x00 5.--7. " REF ,Single channel reference selection" "1.25 V,2.5 V,VDD,5 V,Ext single,2XEXTDIFF,2XVDD,CONF"
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bitfld.long 0x00 3.--4. " RES ,Scan sequence resolution select" "12BIT,8BIT,6BIT,OVS"
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|
bitfld.long 0x00 2. " ADJ ,Scan sequence result adjustment" "Right,Left"
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|
newline
|
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bitfld.long 0x00 1. " DIFF ,Scan sequence differential mode" "Single ended,Differential"
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|
bitfld.long 0x00 0. " REP ,Scan sequence repetitive mode" "Disabled,Enabled"
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line.long 0x04 "SCANCTRLX,Scan Control Register 1"
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bitfld.long 0x04 29.--31. " REPDELAY ,DEPDELAY select for SINGLE REP mode" "No delay,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
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bitfld.long 0x04 27. " CONVSTARTDELAYEN ,Enable delaying next conversion start" "Disabled,Enabled"
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|
bitfld.long 0x04 22.--26. " CONVSTARTDELAY ,Delay value for next conversion start if CONVSTARTDELAYEN is set" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,8 us,9 us,10 us,11 us,12 us,13 us,14 us,15 us,16 us,17 us,18 us,19 us,20 us,21 us,22 us,23 us,24 us,25 us,26 us,27 us,28 us,29 us,30 us,31 us,32 us"
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|
newline
|
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bitfld.long 0x04 17.--21. " PRSSEL ,Single channel PRS trigger select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
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bitfld.long 0x04 16. " PRSMODE ,Single channel PRS trigger mode" "Pulsed,Timed"
|
|
bitfld.long 0x04 14. " FIFOOFACT ,Single channel FIFO overflow action" "Discard,Overwrite"
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|
newline
|
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bitfld.long 0x04 12.--13. " DVL ,Single channel DV level select" "1,2,3,4"
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|
bitfld.long 0x04 8.--11. " VINATT ,Code for VIN attenuation factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 4.--7. " VREFATT ,Code for VREF attenuation factor when VREFSEL is 1,2 or 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x04 3. " VREFATTFIX ,Enable fixed scaling on VREF" "Disabled,Enabled"
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|
bitfld.long 0x04 0.--2. " VREFSEL ,Single channel reference selection" "VBGR,VDDXWATT,VREFPWATT,VREFP,VENTROPY,VREFPNWATT,VREFPN,VBGRLOW"
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|
newline
|
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line.long 0x08 "SCANMASK,Scan Sequence Input Mask Register"
|
|
bitfld.long 0x08 31. " SCANINPUTEN ,Scan sequence input mask [31]" "0,1"
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bitfld.long 0x08 30. ",Scan sequence input mask [30]" "0,1"
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|
bitfld.long 0x08 29. ",Scan sequence input mask [29]" "0,1"
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bitfld.long 0x08 28. ",Scan sequence input mask [28]" "0,1"
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|
bitfld.long 0x08 27. ",Scan sequence input mask [27]" "0,1"
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|
bitfld.long 0x08 26. ",Scan sequence input mask [26]" "0,1"
|
|
bitfld.long 0x08 25. ",Scan sequence input mask [25]" "0,1"
|
|
bitfld.long 0x08 24. ",Scan sequence input mask [24]" "0,1"
|
|
bitfld.long 0x08 23. ",Scan sequence input mask [23]" "0,1"
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|
bitfld.long 0x08 22. ",Scan sequence input mask [22]" "0,1"
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|
bitfld.long 0x08 21. ",Scan sequence input mask [21]" "0,1"
|
|
bitfld.long 0x08 20. ",Scan sequence input mask [20]" "0,1"
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|
bitfld.long 0x08 19. ",Scan sequence input mask [19]" "0,1"
|
|
bitfld.long 0x08 18. ",Scan sequence input mask [18]" "0,1"
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|
bitfld.long 0x08 17. ",Scan sequence input mask [17]" "0,1"
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bitfld.long 0x08 16. ",Scan sequence input mask [16]" "0,1"
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bitfld.long 0x08 15. ",Scan sequence input mask [15]" "0,1"
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|
bitfld.long 0x08 14. ",Scan sequence input mask [14]" "0,1"
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|
bitfld.long 0x08 13. ",Scan sequence input mask [13]" "0,1"
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|
bitfld.long 0x08 12. ",Scan sequence input mask [12]" "0,1"
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|
bitfld.long 0x08 11. ",Scan sequence input mask [11]" "0,1"
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|
bitfld.long 0x08 10. ",Scan sequence input mask [10]" "0,1"
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|
bitfld.long 0x08 9. ",Scan sequence input mask [9]" "0,1"
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|
bitfld.long 0x08 8. ",Scan sequence input mask [8]" "0,1"
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bitfld.long 0x08 7. ",Scan sequence input mask [7]" "0,1"
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bitfld.long 0x08 6. ",Scan sequence input mask [6]" "0,1"
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bitfld.long 0x08 5. ",Scan sequence input mask [5]" "0,1"
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bitfld.long 0x08 4. ",Scan sequence input mask [4]" "0,1"
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bitfld.long 0x08 3. ",Scan sequence input mask [3]" "0,1"
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bitfld.long 0x08 2. ",Scan sequence input mask [2]" "0,1"
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|
bitfld.long 0x08 1. ",Scan sequence input mask [1]" "0,1"
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|
bitfld.long 0x08 0. ",Scan sequence input mask [0]" "0,1"
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|
newline
|
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line.long 0x0C "SCANINPUTSEL,Input Selection Register for Scan Mode"
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bitfld.long 0x0C 24.--28. " INPUT24TO31SEL ,Inputs chosen for INPUT[24:31] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
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bitfld.long 0x0C 16.--20. " INPUT16TO23SEL ,Inputs chosen for INPUT[16:23] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
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newline
|
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bitfld.long 0x0C 8.--12. " INPUT8TO15SEL ,Inputs chosen for INPUT[8:15] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
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bitfld.long 0x0C 0.--4. " INPUT0TO7SEL ,Inputs chosen for INPUT[0:7] as referred in SCANMASK" "APORT0CH0TO7,APORT0CH8TO15,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,APORT2CH0TO7,APORT2CH8TO15,APORT2CH16TO23,APORT2CH24TO31,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31,APORT4CH0TO7,APORT4CH8TO15,APORT4CH16TO23,APORT4CH24TO31,?..."
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line.long 0x10 "SCANNEGSEL,Negative Input Select Register for Scan"
|
|
bitfld.long 0x10 14.--15. " INPUT15NEGSEL ,Negative input select register for INPUT15 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
|
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bitfld.long 0x10 12.--13. " INPUT13NEGSEL ,Negative input select register for INPUT13 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
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|
newline
|
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bitfld.long 0x10 10.--11. " INPUT11NEGSEL ,Negative input select register for INPUT11 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
|
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bitfld.long 0x10 8.--9. " INPUT9NEGSEL ,Negative input select register for INPUT9 in differential scan mode" "INPUT8,INPUT10,INPUT12,INPUT14"
|
|
newline
|
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bitfld.long 0x10 6.--7. " INPUT6NEGSEL ,Negative input select register for INPUT6 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
bitfld.long 0x10 4.--5. " INPUT4NEGSEL ,Negative input select register for INPUT4 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
newline
|
|
bitfld.long 0x10 2.--3. " INPUT2NEGSEL ,Negative input select register for INPUT2 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
bitfld.long 0x10 0.--1. " INPUT0NEGSEL ,Negative input select register for INPUT0 in differential scan mode" "INPUT1,INPUT3,INPUT5,INPUT7"
|
|
line.long 0x14 "CMPTHR,Compare Threshold Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ADGT ,Greater than compare threshold"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADLT ,Less than compare threshold"
|
|
line.long 0x18 "BIASPROG,Bias Programming Register for Various Analog Blocks Used in ADC Operation"
|
|
bitfld.long 0x18 16. " GPBIASACC ,Accuracy setting for system bias during ADC operation" "High accuracy,Low accuracy"
|
|
bitfld.long 0x18 12. " VFAULTCLR ,Clear VREFOF flag" "Not cleared,Cleared"
|
|
bitfld.long 0x18 0.--3. " ADCBIASPROG ,Bias programming value of analog ADC block" "Normal,,,,1/2,,,,1/4,,,,1/8,,1/16,1/32"
|
|
line.long 0x1C "CAL,Calibration Register"
|
|
bitfld.long 0x1C 31. " CALEN ,Calibration mode enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " SCANGAIN ,Scan mode gain calibration value"
|
|
hexmask.long.byte 0x1C 20.--23. 0x10 " SCANOFFSETINV ,Scan mode offset calibration value for negative single-ended mode"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--19. 0x01 " SCANOFFSET ,Scan mode offset calibration value for differential or positive single-ended mode"
|
|
bitfld.long 0x1C 15. " OFFSETINVMODE ,Negative single-ended offset calibration enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x1C 8.--14. 1. " SINGLEGAIN ,Single mode gain calibration value"
|
|
newline
|
|
hexmask.long.byte 0x1C 4.--7. 0x10 " SINGLEOFFSETINV ,Single mode offset calibration value for negative single-ended mode"
|
|
hexmask.long.byte 0x1C 0.--3. 0x01 " SINGLEOFFSET ,Single mode offset calibration value for differential or positive single-ended mode"
|
|
line.long 0x20 "IF,Interrupt Flag Register"
|
|
setclrfld.long 0x20 29. 0x24 29. 0x28 29. " EM23ERR_SET/CLR ,EM23 entry error flag" "No error,Error"
|
|
setclrfld.long 0x20 28. 0x24 28. 0x28 28. " PRSTIMEDERR_SET/CLR ,PRS timed mode error flag" "No error,Error"
|
|
setclrfld.long 0x20 27. 0x24 27. 0x28 27. " SCANPEND_SET/CLR ,Scan trigger pending flag" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x20 26. 0x24 26. 0x28 26. " SCANEXTPEND_SET/CLR ,External scan trigger pending flag" "Not pending,Pending"
|
|
setclrfld.long 0x20 25. 0x24 25. 0x28 25. " PROGERR_SET/CLR ,Programming error interrupt flag" "No error,Error"
|
|
setclrfld.long 0x20 24. 0x24 24. 0x28 24. " VREFOV_SET/CLR ,VREF over voltage interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x20 17. 0x24 17. 0x28 17. " SCANCMP_SET/CLR ,Scan result compare match interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 16. 0x24 16. 0x28 16. " SINGLECMP_SET/CLR ,Single result compare match interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 11. 0x24 11. 0x28 11. " SCANUF_SET/CLR ,Scan FIFO underflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x20 10. 0x24 10. 0x28 10. " SINGLEUF_SET/CLR ,Single FIFO underflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 9. 0x24 9. 0x28 9. " SCANOF_SET/CLR ,Scan FIFO overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x20 8. 0x24 8. 0x28 8. " SINGLEOF_SET/CLR ,Single FIFO overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x20 1. " SCAN ,Scan conversion complete interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 0. " SINGLE ,Single conversion complete interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 29. " EM23ERR ,EM23 entry error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PRSTIMEDERR ,PRS timed mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SCANPEND ,Scan trigger pending interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " SCANEXTPEND ,External scan trigger pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PROGERR ,Programming error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " VREFOV ,VREF over voltage interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " SCANCMP ,Scan result compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SINGLECMP ,Single result compare match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SCANUF ,Scan FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SINGLEUF ,Single FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SCANOF ,Scan FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SINGLEOF ,Single FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SCAN ,Scan conversion complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SINGLE ,Single conversion complete interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "SINGLEDATA,Single Conversion Result Data Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SCANDATA,Scan Conversion Result Data Register"
|
|
in
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "SINGLEDATAP,Scan Conversion Result Data Peek Register"
|
|
line.long 0x04 "SCANDATAP,Scan Sequence Result Data Peek Register"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "SCANDATAX,Scan Sequence Result Data + Data Source Register"
|
|
in
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "SCANDATAXP,Scan Sequence Result Data + Data Source Peek Register"
|
|
bitfld.long 0x00 16.--20. " SCANINPUTIDPEEK ,Scan conversion data source peek" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATAP ,Scan conversion result data peek"
|
|
rgroup.long 0x7C++0x0F
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " APORT0YREQ ,Bus connected to APORT0Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " APORT0XREQ ,Bus connected to APORT0X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,Bus connected to APORT4Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,Bus connected to APORT4X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,Bus connected to APORT3Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,Bus connected to APORT3X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,Bus connected to APORT2Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,Bus connected to APORT2X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
newline
|
|
bitfld.long 0x04 1. " APORT0YCONFLICT ,Bus connected to APORT0Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 0. " APORT0XCONFLICT ,Bus connected to APORT0X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
line.long 0x08 "SINGLEFIFOCOUNT,Single FIFO Count Register"
|
|
bitfld.long 0x08 0.--2. " SINGLEDC ,Single data count" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "SCANFIFOCOUNT,Scan FIFO Count Register"
|
|
bitfld.long 0x0C 0.--2. " SCANDC ,Scan data count" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x07
|
|
line.long 0x00 "SINGLEFIFOCLEAR,Single FIFO Clear Register"
|
|
bitfld.long 0x00 0. " SINGLEFIFOCLEAR ,Clear single FIFO content" "No effect,Clear"
|
|
line.long 0x04 "SCANFIFOCLEAR,Scan FIFO Clear Register"
|
|
bitfld.long 0x04 0. " SCANFIFOCLEAR ,Clear scan FIFO content" "No effect,Clear"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "APORTMASTERDIS,APORT Bus Master Disable Register"
|
|
bitfld.long 0x00 9. " APORT4YMASTERDIS ,APORT4Y master disable" "No,Yes"
|
|
bitfld.long 0x00 8. " APORT4XMASTERDIS ,APORT4X master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " APORT3YMASTERDIS ,APORT3Y master disable" "No,Yes"
|
|
bitfld.long 0x00 6. " APORT3XMASTERDIS ,APORT3X master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " APORT2YMASTERDIS ,APORT2Y master disable" "No,Yes"
|
|
bitfld.long 0x00 4. " APORT2XMASTERDIS ,APORT2X master disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YMASTERDIS ,APORT1Y master disable" "No,Yes"
|
|
bitfld.long 0x00 2. " APORT1XMASTERDIS ,APORT1X master disable" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "IDAC (Current Digital to Analog Converter)"
|
|
base ad:0x40084000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 20.--24. " PRSSEL ,IDAC output PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 19. " MAINOUTENPRS ,PRS controlled main pad output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MAINOUTEN ,Output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " APORTOUTENPRS ,PRS controlled APORT output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " APORTMASTERDIS ,APORT bus master disable" "No,Yes"
|
|
bitfld.long 0x00 13. " EM2DELAY ,EM2 delay" "Turned off,Turned on"
|
|
newline
|
|
bitfld.long 0x00 12. " PWRSEL ,Power select" "AVDD,IOVDD"
|
|
hexmask.long.byte 0x00 4.--11. 1. " APORTOUTSEL ,APORT output select"
|
|
bitfld.long 0x00 3. " APORTOUTEN ,APORT output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MINOUTTRANS ,Minimum output transition enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CURSINK ,Current sink enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Current DAC enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40084000+0x04))&0x03)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CURPROG,Current Programming Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TUNING ,Tune the current to given accuracy"
|
|
bitfld.long 0x00 8.--12. " STEPSEL ,Current step size select" "0.05,0.10,0.15,0.20,0.25,0.30,0.35,0.40,0.45,0.50,0.55,0.60,0.65,0.70,0.75,0.80,0.85,0.90,0.95,1.0,1.05,1.10,1.15,1.20,1.25,1.30,1.35,1.40,1.45,1.50,1.55,1.6"
|
|
bitfld.long 0x00 0.--1. " RANGESEL ,Current range select" "0 - 1.6 uA,1.6 - 4.7 uA,0.5 - 16 uA,2 - 64 uA"
|
|
elif (((per.l(ad:0x40084000+0x04))&0x03)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CURPROG,Current Programming Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TUNING ,Tune the current to given accuracy"
|
|
bitfld.long 0x00 8.--12. " STEPSEL ,Current step size select" "1.6,1.7,1.8,1.9,2.0,2.1,2.2,2.3,2.4,2.5,2.6,2.7,2.8,2.9,3.0,3.1,3.2,3.3,3.4,3.5,3.6,3.7,3.8,3.9,4.0,4.1,4.2,4.3,4.4,4.5,4.6,4.7"
|
|
bitfld.long 0x00 0.--1. " RANGESEL ,Current range select" "0 - 1.6 uA,1.6 - 4.7 uA,0.5 - 16 uA,2 - 64 uA"
|
|
elif (((per.l(ad:0x40084000+0x04))&0x03)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CURPROG,Current Programming Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TUNING ,Tune the current to given accuracy"
|
|
bitfld.long 0x00 8.--12. " STEPSEL ,Current step size select" "0.5,1.0,1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,8.5,9.0,9.5,10.0,10.5,11.0,11.5,12.0,12.5,13.0,13.5,14.0,14.5,15.0,15.5,16.0"
|
|
bitfld.long 0x00 0.--1. " RANGESEL ,Current range select" "0 - 1.6 uA,1.6 - 4.7 uA,0.5 - 16 uA,2 - 64 uA"
|
|
elif (((per.l(ad:0x40084000+0x04))&0x03)==0x03)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CURPROG,Current Programming Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TUNING ,Tune the current to given accuracy"
|
|
bitfld.long 0x00 8.--12. " STEPSEL ,Current step size select" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
bitfld.long 0x00 0.--1. " RANGESEL ,Current range select" "0 - 1.6 uA,1.6 - 4.7 uA,0.5 - 16 uA,2 - 64 uA"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DUTYCONFIG,Duty Cycle Configuration Register"
|
|
bitfld.long 0x00 1. " EM2DUTYCYCLEDIS ,EM2 duty cycle disable" "No,Yes"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 1. " APORTCONFLICT ,APORT conflict output" "Not conflicted,Conflicted"
|
|
bitfld.long 0x00 0. " CURSTABLE ,IDAC output current stable" "Not stable,Stable"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " APORTCONFLICT ,APORT conflict interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CURSTABLE ,Edge triggered interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " APORTCONFLICT ,APORT conflict interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CURSTABLE ,Edge triggered interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X request" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Conflict Status Register"
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,Bus connected to APORT1Y is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,Bus connected to APORT1X is in conflict with another peripheral" "Not conflicted,Conflicted"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LESENSE (Low Energy Sensor)"
|
|
base ad:0x40055000
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 22. " DEBUGRUN ,Debug mode run enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " DMAWU ,DMA wakeup from EM2" "Disabled,BUFDATAV,BUFLEVEL,?..."
|
|
bitfld.long 0x00 18. " BUFIDL ,Result buffer interrupt and DMA trigger level" "Half full,Full"
|
|
newline
|
|
bitfld.long 0x00 17. " STRSCANRES ,Enable storing of SCANRES" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BUFOW ,Result buffer overwrite" "Not overwritten,Overwritten"
|
|
bitfld.long 0x00 13. " DUALSAMPLE ,Enable dual sample mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTEXMAP ,Alternative excitation map" "ALTEX,Channel"
|
|
bitfld.long 0x00 7.--8. " SCANCONF ,Select scan configuration" "DIRMAP,INVMAP,TOGGLE,DECDEF"
|
|
newline
|
|
bitfld.long 0x00 2.--6. " PRSSEL ,Scan start PRS select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x00 0.--1. " SCANMODE ,Configure scan mode" "Periodic,One shot,PRS,?..."
|
|
line.long 0x04 "TIMCTRL,Timing Control Register"
|
|
bitfld.long 0x04 28. " AUXSTARTUP ,AUXHFRCO startup configuration" "Pre demand,On demand"
|
|
bitfld.long 0x04 22.--23. " STARTDLY ,Start delay configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x04 12.--19. 1. " PCTOP ,Period counter top value"
|
|
newline
|
|
bitfld.long 0x04 8.--10. " PCPRESC ,Period counter prescaling" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x04 4.--6. " LFPRESC ,Prescaling factor for low frequency timer" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x04 0.--1. " AUXPRESC ,Prescaling factor for high frequency timer" "/1,/2,/4,/8"
|
|
line.long 0x08 "PERCTRL,Peripheral Control Register"
|
|
bitfld.long 0x08 28.--29. " WARMUPMODE ,ACMP and DAC duty cycle mode" "NORMAL,KEEPACMPWARM,KEEPDACWARM,KEEPACMPDACWARM"
|
|
bitfld.long 0x08 27. " ACMP1HYSTEN ,ACMP1 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " ACMP0HYSTEN ,ACMP0 hysteresis enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " ACMP1INV ,Invert analog comparator 1 output" "Not inverted,Inverted"
|
|
bitfld.long 0x08 24. " ACMP0INV ,Invert analog comparator 0 output" "Not inverted,Inverted"
|
|
bitfld.long 0x08 22.--23. " ACMP1MODE ,ACMP1 mode" "DISABLE,MUX,MUXTHRES,?..."
|
|
newline
|
|
bitfld.long 0x08 20.--21. " ACMP0MODE ,ACMP0 mode" "DISABLE,MUX,MUXTHRES,?..."
|
|
bitfld.long 0x08 8. " DACCONVTRIG ,VDAC conversion trigger configuration" "Channel,Scan"
|
|
bitfld.long 0x08 6. " DACSTARTUP ,VDAC startup configuration" "Full cycle,Half cycle"
|
|
newline
|
|
bitfld.long 0x08 3. " DACCH1DATA ,VDAC CH1 data selection" "DACDATA,THRES"
|
|
bitfld.long 0x08 2. " DACCH0DATA ,VDAC CH0 data selection" "DACDATA,THRES"
|
|
newline
|
|
bitfld.long 0x08 1. " DACCH1EN ,VDAC CH1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DACCH0EN ,VDAC CH0 enable" "Disabled,Enabled"
|
|
line.long 0x0C "DECCTRL,Decoder Control Register"
|
|
bitfld.long 0x0C 25.--29. " PRSSEL3 ,Select PRS input for bit 3 of the LESENSE decoder" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x0C 20.--24. " PRSSEL2 ,Select PRS input for bit 2 of the LESENSE decoder" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x0C 15.--19. " PRSSEL1 ,Select PRS input for the bit 1 of the LESENSE decoder" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
bitfld.long 0x0C 10.--14. " PRSSEL0 ,Select PRS input for the bit 0 of the LESENSE decoder" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
bitfld.long 0x0C 8. " INPUT ,Select input to the LESENSE decoder" "SENSORSTATE,PRS"
|
|
bitfld.long 0x0C 7. " PRSCNT ,Enable count mode on decoder PRS channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " HYSTIRQ ,Enable decoder hysteresis on interrupt requests" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " HYSTPRS2 ,Enable decoder hysteresis on PRS2 output" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " HYSTPRS1 ,Enable decoder hysteresis on PRS1 output" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " HYSTPRS0 ,Enable decoder hysteresis on PRS0 output" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " INTMAP ,Enable decoder to channel interrupt mapping" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ERRCHK ,Enable check of current state" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DISABLE ,Disable the decoder" "No,Yes"
|
|
line.long 0x10 "BIASCTRL,Bias Control Register"
|
|
bitfld.long 0x10 0.--1. " BIASMODE ,Select bias mode" "Don't touch,Duty cycle,High accuracy,?..."
|
|
line.long 0x14 "EVALCTRL,LESENSE Evaluation Control"
|
|
hexmask.long.word 0x14 0.--15. 1. " WINSIZE ,Sliding windows and step detection size"
|
|
line.long 0x18 "PRSCTRL,PRS Control Register"
|
|
bitfld.long 0x18 16. " DECCMPEN ,Enable PRS output DECCMP" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " DECCMPMASK[4:0] ,Decoder state compare value mask bit 4" "0,1"
|
|
bitfld.long 0x18 11. ",Decoder state compare value mask bit 3" "0,1"
|
|
bitfld.long 0x18 10. ",Decoder state compare value mask bit 2" "0,1"
|
|
bitfld.long 0x18 9. ",Decoder state compare value mask bit 1" "0,1"
|
|
bitfld.long 0x18 8. ",Decoder state compare value mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--4. " DECCMPVAL ,Decoder state compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 3. " CLEARBUF ,Clear result buffer" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DECODE ,Start decoder" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Stop scanning of sensors" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Start scanning of sensors" "No effect,Start"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CHEN,Channel enable Register"
|
|
bitfld.long 0x00 15. " CHEN[15] ,Enable scan channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Enable scan channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Enable scan channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Enable scan channel 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " CHEN[11] ,Enable scan channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Enable scan channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Enable scan channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Enable scan channel 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CHEN[7] ,Enable scan channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Enable scan channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable scan channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable scan channel 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CHEN[3] ,Enable scan channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable scan channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Enable scan channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable scan channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "SCANRES,Scan result register"
|
|
bitfld.long 0x04 31. " STEPDIR[15] ,Direction of previous step detection on channel 15" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " [14] ,Direction of previous step detection on channel 14" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " [13] ,Direction of previous step detection on channel 13" "Not detected,Detected"
|
|
bitfld.long 0x04 28. " [12] ,Direction of previous step detection on channel 12" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 27. " STEPDIR[11] ,Direction of previous step detection on channel 11" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " [10] ,Direction of previous step detection on channel 10" "Not detected,Detected"
|
|
bitfld.long 0x04 25. " [9] ,Direction of previous step detection on channel 9" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " [8] ,Direction of previous step detection on channel 8" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 23. " STEPDIR[7] ,Direction of previous step detection on channel 7" "Not detected,Detected"
|
|
bitfld.long 0x04 22. " [6] ,Direction of previous step detection on channel 6" "Not detected,Detected"
|
|
bitfld.long 0x04 21. " [5] ,Direction of previous step detection on channel 5" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " [4] ,Direction of previous step detection on channel 4" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 19. " STEPDIR[3] ,Direction of previous step detection on channel 3" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " [2] ,Direction of previous step detection on channel 2" "Not detected,Detected"
|
|
bitfld.long 0x04 17. " [1] ,Direction of previous step detection on channel 1" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " [0] ,Direction of previous step detection on channel 0" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 15. " SCANRES[15] ,Scan results for channel 15" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Scan results for channel 14" "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Scan results for channel 13" "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Scan results for channel 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " SCANRES[11] ,Scan results for channel 11" "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Scan results for channel 10" "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Scan results for channel 9" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Scan results for channel 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " SCANRES[7] ,Scan results for channel 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Scan results for channel 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Scan results for channel 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Scan results for channel 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " SCANRES[3] ,Scan results for channel 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Scan results for channel 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Scan results for channel 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Scan results for channel 0" "Low,High"
|
|
newline
|
|
rgroup.long 0x28++0x0F
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 5. " DACACTIVE ,LESENSE VDAC interface is active" "Not active,Active"
|
|
bitfld.long 0x00 4. " SCANACTIVE ,LESENSE is currently interfacing sensors" "Not active,Active"
|
|
bitfld.long 0x00 3. " RUNNING ,LESENSE is active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 2. " BUFFULL ,Result buffer full" "Not full,Full"
|
|
bitfld.long 0x00 1. " BUFHALFFULL ,Result buffer half full" "Not half-full,Half full"
|
|
bitfld.long 0x00 0. " BUFDATAV ,Result data valid" "Not valid,Valid"
|
|
line.long 0x04 "PTR,Result Buffer Pointers"
|
|
bitfld.long 0x04 4.--7. " WR ,Result buffer write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " RD ,Result buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "BUFDATA,Result Buffer Data Register"
|
|
bitfld.long 0x08 16.--19. " BUFDATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x08 0.--15. 1. " BUFDATA ,Result data"
|
|
line.long 0x0C "CURCH,Current channel index"
|
|
bitfld.long 0x0C 0.--3. " CURCH ,Current channel index" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "DECSTATE,Current decoder state"
|
|
bitfld.long 0x00 0.--4. " DECSTATE ,Shows the current decoder state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SENSORSTATE,Decoder input register"
|
|
bitfld.long 0x04 0.--3. " SENSORSTATE ,Shows the status of sensors chosen as input to the decoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "IDLECONF,GPIO Idle Phase Configuration"
|
|
bitfld.long 0x08 30.--31. " CH[15] ,Channel 15 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 28.--29. " [14] ,Channel 14 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 26.--27. " [13] ,Channel 13 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 24.--25. " [12] ,Channel 12 idle phase configuration" "Disabled,High,Low,DAC"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " CH[11] ,Channel 11 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 20.--21. " [10] ,Channel 10 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 18.--19. " [9] ,Channel 9 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 16.--17. " [8] ,Channel 8 idle phase configuration" "Disabled,High,Low,DAC"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " CH[7] ,Channel 7 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 12.--13. " [6] ,Channel 6 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 10.--11. " [5] ,Channel 5 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 8.--9. " [4] ,Channel 4 idle phase configuration" "Disabled,High,Low,DAC"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " CH[3] ,Channel 3 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 4.--5. " [2] ,Channel 2 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 2.--3. " [1] ,Channel 1 idle phase configuration" "Disabled,High,Low,DAC"
|
|
bitfld.long 0x08 0.--1. " [0] ,Channel 0 idle phase configuration" "Disabled,High,Low,DAC"
|
|
line.long 0x0C "ALTEXCONF,Alternative Excite Pin Configuration"
|
|
bitfld.long 0x0C 23. " AEX[7] ,ALTEX7 always excite enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [6] ,ALTEX6 always excite enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [5] ,ALTEX5 always excite enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [4] ,ALTEX4 always excite enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " AEX[3] ,ALTEX3 always excite enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [2] ,ALTEX2 always excite enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [1] ,ALTEX1 always excite enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [0] ,ALTEX0 always excite enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " IDLECONF[7] ,ALTEX7 idle phase configuration" "Disabled,High,Low,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,ALTEX6 idle phase configuration" "Disabled,High,Low,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,ALTEX5 idle phase configuration" "Disabled,High,Low,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,ALTEX4 idle phase configuration" "Disabled,High,Low,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " IDLECONF[3] ,ALTEX3 idle phase configuration" "Disabled,High,Low,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,ALTEX2 idle phase configuration" "Disabled,High,Low,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,ALTEX1 idle phase configuration" "Disabled,High,Low,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,ALTEX0 idle phase configuration" "Disabled,High,Low,?..."
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " CNTOF ,Set when the LESENSE counter overflows" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " BUFOF ,Set when the result buffer overflows" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " BUFLEVEL ,Set when the data buffer is full" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " BUFDATAV ,Set when data is available in the result buffer" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " DECERR ,Set when the decoder detects an error" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DEC ,Set when the decoder has issued and interrupt request" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SCANCOMPLETE ,Set when a scan sequence is completed" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CH15 ,Set when channel 15 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " CH14 ,Set when channel 14 triggers" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " CH13 ,Set when channel 13 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CH12 ,Set when channel 12 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " CH11 ,Set when channel 11 triggers" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " CH10 ,Set when channel 10 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CH9 ,Set when channel 9 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " CH8 ,Set when channel 8 triggers" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CH7 ,Set when channel 7 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CH6 ,Set when channel 6 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CH5 ,Set when channel 5 triggers" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CH4 ,Set when channel 4 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CH3 ,Set when channel 3 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CH2 ,Set when channel 2 triggers" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CH1 ,Set when channel 1 triggers" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CH0 ,Set when channel 0 triggers" "No interrupt,Interrupt"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 22. " CNTOF ,Set to enable interrupt on the CNTOF interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BUFOF ,Set to enable interrupt on the BUFOF interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BUFLEVEL ,Set to enable interrupt on the BUFLEVEL interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " BUFDATAV ,Set to enable interrupt on the BUFDATAV interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DECERR ,Set to enable interrupt on the DECERR interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DEC ,Set to enable interrupt on the DEC interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SCANCOMPLETE ,Set to enable interrupt on the SCANCOMPLETE interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CH15 ,Set to enable interrupt on the CH15 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CH14 ,Set to enable interrupt on the CH14 interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " CH13 ,Set to enable interrupt on the CH13 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CH12 ,Set to enable interrupt on the CH12 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CH11 ,Set to enable interrupt on the CH11 interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CH10 ,Set to enable interrupt on the CH10 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CH9 ,Set to enable interrupt on the CH9 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH8 ,Set to enable interrupt on the CH8 interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CH7 ,Set to enable interrupt on the CH7 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CH6 ,Set to enable interrupt on the CH6 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH5 ,Set to enable interrupt on the CH5 interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " CH4 ,Set to enable interrupt on the CH4 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CH3 ,Set to enable interrupt on the CH3 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH2 ,Set to enable interrupt on the CH2 interrupt flag" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CH1 ,Set to enable interrupt on the CH1 interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Set to enable interrupt on the CH0 interrupt flag" "Disabled,Enabled"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x00 7. " CMD ,CMD register busy" "Not busy,Busy"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "ROUTE,I/O Routing Register"
|
|
bitfld.long 0x00 23. " ALTEX[7]PEN ,ALTEX7 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,ALTEX6 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,ALTEX5 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,ALTEX4 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " ALTEX[3]PEN ,ALTEX3 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,ALTEX2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,ALTEX1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,ALTEX0 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " CH[15]PEN ,CH15 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,CH14 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,CH13 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,CH12 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " CH[11]PEN ,CH11 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,CH10 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,CH9 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,CH8 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CH[7]PEN ,CH7 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,CH6 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,CH5 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,CH4 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CH[3]PEN ,CH3 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,CH2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,CH1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,CH0 pin enable" "Disabled,Enabled"
|
|
tree "State Transition Registers"
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x100++0x07 "State Transition Registers 0"
|
|
line.long 0x00 "ST0_TCONFA,State Transition 0 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST0_TCONFB,State Transition 0 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x100++0x07 "State Transition Registers 0"
|
|
line.long 0x00 "ST0_TCONFA,State Transition 0 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST0_TCONFB,State Transition 0 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x108++0x07 "State Transition Registers 1"
|
|
line.long 0x00 "ST1_TCONFA,State Transition 1 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST1_TCONFB,State Transition 1 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x108++0x07 "State Transition Registers 1"
|
|
line.long 0x00 "ST1_TCONFA,State Transition 1 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST1_TCONFB,State Transition 1 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x110++0x07 "State Transition Registers 2"
|
|
line.long 0x00 "ST2_TCONFA,State Transition 2 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST2_TCONFB,State Transition 2 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x110++0x07 "State Transition Registers 2"
|
|
line.long 0x00 "ST2_TCONFA,State Transition 2 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST2_TCONFB,State Transition 2 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x118++0x07 "State Transition Registers 3"
|
|
line.long 0x00 "ST3_TCONFA,State Transition 3 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST3_TCONFB,State Transition 3 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x118++0x07 "State Transition Registers 3"
|
|
line.long 0x00 "ST3_TCONFA,State Transition 3 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST3_TCONFB,State Transition 3 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x120++0x07 "State Transition Registers 4"
|
|
line.long 0x00 "ST4_TCONFA,State Transition 4 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST4_TCONFB,State Transition 4 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x120++0x07 "State Transition Registers 4"
|
|
line.long 0x00 "ST4_TCONFA,State Transition 4 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST4_TCONFB,State Transition 4 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x128++0x07 "State Transition Registers 5"
|
|
line.long 0x00 "ST5_TCONFA,State Transition 5 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST5_TCONFB,State Transition 5 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x128++0x07 "State Transition Registers 5"
|
|
line.long 0x00 "ST5_TCONFA,State Transition 5 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST5_TCONFB,State Transition 5 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x130++0x07 "State Transition Registers 6"
|
|
line.long 0x00 "ST6_TCONFA,State Transition 6 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST6_TCONFB,State Transition 6 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x130++0x07 "State Transition Registers 6"
|
|
line.long 0x00 "ST6_TCONFA,State Transition 6 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST6_TCONFB,State Transition 6 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x138++0x07 "State Transition Registers 7"
|
|
line.long 0x00 "ST7_TCONFA,State Transition 7 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST7_TCONFB,State Transition 7 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x138++0x07 "State Transition Registers 7"
|
|
line.long 0x00 "ST7_TCONFA,State Transition 7 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST7_TCONFB,State Transition 7 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x140++0x07 "State Transition Registers 8"
|
|
line.long 0x00 "ST8_TCONFA,State Transition 8 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST8_TCONFB,State Transition 8 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x140++0x07 "State Transition Registers 8"
|
|
line.long 0x00 "ST8_TCONFA,State Transition 8 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST8_TCONFB,State Transition 8 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x148++0x07 "State Transition Registers 9"
|
|
line.long 0x00 "ST9_TCONFA,State Transition 9 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST9_TCONFB,State Transition 9 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x148++0x07 "State Transition Registers 9"
|
|
line.long 0x00 "ST9_TCONFA,State Transition 9 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST9_TCONFB,State Transition 9 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x150++0x07 "State Transition Registers 10"
|
|
line.long 0x00 "ST10_TCONFA,State Transition 10 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST10_TCONFB,State Transition 10 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x150++0x07 "State Transition Registers 10"
|
|
line.long 0x00 "ST10_TCONFA,State Transition 10 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST10_TCONFB,State Transition 10 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x158++0x07 "State Transition Registers 11"
|
|
line.long 0x00 "ST11_TCONFA,State Transition 11 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST11_TCONFB,State Transition 11 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x158++0x07 "State Transition Registers 11"
|
|
line.long 0x00 "ST11_TCONFA,State Transition 11 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST11_TCONFB,State Transition 11 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x160++0x07 "State Transition Registers 12"
|
|
line.long 0x00 "ST12_TCONFA,State Transition 12 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST12_TCONFB,State Transition 12 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x160++0x07 "State Transition Registers 12"
|
|
line.long 0x00 "ST12_TCONFA,State Transition 12 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST12_TCONFB,State Transition 12 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x168++0x07 "State Transition Registers 13"
|
|
line.long 0x00 "ST13_TCONFA,State Transition 13 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST13_TCONFB,State Transition 13 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x168++0x07 "State Transition Registers 13"
|
|
line.long 0x00 "ST13_TCONFA,State Transition 13 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST13_TCONFB,State Transition 13 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x170++0x07 "State Transition Registers 14"
|
|
line.long 0x00 "ST14_TCONFA,State Transition 14 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST14_TCONFB,State Transition 14 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x170++0x07 "State Transition Registers 14"
|
|
line.long 0x00 "ST14_TCONFA,State Transition 14 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST14_TCONFB,State Transition 14 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x178++0x07 "State Transition Registers 15"
|
|
line.long 0x00 "ST15_TCONFA,State Transition 15 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST15_TCONFB,State Transition 15 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x178++0x07 "State Transition Registers 15"
|
|
line.long 0x00 "ST15_TCONFA,State Transition 15 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST15_TCONFB,State Transition 15 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x180++0x07 "State Transition Registers 16"
|
|
line.long 0x00 "ST16_TCONFA,State Transition 16 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST16_TCONFB,State Transition 16 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x180++0x07 "State Transition Registers 16"
|
|
line.long 0x00 "ST16_TCONFA,State Transition 16 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST16_TCONFB,State Transition 16 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x188++0x07 "State Transition Registers 17"
|
|
line.long 0x00 "ST17_TCONFA,State Transition 17 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST17_TCONFB,State Transition 17 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x188++0x07 "State Transition Registers 17"
|
|
line.long 0x00 "ST17_TCONFA,State Transition 17 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST17_TCONFB,State Transition 17 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x190++0x07 "State Transition Registers 18"
|
|
line.long 0x00 "ST18_TCONFA,State Transition 18 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST18_TCONFB,State Transition 18 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x190++0x07 "State Transition Registers 18"
|
|
line.long 0x00 "ST18_TCONFA,State Transition 18 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST18_TCONFB,State Transition 18 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x198++0x07 "State Transition Registers 19"
|
|
line.long 0x00 "ST19_TCONFA,State Transition 19 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST19_TCONFB,State Transition 19 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x198++0x07 "State Transition Registers 19"
|
|
line.long 0x00 "ST19_TCONFA,State Transition 19 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST19_TCONFB,State Transition 19 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1A0++0x07 "State Transition Registers 20"
|
|
line.long 0x00 "ST20_TCONFA,State Transition 20 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST20_TCONFB,State Transition 20 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1A0++0x07 "State Transition Registers 20"
|
|
line.long 0x00 "ST20_TCONFA,State Transition 20 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST20_TCONFB,State Transition 20 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1A8++0x07 "State Transition Registers 21"
|
|
line.long 0x00 "ST21_TCONFA,State Transition 21 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST21_TCONFB,State Transition 21 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1A8++0x07 "State Transition Registers 21"
|
|
line.long 0x00 "ST21_TCONFA,State Transition 21 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST21_TCONFB,State Transition 21 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1B0++0x07 "State Transition Registers 22"
|
|
line.long 0x00 "ST22_TCONFA,State Transition 22 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST22_TCONFB,State Transition 22 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1B0++0x07 "State Transition Registers 22"
|
|
line.long 0x00 "ST22_TCONFA,State Transition 22 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST22_TCONFB,State Transition 22 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1B8++0x07 "State Transition Registers 23"
|
|
line.long 0x00 "ST23_TCONFA,State Transition 23 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST23_TCONFB,State Transition 23 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1B8++0x07 "State Transition Registers 23"
|
|
line.long 0x00 "ST23_TCONFA,State Transition 23 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST23_TCONFB,State Transition 23 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1C0++0x07 "State Transition Registers 24"
|
|
line.long 0x00 "ST24_TCONFA,State Transition 24 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST24_TCONFB,State Transition 24 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1C0++0x07 "State Transition Registers 24"
|
|
line.long 0x00 "ST24_TCONFA,State Transition 24 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST24_TCONFB,State Transition 24 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1C8++0x07 "State Transition Registers 25"
|
|
line.long 0x00 "ST25_TCONFA,State Transition 25 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST25_TCONFB,State Transition 25 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1C8++0x07 "State Transition Registers 25"
|
|
line.long 0x00 "ST25_TCONFA,State Transition 25 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST25_TCONFB,State Transition 25 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1D0++0x07 "State Transition Registers 26"
|
|
line.long 0x00 "ST26_TCONFA,State Transition 26 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST26_TCONFB,State Transition 26 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1D0++0x07 "State Transition Registers 26"
|
|
line.long 0x00 "ST26_TCONFA,State Transition 26 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST26_TCONFB,State Transition 26 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1D8++0x07 "State Transition Registers 27"
|
|
line.long 0x00 "ST27_TCONFA,State Transition 27 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST27_TCONFB,State Transition 27 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1D8++0x07 "State Transition Registers 27"
|
|
line.long 0x00 "ST27_TCONFA,State Transition 27 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST27_TCONFB,State Transition 27 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1E0++0x07 "State Transition Registers 28"
|
|
line.long 0x00 "ST28_TCONFA,State Transition 28 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST28_TCONFB,State Transition 28 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x07 "State Transition Registers 28"
|
|
line.long 0x00 "ST28_TCONFA,State Transition 28 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST28_TCONFB,State Transition 28 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1E8++0x07 "State Transition Registers 29"
|
|
line.long 0x00 "ST29_TCONFA,State Transition 29 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST29_TCONFB,State Transition 29 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E8++0x07 "State Transition Registers 29"
|
|
line.long 0x00 "ST29_TCONFA,State Transition 29 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST29_TCONFB,State Transition 29 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1F0++0x07 "State Transition Registers 30"
|
|
line.long 0x00 "ST30_TCONFA,State Transition 30 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST30_TCONFB,State Transition 30 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1F0++0x07 "State Transition Registers 30"
|
|
line.long 0x00 "ST30_TCONFA,State Transition 30 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST30_TCONFB,State Transition 30 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40055000+0x0C))&0x80)==0x00)
|
|
group.long 0x1F8++0x07 "State Transition Registers 31"
|
|
line.long 0x00 "ST31_TCONFA,State Transition 31 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST31_TCONFB,State Transition 31 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,PRS0,PRS1,PRS01,PRS2,PRS02,PRS12,PRS012"
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1F8++0x07 "State Transition Registers 31"
|
|
line.long 0x00 "ST31_TCONFA,State Transition 31 Configuration A"
|
|
bitfld.long 0x00 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x00 15. " SETIF ,Set interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CHAIN ,State descriptor chaining enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x00 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x00 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x00 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ST31_TCONFB,State Transition 31 Configuration B"
|
|
bitfld.long 0x04 16.--18. " PRSACT ,Configure transition action" "None,Up,Down,,PRS2,Up and PRS2,Down and PRS2,?..."
|
|
bitfld.long 0x04 15. " SETIF ,Set interrupt flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--11. " NEXTSTATE ,Next state index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. " MASK[3:0] ,Sensor mask bit 3" "0,1"
|
|
bitfld.long 0x04 6. ",Sensor mask bit 2" "0,1"
|
|
bitfld.long 0x04 5. ",Sensor mask bit 1" "0,1"
|
|
bitfld.long 0x04 4. ",Sensor mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " COMP ,Sensor compare value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Scan Results"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "BUF0_DATA,Scan Results 0 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "BUF1_DATA,Scan Results 1 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "BUF2_DATA,Scan Results 2 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "BUF3_DATA,Scan Results 3 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "BUF4_DATA,Scan Results 4 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "BUF5_DATA,Scan Results 5 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "BUF6_DATA,Scan Results 6 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "BUF7_DATA,Scan Results 7 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "BUF8_DATA,Scan Results 8 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "BUF9_DATA,Scan Results 9 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "BUF10_DATA,Scan Results 10 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "BUF11_DATA,Scan Results 11 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "BUF12_DATA,Scan Results 12 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "BUF13_DATA,Scan Results 13 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "BUF14_DATA,Scan Results 14 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "BUF15_DATA,Scan Results 15 Register"
|
|
rbitfld.long 0x00 16.--19. " DATASRC ,Result data source" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Scan result buffer"
|
|
tree.end
|
|
tree "Scan Configuration Registers"
|
|
group.long 0x240++0x0B "State Configuration Registers 0"
|
|
line.long 0x00 "CH0_TIMING,Scan Timing Configuration 0 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH0_INTERACT,Scan Interact Configuration 0 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH0_EVAL,Scan Evaluation Configuration 0 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x250++0x0B "State Configuration Registers 1"
|
|
line.long 0x00 "CH1_TIMING,Scan Timing Configuration 1 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH1_INTERACT,Scan Interact Configuration 1 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH1_EVAL,Scan Evaluation Configuration 1 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x260++0x0B "State Configuration Registers 2"
|
|
line.long 0x00 "CH2_TIMING,Scan Timing Configuration 2 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH2_INTERACT,Scan Interact Configuration 2 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH2_EVAL,Scan Evaluation Configuration 2 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x270++0x0B "State Configuration Registers 3"
|
|
line.long 0x00 "CH3_TIMING,Scan Timing Configuration 3 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH3_INTERACT,Scan Interact Configuration 3 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH3_EVAL,Scan Evaluation Configuration 3 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x280++0x0B "State Configuration Registers 4"
|
|
line.long 0x00 "CH4_TIMING,Scan Timing Configuration 4 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH4_INTERACT,Scan Interact Configuration 4 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH4_EVAL,Scan Evaluation Configuration 4 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x290++0x0B "State Configuration Registers 5"
|
|
line.long 0x00 "CH5_TIMING,Scan Timing Configuration 5 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH5_INTERACT,Scan Interact Configuration 5 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH5_EVAL,Scan Evaluation Configuration 5 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x2A0++0x0B "State Configuration Registers 6"
|
|
line.long 0x00 "CH6_TIMING,Scan Timing Configuration 6 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH6_INTERACT,Scan Interact Configuration 6 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH6_EVAL,Scan Evaluation Configuration 6 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x2B0++0x0B "State Configuration Registers 7"
|
|
line.long 0x00 "CH7_TIMING,Scan Timing Configuration 7 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH7_INTERACT,Scan Interact Configuration 7 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH7_EVAL,Scan Evaluation Configuration 7 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x2C0++0x0B "State Configuration Registers 8"
|
|
line.long 0x00 "CH8_TIMING,Scan Timing Configuration 8 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH8_INTERACT,Scan Interact Configuration 8 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH8_EVAL,Scan Evaluation Configuration 8 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x2D0++0x0B "State Configuration Registers 9"
|
|
line.long 0x00 "CH9_TIMING,Scan Timing Configuration 9 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH9_INTERACT,Scan Interact Configuration 9 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH9_EVAL,Scan Evaluation Configuration 9 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x2E0++0x0B "State Configuration Registers 10"
|
|
line.long 0x00 "CH10_TIMING,Scan Timing Configuration 10 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH10_INTERACT,Scan Interact Configuration 10 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH10_EVAL,Scan Evaluation Configuration 10 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x2F0++0x0B "State Configuration Registers 11"
|
|
line.long 0x00 "CH11_TIMING,Scan Timing Configuration 11 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH11_INTERACT,Scan Interact Configuration 11 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,?..."
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH11_EVAL,Scan Evaluation Configuration 11 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x300++0x0B "State Configuration Registers 12"
|
|
line.long 0x00 "CH12_TIMING,Scan Timing Configuration 12 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH12_INTERACT,Scan Interact Configuration 12 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH12_EVAL,Scan Evaluation Configuration 12 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x310++0x0B "State Configuration Registers 13"
|
|
line.long 0x00 "CH13_TIMING,Scan Timing Configuration 13 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH13_INTERACT,Scan Interact Configuration 13 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH13_EVAL,Scan Evaluation Configuration 13 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x320++0x0B "State Configuration Registers 14"
|
|
line.long 0x00 "CH14_TIMING,Scan Timing Configuration 14 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH14_INTERACT,Scan Interact Configuration 14 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH14_EVAL,Scan Evaluation Configuration 14 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
group.long 0x330++0x0B "State Configuration Registers 15"
|
|
line.long 0x00 "CH15_TIMING,Scan Timing Configuration 15 Register"
|
|
hexmask.long.word 0x00 14.--23. 1. " MEASUREDLY ,Set measure delay"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SAMPLEDLY ,Set sample delay"
|
|
bitfld.long 0x00 0.--5. " EXTIME ,Set excitation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CH15_INTERACT,Scan Interact Configuration 15 Register"
|
|
bitfld.long 0x04 21. " ALTEX ,Use alternative excite pin" "Not used,Used"
|
|
bitfld.long 0x04 20. " SAMPLECLK ,Select clock used for timing of sample delay" "LFACLK,AUXHFRCO"
|
|
bitfld.long 0x04 19. " EXCLK ,Select clock used for excitation timing" "LFACLK,AUXHFRCO"
|
|
newline
|
|
bitfld.long 0x04 17.--18. " EXMODE ,Set GPIO mode" "Disabled,High,Low,DAC out"
|
|
bitfld.long 0x04 14.--16. " SETIF ,Enable interrupt generation" "None,Level,POSEDGE,NEGEDGE,BOTHEDGES,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " SAMPLE ,Select sample mode" "ACMPCOUNT,ACMP,ADC,ADCDIFF"
|
|
hexmask.long.word 0x04 0.--11. 1. " THRES ,Set ACMP threshold"
|
|
line.long 0x08 "CH15_EVAL,Scan Evaluation Configuration 15 Register"
|
|
bitfld.long 0x08 21.--22. " MODE ,Configure evaluation mode" "THRES,SLIDINGWIN,STEPDET,?..."
|
|
bitfld.long 0x08 20. " SCANRESINV ,Enable inversion of result" "Disabled,Enabled"
|
|
bitfld.long 0x08 18.--19. " STRSAMPLE ,Enable storing of sensor sample in result buffer" "Disabled,Data,Data source,?..."
|
|
newline
|
|
bitfld.long 0x08 17. " DECODE ,Send result to decoder" "Not shifted,Shifted"
|
|
bitfld.long 0x08 16. " COMP ,Select mode for counter comparison" "LESS,GE"
|
|
hexmask.long.word 0x08 0.--15. 1. " COMPTHRES ,Decision threshold for sensor data"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPCRC (General Purpose Cyclic Redundancy Check)"
|
|
base ad:0x4001C000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 13. " AUTOINIT ,Auto init enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BYTEREVERSE ,Byte reverse mode" "Not reversed,Reversed"
|
|
bitfld.long 0x00 9. " BITREVERSE ,Byte-level bit reverse enable" "Not reversed,Reversed"
|
|
newline
|
|
bitfld.long 0x00 8. " BYTEMODE ,Byte mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " POLYSEL ,Polynomial select" "CRC32,CRC16"
|
|
bitfld.long 0x00 0. " EN ,CRC functionality enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 0. " INIT ,Initialization enable" "No effect,Enable"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "INIT,CRC Init Value"
|
|
line.long 0x04 "POLY,CRC Polynomial Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " POLY ,CRC polynomial value"
|
|
wgroup.long 0x10++0x0B
|
|
line.long 0x00 "INPUTDATA,Input 32-bit Data Register"
|
|
line.long 0x04 "INPUTDATAHWORD,Input 16-bit Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INPUTDATAHWORD ,Input data for 16-bit"
|
|
line.long 0x08 "INPUTDATABYTE,Input 8-bit Data Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " INPUTDATABYTE ,Input data for 8-bit"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "DATA,CRC Data Register"
|
|
line.long 0x04 "DATAREV,CRC Data Reverse Register"
|
|
line.long 0x08 "DATABYTEREV,CRC Data Byte Reverse Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x4001D000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONTROL,Main Control Register"
|
|
bitfld.long 0x00 13. " BYPAIS31 ,AIS31 start-up test bypass" "Normal,Bypassed"
|
|
bitfld.long 0x00 12. " BYPNIST ,NIST start-up test bypass" "Normal,Bypassed"
|
|
bitfld.long 0x00 11. " FORCERUN ,Oscillator force run" "Normal,Run"
|
|
newline
|
|
bitfld.long 0x00 10. " ALMIEN ,Interrupt enable for AIS31 noise alarm" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREIEN ,Interrupt enable for AIS31 preliminary noise alarm" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " FULLIEN ,Interrupt enable for FIFO full" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " APT4096IEN ,Interrupt enable for adaptive proportion test failure (4096-sample window)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " APT64IEN ,Interrupt enable for adaptive proportion test failure (64-sample window)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " REPCOUNTIEN ,Interrupt enable for repetition count test failure" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CONDBYPASS ,Condition bypass" "Normal,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 2. " TESTEN ,Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,TRNG module enable" "Disabled,Enabled"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "FIFOLEVEL,FIFO Level Register"
|
|
in
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "FIFODEPTH,FIFO Depth Register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "KEY0,Key Register 0"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "KEY1,Key Register 1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "KEY2,Key Register 2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "KEY3,Key Register 3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TESTDATA,Test Data Register"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "STATUS,Status Register"
|
|
rbitfld.long 0x00 9. " ALMIF ,AIS31 noise alarm interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PREIF ,AIS31 preliminary noise alarm interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " FULLIF ,FIFO full interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 6. " APT4096IF ,Adaptive proportion test failure (4096-sample window) interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " APT64IF ,Adaptive proportion test failure (64-sample window) interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 4. " REPCOUNTIF ,Repetition count test interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " TESTDATABUSY ,Test data busy" "Idle,Busy"
|
|
line.long 0x04 "INITWAITVAL,Initial Wait Counter"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VALUE ,Wait counter value"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "FIFO,FIFO Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRYPTO (Crypto Accelerator)"
|
|
base ad:0x400F0000
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. " COMBDMA0WEREQ ,Combined data 0 write DMA request" "Not requested,Requested"
|
|
bitfld.long 0x00 28.--29. " DMA1RSEL ,Data1 DMA unaligned read register select" "DATA1,DDATA1,QDATA1,QDATA1BIG"
|
|
bitfld.long 0x00 24.--25. " DMA1MODE ,DMA1 read mode" "Full,LENLIMIT,FULLBYTE,LENLIMITBYTE"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " DMA0RSEL ,DMA0 read register select" "DATA0,DDATA0,DDATA0BIG,QDATA0"
|
|
bitfld.long 0x00 16.--17. " DMA0MODE ,DMA0 read mode" "Full,LENLIMIT,FULLBYTE,LENLIMITBYTE"
|
|
bitfld.long 0x00 14.--15. " INCWIDTH ,Increment width" "INCWIDTH1,INCWIDTH2,INCWIDTH3,INCWIDTH4"
|
|
newline
|
|
bitfld.long 0x00 10. " NOBUSYSTALL ,No stalling of bus when busy" "No stalled,Stalled"
|
|
bitfld.long 0x00 2. " SHA ,SHA mode" "SHA1,SHA2"
|
|
newline
|
|
bitfld.long 0x00 1. " KEYBUFDIS ,Key buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " AES ,AES mode" "AES128,AES256"
|
|
line.long 0x04 "WAC,Wide Arithmetic Configuration Register"
|
|
bitfld.long 0x04 10.--11. " RESULTWIDTH ,Result width" "256 bit,128 bit,260 bit,?..."
|
|
bitfld.long 0x04 8.--9. " MULWIDTH ,Multiply width" "256 bit,128 bit,MULMOD,?..."
|
|
newline
|
|
bitfld.long 0x04 4. " MODOP ,Modular operation field type" "Binary,Regular"
|
|
bitfld.long 0x04 0.--3. " MODULUS ,Modular operation modulus" "BIN256,BIN128,ECCBIN233P,ECCBIN163P,GCMBIN128,ECCPRIME256P,ECCPRIME224P,ECCPRIME192P,ECCBIN233N,ECCBIN233KN,ECCBIN163N,ECCBIN163KN,ECCPRIME256N,ECCPRIME224N,ECCPRIME192N,?..."
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 11. " SEQSTEP ,Sequence step" "No effect,Execute"
|
|
bitfld.long 0x00 10. " SEQSTOP ,Sequence stop" "No effect,Stop"
|
|
newline
|
|
bitfld.long 0x00 9. " SEQSTART ,Sequence start" "No effect,Start"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INSTR ,Execute instruction"
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 2. " DMAACTIVE ,DMA action is active" "Not active,Active"
|
|
bitfld.long 0x00 1. " INSTRRUNNING ,Action is active" "Not active,Active"
|
|
bitfld.long 0x00 0. " SEQRUNNING ,AES sequence running" "Not running,Running"
|
|
line.long 0x04 "DSTATUS,Data Status Register"
|
|
bitfld.long 0x04 24. " CARRY ,Carry from arithmetic operation" "Not carried,Carried"
|
|
bitfld.long 0x04 20. " DDATA1MSB ,MSB in DDATA1 allow" "Not allowed,Allowed"
|
|
bitfld.long 0x04 16.--19. " DDATA0MSB ,MSB in DDATA1 allow" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DDATA0LSBS ,LSBs in DDATA0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " DATA0ZERO ,Data 0 zero" ",ZERO0TO31,ZERO32TO63,,ZERO64TO95,,,,ZERO96TO127,?..."
|
|
line.long 0x08 "CSTATUS,Control Status Register"
|
|
bitfld.long 0x08 20.--24. " SEQIP ,Sequence next instruction pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 17. " SEQSKIP ,Sequence skip next instruction" "Not skipped,Skipped"
|
|
bitfld.long 0x08 16. " SEQPART ,Sequence part" "SEQA,SEQB"
|
|
newline
|
|
bitfld.long 0x08 8.--10. " V1 ,Selected ALU operand 1" "DDATA0,DDATA1,DDATA2,DDATA3,DDATA4,DATA0,DATA1,DATA2"
|
|
bitfld.long 0x08 0.--2. " V0 ,Selected ALU operand 0" "DDATA0,DDATA1,DDATA2,DDATA3,DDATA4,DATA0,DATA1,DATA2"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "KEY,KEY Register Access"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "KEYBUF,KEY Buffer Register Access"
|
|
in
|
|
newline
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SEQCTRL,Sequence Control Register"
|
|
bitfld.long 0x00 31. " HALT ,Halt sequence allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " DMA1PRESA ,DMA1 preserve A" "Not preserved,Preserved"
|
|
bitfld.long 0x00 28. " DMA0PRESA ,DMA0 preserve A" "Not preserved,Preserved"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " DMA1SKIP ,DMA1 skip" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DMA0SKIP ,DMA0 skip" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " BLOCKSIZE ,Size of data blocks" "16 bytes,32 bytes,64 bytes,?..."
|
|
hexmask.long.word 0x00 0.--13. 1. " LENGTHA ,Buffer length A in bytes"
|
|
line.long 0x04 "SEQCTRLB,Sequence Control B"
|
|
bitfld.long 0x04 29. " DMA1PRESB ,DMA1 preserve B" "Not preserved,Preserved"
|
|
bitfld.long 0x04 28. " DMA0PRESB ,DMA0 preserve B" "Not preserved,Preserved"
|
|
hexmask.long.word 0x04 0.--13. 1. " LENGTHB ,Buffer length B in bytes"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF_SET/CLR,AES Interrupt Set/Clear Flags Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SEQDONE ,Sequence done" "Not done,Done"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " INSTRDONE ,Instruction done" "Not done,Done"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " SEQDONE ,Sequence done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INSTRDONE ,Instruction done interrupt enable" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SEQ0,Sequence Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INSTR3 ,Sequence instruction 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INSTR2 ,Sequence instruction 2 "
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " INSTR1 ,Sequence instruction 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INSTR0 ,Sequence instruction 0 "
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SEQ1,Sequence Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INSTR7 ,Sequence instruction 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INSTR6 ,Sequence instruction 6 "
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " INSTR5 ,Sequence instruction 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INSTR4 ,Sequence instruction 4 "
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SEQ2,Sequence Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INSTR11 ,Sequence instruction 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INSTR10 ,Sequence instruction 10"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " INSTR9 ,Sequence instruction 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INSTR8 ,Sequence instruction 8 "
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SEQ3,Sequence Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INSTR15 ,Sequence instruction 15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INSTR14 ,Sequence instruction 14"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " INSTR13 ,Sequence instruction 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INSTR12 ,Sequence instruction 12"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SEQ4,Sequence Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INSTR19 ,Sequence instruction 19"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INSTR18 ,Sequence instruction 18"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " INSTR17 ,Sequence instruction 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INSTR16 ,Sequence instruction 16"
|
|
newline
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "DATA0,DATA0 Register Access"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "DATA1,DATA1 Register Access"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "DATA2,DATA2 Register Access"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "DATA3,DATA3 Register Access"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "DATA0XOR,DATA0XOR Register Access"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "DATA0BYTE,DATA0 Register Byte Access"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "DATA1BYTE,DATA1 Register Byte Access"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "DATA0XORBYTE,DATA0 Register Byte XOR Access"
|
|
in
|
|
newline
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DATA0BYTE12,DATA0 Register Byte 12 Access"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0BYTE12 ,Data 0 byte 12 access"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DATA0BYTE13,DATA0 Register Byte 13 Access"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0BYTE13 ,Data 0 byte 13 access"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DATA0BYTE14,DATA0 Register Byte 14 Access"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0BYTE14 ,Data 0 byte 14 access"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DATA0BYTE15,DATA0 Register Byte 15 Access"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0BYTE15 ,Data 0 byte 15 access"
|
|
newline
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "DDATA0,DDATA0 Register Access"
|
|
in
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "DDATA1,DDATA1 Register Access"
|
|
in
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "DDATA2,DDATA2 Register Access"
|
|
in
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "DDATA3,DDATA3 Register Access"
|
|
in
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "DDATA4,DDATA4 Register Access"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "DDATA0BIG,DDATA0 Register Big Endian Access"
|
|
in
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "DDATA0BYTE,DDATA0 Register Byte Access"
|
|
in
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "DDATA1BYTE,DDATA1 Register Byte Access"
|
|
in
|
|
newline
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DDATA0BYTE32,DDATA0 Register Byte 32 Access"
|
|
bitfld.long 0x00 0.--3. " DDATA0BYTE32 ,DDDATA0 byte 32 access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "QDATA0,QDATA0 Register Access"
|
|
in
|
|
hgroup.long 0x184++0x03
|
|
hide.long 0x00 "QDATA1,QDATA1 Register Access"
|
|
in
|
|
hgroup.long 0x1A4++0x03
|
|
hide.long 0x00 "QDATA1BIG,QDATA1 Register Big Endian Access"
|
|
in
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "QDATA0BYTE,QDATA0 Register Byte Access"
|
|
in
|
|
hgroup.long 0x1C4++0x03
|
|
hide.long 0x00 "QDATA1BYTE,QDATA1 Register Byte Access"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base ad:0x40088000
|
|
sif cpuis("EFM32GG11B8*")
|
|
width 13.
|
|
tree "GPIO PA"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 20.--23. " MODE[5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x0+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 8.--11. " MODE[10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 10. " DOUT[10] ,Pin 10 data out " "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 10. " DOUTTGL[10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 10. " DIN[10] ,Pin 10 data in " "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 10. " PINLOCKN[10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 10. " OVTDIS[10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
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|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
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|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
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|
group.long (0x0+0x28)++0x03
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|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
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bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
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|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
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|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
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|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
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|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
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|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
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|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
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|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PB"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x30+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x30+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 24.--27. " MODE[14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 14. " DOUT[14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " DOUT[11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " DOUT[7] ,Pin 7 data out " "Low,High"
|
|
newline
|
|
wgroup.long (0x30+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 14. " DOUTTGL[14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " DOUTTGL[11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " DOUTTGL[7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
newline
|
|
rgroup.long (0x30+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 14. " DIN[14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " DIN[11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " DIN[7] ,Pin 7 data in " "Low,High"
|
|
newline
|
|
group.long (0x30+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 14. " PINLOCKN[14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " PINLOCKN[11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " PINLOCKN[7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
newline
|
|
group.long (0x30+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 14. " OVTDIS[14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " OVTDIS[11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " OVTDIS[7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
newline
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x30+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
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|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x30+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x30+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
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|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
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|
newline
|
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bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x30+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
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bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
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|
newline
|
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bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
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|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
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|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
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|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
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bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
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|
endif
|
|
width 0x0B
|
|
tree.end
|
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tree "GPIO PC"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
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group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x60+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x00 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
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bitfld.long 0x00 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
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bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x60+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 data out " "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " DOUT[11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 data out " "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " DOUT[7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 data out " "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " DOUTTGL[11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " DOUTTGL[7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x60+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " DIN[11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " DIN[7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x60+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " PINLOCKN[11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " PINLOCKN[7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x60+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " OVTDIS[11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " OVTDIS[7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x60+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x60+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x60+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PD"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x90+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x90+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 0.--3. " MODE[8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 8. " DOUT[8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " DOUT[7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 data out " "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x90+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 8. " DOUTTGL[8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " DOUTTGL[7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x90+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 8. " DIN[8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " DIN[7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x90+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 8. " PINLOCKN[8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " PINLOCKN[7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x90+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 8. " OVTDIS[8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " OVTDIS[7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x90+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x90+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x90+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x90+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PE"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0xC0+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 data out " "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " DOUT[11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 data out " "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
wgroup.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " DOUTTGL[11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
rgroup.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " DIN[11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
group.long (0xC0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " PINLOCKN[11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
group.long (0xC0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " OVTDIS[11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
else
|
|
group.long 0xC0++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0xC0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0xC0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PF"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0xF0+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 20.--23. " MODE[5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0xF0+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0xF0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0xF0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0xF0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0xF0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0xF0++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x08 24.--27. " MODE[14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x0C 14. " DOUT[14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0xF0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " DOUTTGL[14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0xF0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " DIN[14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0xF0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " PINLOCKN[14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0xF0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " OVTDIS[14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PG"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x120+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x120+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x120+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x120+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x120+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x120++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x120+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x120+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x120+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x120+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PH"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x150+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x150+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x150+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x150+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x150+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x150++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x150+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x150+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x150+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x150+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PI"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x180+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x180+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x180+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x180+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x180+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x180++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x180+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x180+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x180+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x180+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
width 13.
|
|
tree "Common"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "EXTIPSELL,External Interrupt Port Select Low Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 28.--31. " EXTIPSEL[7] ,External interrupt 7 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,External interrupt 6 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,External interrupt 5 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,External interrupt 4 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " EXTIPSEL[3] ,External interrupt 3 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,External interrupt 2 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,External interrupt 1 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,External interrupt 0 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
else
|
|
bitfld.long 0x00 28.--31. " EXTIPSEL[7] ,External interrupt 7 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,External interrupt 6 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,External interrupt 5 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,External interrupt 4 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " EXTIPSEL[3] ,External interrupt 3 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,External interrupt 2 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,External interrupt 1 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,External interrupt 0 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
endif
|
|
line.long 0x04 "EXTIPSELH,External Interrupt Port Select High Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x04 28.--31. " EXTIPSEL[15] ,External interrupt 15 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,External interrupt 14 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,External interrupt 13 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,External interrupt 12 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. " EXTIPSEL[11] ,External interrupt 11 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,External interrupt 10 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,External interrupt 9 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,External interrupt 8 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
else
|
|
bitfld.long 0x04 28.--31. " EXTIPSEL[15] ,External interrupt 15 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,External interrupt 14 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,External interrupt 13 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,External interrupt 12 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. " EXTIPSEL[11] ,External interrupt 11 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,External interrupt 10 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,External interrupt 9 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,External interrupt 8 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
endif
|
|
line.long 0x08 "EXTIPINSELL,External Interrupt Pin Select Low Register"
|
|
bitfld.long 0x08 28.--29. " EXTIPINSEL[7] ,External interrupt 7 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 24.--25. " [6] ,External interrupt 6 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 20.--21. " [5] ,External interrupt 5 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 16.--17. " [4] ,External interrupt 4 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
newline
|
|
bitfld.long 0x08 12.--13. " EXTIPINSEL[3] ,External interrupt 3 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 8.--9. " [2] ,External interrupt 2 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 4.--5. " [1] ,External interrupt 1 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 0.--1. " [0] ,External interrupt 0 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
line.long 0x0C "EXTIPINSELH,External Interrupt Pin Select High Register"
|
|
bitfld.long 0x0C 28.--29. " EXTPINSEL[15] ,External interrupt 15 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 24.--25. " [14] ,External interrupt 14 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 20.--21. " [13] ,External interrupt 13 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 16.--17. " [12] ,External interrupt 12 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
newline
|
|
bitfld.long 0x0C 12.--13. " EXTPINSEL[11] ,External interrupt 11 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 8.--9. " [10] ,External interrupt 10 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 4.--5. " [9] ,External interrupt 9 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 0.--1. " [8] ,External interrupt 8 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
line.long 0x10 "EXTIRISE,External Interrupt Rising Edge Trigger Register"
|
|
bitfld.long 0x10 15. " EXTIRISE[15] ,External interrupt 15 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " [14] ,External interrupt 14 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " [13] ,External interrupt 13 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " [12] ,External interrupt 12 rising edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 11. " EXTIRISE[11] ,External interrupt 11 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " [10] ,External interrupt 10 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " [9] ,External interrupt 9 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " [8] ,External interrupt 8 rising edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 7. " EXTIRISE[7] ,External interrupt 7 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " [6] ,External interrupt 6 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " [5] ,External interrupt 5 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " [4] ,External interrupt 4 rising edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. " EXTIRISE[3] ,External interrupt 3 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " [2] ,External interrupt 2 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " [1] ,External interrupt 1 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " [0] ,External interrupt 0 rising edge trigger enable" "Disabled,Enabled"
|
|
line.long 0x14 "EXTIFALL,External Interrupt Falling Edge Trigger Register"
|
|
bitfld.long 0x14 15. " EXTIFALL[15] ,External interrupt 15 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " [14] ,External interrupt 14 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " [13] ,External interrupt 13 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " [12] ,External interrupt 12 falling edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 11. " EXTIFALL[11] ,External interrupt 11 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " [10] ,External interrupt 10 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " [9] ,External interrupt 9 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " [8] ,External interrupt 8 falling edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 7. " EXTIFALL[7] ,External interrupt 7 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " [6] ,External interrupt 6 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " [5] ,External interrupt 5 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " [4] ,External interrupt 4 falling edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " EXTIFALL[3] ,External interrupt 3 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " [2] ,External interrupt 2 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " [1] ,External interrupt 1 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " [0] ,External interrupt 0 falling edge trigger enable" "Disabled,Enabled"
|
|
line.long 0x18 "EXTILEVEL,External Interrupt Level Register"
|
|
bitfld.long 0x18 25. " EM4WU[9] ,EM4 wake up level for EM4WU9 pin" "Low,High"
|
|
bitfld.long 0x18 24. " [8] ,EM4 wake up level for EM4WU8 pin" "Low,High"
|
|
bitfld.long 0x18 23. " [7] ,EM4 wake up level for EM4WU7 pin" "Low,High"
|
|
bitfld.long 0x18 22. " [6] ,EM4 wake up level for EM4WU6 pin" "Low,High"
|
|
newline
|
|
bitfld.long 0x18 21. " EM4WU[5] ,EM4 wake up level for EM4WU5 pin" "Low,High"
|
|
bitfld.long 0x18 20. " [4] ,EM4 wake up level for EM4WU4 pin" "Low,High"
|
|
bitfld.long 0x18 19. " [3] ,EM4 wake up level for EM4WU3 pin" "Low,High"
|
|
newline
|
|
bitfld.long 0x18 18. " EM4WU[2] ,EM4 wake up level for EM4WU2 pin" "Low,High"
|
|
bitfld.long 0x18 17. " [1] ,EM4 wake up level for EM4WU1 pin" "Low,High"
|
|
bitfld.long 0x18 16. " [0] ,EM4 wake up level for EM4WU0 pin" "Low,High"
|
|
line.long 0x1C "IF_SETCLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x1C 31. 0x20 31. 0x24 31. " EM4WU[15] ,EM4 wake up pin 15 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 30. 0x20 30. 0x24 30. " [14] ,EM4 wake up pin 14 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 29. 0x20 29. 0x24 29. " [13] ,EM4 wake up pin 13 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 28. 0x20 28. 0x24 28. " [12] ,EM4 wake up pin 12 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 27. 0x20 27. 0x24 27. " EM4WU[11] ,EM4 wake up pin 11 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 26. 0x20 26. 0x24 26. " [10] ,EM4 wake up pin 10 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 25. 0x20 25. 0x24 25. " [9] ,EM4 wake up pin 9 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 24. 0x20 24. 0x24 24. " [8] ,EM4 wake up pin 8 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 23. 0x20 23. 0x24 23. " EM4WU[7] ,EM4 wake up pin 7 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 22. 0x20 22. 0x24 22. " [6] ,EM4 wake up pin 6 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 21. 0x20 21. 0x24 21. " [5] ,EM4 wake up pin 5 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 20. 0x20 20. 0x24 20. " [4] ,EM4 wake up pin 4 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 19. 0x20 19. 0x24 19. " EM4WU[3] ,EM4 wake up pin 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 18. 0x20 18. 0x24 18. " [2] ,EM4 wake up pin 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 17. 0x20 17. 0x24 17. " [1] ,EM4 wake up pin 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 16. 0x20 16. 0x24 16. " [0] ,EM4 wake up pin 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 15. 0x20 15. 0x24 15. " EXT[15] ,External pin 15 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 14. 0x20 14. 0x24 14. " [14] ,External pin 14 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 13. 0x20 13. 0x24 13. " [13] ,External pin 13 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 12. 0x20 12. 0x24 12. " [12] ,External pin 12 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 11. 0x20 11. 0x24 11. " EXT[11] ,External pin 11 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 10. 0x20 10. 0x24 10. " [10] ,External pin 10 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 9. 0x20 9. 0x24 9. " [9] ,External pin 9 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 8. 0x20 8. 0x24 8. " [8] ,External pin 8 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 7. 0x20 7. 0x24 7. " EXT[7] ,External pin 7 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 6. 0x20 6. 0x24 6. " [6] ,External pin 6 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 5. 0x20 5. 0x24 5. " [5] ,External pin 5 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 4. 0x20 4. 0x24 4. " [4] ,External pin 4 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 3. 0x20 3. 0x24 3. " EXT[3] ,External pin 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 2. 0x20 2. 0x24 2. " [2] ,External pin 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 1. 0x20 1. 0x24 1. " [1] ,External pin 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 0. 0x20 0. 0x24 0. " [0] ,External pin 0 interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x428++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " EM4WU[15] ,EM4 wake up pin 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,EM4 wake up pin 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,EM4 wake up pin 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,EM4 wake up pin 12 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " EM4WU[11] ,EM4 wake up pin 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,EM4 wake up pin 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,EM4 wake up pin 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,EM4 wake up pin 8 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " EM4WU[7] ,EM4 wake up pin 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,EM4 wake up pin 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,EM4 wake up pin 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,EM4 wake up pin 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " EM4WU[3] ,EM4 wake up pin 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,EM4 wake up pin 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,EM4 wake up pin 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,EM4 wake up pin 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " EXT[15] ,External pin 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,External pin 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,External pin 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,External pin 12 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " EXT[11] ,External pin 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,External pin 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,External pin 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,External pin 8 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " EXT[7] ,External pin 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,External pin 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,External pin 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,External pin 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " EXT[3] ,External pin 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,External pin 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,External pin 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,External pin 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EM4WUEN,EM4 Wake Up Enable Register"
|
|
bitfld.long 0x04 31. " EM4WUEN[15] ,EM4 wake up pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [14] ,EM4 wake up pin 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [13] ,EM4 wake up pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [12] ,EM4 wake up pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " EM4WUEN[11] ,EM4 wake up pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [10] ,EM4 wake up pin 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [9] ,EM4 wake up pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [8] ,EM4 wake up pin 8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " EM4WUEN[7] ,EM4 wake up pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,EM4 wake up pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,EM4 wake up pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,EM4 wake up pin 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " EM4WUEN[3] ,EM4 wake up pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,EM4 wake up pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,EM4 wake up pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,EM4 wake up pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x440++0x07
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 20. " ETMTD3PEN ,ETM trace data pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ETMTD2PEN ,ETM trace data pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ETMTD1PEN ,ETM trace data pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ETMTD0PEN ,ETM trace data pin 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " ETMTCLKPEN ,ETM trace clock pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SWVPEN ,Serial wire viewer output pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TDIPEN ,JTAG test debug input pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TDOPEN ,JTAG test debug output pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SWDIOTMSPEN ,Serial wire data and JTAG test mode select pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWCLKTCKPEN ,Serial wire clock and JTAG test clock pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 6.--11. " ETMLOC ,ETM pins location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x04 0.--5. " SWVLOC ,SWV pins location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
group.long 0x450++0x07
|
|
line.long 0x00 "INSENSE,Input Sense Register"
|
|
bitfld.long 0x00 1. " EM4WU ,EM4WU interrupt sense enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT ,Interrupt sense enable" "Disabled,Enabled"
|
|
line.long 0x04 "LOCK,Configuration Lock Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOCKKEY ,Configuration lock key"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
tree "GPIO PA"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 20.--23. " MODE[5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x0+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 8.--11. " MODE[10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 10. " DOUT[10] ,Pin 10 data out " "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 10. " DOUTTGL[10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 10. " DIN[10] ,Pin 10 data in " "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 10. " PINLOCKN[10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 10. " OVTDIS[10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
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bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PB"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x30+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x30+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 24.--27. " MODE[14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 14. " DOUT[14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " DOUT[11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " DOUT[7] ,Pin 7 data out " "Low,High"
|
|
newline
|
|
wgroup.long (0x30+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 14. " DOUTTGL[14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " DOUTTGL[11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " DOUTTGL[7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
newline
|
|
rgroup.long (0x30+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 14. " DIN[14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " DIN[11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " DIN[7] ,Pin 7 data in " "Low,High"
|
|
newline
|
|
group.long (0x30+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 14. " PINLOCKN[14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " PINLOCKN[11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " PINLOCKN[7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
newline
|
|
group.long (0x30+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 14. " OVTDIS[14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " OVTDIS[11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " OVTDIS[7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
newline
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x30+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x30+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x30+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x30+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PC"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x60+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x60+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
bitfld.long 0x00 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
bitfld.long 0x00 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x00 16.--19. " [12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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newline
|
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bitfld.long 0x00 12.--15. " MODE[11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x00 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x00 4.--7. " [9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
newline
|
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line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 15. " DOUT[15] ,Pin 15 data out " "Low,High"
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bitfld.long 0x04 14. " [14] ,Pin 14 data out " "Low,High"
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bitfld.long 0x04 13. " [13] ,Pin 13 data out " "Low,High"
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bitfld.long 0x04 12. " [12] ,Pin 12 data out " "Low,High"
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newline
|
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bitfld.long 0x04 11. " DOUT[11] ,Pin 11 data out " "Low,High"
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bitfld.long 0x04 10. " [10] ,Pin 10 data out " "Low,High"
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bitfld.long 0x04 9. " [9] ,Pin 9 data out " "Low,High"
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|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
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|
newline
|
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bitfld.long 0x04 7. " DOUT[7] ,Pin 7 data out " "Low,High"
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|
bitfld.long 0x04 6. " [6] ,Pin 6 data out " "Low,High"
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bitfld.long 0x04 5. " [5] ,Pin 5 data out " "Low,High"
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bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
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newline
|
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bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
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bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
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bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
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|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
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|
wgroup.long (0x60+0x18)++0x03
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|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
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bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 12. " [12] ,Pin 12 data out toggle " "No effect,Toggle"
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newline
|
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bitfld.long 0x00 11. " DOUTTGL[11] ,Pin 11 data out toggle " "No effect,Toggle"
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|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 9. " [9] ,Pin 9 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
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|
newline
|
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bitfld.long 0x00 7. " DOUTTGL[7] ,Pin 7 data out toggle " "No effect,Toggle"
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|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 5. " [5] ,Pin 5 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
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|
newline
|
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bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
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|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
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bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
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rgroup.long (0x60+0x1C)++0x03
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|
line.long 0x00 "DIN,Port Data In Register"
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bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
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bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
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bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
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bitfld.long 0x00 12. " [12] ,Pin 12 data in " "Low,High"
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newline
|
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bitfld.long 0x00 11. " DIN[11] ,Pin 11 data in " "Low,High"
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bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
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|
bitfld.long 0x00 9. " [9] ,Pin 9 data in " "Low,High"
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bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
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|
newline
|
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bitfld.long 0x00 7. " DIN[7] ,Pin 7 data in " "Low,High"
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bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
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bitfld.long 0x00 5. " [5] ,Pin 5 data in " "Low,High"
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bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
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newline
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bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
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bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
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bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
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bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
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group.long (0x60+0x20)++0x03
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line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
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bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
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bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
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bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
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bitfld.long 0x00 12. " [12] ,Pin 12 unlock " "Locked,Unlocked"
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newline
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bitfld.long 0x00 11. " PINLOCKN[11] ,Pin 11 unlock " "Locked,Unlocked"
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bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
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bitfld.long 0x00 9. " [9] ,Pin 9 unlock " "Locked,Unlocked"
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bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
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newline
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bitfld.long 0x00 7. " PINLOCKN[7] ,Pin 7 unlock " "Locked,Unlocked"
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bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
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bitfld.long 0x00 5. " [5] ,Pin 5 unlock " "Locked,Unlocked"
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bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
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newline
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bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
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bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
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bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
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bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
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group.long (0x60+0x28)++0x03
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line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
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bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 12. " [12] ,Pin 12 disable over voltage capability " "No,Yes"
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newline
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bitfld.long 0x00 11. " OVTDIS[11] ,Pin 11 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 9. " [9] ,Pin 9 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
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newline
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bitfld.long 0x00 7. " OVTDIS[7] ,Pin 7 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 5. " [5] ,Pin 5 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
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newline
|
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bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
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bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
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else
|
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group.long 0x60++0x0F
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line.long 0x00 "CTRL,Port Control Register"
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bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
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bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
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bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
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newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
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bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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newline
|
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bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
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bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
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bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
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bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x60+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x60+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x60+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PD"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0x90+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0x90+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 0.--3. " MODE[8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 8. " DOUT[8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " DOUT[7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 data out " "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x90+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 8. " DOUTTGL[8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " DOUTTGL[7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x90+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 8. " DIN[8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " DIN[7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x90+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 8. " PINLOCKN[8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " PINLOCKN[7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x90+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 8. " OVTDIS[8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " OVTDIS[7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0x90+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0x90+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0x90+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0x90+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PE"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0xC0+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x00 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 16.--19. " [12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 data out " "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " DOUT[11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 data out " "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 data out " "Low,High"
|
|
newline
|
|
wgroup.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " DOUTTGL[11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
newline
|
|
rgroup.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " DIN[11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
newline
|
|
group.long (0xC0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " PINLOCKN[11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
newline
|
|
group.long (0xC0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " OVTDIS[11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
newline
|
|
else
|
|
group.long 0xC0++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0xC0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0xC0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PF"
|
|
width 9.
|
|
sif cpuis("EFM32GG11B1*")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
group.long (0xF0+0x04)++0x03
|
|
line.long 0x00 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x00 20.--23. " MODE[5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
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|
bitfld.long 0x00 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
group.long (0xF0+0x08)++0x07
|
|
line.long 0x00 "MODEH,Port Pin Mode High Register"
|
|
newline
|
|
line.long 0x04 "DOUT,Port Data Out Register"
|
|
bitfld.long 0x04 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " DOUT[3] ,Pin 3 data out " "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0xF0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " DOUTTGL[3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0xF0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " DIN[3] ,Pin 3 data in " "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0xF0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " PINLOCKN[3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0xF0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " OVTDIS[3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
else
|
|
group.long 0xF0++0x0F
|
|
line.long 0x00 "CTRL,Port Control Register"
|
|
bitfld.long 0x00 28. " DINDISALT ,Alternate data in disable" "No,Yes"
|
|
bitfld.long 0x00 20.--22. " SLEWRATEALT ,Alternate slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " DRIVESTRENGTHALT ,Alternate drive strength for port" "Strong,Weak"
|
|
newline
|
|
bitfld.long 0x00 12. " DINDIS ,Data in disable" "No,Yes"
|
|
bitfld.long 0x00 4.--6. " SLEWRATE ,Slewrate limit for port" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DRIVESTRENGTH ,Drive strength for port" "Strong,Weak"
|
|
newline
|
|
line.long 0x04 "MODEL,Port Pin Mode Low Register"
|
|
bitfld.long 0x04 28.--31. " MODE[7] ,Pin 7 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 24.--27. " [6] ,Pin 6 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 20.--23. " [5] ,Pin 5 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 16.--19. " [4] ,Pin 4 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " MODE[3] ,Pin 3 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 8.--11. " [2] ,Pin 2 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 4.--7. " [1] ,Pin 1 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x04 0.--3. " [0] ,Pin 0 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
line.long 0x08 "MODEH,Port Pin Mode High Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x08 28.--31. " MODE[15] ,Pin 15 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 24.--27. " [14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x08 24.--27. " MODE[14] ,Pin 14 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 20.--23. " [13] ,Pin 13 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x08 16.--19. " MODE[12] ,Pin 12 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 12.--15. " [11] ,Pin 11 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 8.--11. " [10] ,Pin 10 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 4.--7. " MODE[9] ,Pin 9 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
bitfld.long 0x08 0.--3. " [8] ,Pin 8 mode" "Disabled,INPUT,INPUTPULL,INPUTPULLFILTER,PUSHPULL,PUSHPULLALT,WIREDOR,WIREDORPULLDOWN,WIREDAND,WIREDANDFILTER,WIREDANDPULLUP,WIREDANDPULLUPFILTER,WIREDANDALT,WIREDANDALTFILTER,WIREDANDALTPULLUP,WIREDANDALTPULLUPFILTER"
|
|
newline
|
|
line.long 0x0C "DOUT,Port Data Out Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x0C 15. " DOUT[15] ,Pin 15 data out " "Low,High"
|
|
bitfld.long 0x0C 14. " [14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x0C 14. " DOUT[14] ,Pin 14 data out " "Low,High"
|
|
bitfld.long 0x0C 13. " [13] ,Pin 13 data out " "Low,High"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x0C 12. " DOUT[12] ,Pin 12 data out " "Low,High"
|
|
bitfld.long 0x0C 11. " [11] ,Pin 11 data out " "Low,High"
|
|
bitfld.long 0x0C 10. " [10] ,Pin 10 data out " "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 9. " DOUT[9] ,Pin 9 data out " "Low,High"
|
|
bitfld.long 0x0C 8. " [8] ,Pin 8 data out " "Low,High"
|
|
bitfld.long 0x0C 7. " [7] ,Pin 7 data out " "Low,High"
|
|
bitfld.long 0x0C 6. " [6] ,Pin 6 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 5. " DOUT[5] ,Pin 5 data out " "Low,High"
|
|
bitfld.long 0x0C 4. " [4] ,Pin 4 data out " "Low,High"
|
|
bitfld.long 0x0C 3. " [3] ,Pin 3 data out " "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 2. " DOUT[2] ,Pin 2 data out " "Low,High"
|
|
bitfld.long 0x0C 1. " [1] ,Pin 1 data out " "Low,High"
|
|
bitfld.long 0x0C 0. " [0] ,Pin 0 data out " "Low,High"
|
|
wgroup.long (0xF0+0x18)++0x03
|
|
line.long 0x00 "DOUTTGL,Port Data Out Toggle Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " DOUTTGL[15] ,Pin 15 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " DOUTTGL[14] ,Pin 14 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data out toggle " "No effect,Toggle"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " DOUTTGL[12] ,Pin 12 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data out toggle " "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " DOUTTGL[9] ,Pin 9 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " DOUTTGL[5] ,Pin 5 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data out toggle " "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " DOUTTGL[2] ,Pin 2 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data out toggle " "No effect,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data out toggle " "No effect,Toggle"
|
|
rgroup.long (0xF0+0x1C)++0x03
|
|
line.long 0x00 "DIN,Port Data In Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " DIN[15] ,Pin 15 data in " "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " DIN[14] ,Pin 14 data in " "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 data in " "Low,High"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " DIN[12] ,Pin 12 data in " "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 data in " "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 data in " "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " DIN[9] ,Pin 9 data in " "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 data in " "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 data in " "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " DIN[5] ,Pin 5 data in " "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 data in " "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 data in " "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DIN[2] ,Pin 2 data in " "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 data in " "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 data in " "Low,High"
|
|
group.long (0xF0+0x20)++0x03
|
|
line.long 0x00 "PINLOCK,Port Unlocked Pins Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " PINLOCKN[15] ,Pin 15 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " PINLOCKN[14] ,Pin 14 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 unlock " "Locked,Unlocked"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " PINLOCKN[12] ,Pin 12 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 unlock " "Locked,Unlocked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " PINLOCKN[9] ,Pin 9 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 5. " PINLOCKN[5] ,Pin 5 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 unlock " "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 2. " PINLOCKN[2] ,Pin 2 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 unlock " "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 unlock " "Locked,Unlocked"
|
|
group.long (0xF0+0x28)++0x03
|
|
line.long 0x00 "OVTDIS,Over Voltage Disable for All Modes"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 15. " OVTDIS[15] ,Pin 15 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
elif cpuis("EFM32GG11B5*")
|
|
bitfld.long 0x00 14. " OVTDIS[14] ,Pin 14 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 disable over voltage capability " "No,Yes"
|
|
newline
|
|
endif
|
|
sif !cpuis("EFM32GG11B3*")
|
|
bitfld.long 0x00 12. " OVTDIS[12] ,Pin 12 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 disable over voltage capability " "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " OVTDIS[9] ,Pin 9 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " OVTDIS[5] ,Pin 5 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 disable over voltage capability " "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " OVTDIS[2] ,Pin 2 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 disable over voltage capability " "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 disable over voltage capability " "No,Yes"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
width 13.
|
|
tree "Common"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "EXTIPSELL,External Interrupt Port Select Low Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x00 28.--31. " EXTIPSEL[7] ,External interrupt 7 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,External interrupt 6 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,External interrupt 5 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,External interrupt 4 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " EXTIPSEL[3] ,External interrupt 3 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,External interrupt 2 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,External interrupt 1 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,External interrupt 0 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
else
|
|
bitfld.long 0x00 28.--31. " EXTIPSEL[7] ,External interrupt 7 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,External interrupt 6 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,External interrupt 5 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,External interrupt 4 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " EXTIPSEL[3] ,External interrupt 3 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,External interrupt 2 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,External interrupt 1 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,External interrupt 0 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
endif
|
|
line.long 0x04 "EXTIPSELH,External Interrupt Port Select High Register"
|
|
sif cpuis("EFM32GG11B8*")
|
|
bitfld.long 0x04 28.--31. " EXTIPSEL[15] ,External interrupt 15 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,External interrupt 14 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,External interrupt 13 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,External interrupt 12 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. " EXTIPSEL[11] ,External interrupt 11 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,External interrupt 10 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,External interrupt 9 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,External interrupt 8 port select" "Port A,Port B,Port C,Port D,Port E,Port F,Port G,Port H,Port I,?..."
|
|
else
|
|
bitfld.long 0x04 28.--31. " EXTIPSEL[15] ,External interrupt 15 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,External interrupt 14 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,External interrupt 13 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,External interrupt 12 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. " EXTIPSEL[11] ,External interrupt 11 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,External interrupt 10 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,External interrupt 9 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,External interrupt 8 port select" "Port A,Port B,Port C,Port D,Port E,Port F,?..."
|
|
endif
|
|
line.long 0x08 "EXTIPINSELL,External Interrupt Pin Select Low Register"
|
|
bitfld.long 0x08 28.--29. " EXTIPINSEL[7] ,External interrupt 7 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 24.--25. " [6] ,External interrupt 6 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 20.--21. " [5] ,External interrupt 5 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 16.--17. " [4] ,External interrupt 4 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
newline
|
|
bitfld.long 0x08 12.--13. " EXTIPINSEL[3] ,External interrupt 3 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 8.--9. " [2] ,External interrupt 2 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 4.--5. " [1] ,External interrupt 1 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
bitfld.long 0x08 0.--1. " [0] ,External interrupt 0 pin select" "PIN4,PIN5,PIN6,PIN7"
|
|
line.long 0x0C "EXTIPINSELH,External Interrupt Pin Select High Register"
|
|
bitfld.long 0x0C 28.--29. " EXTPINSEL[15] ,External interrupt 15 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 24.--25. " [14] ,External interrupt 14 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 20.--21. " [13] ,External interrupt 13 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 16.--17. " [12] ,External interrupt 12 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
newline
|
|
bitfld.long 0x0C 12.--13. " EXTPINSEL[11] ,External interrupt 11 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 8.--9. " [10] ,External interrupt 10 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 4.--5. " [9] ,External interrupt 9 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
bitfld.long 0x0C 0.--1. " [8] ,External interrupt 8 pin select" "PIN12,PIN13,PIN14,PIN15"
|
|
line.long 0x10 "EXTIRISE,External Interrupt Rising Edge Trigger Register"
|
|
bitfld.long 0x10 15. " EXTIRISE[15] ,External interrupt 15 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " [14] ,External interrupt 14 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " [13] ,External interrupt 13 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " [12] ,External interrupt 12 rising edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 11. " EXTIRISE[11] ,External interrupt 11 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " [10] ,External interrupt 10 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " [9] ,External interrupt 9 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " [8] ,External interrupt 8 rising edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 7. " EXTIRISE[7] ,External interrupt 7 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " [6] ,External interrupt 6 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " [5] ,External interrupt 5 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " [4] ,External interrupt 4 rising edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. " EXTIRISE[3] ,External interrupt 3 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " [2] ,External interrupt 2 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " [1] ,External interrupt 1 rising edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " [0] ,External interrupt 0 rising edge trigger enable" "Disabled,Enabled"
|
|
line.long 0x14 "EXTIFALL,External Interrupt Falling Edge Trigger Register"
|
|
bitfld.long 0x14 15. " EXTIFALL[15] ,External interrupt 15 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " [14] ,External interrupt 14 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " [13] ,External interrupt 13 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " [12] ,External interrupt 12 falling edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 11. " EXTIFALL[11] ,External interrupt 11 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " [10] ,External interrupt 10 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " [9] ,External interrupt 9 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " [8] ,External interrupt 8 falling edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 7. " EXTIFALL[7] ,External interrupt 7 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " [6] ,External interrupt 6 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " [5] ,External interrupt 5 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " [4] ,External interrupt 4 falling edge trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " EXTIFALL[3] ,External interrupt 3 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " [2] ,External interrupt 2 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " [1] ,External interrupt 1 falling edge trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " [0] ,External interrupt 0 falling edge trigger enable" "Disabled,Enabled"
|
|
line.long 0x18 "EXTILEVEL,External Interrupt Level Register"
|
|
bitfld.long 0x18 25. " EM4WU[9] ,EM4 wake up level for EM4WU9 pin" "Low,High"
|
|
bitfld.long 0x18 24. " [8] ,EM4 wake up level for EM4WU8 pin" "Low,High"
|
|
bitfld.long 0x18 23. " [7] ,EM4 wake up level for EM4WU7 pin" "Low,High"
|
|
bitfld.long 0x18 22. " [6] ,EM4 wake up level for EM4WU6 pin" "Low,High"
|
|
newline
|
|
bitfld.long 0x18 21. " EM4WU[5] ,EM4 wake up level for EM4WU5 pin" "Low,High"
|
|
bitfld.long 0x18 20. " [4] ,EM4 wake up level for EM4WU4 pin" "Low,High"
|
|
bitfld.long 0x18 19. " [3] ,EM4 wake up level for EM4WU3 pin" "Low,High"
|
|
newline
|
|
bitfld.long 0x18 18. " EM4WU[2] ,EM4 wake up level for EM4WU2 pin" "Low,High"
|
|
bitfld.long 0x18 17. " [1] ,EM4 wake up level for EM4WU1 pin" "Low,High"
|
|
bitfld.long 0x18 16. " [0] ,EM4 wake up level for EM4WU0 pin" "Low,High"
|
|
line.long 0x1C "IF_SETCLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x1C 31. 0x20 31. 0x24 31. " EM4WU[15] ,EM4 wake up pin 15 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 30. 0x20 30. 0x24 30. " [14] ,EM4 wake up pin 14 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 29. 0x20 29. 0x24 29. " [13] ,EM4 wake up pin 13 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 28. 0x20 28. 0x24 28. " [12] ,EM4 wake up pin 12 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 27. 0x20 27. 0x24 27. " EM4WU[11] ,EM4 wake up pin 11 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 26. 0x20 26. 0x24 26. " [10] ,EM4 wake up pin 10 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 25. 0x20 25. 0x24 25. " [9] ,EM4 wake up pin 9 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 24. 0x20 24. 0x24 24. " [8] ,EM4 wake up pin 8 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 23. 0x20 23. 0x24 23. " EM4WU[7] ,EM4 wake up pin 7 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 22. 0x20 22. 0x24 22. " [6] ,EM4 wake up pin 6 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 21. 0x20 21. 0x24 21. " [5] ,EM4 wake up pin 5 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 20. 0x20 20. 0x24 20. " [4] ,EM4 wake up pin 4 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 19. 0x20 19. 0x24 19. " EM4WU[3] ,EM4 wake up pin 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 18. 0x20 18. 0x24 18. " [2] ,EM4 wake up pin 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 17. 0x20 17. 0x24 17. " [1] ,EM4 wake up pin 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 16. 0x20 16. 0x24 16. " [0] ,EM4 wake up pin 0 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 15. 0x20 15. 0x24 15. " EXT[15] ,External pin 15 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 14. 0x20 14. 0x24 14. " [14] ,External pin 14 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 13. 0x20 13. 0x24 13. " [13] ,External pin 13 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 12. 0x20 12. 0x24 12. " [12] ,External pin 12 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 11. 0x20 11. 0x24 11. " EXT[11] ,External pin 11 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 10. 0x20 10. 0x24 10. " [10] ,External pin 10 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 9. 0x20 9. 0x24 9. " [9] ,External pin 9 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 8. 0x20 8. 0x24 8. " [8] ,External pin 8 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 7. 0x20 7. 0x24 7. " EXT[7] ,External pin 7 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 6. 0x20 6. 0x24 6. " [6] ,External pin 6 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 5. 0x20 5. 0x24 5. " [5] ,External pin 5 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 4. 0x20 4. 0x24 4. " [4] ,External pin 4 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x1C 3. 0x20 3. 0x24 3. " EXT[3] ,External pin 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 2. 0x20 2. 0x24 2. " [2] ,External pin 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 1. 0x20 1. 0x24 1. " [1] ,External pin 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x1C 0. 0x20 0. 0x24 0. " [0] ,External pin 0 interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x428++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " EM4WU[15] ,EM4 wake up pin 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,EM4 wake up pin 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,EM4 wake up pin 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,EM4 wake up pin 12 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " EM4WU[11] ,EM4 wake up pin 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,EM4 wake up pin 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,EM4 wake up pin 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,EM4 wake up pin 8 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " EM4WU[7] ,EM4 wake up pin 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,EM4 wake up pin 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,EM4 wake up pin 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,EM4 wake up pin 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " EM4WU[3] ,EM4 wake up pin 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,EM4 wake up pin 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,EM4 wake up pin 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,EM4 wake up pin 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " EXT[15] ,External pin 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,External pin 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,External pin 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,External pin 12 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " EXT[11] ,External pin 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,External pin 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,External pin 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,External pin 8 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " EXT[7] ,External pin 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,External pin 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,External pin 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,External pin 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " EXT[3] ,External pin 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,External pin 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,External pin 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,External pin 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EM4WUEN,EM4 Wake Up Enable Register"
|
|
bitfld.long 0x04 31. " EM4WUEN[15] ,EM4 wake up pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [14] ,EM4 wake up pin 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [13] ,EM4 wake up pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [12] ,EM4 wake up pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " EM4WUEN[11] ,EM4 wake up pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [10] ,EM4 wake up pin 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [9] ,EM4 wake up pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [8] ,EM4 wake up pin 8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " EM4WUEN[7] ,EM4 wake up pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,EM4 wake up pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,EM4 wake up pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,EM4 wake up pin 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " EM4WUEN[3] ,EM4 wake up pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,EM4 wake up pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,EM4 wake up pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,EM4 wake up pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x440++0x07
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 20. " ETMTD3PEN ,ETM trace data pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ETMTD2PEN ,ETM trace data pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ETMTD1PEN ,ETM trace data pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ETMTD0PEN ,ETM trace data pin 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " ETMTCLKPEN ,ETM trace clock pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SWVPEN ,Serial wire viewer output pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TDIPEN ,JTAG test debug input pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TDOPEN ,JTAG test debug output pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SWDIOTMSPEN ,Serial wire data and JTAG test mode select pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWCLKTCKPEN ,Serial wire clock and JTAG test clock pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Routing Location Register"
|
|
bitfld.long 0x04 6.--11. " ETMLOC ,ETM pins location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x04 0.--5. " SWVLOC ,SWV pins location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
group.long 0x450++0x07
|
|
line.long 0x00 "INSENSE,Input Sense Register"
|
|
bitfld.long 0x00 1. " EM4WU ,EM4WU interrupt sense enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT ,Interrupt sense enable" "Disabled,Enabled"
|
|
line.long 0x04 "LOCK,Configuration Lock Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOCKKEY ,Configuration lock key"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "EBI (External Bus Interface)"
|
|
base ad:0x4000B000
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CTRL,EBI Control Register"
|
|
bitfld.long 0x00 31. " ALTMAP ,Alternative address map enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ITS ,Individual timing set, line polarity and mode definition enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BL3 ,Byte lane enable for bank 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " BL2 ,Byte lane enable for bank 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BL1 ,Byte lane enable for bank 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " BL ,Byte lane enable for bank 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " ARDYTO3DIS ,ARDY Timeout disable for bank 3" "No,Yes"
|
|
bitfld.long 0x00 22. " ARDY3EN ,ARDY enable for bank 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ARDYTO2DIS ,ARDY timeout disable for bank 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " ARDY2EN ,ARDY enable for bank 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ARDYTO1DIS ,ARDY timeout disable for bank 1" "No,Yes"
|
|
bitfld.long 0x00 18. " ARDY1EN ,ARDY enable for bank 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " ARDYTODIS ,ARDY timeout disable" "No,Yes"
|
|
bitfld.long 0x00 16. " ARDYEN ,ARDY enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NOIDLE3 ,No idle cycle insertion on bank 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " NOIDLE2 ,No idle cycle insertion on bank 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOIDLE1 ,No idle cycle insertion on bank 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " NOIDLE ,No idle cycle insertion on bank 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " BANK3EN ,Bank 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BANK2EN ,Bank 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BANK1EN ,Bank 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " BANK0EN ,Bank 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " MODE3 ,Mode 3" "D8A8,D16A16ALE,D8A24ALE,D16"
|
|
bitfld.long 0x00 4.--5. " MODE2 ,Mode 2" "D8A8,D16A16ALE,D8A24ALE,D16"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " MODE1 ,Mode 1" "D8A8,D16A16ALE,D8A24ALE,D16"
|
|
bitfld.long 0x00 0.--1. " MODE ,Mode" "D8A8,D16A16ALE,D8A24ALE,D16"
|
|
line.long 0x04 "ADDRTIMIN,Address Timing Register"
|
|
bitfld.long 0x04 28. " HALFALE ,Half cycle ALE strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--10. " ADDRHOLD ,Address hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x04 0.--2. " ADDRSETUP ,Address setup time" "1 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x08 "RDTIMING,Read Timing Register"
|
|
bitfld.long 0x08 30. " PAGEMODE ,Page mode access enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " PREFETCH ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HALFRE ,Half cycle REn strobe duration enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " RDHOLD ,Read hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RDSTRB ,Read strobe time"
|
|
bitfld.long 0x08 0.--2. " RDSETUP ,Read setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x0C "WRTIMING,Write Timing Register"
|
|
bitfld.long 0x0C 29. " WBUFDIS ,Write buffer disable" "No,Yes"
|
|
bitfld.long 0x0C 28. " HALFWE ,Half cycle WEn strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--18. " WRHOLD ,Write hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--14. 1. " WRSTRB ,Write strobe time"
|
|
bitfld.long 0x0C 0.--2. " WRSETUP ,Write setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x10 "POLARITY,Polarity Register"
|
|
bitfld.long 0x10 5. " BLPOL ,BL polarity" "Active low,Active High"
|
|
bitfld.long 0x10 4. " ARDYPOL ,ARDY polarity" "Active low,Active High"
|
|
bitfld.long 0x10 3. " ALEPOL ,Address latch polarity" "Active low,Active High"
|
|
newline
|
|
bitfld.long 0x10 2. " WEPOL ,Write enable polarity" "Active low,Active High"
|
|
bitfld.long 0x10 1. " REPOL ,Read enable polarity" "Active low,Active High"
|
|
bitfld.long 0x10 0. " CSPOL ,Chip select polarity" "Active low,Active High"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "ADDRTIMING1,Address Timing Register 1"
|
|
bitfld.long 0x00 28. " HALFALE ,Half cycle ALE strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " ADDRHOLD ,Address hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " ADDRSETUP ,Address setup time" "1 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x04 "RDTIMING1,Read Timing Register 1"
|
|
bitfld.long 0x04 30. " PAGEMODE ,Page mode access enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " PREFETCH ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " HALFRE ,Half cycle REn strobe duration enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " RDHOLD ,Read hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
hexmask.long.byte 0x04 8.--14. 1. " RDSTRB ,Read strobe time"
|
|
bitfld.long 0x04 0.--2. " RDSETUP ,Read setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x08 "WRTIMING1,Write Timing Register 1"
|
|
bitfld.long 0x08 29. " WBUFDIS ,Write buffer disable" "No,Yes"
|
|
bitfld.long 0x08 28. " HALFWE ,Half cycle WEn strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " WRHOLD ,Write hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--14. 1. " WRSTRB ,Write strobe time"
|
|
bitfld.long 0x08 0.--2. " WRSETUP ,Write setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x0C "POLARITY1,Polarity Register 1"
|
|
bitfld.long 0x0C 5. " BLPOL ,BL polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 4. " ARDYPOL ,ARDY polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 3. " ALEPOL ,Address latch polarity" "Active low,Active High"
|
|
newline
|
|
bitfld.long 0x0C 2. " WEPOL ,Write enable polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 1. " REPOL ,Read enable polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 0. " CSPOL ,Chip select polarity" "Active low,Active High"
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "ADDRTIMING2,Address Timing Register 2"
|
|
bitfld.long 0x00 28. " HALFALE ,Half cycle ALE strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " ADDRHOLD ,Address hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " ADDRSETUP ,Address setup time" "1 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x04 "RDTIMING2,Read Timing Register 2"
|
|
bitfld.long 0x04 30. " PAGEMODE ,Page mode access enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " PREFETCH ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " HALFRE ,Half cycle REn strobe duration enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " RDHOLD ,Read hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
hexmask.long.byte 0x04 8.--14. 1. " RDSTRB ,Read strobe time"
|
|
bitfld.long 0x04 0.--2. " RDSETUP ,Read setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x08 "WRTIMING2,Write Timing Register 2"
|
|
bitfld.long 0x08 29. " WBUFDIS ,Write buffer disable" "No,Yes"
|
|
bitfld.long 0x08 28. " HALFWE ,Half cycle WEn strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " WRHOLD ,Write hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--14. 1. " WRSTRB ,Write strobe time"
|
|
bitfld.long 0x08 0.--2. " WRSETUP ,Write setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x0C "POLARITY2,Polarity Register 2"
|
|
bitfld.long 0x0C 5. " BLPOL ,BL polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 4. " ARDYPOL ,ARDY polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 3. " ALEPOL ,Address latch polarity" "Active low,Active High"
|
|
newline
|
|
bitfld.long 0x0C 2. " WEPOL ,Write enable polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 1. " REPOL ,Read enable polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 0. " CSPOL ,Chip select polarity" "Active low,Active High"
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "ADDRTIMING3,Address Timing Register 3"
|
|
bitfld.long 0x00 28. " HALFALE ,Half cycle ALE strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " ADDRHOLD ,Address hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " ADDRSETUP ,Address setup time" "1 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x04 "RDTIMING3,Read Timing Register 3"
|
|
bitfld.long 0x04 30. " PAGEMODE ,Page mode access enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " PREFETCH ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " HALFRE ,Half cycle REn strobe duration enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " RDHOLD ,Read hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
hexmask.long.byte 0x04 8.--14. 1. " RDSTRB ,Read strobe time"
|
|
bitfld.long 0x04 0.--2. " RDSETUP ,Read setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x08 "WRTIMING3,Write Timing Register 3"
|
|
bitfld.long 0x08 29. " WBUFDIS ,Write buffer disable" "No,Yes"
|
|
bitfld.long 0x08 28. " HALFWE ,Half cycle WEn strobe duration enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " WRHOLD ,Write hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--14. 1. " WRSTRB ,Write strobe time"
|
|
bitfld.long 0x08 0.--2. " WRSETUP ,Write setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
line.long 0x0C "POLARITY3,Polarity Register 3"
|
|
bitfld.long 0x0C 5. " BLPOL ,BL polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 4. " ARDYPOL ,ARDY polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 3. " ALEPOL ,Address latch polarity" "Active low,Active High"
|
|
newline
|
|
bitfld.long 0x0C 2. " WEPOL ,Write enable polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 1. " REPOL ,Read enable polarity" "Active low,Active High"
|
|
bitfld.long 0x0C 0. " CSPOL ,Chip select polarity" "Active low,Active High"
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "PAGECTRL,Page Control Register"
|
|
hexmask.long.byte 0x00 20.--26. 1. " KEEPOPEN ,Maximum page open time"
|
|
bitfld.long 0x00 8.--11. " RDPA ,Page read access time" "1 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 4. " INCHIT ,Intrapage hit only on incremental addresses" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " PAGELEN ,Page length" "4 members,8 members,16 members,32 members"
|
|
line.long 0x04 "NANDCTRL,NAND Control Register"
|
|
bitfld.long 0x04 4.--5. " BANKSEL ,NAND flash bank" "Bank 0,Bank 1,Bank 2,Bank 3"
|
|
bitfld.long 0x04 0. " EN ,NAND flash control enable" "Disabled,Enabled"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 2. " ECCCLEAR ,Error correction code clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ECCSTOP ,Error correction code generation stop" "No effect,Stop"
|
|
bitfld.long 0x00 0. " ECCSTART ,Error correction code generation start" "No effect,Start"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 13. " TFTDDEMPTY ,TFTDD register is empty" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " DDACT ,EBI busy with direct drive transactions" "Not busy,Busy"
|
|
bitfld.long 0x00 10. " TFTPIXELFULL ,TFTPIXEL0 is full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 9. " TFTPIXEL1EMPTY ,TFTPIXEL1 is empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TFTPIXEL0EMPTY ,TFTPIXEL0 is empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 4. " ECCACT ,EBI ECC generation active" "Not generated,Generated"
|
|
bitfld.long 0x00 0. " AHBACT ,EBI busy with AHB transaction" "Not busy,Busy"
|
|
line.long 0x04 "ECCPARITY,ECC parity register"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "TFTCTRL,TFT Control Register"
|
|
bitfld.long 0x00 22.--23. " ALIASBANK ,Graphic bank select aliasing" "Bank 0,Bank 1,Bank 2,Bank 3"
|
|
bitfld.long 0x00 20.--21. " BANKSEL ,Graphics bank" "Bank 0,Bank 1,Bank 2,Bank 3"
|
|
bitfld.long 0x00 19. " ALIASBANKEN ,Alias to graphics bank enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " WIDTH ,TFT transaction width" "Byte,Halfword,?..."
|
|
bitfld.long 0x00 12. " COLOR1SRC ,Masking/alpha blending color1 source" "MEM,PIXEL1"
|
|
bitfld.long 0x00 10.--11. " INTERLEAVE ,Interleave mode" "Unlimited,ONEPERDCLK,PORCH,?..."
|
|
newline
|
|
bitfld.long 0x00 9. " FBCTRIG ,TFT frame base copy trigger" "VSYNC,HSYNC"
|
|
bitfld.long 0x00 8. " SHIFTDCLKEN ,TFT DCLK shift enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--5. " MASKBLEND ,TFT mask and blend mode" "Disabled,IMASK,IALPHA,IMASKIALPHA,EFBMASK,EFBALPHA,EFBMASKALPHA,IFBMASK,IFBALPHA,IFBMASKALPHA,?..."
|
|
bitfld.long 0x00 0.--1. " DD ,TFT direct drive mode" "Disabled,Internal,External,?..."
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "TFTSTATUS,TFT Status Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " VCNT ,Vertical count"
|
|
hexmask.long.word 0x00 0.--10. 1. " HCNT ,Horizontal count"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "TFTCOLORFORMAT,Color Format Register"
|
|
bitfld.long 0x00 8.--9. " PIXEL1FORMAT ,Source and destination pixel color format" "RGB555,RGB565,RGB666,RGB888"
|
|
bitfld.long 0x00 0.--2. " PIXEL0FORMAT ,Sprite pixel color format" "ARGB0555,ARGB0565,ARGB0666,ARGB0888,ARGB5555,ARGB6565,ARGB6666,ARGB8888"
|
|
line.long 0x04 "TFTFRAMEBASE,TFT Frame Base Register"
|
|
hexmask.long 0x04 0.--27. 1. " FRAMEBASE ,Frame base address"
|
|
group.long 0x70++0x27
|
|
line.long 0x00 "TFTSTRIDE,TFT Stride Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " HSTRIDE ,Horizontal stride"
|
|
line.long 0x04 "TFTSIZE,TFT Size Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " VSZ ,Vertical size (excluding porches)"
|
|
hexmask.long.word 0x04 0.--9. 1. " HSZ ,Horizontal size (excluding porches)"
|
|
line.long 0x08 "TFTHPORCH,TFT Horizontal Porch Register"
|
|
bitfld.long 0x08 28.--29. " HSYNCSTART ,HSync start delay" "0,1,2,3"
|
|
hexmask.long.byte 0x08 18.--25. 1. " HBPORCH ,Horizontal back porch size"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " HFPORCH ,Horizontal front porch size"
|
|
hexmask.long.byte 0x08 0.--6. 1. " HSYNC ,Horizontal synchronization pulse width"
|
|
line.long 0x0C "TFTVPORCH,TFT Vertical Porch Register"
|
|
hexmask.long.word 0x0C 20.--31. 1. " VBPORCH ,Vertical back porch size"
|
|
hexmask.long.word 0x0C 8.--19. 1. " VFPORCH ,Vertical front porch size"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " VSYNC ,Vertical synchronization pulse width"
|
|
line.long 0x10 "TFTTIMING,TFT Timing Register"
|
|
bitfld.long 0x10 28.--30. " TFTHOLD ,TFT hold time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x10 24.--26. " TFTSETUP ,TFT setup time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
newline
|
|
hexmask.long.word 0x10 12.--23. 1. " TFTSTART ,TFT direct drive transaction start"
|
|
hexmask.long.word 0x10 0.--11. 1. " DCLKPERIOD ,TFT direct drive transaction (DCLK) period"
|
|
line.long 0x14 "TFTPOLARITY,TFT Polarity Register"
|
|
bitfld.long 0x14 4. " VSYNCPOL ,VSYNC polarity" "Active low,Active High"
|
|
bitfld.long 0x14 3. " HSYNCPOL ,Address latch polarity" "Active low,Active High"
|
|
bitfld.long 0x14 2. " DATAENPOL ,TFT DATAEN polarity" "Active low,Active High"
|
|
newline
|
|
bitfld.long 0x14 1. " DCLKPOL ,TFT DCLK polarity" "Active falling,Active rising"
|
|
bitfld.long 0x14 0. " CSPOL ,TFT chip select polarity" "Active low,Active High"
|
|
line.long 0x18 "TFTDD,TFT Direct Drive Data Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " DATA ,TFT direct drive data from internal memory"
|
|
line.long 0x1C "TFTALPHA,TFT Alpha Blending Register"
|
|
hexmask.long.word 0x1C 0.--8. 1. " ALPHA ,TFT alpha blending factor"
|
|
line.long 0x20 "TFTPIXEL0,TFT Pixel 0 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " DATA ,RGB data"
|
|
line.long 0x24 "TFTPIXEL1,TFT Pixel 1 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " DATA ,RGB data"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TFTPIXEL,TFT Alpha Blending Result Pixel Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Alpha blending result"
|
|
group.long 0x9C++0x07
|
|
line.long 0x00 "TFTMASK,TFT Masking Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TFTMASK ,TFT mask value"
|
|
line.long 0x04 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 9. 0x08 9. 0x0C 9. " TFTPIXELOF ,TFTPIXEL register overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x08 8. 0x0C 8. " TFTPIXELFULL ,TFTPIXEL is full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " TFTPIXEL1EMPTY ,TFTPIXEL1 is empty interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " TFTPIXEL0EMPTY ,TFTPIXEL0 is empty interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " DDJIT ,Direct drive jitter interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " DDEMPTY ,Direct drive data empty interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " VFPORCH ,Vertical front porch interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " VBPORCH ,Vertical back porch interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " HSYNC ,Horizontal sync interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " VSYNC ,Vertical sync interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0xAC++0x0F
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " TFTPIXELOF ,TFTPIXEL register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TFTPIXELFULL ,TFTPIXEL is full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TFTPIXEL1EMPTY ,TFTPIXEL1 is empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TFTPIXEL0EMPTY ,TFTPIXEL0 is empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DDJIT ,Direct drive jitter interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DDEMPTY ,Direct drive data empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VFPORCH ,Vertical front porch interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " VBPORCH ,Vertical back porch interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HSYNC ,Horizontal sync interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VSYNC ,Vertical sync interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTEPEN,I/O Routing Register"
|
|
bitfld.long 0x04 26. " CSTFTPEN ,CSTFT pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DATAENPEN ,DATA pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " TFTPEN ,TFT pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 18.--22. " APEN ,A pin enable" "A0,,,,,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27,A28,?..."
|
|
bitfld.long 0x04 16.--17. " ALB ,Sets the lower bound for A enabling" "A0,A8,A16,A24"
|
|
bitfld.long 0x04 12. " NANDPEN ,NANDRE and NANDWE pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " BLPEN ,BL pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ARDYPEN ,ARDY pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ALEPEN ,ALE pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CS3PEN ,CS3 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CS2PEN ,CS2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CS1PEN ,CS1 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CS0PEN ,CS0 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EBIPEN ,EBI pin enable" "Disabled,Enabled"
|
|
line.long 0x08 "ROUTELOC0,I/O Routing Location Register 0"
|
|
bitfld.long 0x08 24.--29. " TFTLOC ,TFT I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x08 16.--21. " NANDLOC ,NAND I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
newline
|
|
bitfld.long 0x08 8.--13. " CSLOC ,CS I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,?..."
|
|
bitfld.long 0x08 0.--5. " EBILOC ,EBI I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
line.long 0x0C "ROUTELOC1,I/O Routing Location Register 1"
|
|
bitfld.long 0x0C 16.--21. " RDYLOC ,RDY I/O location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,?..."
|
|
bitfld.long 0x0C 8.--13. " ALOC ,A I/O location" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x0C 0.--5. " ADLOC ,AD I/O location" "LOC0,LOC1,LOC2,?..."
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("EFM32GG11B420*")||cpuis("EFM32GG11B820*")||cpuis("EFM32GG11B840*")
|
|
tree "QSPI (Quad- and Octal-SPI Flash Controller)"
|
|
base ad:0x4001C400
|
|
width 28.
|
|
if (((per.l(ad:0x4001C400))&0x08)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,Octal-SPI Configuration Register"
|
|
rbitfld.long 0x00 31. " IDLE ,Serial interface and low level SPI pipeline is IDLE" "Not idle,Idle"
|
|
bitfld.long 0x00 30. " DUALBYTEOPCODEEN ,Dual-byte opcode mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CRCENABLE ,CRC enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " PIPELINEPHY ,Pipeline PHY mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENABLEDTRPROTOCOL ,Enable DTR protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENABLEAHBDECODER ,Enable address decoder" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19.--22. " MSTRBAUDDIV ,Master mode baud rate divisor" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 18. " ENTERXIPMODEIMM ,Enter XIP mode immediately" "Not entered,Entered"
|
|
bitfld.long 0x00 17. " ENTERXIPMODE ,Enter XIP mode on next READ" "Not entered,Entered"
|
|
newline
|
|
bitfld.long 0x00 16. " ENBAHBADDRREMAP ,Enable address remapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WRPROTFLASH ,Write protect flash pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " PERIPHCSLINES ,Peripheral chip select lines" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. " PERIPHSELDEC ,Peripheral select decode" "One CS,Two CS"
|
|
bitfld.long 0x00 8. " ENBLEGACYIPMODE ,Legacy IP mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENBDIRACCCTLR ,Enable direct access controller" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " PHYMODEENABLE ,PHY mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SELCLKPHASE ,Clock phase CPHA" "Rising,Falling"
|
|
bitfld.long 0x00 1. " SELCLKPOL ,Clock polarity CPOL" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " ENBSPI ,QSPI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,Octal-SPI Configuration Register"
|
|
rbitfld.long 0x00 31. " IDLE ,Serial interface and low level SPI pipeline is IDLE" "Not idle,Idle"
|
|
bitfld.long 0x00 30. " DUALBYTEOPCODEEN ,Dual-byte opcode mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CRCENABLE ,CRC enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " PIPELINEPHY ,Pipeline PHY mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENABLEDTRPROTOCOL ,Enable DTR protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENABLEAHBDECODER ,Enable address decoder" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " ENTERXIPMODEIMM ,Enter XIP mode immediately" "Not entered,Entered"
|
|
bitfld.long 0x00 17. " ENTERXIPMODE ,Enter XIP mode on next READ" "Not entered,Entered"
|
|
bitfld.long 0x00 16. " ENBAHBADDRREMAP ,Enable address remapping" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " WRPROTFLASH ,Write protect flash pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " PERIPHCSLINES ,Peripheral chip select lines" "0,1,2,3"
|
|
bitfld.long 0x00 9. " PERIPHSELDEC ,Peripheral select decode" "One CS,Two CS"
|
|
newline
|
|
bitfld.long 0x00 8. " ENBLEGACYIPMODE ,Legacy IP mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENBDIRACCCTLR ,Enable direct access controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PHYMODEENABLE ,PHY mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SELCLKPHASE ,Clock phase CPHA" "Rising,Falling"
|
|
bitfld.long 0x00 1. " SELCLKPOL ,Clock polarity CPOL" "Low,High"
|
|
bitfld.long 0x00 0. " ENBSPI ,QSPI enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x4001C400+0x04))&0x300)==0x00)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "DEVINSTRRDCONFIG,Device Read Instruction Configuration Register"
|
|
bitfld.long 0x00 24.--28. " DUMMYRDCLKCYCLES ,Dummy read clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " MODEBITENABLE ,Mode bit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " DATAXFERTYPEEXTMODE ,Data transfer type for standard SPI modes" "Single mode,Dual mode,Quad mode,Octal mode"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " ADDRXFERTYPESTDMODE ,Address transfer type for standard SPI modes" "Single mode,Dual mode,Quad mode,Octal mode"
|
|
bitfld.long 0x00 10. " DDREN ,DDR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSTRTYPE ,Instruction type" "Single mode,Dual mode,Quad mode,Octal mode"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDOPCODENONXIP ,Read opcode in non-XIP mode"
|
|
line.long 0x04 "DEVINSTRWRCONFIG,Device Write Instruction Configuration Register"
|
|
bitfld.long 0x04 24.--28. " DUMMYWRCLKCYCLES ,Dummy write clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--17. " DATAXFERTYPEEXTMODE ,Data transfer type for standard SPI modes" "Single mode,Dual mode,Quad mode,Octal mode"
|
|
bitfld.long 0x04 12.--13. " ADDRXFERTYPESTDMODE ,Address transfer type for standard SPI modes" "Single mode,Dual mode,Quad mode,Octal mode"
|
|
newline
|
|
bitfld.long 0x04 8. " WELDIS ,WEL disable" "No,Yes"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WROPCODE ,Write opcode"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "DEVINSTRRDCONFIG,Device Read Instruction Configuration Register"
|
|
bitfld.long 0x00 24.--28. " DUMMYRDCLKCYCLES ,Dummy read clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " MODEBITENABLE ,Mode bit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DDREN ,DDR enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " INSTRTYPE ,Instruction type" "Single mode,Dual mode,Quad mode,Octal mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDOPCODENONXIP ,Read opcode in non-XIP mode"
|
|
line.long 0x04 "DEVINSTRWRCONFIG,Device Write Instruction Configuration Register"
|
|
bitfld.long 0x04 24.--28. " DUMMYWRCLKCYCLES ,Dummy write clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8. " WELDIS ,WEL disable" "No,Yes"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WROPCODE ,Write opcode"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DEVDELAY,Device Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DNSS ,Clock delay for chip select deassert"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DBTWN ,Clock delay between two chip selects"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DAFTER ,Clock delay for last transaction bit"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DINIT ,Clock delay for CS"
|
|
if (((per.l(ad:0x4001C400))&0x08)==0x00)&&(((per.l(ad:0x4001C400+0x04))&0x400)==0x400)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RDDATACAPTURE,Read Data Capture Register"
|
|
bitfld.long 0x00 16.--19. " DDRREADDELAY ,DDR read delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " DELAY ,Read delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass the adapted loopback clock circuit" ",Bypassed"
|
|
elif (((per.l(ad:0x4001C400))&0x08)==0x08)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RDDATACAPTURE,Read Data Capture Register"
|
|
bitfld.long 0x00 8. " DQSENABLE ,DQS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass the adapted loopback clock circuit" ",Bypassed"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RDDATACAPTURE,Read Data Capture Register"
|
|
bitfld.long 0x00 8. " DQSENABLE ,DQS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--4. " DELAY ,Read delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass the adapted loopback clock circuit" ",Bypassed"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DEVSIZECONFIG,Device Size Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MEMSIZEONCS1 ,Size of flash device connected to CS[1] pin" "64MB,128MB,256MB,512MB"
|
|
bitfld.long 0x00 21.--22. " MEMSIZEONCS0 ,Size of flash device connected to CS[0] pin" "64MB,128MB,256MB,512MB"
|
|
bitfld.long 0x00 16.--20. " BYTESPERSUBSECTOR ,Number of bytes per block" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. " BYTESPERDEVICEPAGE ,Number of bytes per device page"
|
|
bitfld.long 0x00 0.--3. " NUMADDRBYTES ,Number of address bytes" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "SRAMPARTITIONCFG,SRAM Partition Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADDR ,Indirect read partition size"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "INDAHBADDRTRIGGER,Indirect Address Trigger Register"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "REMAPADDR,Remap Address Register"
|
|
line.long 0x04 "MODEBITCONFIG,Mode Bit Configuration Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RXCRCDATALOW ,RX CRC data (lower)"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RXCRCDATAUP ,RX CRC data (upper)"
|
|
bitfld.long 0x04 15. " CRCOUTENABLE ,CRC# output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8.--10. " CHUNKSIZE ,Chunk size" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MODE ,Mode bits"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SRAMFILL,SRAM Fill Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SRAMFILLINDACWRITE ,SRAM fill level (indirect write partition)"
|
|
hexmask.long.word 0x00 0.--15. 1. " SRAMFILLINDACREAD ,SRAM fill level (indirect read partition)"
|
|
if (((per.l(ad:0x4001C400))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TXTHRESH,TX Threshold Register"
|
|
bitfld.long 0x00 0.--4. " LEVEL ,Threshold level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Highest"
|
|
line.long 0x04 "RXTHRESH,RX Threshold Register"
|
|
bitfld.long 0x04 0.--4. " LEVEL ,Threshold level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Highest"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TXTHRESH,TX Threshold Register"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "RXTHRESH,RX Threshold Register"
|
|
endif
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "WRITECOMPLETIONCTRL,Write Completion Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POLLREPDELAY ,Poll repetition delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POLLCOUNT ,Poll count"
|
|
bitfld.long 0x00 15. " ENABLEPOLLINGEXP ,Enable polling expiration" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " DISABLEPOLLING ,Disable polling" "No,Yes"
|
|
bitfld.long 0x00 13. " POLLINGPOLARITY ,Polling polarity" "Low,High"
|
|
bitfld.long 0x00 8.--10. " POLLINGBITINDEX ,Polling bit index" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Opcode"
|
|
line.long 0x04 "NOOFPOLLSBEFEXP,Polling Expiration Register"
|
|
if (((per.l(ad:0x4001C400))&0x100)==0x100)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 18. " TXCRCCHUNKBRK ,TX CRC chunk was broken" "Not broken,Broken"
|
|
bitfld.long 0x00 17. " RXCRCDATAVAL ,RX CRC data valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " RXCRCDATAERR ,RX CRC data error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 14. " STIGREQINT ,The controller is ready for getting another STIG request" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " POLLEXPINT ,The maximum number of programmed polls cycles expired" "Not expired,Expired"
|
|
bitfld.long 0x00 12. " INDRDSRAMFULL ,Indirect read partition overflow" "No overflow,Overflow"
|
|
newline
|
|
bitfld.long 0x00 11. " RXFIFOFULL ,Small RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 10. " RXFIFONOTEMPTY ,Small RX FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 9. " TXFIFOFULL ,Small TX FIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 8. " TXFIFONOTFULL ,Small TX FIFO not full" "Full,Not full"
|
|
bitfld.long 0x00 7. " RECVOVERFLOW ,Receive overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " INDIRECTXFERLEVELBREACH ,Indirect transfer watermark level breached" "Not breached,Breached"
|
|
newline
|
|
bitfld.long 0x00 5. " ILLEGALACCESSDET ,Illegal memory access has been detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " PROTWRATTEMPT ,Write to protected area was attempted and rejected" "Not rejected,Rejected"
|
|
bitfld.long 0x00 3. " INDIRECTREADREJECT ,Indirect operation was requested but could not be accepted" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " INDIRECTOPDONE ,Indirect operation complete" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " UNDERFLOWDET ,Underflow detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " MODEMFAIL ,Mode M failure" "No failure,Failure"
|
|
line.long 0x04 "IRQMASK,Interrupt Mask Register"
|
|
bitfld.long 0x04 18. " TXCRCCHUNKBRKMASK ,TX CRC chunk was broken mask" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " RXCRCDATAVALMASK ,RX CRC data valid mask" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " RXCRCDATAERRMASK ,RX CRC data error mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 14. " STIGREQINTMASK ,STIG request completion mask" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " POLLEXPINTMASK ,Polling expiration detected mask" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " INDRDSRAMFULLMASK ,Indirect read partition overflow mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 11. " RXFIFOFULLMASK ,Small RX FIFO full mask" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " RXFIFONOTEMPTYMASK ,Small RX FIFO not empty mask" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " TXFIFOFULLMASK ,Small TX FIFO full mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " TXFIFONOTFULLMASK ,Small TX FIFO not full mask" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " RECVOVERFLOWMASK ,Receive overflow mask" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " INDIRECTXFERLEVELBREACHMASK ,Indirect transfer watermark level breached mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 5. " ILLEGALACCESSDETMASK ,Illegal memory access has been detected mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " PROTWRATTEMPTMASK ,Write to protected area was attempted and rejected mask" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " INDIRECTREADREJECTMASK ,Indirect operation was requested but could not be accepted mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 2. " INDIRECTOPDONEMASK ,Indirect operation complete mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " UNDERFLOWDETMASK ,Underflow detected mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " MODEMFAILMASK ,Mode M failure mask" "Not masked,Masked"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 18. " TXCRCCHUNKBRK ,TX CRC chunk was broken" "Not broken,Broken"
|
|
bitfld.long 0x00 17. " RXCRCDATAVAL ,RX CRC data valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " RXCRCDATAERR ,RX CRC data error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 14. " STIGREQINT ,The controller is ready for getting another STIG request" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " POLLEXPINT ,The maximum number of programmed polls cycles expired" "Not expired,Expired"
|
|
bitfld.long 0x00 12. " INDRDSRAMFULL ,Indirect read partition overflow" "No overflow,Overflow"
|
|
newline
|
|
bitfld.long 0x00 6. " INDIRECTXFERLEVELBREACH ,Indirect transfer watermark level breached" "Not breached,Breached"
|
|
bitfld.long 0x00 5. " ILLEGALACCESSDET ,Illegal memory access has been detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " PROTWRATTEMPT ,Write to protected area was attempted and rejected" "Not rejected,Rejected"
|
|
newline
|
|
bitfld.long 0x00 3. " INDIRECTREADREJECT ,Indirect operation was requested but could not be accepted" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INDIRECTOPDONE ,Indirect operation complete" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " UNDERFLOWDET ,Underflow detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 0. " MODEMFAIL ,Mode M failure" "No failure,Failure"
|
|
line.long 0x04 "IRQMASK,Interrupt Mask Register"
|
|
bitfld.long 0x04 18. " TXCRCCHUNKBRKMASK ,TX CRC chunk was broken mask" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " RXCRCDATAVALMASK ,RX CRC data valid mask" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " RXCRCDATAERRMASK ,RX CRC data error mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 14. " STIGREQINTMASK ,STIG request completion mask" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " POLLEXPINTMASK ,Polling expiration detected mask" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " INDRDSRAMFULLMASK ,Indirect read partition overflow mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 6. " INDIRECTXFERLEVELBREACHMASK ,Indirect transfer watermark level breached mask" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " ILLEGALACCESSDETMASK ,Illegal memory access has been detected mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " PROTWRATTEMPTMASK ,Write to protected area was attempted and rejected mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 3. " INDIRECTREADREJECTMASK ,Indirect operation was requested but could not be accepted mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " INDIRECTOPDONEMASK ,Indirect operation complete mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " UNDERFLOWDETMASK ,Underflow detected mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 0. " MODEMFAILMASK ,Mode M failure mask" "Not masked,Masked"
|
|
endif
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "LOWERWRPROT,Lower Write Protection Register"
|
|
line.long 0x04 "UPPERWRPROT,Upper Write Protection Register"
|
|
line.long 0x08 "WRPROTCTRL,Write Protection Control Register"
|
|
bitfld.long 0x08 1. " ENB ,Write protection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INV ,Write protection inversion bit" "Not inverted,Inverted"
|
|
group.long 0x60++0x23
|
|
line.long 0x00 "INDIRECTREADXFERCTRL,Indirect Read Transfer Control Register"
|
|
rbitfld.long 0x00 6.--7. " NUMINDOPSDONE ,Number indirect operations done" "0,1,2,3"
|
|
eventfld.long 0x00 5. " INDOPSDONESTATUS ,Indirect completion status" "Not completed,Completed"
|
|
rbitfld.long 0x00 4. " RDQUEUED ,Two indirect read operations have been queued" "Not queued,Queued"
|
|
newline
|
|
eventfld.long 0x00 3. " SRAMFULL ,SRAM full" "Not full,Full"
|
|
rbitfld.long 0x00 2. " RDSTATUS ,Indirect read status" "No read,Read"
|
|
bitfld.long 0x00 1. " CANCEL ,Cancel indirect read" "Not canceled,Canceled"
|
|
newline
|
|
bitfld.long 0x00 0. " START ,Start indirect read" "Not started,Started"
|
|
line.long 0x04 "INDIRECTREADXFERWATERMARK,Indirect Read Transfer Watermark Register"
|
|
line.long 0x08 "INDIRECTREADXFERSTART,Indirect Read Transfer Start Address Register"
|
|
line.long 0x0C "INDIRECTREADXFERNUMBYTES,Indirect Read Transfer Number Bytes Register"
|
|
line.long 0x10 "INDIRECTWRITEXFERCTRL,Indirect Write Transfer Control Register"
|
|
rbitfld.long 0x10 6.--7. " NUMINDOPSDONE ,Number operations done" "0,1,2,3"
|
|
eventfld.long 0x10 5. " INDOPSDONESTATUS ,Indirect completion status" "Not completed,Completed"
|
|
rbitfld.long 0x10 4. " WRQUEUED ,Two indirect write operations have been queued" "Not queued,Queued"
|
|
newline
|
|
rbitfld.long 0x10 2. " WRSTATUS ,Indirect write status" "Not in progress,In progress"
|
|
bitfld.long 0x10 1. " CANCEL ,Cancel indirect write" "Not canceled,Canceled"
|
|
bitfld.long 0x10 0. " START ,Start indirect write" "Not started,Started"
|
|
line.long 0x14 "INDIRECTWRITEXFERWATERMARK,Indirect Write Transfer Watermark Register"
|
|
line.long 0x18 "INDIRECTWRITEXFERSTART,Indirect Write Transfer Start Address Register"
|
|
line.long 0x1C "INDIRECTWRITEXFERNUMBYTES,Indirect Write Transfer Number Bytes Register"
|
|
line.long 0x20 "INDIRECTTRIGGERADDRRANGE,Indirect Trigger Address Range Register"
|
|
bitfld.long 0x20 0.--3. " INDRANGEWIDTH ,Indirect trigger address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8C++0x0B
|
|
line.long 0x00 "FLASHCOMMANDCTRLMEM,Flash Command Control Memory Register"
|
|
hexmask.long.word 0x00 20.--28. 0x10 " MEMBANKADDR ,Memory bank address"
|
|
bitfld.long 0x00 16.--18. " NBOFSTIGREADBYTES ,Number of read bytes for the extended STIG" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMBANKREADDATA ,Last requested data from the STIG memory bank"
|
|
newline
|
|
rbitfld.long 0x00 1. " MEMBANKREQINPROGRESS ,Memory bank data request in progress" "Not in progress,In progress"
|
|
bitfld.long 0x00 0. " TRIGGERMEMBANKREQ ,Trigger the memory bank data request" "Not requested,Requested"
|
|
line.long 0x04 "FLASHCMDCTRL,Flash Command Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CMDOPCODE ,Command opcode"
|
|
bitfld.long 0x04 23. " ENBREADDATA ,Read data enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20.--22. " NUMRDDATABYTES ,Number of read data bytes" "1,2,3,4,5,6,7,8"
|
|
newline
|
|
bitfld.long 0x04 19. " ENBCOMDADDR ,Command address enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ENBMODEBIT ,Mode bit enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " NUMADDRBYTES ,Number of address bytes" "1,2,3,4"
|
|
newline
|
|
bitfld.long 0x04 15. " ENBWRITEDATA ,Write data enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--14. " NUMWRDATABYTES ,Number of write data bytes" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x04 7.--11. " NUMDUMMYCYCLES ,Number of dummy cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
newline
|
|
bitfld.long 0x04 2. " STIGMEMBANKEN ,STIG memory bank enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x04 1. " CMDEXECSTATUS ,Command execution in progress" "Not in progress,In progress"
|
|
bitfld.long 0x04 0. " CMDEXEC ,Execute the command" "Not executed,Executed"
|
|
line.long 0x08 "FLASHCMDADDR,Flash Command Address Register"
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "FLASHRDDATALOWER,Flash Command Read Data Register (Lower) (STIG)"
|
|
line.long 0x04 "FLASHRDDATAUPPER,Flash Command Read Data Register (Upper) (STIG)"
|
|
group.long 0xA8++0x0F
|
|
line.long 0x00 "FLASHWRDATALOWER,Flash Command Write Data Register (Lower) (STIG)"
|
|
line.long 0x04 "FLASHWRDATAUPPER,Flash Command Write Data Register (Upper) (STIG)"
|
|
line.long 0x08 "POLLINGFLASHSTATUS,Polling Flash Status Register"
|
|
bitfld.long 0x08 16.--19. " DEVICESTATUSNBDUMMY ,Auto-polling dummy cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rbitfld.long 0x08 8. " DEVICESTATUSVALID ,Device status valid" "Not valid,Valid"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DEVICESTATUS ,Device status"
|
|
line.long 0x0C "PHYCONFIGURATION,PHY Configuration Register"
|
|
bitfld.long 0x0C 31. " PHYCONFIGRESYNC ,PHY config resync" "No resync,Resync"
|
|
hexmask.long.byte 0x0C 16.--22. 1. " PHYCONFIGTXDLLDELAY ,TX DLL delay"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " PHYCONFIGRXDLLDELAY ,RX DLL delay"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "OPCODEEXTLOWER,Opcode Extension Register (Lower)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXTREADOPCODE ,Read opcode extension"
|
|
hexmask.long.byte 0x00 16.--23. 1. " EXTWRITEOPCODE ,Write opcode extension"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTPOLLOPCODE ,Polling opcode extension"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " EXTSTIGOPCODE ,STIG opcode extension"
|
|
line.long 0x04 "OPCODEEXTUPPER,Opcode Extension Register (Upper)"
|
|
hexmask.long.byte 0x04 24.--31. 1. " WELOPCODE ,WEL opcode"
|
|
hexmask.long.byte 0x04 16.--23. 1. " EXTWELOPCODE ,WEL opcode extension"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "MODULEID,Module ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FIXPATCH ,Fix/patch number"
|
|
hexmask.long.word 0x00 8.--23. 1. " MODULEID ,Module/Revision ID number"
|
|
bitfld.long 0x00 0.--1. " CONF ,Configuration ID number" "0,1,2,3"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "ROUTEPEN,I/O Routing Pin Enable Register"
|
|
bitfld.long 0x00 14. " SCLKINPEN ,SCLKIN pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DQSPEN ,DQS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DQ7PEN ,DQ7 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " DQ6PEN ,DQ6 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DQ5PEN ,DQ5 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DQ4PEN ,DQ4 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " DQ3PEN ,DQ3 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DQ2PEN ,DQ2 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DQ1PEN ,DQ1 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DQ0PEN ,DQ0 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CS1PEN ,CS1 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CS0PEN ,CS0 pin enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " SCLKPEN ,SCLK pin enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Route Location Register 0"
|
|
bitfld.long 0x04 0.--5. " QSPILOC ,I/O location" "LOC0,LOC1,LOC2,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB (Universal Serial Bus Controller)"
|
|
base ad:0x40022000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,System Control Register"
|
|
bitfld.long 0x00 31. " SDEN ,Secondary detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PDEN ,Primary detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCDEN ,Data contact detection enable" "Disabled,Timeout,Enabled,?..."
|
|
bitfld.long 0x00 27. " OTGPHYCTRLDIS ,OTG control signals to PHY disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " OTGIDINDIS ,OTG ID input disable" "No,Yes"
|
|
bitfld.long 0x00 25. " OTGCLKCDIS ,OTG CLKC disable" "No,Yes"
|
|
bitfld.long 0x00 12. " IDCDEN ,ID pull-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LEMIDLEEN ,Low energy mode on bus idle enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " LEMPHYCTRL ,Low energy mode USB PHY control" "None,LEM"
|
|
bitfld.long 0x00 4.--5. " LEMOSCCTRL ,Low energy mode oscillator control" "None,Gate,?..."
|
|
bitfld.long 0x00 3. " SELFPOWERED ,PHY power" "Low,High"
|
|
bitfld.long 0x00 0. " VBUSENAP ,VBUSEN active polarity" "High,Low"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,System Status Register"
|
|
bitfld.long 0x00 15. " USBCDBUSY ,USB charger detect busy" "Not busy,Busy"
|
|
bitfld.long 0x00 13. " ACALS ,ACA low speed TypeB device detect" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ACAFS ,ACA full speed TypeB device" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " DCP ,Dedicated charging port detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 10. " CDP ,Charging downstream port detected" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SDP ,Standard downstream port detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " DCDTO ,Data contact detection timeout" "No time,Timeout"
|
|
bitfld.long 0x00 2. " LEMACTIVE ,Low energy mode active" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 0. " VBUSDETH ,VBUS detect high" "Low,High"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SD ,Secondary detection complete interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PD ,Primary detection complete interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DCD ,Data contact detection complete interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERR ,Detection error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " VBUSDETL ,VBUS detect low interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " VBUSDETH ,VBUS detect high interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SD ,SD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PD ,PD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DCD ,DCD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERR ,ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " VBUSDETL ,VBUSDETL interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VBUSDETH ,VBUSDETH interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTE,Interrupt Enable Register"
|
|
bitfld.long 0x04 1. " VBUSENPEN ,VBUSEN pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PHYPEN ,USB PHY pin enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CDCONF,Charger Detect Configuration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DCDTOCONF ,DCD timeout configuration"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 1. " STOPCD ,Start charger detection in progress" "In progress,Stopped"
|
|
bitfld.long 0x00 0. " STARTCD ,Start charger detection enabled" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DATTRIM1,Data TRIM 1 Values for USB DP and DM Register"
|
|
bitfld.long 0x00 18.--19. " TRDPFS ,Trim for DP rise time in FS" "Min,1,2,Max"
|
|
bitfld.long 0x00 16.--17. " TFDPFS ,Trim for DP fall time in FS" "Min,1,2,Max"
|
|
bitfld.long 0x00 14.--15. " TRDMFS ,Trim for DM rise time in FS" "Min,1,2,Max"
|
|
bitfld.long 0x00 12.--13. " TFDMFS ,Trim for DM fall time in FS" "Min,1,2,Max"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " VCRSFS ,Trim for falling crossover voltage in FS" "Min,1,2,Max"
|
|
bitfld.long 0x00 8.--9. " DLYPULLUPFS ,Trim for rising crossover voltage in FS" "Min,1,2,Max"
|
|
bitfld.long 0x00 7. " ENDLYPULLUP ,Enables delay of pull in TX mode for both FS and LS" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " ROUT[1] ,Trim for DP and DM output impedance for both FS and LS (control pull up resistance)" "Min,1,2,3,4,5,6,Max"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " ROUT[0] ,Trim for DP and DM output impedance for both FS and LS (control pull down resistance)" "Min,1,2,3,4,5,6,Max"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "LEMCTRL,USB LEM Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " TIMEBASE ,Number of LFC clk counts to form 3ms"
|
|
group.long 0xDE000++0x07
|
|
line.long 0x00 "GOTGCTL,OTG Control And Status Register"
|
|
rbitfld.long 0x00 21. " CURMOD ,Current mode of operation" "Device,Host"
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "1.3,2.0"
|
|
rbitfld.long 0x00 19. " BSESVLD ,B-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 18. " ASESVLD ,A-session valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 17. " DBNCTIME ,Long/short debounce time" "Long,Short"
|
|
rbitfld.long 0x00 16. " CONIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
bitfld.long 0x00 15. " DBNCEFLTRBYPASS ,DBNCEFLTRBYPASS" "0,1"
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " DEVHNPEN ,Device HNP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HSTSETHNPEN ,Host set HNP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HNPREQ ,HNP request" "Not requested,Requested"
|
|
rbitfld.long 0x00 8. " HSTNEGSCS ,Host negotiation success" "Failure,Success"
|
|
newline
|
|
bitfld.long 0x00 7. " BVALIDOVVAL ,B-Peripheral session valid override value" "0,1"
|
|
bitfld.long 0x00 6. " BVALIDOVEN ,B-Peripheral session valid override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AVALIDOVVAL ,A-Peripheral session valid override value" "0,1"
|
|
bitfld.long 0x00 4. " AVALIDOVEN ,A-Peripheral session valid override enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " VBVALIDOVVAL ,VBUS valid override value" "0,1"
|
|
bitfld.long 0x00 2. " VBVALIDOVEN ,VBUS valid override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SESREQ ,Session request" "Not requested,Requested"
|
|
rbitfld.long 0x00 0. " SESREQSCS ,Session request success" "Failure,Success"
|
|
line.long 0x04 "GOTGINT,OTG Interrupt Register"
|
|
bitfld.long 0x04 19. " DBNCEDONE ,Debounce done" "Not done,Done"
|
|
bitfld.long 0x04 18. " ADEVTOUTCHG ,A-Device timeout change" "Not changed,Changed"
|
|
bitfld.long 0x04 17. " HSTNEGDET ,Host negotiation detected" "Not detected,Detected"
|
|
bitfld.long 0x04 9. " HSTNEGSUCSTSCHNG ,Host negotiation success status change" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 8. " SESREQSUCSTSCHNG ,Session request success status change" "Not changed,Changed"
|
|
bitfld.long 0x04 2. " SESENDDET ,Session end detected" "Not detected,Detected"
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x200000)==0x200000)
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x20)==0x20)
|
|
group.long 0xDE008++0x03
|
|
line.long 0x00 "GAHBCFG,AHB Configuration Register"
|
|
bitfld.long 0x00 23. " AHBSINGLE ,AHB single support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " NOTIALLDMAWRIT ,Notify all DMA write transactions" "Not notified,Notified"
|
|
newline
|
|
bitfld.long 0x00 21. " REMMEMSUPP ,Remote memory support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--4. " HBSTLEN ,Burst length/type" "1 word,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..."
|
|
bitfld.long 0x00 0. " GLBLINTRMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0xDE008++0x03
|
|
line.long 0x00 "GAHBCFG,AHB Configuration Register"
|
|
bitfld.long 0x00 23. " AHBSINGLE ,AHB single support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " NOTIALLDMAWRIT ,Notify all DMA write transactions" "Not notified,Notified"
|
|
newline
|
|
bitfld.long 0x00 21. " REMMEMSUPP ,Remote memory support" "Not supported,Supported"
|
|
bitfld.long 0x00 8. " PTXFEMPLVL ,Periodic TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x00 7. " NPTXFEMPLVL ,Non-periodic TxFIFO empty level" "Half empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--4. " HBSTLEN ,Burst length/type" "1 word,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..."
|
|
bitfld.long 0x00 0. " GLBLINTRMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x20)==0x20)
|
|
group.long 0xDE008++0x03
|
|
line.long 0x00 "GAHBCFG,AHB Configuration Register"
|
|
bitfld.long 0x00 23. " AHBSINGLE ,AHB single support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 21. " REMMEMSUPP ,Remote memory support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--4. " HBSTLEN ,Burst length/type" "1 word,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..."
|
|
bitfld.long 0x00 0. " GLBLINTRMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0xDE008++0x03
|
|
line.long 0x00 "GAHBCFG,AHB Configuration Register"
|
|
bitfld.long 0x00 23. " AHBSINGLE ,AHB single support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 21. " REMMEMSUPP ,Remote memory support" "Not supported,Supported"
|
|
bitfld.long 0x00 8. " PTXFEMPLVL ,Periodic TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x00 7. " NPTXFEMPLVL ,Non-periodic TxFIFO empty level" "Half empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--4. " HBSTLEN ,Burst length/type" "1 word,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..."
|
|
bitfld.long 0x00 0. " GLBLINTRMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
endif
|
|
newline
|
|
group.long 0xDE00C++0x03
|
|
line.long 0x00 "GUSBCFG,USB Configuration Register"
|
|
bitfld.long 0x00 31. " CORRUPTTXPKT ,CORRUPTTXPKT" "0,1"
|
|
bitfld.long 0x00 30. " FORCEDEVMODE ,Force device mode" "Not forced,Forced"
|
|
bitfld.long 0x00 29. " FORCEHSTMODE ,Force host mode" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x00 28. " TXENDDELAY ,Tx end delay enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TERMSELDLPULSE ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel"
|
|
bitfld.long 0x00 10.--13. " USBTRDTIM ,USB turnaround time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 9. " HNPCAP ,HNP-capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SRPCAP ,SRP-capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSINTF ,Full-speed serial interface select" "6-pin unidirectional,3-pin bidirectional"
|
|
newline
|
|
bitfld.long 0x00 3. " PHYIF ,PHY interface" "8 bits,16 bits"
|
|
bitfld.long 0x00 0.--2. " TOUTCAL ,HS/FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
group.long 0xDE010++0x03
|
|
line.long 0x00 "GRSTCTL,Reset Register"
|
|
rbitfld.long 0x00 31. " AHBIDLE ,AHB master idle" "Not idle,Idle"
|
|
rbitfld.long 0x00 30. " DMAREQ ,DMA request signal in progress" "Not in progress,In progress"
|
|
bitfld.long 0x00 6.--10. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 5. " TXFFLSH ,TxFIFO flush" "Not flushed,Flushed"
|
|
newline
|
|
eventfld.long 0x00 4. " RXFFLSH ,RxFIFO flush" "Not flushed,Flushed"
|
|
eventfld.long 0x00 2. " FRMCNTRRST ,Host frame counter reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PIUFSSFTRST ,PIU FS dedicated controller soft reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " CSFTRST ,Core soft reset" "No reset,Reset"
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x200000)
|
|
group.long 0xDE014++0x03
|
|
line.long 0x00 "GINTSTS,Interrupt Register"
|
|
bitfld.long 0x00 31. " WKUPINT ,Resume/Remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " SESSREQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DISCONNINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " CONIDSTSCHNG ,Connector ID status change" "Not changed,Changed"
|
|
newline
|
|
rbitfld.long 0x00 26. " PTXFEMP ,Periodic TxFIFO empty" "Half empty,Empty"
|
|
rbitfld.long 0x00 25. " HCHINT ,Host channels interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 24. " PRTINT ,Host port interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " FETSUSP ,Data fetch suspended" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. " INCOMPLP ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INCOMPISOIN ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ISOOUTDROP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " ENUMDONE ,Enumeration done" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset"
|
|
bitfld.long 0x00 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 10. " ERLYSUSP ,Early suspend" "Not suspended,Suspended"
|
|
newline
|
|
rbitfld.long 0x00 7. " GOUTNAKEFF ,Global OUT NAK effective" "Not effective,Effective"
|
|
rbitfld.long 0x00 6. " GINNAKEFF ,Global IN non-periodic NAK effective" "Not effective,Effective"
|
|
rbitfld.long 0x00 5. " NPTXFEMP ,Non-periodic TxFIFO empty" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 3. " SOF ,Start of (micro) frame" "Not started,Started"
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " MODEMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " CURMOD ,Current mode of operation" "Device,Host"
|
|
else
|
|
group.long 0xDE014++0x03
|
|
line.long 0x00 "GINTSTS,Interrupt Register"
|
|
bitfld.long 0x00 31. " WKUPINT ,Resume/Remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " SESSREQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DISCONNINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " CONIDSTSCHNG ,Connector ID status change" "Not changed,Changed"
|
|
newline
|
|
rbitfld.long 0x00 26. " PTXFEMP ,Periodic TxFIFO empty" "Half empty,Empty"
|
|
bitfld.long 0x00 23. " RESETDET ,Reset detected interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " FETSUSP ,Data fetch suspended" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INCOMPLP ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 20. " INCOMPISOIN ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 19. " OEPINT ,OUT endpoints interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 18. " IEPINT ,IN endpoints interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 14. " ISOOUTDROP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ENUMDONE ,Enumeration done" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset"
|
|
bitfld.long 0x00 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 10. " ERLYSUSP ,Early suspend" "Not suspended,Suspended"
|
|
rbitfld.long 0x00 7. " GOUTNAKEFF ,Global OUT NAK effective" "Not effective,Effective"
|
|
rbitfld.long 0x00 6. " GINNAKEFF ,Global IN non-periodic NAK effective" "Not effective,Effective"
|
|
rbitfld.long 0x00 5. " NPTXFEMP ,Non-periodic TxFIFO empty" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
bitfld.long 0x00 3. " SOF ,Start of (micro) frame" "Not started,Started"
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " MODEMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " CURMOD ,Current mode of operation" "Device,Host"
|
|
endif
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x200000)
|
|
group.long 0xDE018++0x03
|
|
line.long 0x00 "GINTMSK,Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " WKUPINTMSK ,Resume/Remote wakeup detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " SESSREQINTMSK ,Session request/new session detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DISCONNINTMSK ,Disconnect detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " CONIDSTSCHNGMSK ,Connector ID status change mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 26. " PTXFEMPMSK ,Periodic TxFIFO empty mask" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " HCHINTMSK ,Host channels interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PRTINTMSK ,Host port interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " FETSUSPMSK ,Data fetch suspended mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 21. " INCOMPLPMSK ,Incomplete periodic transfer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " INCOMPISOINMSK ,Incomplete isochronous IN transfer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " EPMISMSK ,Endpoint mismatch interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " EOPFMSK ,End of periodic frame interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 14. " ISOOUTDROPMSK ,Isochronous OUT packet dropped interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " ENUMDONEMSK ,Enumeration done mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " USBRSTMSK ,USB reset mask" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " USBSUSPMSK ,USB suspend mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " ERLYSUSPMSK ,Early suspend mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " GOUTNAKEFFMSK ,Global OUT NAK effective mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " GINNAKEFFMSK ,Global IN non-periodic NAK effective mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " NPTXFEMPMSK ,Non-periodic TxFIFO empty mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " RXFLVLMSK ,RxFIFO non-empty mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " SOFMSK ,Start of (micro) frame mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " OTGINTMSK ,OTG interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " MODEMISMSK ,Mode mismatch interrupt mask" "Not masked,Masked"
|
|
else
|
|
group.long 0xDE018++0x03
|
|
line.long 0x00 "GINTMSK,Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " WKUPINTMSK ,Resume/Remote wakeup detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " SESSREQINTMSK ,Session request/new session detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DISCONNINTMSK ,Disconnect detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " CONIDSTSCHNGMSK ,Connector ID status change mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 26. " PTXFEMPMSK ,Periodic TxFIFO empty mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " RESETDETMSK ,Reset detected interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " FETSUSPMSK ,Data fetch suspended mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " INCOMPLPMSK ,Incomplete periodic transfer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 20. " INCOMPISOINMSK ,Incomplete isochronous IN transfer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " OEPINTMSK ,OUT endpoints interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " IEPINTMSK ,IN endpoints interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " EPMISMSK ,Endpoint mismatch interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 15. " EOPFMSK ,End of periodic frame interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " ISOOUTDROPMSK ,Isochronous OUT packet dropped interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " ENUMDONEMSK ,Enumeration done mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " USBRSTMSK ,USB reset mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " USBSUSPMSK ,USB suspend mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " ERLYSUSPMSK ,Early suspend mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " GOUTNAKEFFMSK ,Global OUT NAK effective mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " GINNAKEFFMSK ,Global IN non-periodic NAK effective mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 5. " NPTXFEMPMSK ,Non-periodic TxFIFO empty mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " RXFLVLMSK ,RxFIFO non-empty mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " SOFMSK ,Start of (micro) frame mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " OTGINTMSK ,OTG interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " MODEMISMSK ,Mode mismatch interrupt mask" "Not masked,Masked"
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x00)
|
|
if (((per.l(ad:0x40022000+0xDE920))&0xC0000)==0x40000)
|
|
rgroup.long 0xDE01C++0x07
|
|
line.long 0x00 "GRXSTSR,Receive Status Debug Read Register"
|
|
bitfld.long 0x00 21.--24. " FN ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,SETUP transaction completed,,SETUP data packet received,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "GRXSTSP,Receive Status Read/Pop Register"
|
|
bitfld.long 0x04 21.--24. " FN ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,SETUP transaction completed,,SETUP data packet received,?..."
|
|
newline
|
|
bitfld.long 0x04 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x04 4.--14. 1. " BCNT ,Byte count"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xDE01C++0x07
|
|
line.long 0x00 "GRXSTSR,Receive Status Debug Read Register"
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,SETUP transaction completed,,SETUP data packet received,?..."
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count"
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "GRXSTSP,Receive Status Read/Pop Register"
|
|
bitfld.long 0x04 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,SETUP transaction completed,,SETUP data packet received,?..."
|
|
bitfld.long 0x04 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
newline
|
|
hexmask.long.word 0x04 4.--14. 1. " BCNT ,Byte count"
|
|
bitfld.long 0x04 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40022000+0xDE500))&0xC8000)==0x40000)
|
|
rgroup.long 0xDE01C++0x07
|
|
line.long 0x00 "GRXSTSR,Receive Status Debug Read Register"
|
|
bitfld.long 0x00 21.--24. " FN ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..."
|
|
newline
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "GRXSTSP,Receive Status Read/Pop Register"
|
|
bitfld.long 0x04 21.--24. " FN ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..."
|
|
newline
|
|
bitfld.long 0x04 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x04 4.--14. 1. " BCNT ,Byte count"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xDE01C++0x07
|
|
line.long 0x00 "GRXSTSR,Receive Status Debug Read Register"
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..."
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count"
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "GRXSTSP,Receive Status Read/Pop Register"
|
|
bitfld.long 0x04 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..."
|
|
bitfld.long 0x04 15.--16. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
newline
|
|
hexmask.long.word 0x04 4.--14. 1. " BCNT ,Byte count"
|
|
bitfld.long 0x04 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
newline
|
|
group.long 0xDE024++0x07
|
|
line.long 0x00 "GRXFSIZ,Receive FIFO Size Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " RXFDEP ,RxFIFO depth"
|
|
line.long 0x04 "GNPTXFSIZ,Non-Periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " NPTXFDEP ,Non-periodic TxFIFO depth"
|
|
hexmask.long.word 0x04 0.--15. 1. " NPTXFSTADDR ,Non-periodic transmit RAM start address"
|
|
rgroup.long 0xDE02C++0x03
|
|
line.long 0x00 "GNPTXSTS,Non-periodic Transmit FIFO/Queue Status Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NPTXQTOP ,Top of the non-periodic transmit request queue"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NPTXQSPCAVAIL ,Non-periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " NPTXFSPCAVAIL ,Non-periodic TxFIFO space avail"
|
|
rgroup.long 0xDE040++0x03
|
|
line.long 0x00 "GSNPSID,Synopsys ID Register"
|
|
group.long 0xDE05C++0x03
|
|
line.long 0x00 "GDFIFOCFG,Global DFIFO Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " EPINFOBASEADDR ,EPINFOBASEADDR"
|
|
hexmask.long.word 0x00 0.--15. 1. " GDFIFOCFG ,GDFIFOCFG"
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x200000)
|
|
group.long 0xDE100++0x03
|
|
line.long 0x00 "HPTXFSIZ,Host Periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " PTXFSIZE ,Host periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " PTXFSTADDR ,Host periodic TxFIFO start address"
|
|
else
|
|
hgroup.long 0xDE100++0x03
|
|
hide.long 0x00 "HPTXFSIZ,Host Periodic Transmit FIFO Size Register"
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x00)
|
|
group.long 0xDE104++0x03
|
|
line.long 0x00 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " INEPNTXFDEP ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " INEPNTXFSTADDR ,IN endpoint FIFOn transmit RAM start address"
|
|
group.long 0xDE108++0x03
|
|
line.long 0x00 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " INEPNTXFDEP ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " INEPNTXFSTADDR ,IN endpoint FIFOn transmit RAM start address"
|
|
group.long 0xDE10C++0x03
|
|
line.long 0x00 "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " INEPNTXFDEP ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " INEPNTXFSTADDR ,IN endpoint FIFOn transmit RAM start address"
|
|
group.long 0xDE110++0x03
|
|
line.long 0x00 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " INEPNTXFDEP ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " INEPNTXFSTADDR ,IN endpoint FIFOn transmit RAM start address"
|
|
group.long 0xDE114++0x03
|
|
line.long 0x00 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " INEPNTXFDEP ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " INEPNTXFSTADDR ,IN endpoint FIFOn transmit RAM start address"
|
|
group.long 0xDE118++0x03
|
|
line.long 0x00 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " INEPNTXFDEP ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " INEPNTXFSTADDR ,IN endpoint FIFOn transmit RAM start address"
|
|
else
|
|
hgroup.long 0xDE104++0x03
|
|
hide.long 0x00 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hgroup.long 0xDE108++0x03
|
|
hide.long 0x00 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hgroup.long 0xDE10C++0x03
|
|
hide.long 0x00 "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hgroup.long 0xDE110++0x03
|
|
hide.long 0x00 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hgroup.long 0xDE114++0x03
|
|
hide.long 0x00 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
hgroup.long 0xDE118++0x03
|
|
hide.long 0x00 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register 1"
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x200000)
|
|
group.long 0xDE400++0x03
|
|
line.long 0x00 "HCFG,Host Configuration Register"
|
|
bitfld.long 0x00 31. " MODECHTIMEN ,MODECHTIMEN" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RESVALID ,Resume validation period"
|
|
bitfld.long 0x00 7. " ENA32KHZS ,Enable 32 kHz suspend mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSLSSUPP ,FS- and LS-only support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " FSLSPCLKSEL ,FS/LS PHY clock select" "30/60 MHz,48 MHz,6 MHz,?..."
|
|
group.long 0xDE404++0x03
|
|
line.long 0x00 "HFIR,Host Frame Interval Register"
|
|
bitfld.long 0x00 16. " HFIRRLDCTRL ,Reload control" "No dynamic control,Dynamic control"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRINT ,Frame interval"
|
|
rgroup.long 0xDE408++0x03
|
|
line.long 0x00 "HFNUM,Host Frame Number/Frame Time Remaining Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FRREM ,Frame time remaining"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number"
|
|
rgroup.long 0xDE410++0x07
|
|
line.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PTXQTOP ,Top of the periodic transmit request queue"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PTXQSPCAVAIL ,Periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " PTXFSPCAVAIL ,Periodic transmit data FIFO space available"
|
|
newline
|
|
line.long 0x04 "HAINT,Host All Channels Interrupt Register"
|
|
bitfld.long 0x04 13. " HAINT[13] ,Host channel 13 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " [12] ,Host channel 12 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " [11] ,Host channel 11 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,Host channel 10 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Host channel 9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,Host channel 8 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " [7] ,Host channel 7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " [6] ,Host channel 6 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Host channel 5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Host channel 4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " [3] ,Host channel 3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Host channel 2 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Host channel 1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [0] ,Host channel 0 interrupt" "No interrupt,Interrupt"
|
|
group.long 0xDE418++0x03
|
|
line.long 0x00 "HAINTMSK,Host All Channels Interrupt Mask Register"
|
|
bitfld.long 0x00 13. " HAINTMSK[13] ,Host channel 13 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Host channel 12 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Host channel 11 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Host channel 10 interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Host channel 9 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Host channel 8 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Host channel 7 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Host channel 6 interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Host channel 5 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Host channel 4 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Host channel 3 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Host channel 2 interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Host channel 1 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Host channel 0 interrupt mask" "Not masked,Masked"
|
|
newline
|
|
group.long 0xDE440++0x03
|
|
line.long 0x00 "HPRT,Host Port Control and Status Register"
|
|
rbitfld.long 0x00 17.--18. " PRTSPD ,Port speed" "High speed,Full speed,Low speed,?..."
|
|
bitfld.long 0x00 13.--16. " PRTTSTCTL ,Port test control" "High speed,Full speed,Low speed,?..."
|
|
bitfld.long 0x00 12. " PRTPWR ,Port power" "Powered off,Powered on"
|
|
newline
|
|
rbitfld.long 0x00 10.--11. " PRTLNSTS ,Port line status" ",,D+,D-"
|
|
bitfld.long 0x00 8. " PRTRST ,Port reset" "No reset,Reset"
|
|
eventfld.long 0x00 7. " PRTSUSP ,Port suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 6. " PRTRES ,Port resume" "Not resumed,Resumed"
|
|
eventfld.long 0x00 5. " PRTOVRCURRCHNG ,Port overcurrent change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " PRTOVRCURRACT ,Port overcurrent active" "Inactive,Active"
|
|
newline
|
|
eventfld.long 0x00 3. " PRTENCHNG ,Port enable/disable change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PRTENA ,Port enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " PRTCONNDET ,Port connect detected" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 0. " PRTCONNSTS ,Port connect status" "Not connected,Connected"
|
|
if (((per.l(ad:0x40022000+0xDE500))&0xC0000)==(0x40000||0xC0000))
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x20)==0x20)
|
|
group.long 0xDE500++0x03
|
|
line.long 0x00 "HC0_CHAR,Host Channel 0 Characteristics Register"
|
|
eventfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
newline
|
|
hexmask.long.byte 0x00 22.--28. 0x40 " DEVADDR ,Device address"
|
|
bitfld.long 0x00 20.--21. " MC ,Multi count (MC) / error count" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " LSPDDEV ,Low-speed device" "No low speed,Low speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "Out,In"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
else
|
|
group.long 0xDE500++0x03
|
|
line.long 0x00 "HC0_CHAR,Host Channel 0 Characteristics Register"
|
|
eventfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
newline
|
|
hexmask.long.byte 0x00 22.--28. 0x40 " DEVADDR ,Device address"
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSPDDEV ,Low-speed device" "No low speed,Low speed"
|
|
newline
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "Out,In"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x20)==0x20)
|
|
group.long 0xDE500++0x03
|
|
line.long 0x00 "HC0_CHAR,Host Channel 0 Characteristics Register"
|
|
eventfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
hexmask.long.byte 0x00 22.--28. 0x40 " DEVADDR ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MC ,Multi count (MC) / error count" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSPDDEV ,Low-speed device" "No low speed,Low speed"
|
|
newline
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "Out,In"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
else
|
|
group.long 0xDE500++0x03
|
|
line.long 0x00 "HC0_CHAR,Host Channel 0 Characteristics Register"
|
|
eventfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
hexmask.long.byte 0x00 22.--28. 0x40 " DEVADDR ,Device address"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSPDDEV ,Low-speed device" "No low speed,Low speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
endif
|
|
endif
|
|
group.long 0xDE504++0x13
|
|
line.long 0x00 "HC0_SPLT,Host Channel 0 Split Control Register"
|
|
bitfld.long 0x00 31. " SPLTENA ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " COMPSPLT ,Do complete split" "No split,Split"
|
|
bitfld.long 0x00 14.--15. " XACTPOS ,Transaction position" "Mid,End,Begin,All"
|
|
newline
|
|
hexmask.long.byte 0x00 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x04 "HC0_INT,Host Channel 0 Interrupt Register"
|
|
bitfld.long 0x04 10. " DATATGLERR ,DATATGLERR" "No error,Error"
|
|
bitfld.long 0x04 9. " FRMOVRUN ,FRMOVRUN" "No overrun,Overrun"
|
|
eventfld.long 0x04 8. " BBLERR ,Babble error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 7. " XACTERR ,Transaction error" "No error,Error"
|
|
eventfld.long 0x04 5. " ACK ,Response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " NAK ,Response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 3. " STALL ,Response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " AHBERR ,AHB error" "No error,Error"
|
|
bitfld.long 0x04 1. " CHHLTD ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x04 0. " XFERCOMPL ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x08 "HC0_INTMSK,Host Channel 0 Interrupt Mask Register"
|
|
bitfld.long 0x08 10. " DATATGLERRMSK ,Data toggle error mask" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " FRMOVRUNMSK ,Frame overrun mask" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " BBLERRMSK ,Babble error mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " XACTERRMSK ,Transaction error mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " ACKMSK ,ACK response received/transmitted interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " NAKMSK ,NAK response received interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 3. " STALLMSK ,STALL response received interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " AHBERRMSK ,AHB error mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CHHLTDMSK ,Channel halted mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 0. " XFERCOMPLMSK ,Transfer completed mask" "Not masked,Masked"
|
|
line.long 0x0C "HC0_TSIZ,Host Channel 0 Transfer Size Register"
|
|
bitfld.long 0x0C 29.--30. " PID ,Type of the initial transaction" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x0C 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x0C 0.--18. 1. " XFERSIZE ,Transfer size"
|
|
line.long 0x10 "HC0_DMAADDR,Host Channel 0 DMA Address Register"
|
|
newline
|
|
else
|
|
hgroup.long 0xDE400++0x03
|
|
hide.long 0x00 "HCFG,Host Configuration Register"
|
|
hgroup.long 0xDE404++0x03
|
|
hide.long 0x00 "HFIR,Host Frame Interval Register"
|
|
hgroup.long 0xDE408++0x03
|
|
hide.long 0x00 "HFNUM,Host Frame Number/Frame Time Remaining Register"
|
|
hgroup.long 0xDE410++0x03
|
|
hide.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
hgroup.long 0xDE414++0x03
|
|
hide.long 0x00 "HAINT,Host All Channels Interrupt Register"
|
|
hgroup.long 0xDE440++0x03
|
|
hide.long 0x00 "HPRT,Host Port Control and Status Register"
|
|
hgroup.long 0xDE500++0x03
|
|
hide.long 0x00 "HC0_CHAR,Host Channel 0 Characteristics Register"
|
|
hgroup.long 0xDE504++0x03
|
|
hide.long 0x00 "HC0_SPLT,Host Channel 0 Split Control Register"
|
|
hgroup.long 0xDE508++0x03
|
|
hide.long 0x00 "HC0_INT,Host Channel 0 Interrupt Register"
|
|
hgroup.long 0xDE50C++0x03
|
|
hide.long 0x00 "HC0_INTMSK,Host Channel 0 Interrupt Mask Register"
|
|
hgroup.long 0xDE510++0x03
|
|
hide.long 0x00 "HC0_TSIZ,Host Channel 0 Transfer Size Register"
|
|
hgroup.long 0xDE514++0x03
|
|
hide.long 0x00 "HC0_DMAADDR,Host Channel 0 DMA Address Register"
|
|
newline
|
|
endif
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x00)
|
|
if (((per.l(ad:0x40022000+0xDE800))&0x08)==0x08)
|
|
group.long 0xDE800++0x03
|
|
line.long 0x00 "DCFG,Device Configuration Register"
|
|
bitfld.long 0x00 26.--31. " RESVALID ,Resume validation period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " ERRATICINTMSK ,ERRATICINTMSK" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " XCVRDLY ,XCVRDLY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " ENDEVOUTNAK ,Enable device OUT NAK" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--12. " PERFRINT ,Periodic frame interval" "80%,85%,90%,95%"
|
|
hexmask.long.byte 0x00 4.--10. 0x10 " DEVADDR ,Device address"
|
|
newline
|
|
bitfld.long 0x00 3. " ENA32KHZSUSP ,Enable 32 kHz suspend mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NZSTSOUTHSHK ,Non-zero-length status OUT handshake" "No handshake,Handshake"
|
|
bitfld.long 0x00 0.--1. " DEVSPD ,Device speed" "High speed,Full speed,Low speed,Full speed"
|
|
else
|
|
group.long 0xDE800++0x03
|
|
line.long 0x00 "DCFG,Device Configuration Register"
|
|
bitfld.long 0x00 15. " ERRATICINTMSK ,ERRATICINTMSK" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " XCVRDLY ,XCVRDLY" "0,1"
|
|
bitfld.long 0x00 13. " ENDEVOUTNAK ,Enable device OUT NAK" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PERFRINT ,Periodic frame interval" "80%,85%,90%,95%"
|
|
hexmask.long.byte 0x00 4.--10. 0x10 " DEVADDR ,Device address"
|
|
bitfld.long 0x00 3. " ENA32KHZSUSP ,Enable 32 kHz suspend mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " NZSTSOUTHSHK ,Non-zero-length status OUT handshake" "No handshake,Handshake"
|
|
bitfld.long 0x00 0.--1. " DEVSPD ,Device speed" "High speed,Full speed,Low speed,Full speed"
|
|
endif
|
|
group.long 0xDE804++0x03
|
|
line.long 0x00 "DCTL,Device Control Register"
|
|
bitfld.long 0x00 16. " NAKONBBLE ,NAK on babble error" "No error,Error"
|
|
bitfld.long 0x00 15. " IGNRFRMNUM ,Ignore frame number for isochronous end points" "Not ignored,Ignored"
|
|
bitfld.long 0x00 11. " PWRONPRGDONE ,Power-on programming done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 10. " CGOUTNAK ,Clear global OUT NAK" "No clear,Clear"
|
|
bitfld.long 0x00 9. " SGOUTNAK ,Set global OUT NAK" "No set,Set"
|
|
bitfld.long 0x00 8. " CGNPINNAK ,Clear global non-periodic IN NAK" "No clear,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " SGNPINNAK ,Set global non-periodic IN NAK" "No set,Set"
|
|
bitfld.long 0x00 4.--6. " TSTCTL ,Test control" "Disabled,Test J,Test K,Test SE0 NAK,Test packet,Test force enable,?..."
|
|
rbitfld.long 0x00 3. " GOUTNAKSTS ,Global OUT NAK status" "Handshake sent,No data written"
|
|
newline
|
|
rbitfld.long 0x00 2. " GNPINNAKSTS ,Global non-periodic IN NAK status" "Handshake sent,NAK handshake sent"
|
|
bitfld.long 0x00 1. " SFTDISCON ,Soft disconnect" "Not disconnected,Disconnected"
|
|
bitfld.long 0x00 0. " RMTWKUPSIG ,Remote wakeup signaling" "No signaling,Signaling"
|
|
rgroup.long 0xDE808++0x03
|
|
line.long 0x00 "DSTS,Device Status Register"
|
|
bitfld.long 0x00 22.--23. " DEVLNSTS ,Device line status" ",D-,D+,?..."
|
|
hexmask.long.word 0x00 8.--21. 1. " SOFFN ,Frame or microframe number of the received SOF"
|
|
bitfld.long 0x00 3. " ERRTICERR ,Erratic error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" "High speed,Full speed,Low speed,Full speed"
|
|
bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended"
|
|
group.long 0xDE810++0x07
|
|
line.long 0x00 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
|
|
bitfld.long 0x00 13. " NAKMSK ,NAK interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " TXFIFOUNDRNMSK ,Fifo underrun mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " INEPNAKEFFMSK ,IN endpoint NAK effective mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 5. " INTKNEPMISMSK ,IN token received with EP mismatch mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " INTKNTXFEMPMSK ,IN token received when TxFIFO empty mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " TIMEOUTMSK ,Timeout condition mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 2. " AHBERRMSK ,AHB error mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EPDISBLDMSK ,Endpoint disabled interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " XFERCOMPLMSK ,Transfer completed interrupt mask" "Not masked,Masked"
|
|
line.long 0x04 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
|
|
bitfld.long 0x04 13. " NAKMSK ,NAK interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " BBLEERRMSK ,Babble error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " OUTPKTERRMSK ,OUT packet error mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 6. " BACK2BACKSETUP ,Back-to-back SETUP packets received mask" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " STSPHSERCVDMSK ,Status phase received mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " OUTTKNEPDISMSK ,OUT token received when endpoint disabled mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 3. " SETUPMSK ,SETUP phase done mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " AHBERRMSK ,AHB error mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " EPDISBLDMSK ,Endpoint disabled interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFERCOMPLMSK ,Transfer completed interrupt mask" "Not masked,Masked"
|
|
rgroup.long 0xDE818++0x03
|
|
line.long 0x00 "DAINT,Device All Endpoints Interrupt Register"
|
|
bitfld.long 0x00 22. " OUTEPINT6 ,OUTEPINT6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " OUTEPINT5 ,OUTEPINT5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " OUTEPINT4 ,OUTEPINT4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " OUTEPINT3 ,OUTEPINT3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " OUTEPINT2 ,OUTEPINT2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " OUTEPINT1 ,OUTEPINT1" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. " OUTEPINT0 ,OUTEPINT0" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. " INEPINT6 ,INEPINT6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INEPINT5 ,INEPINT5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INEPINT4 ,INEPINT4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " INEPINT3 ,INEPINT3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INEPINT2 ,INEPINT2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INEPINT1 ,INEPINT1" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " INEPINT0 ,INEPINT0" "No interrupt,Interrupt"
|
|
group.long 0xDE81C++0x03
|
|
line.long 0x00 "DAINTMSK,Device All Endpoints Interrupt Mask Register"
|
|
bitfld.long 0x00 22. " OUTEPMSK6 ,OUTEPMSK6" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " OUTEPMSK5 ,OUTEPMSK5" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " OUTEPMSK4 ,OUTEPMSK4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " OUTEPMSK3 ,OUTEPMSK3" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " OUTEPMSK2 ,OUTEPMSK2" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " OUTEPMSK1 ,OUTEPMSK1" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " OUTEPMSK0 ,OUTEPMSK0" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " INEPMSK6 ,INEPMSK6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " INEPMSK5 ,INEPMSK5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " INEPMSK4 ,INEPMSK4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " INEPMSK3 ,INEPMSK3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " INEPMSK2 ,INEPMSK2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " INEPMSK1 ,INEPMSK1" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 0. " INEPMSK0 ,INEPMSK0" "Not masked,Masked"
|
|
group.long 0xDE828++0x07
|
|
line.long 0x00 "DVBUSDIS,Device VBUS Discharge Time Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DVBUSDIS ,Device VBUS discharge time"
|
|
line.long 0x04 "DVBUSPULSE,Device VBUS Pulsing Time Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DVBUSPULSE ,Device VBUS pulsing time"
|
|
group.long 0xDE830++0x07
|
|
line.long 0x00 "DTHRCTL,Device Threshold Control Register"
|
|
bitfld.long 0x00 27. " ARBPRKEN ,Arbiter parking enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 17.--25. 1. " RXTHRLEN ,Receive threshold length"
|
|
bitfld.long 0x00 16. " RXTHREN ,Receive threshold enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " AHBTHRRATIO ,AHB threshold ratio" "MAC trsh,MAC trsh/2,MAC trsh/4,MAC trsh/8"
|
|
hexmask.long.word 0x00 2.--10. 1. " TXTHRLEN ,Transmit threshold length"
|
|
bitfld.long 0x00 1. " ISOTHREN ,ISO IN endpoints threshold enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " NONISOTHREN ,Non-ISO IN endpoints threshold enable" "Disabled,Enabled"
|
|
newline
|
|
line.long 0x04 "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
bitfld.long 0x04 15. " DIEPEMPMSK[15] ,IN EP 15 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " [14] ,IN EP 14 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " [13] ,IN EP 13 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " [12] ,IN EP 12 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,IN EP 11 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " [10] ,IN EP 10 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [9] ,IN EP 9 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [8] ,IN EP 8 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,IN EP 7 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [6] ,IN EP 6 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [5] ,IN EP 5 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,IN EP 4 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,IN EP 3 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [2] ,IN EP 2 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " [1] ,IN EP 1 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,IN EP 0 Tx FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
group.long 0xDE900++0x03
|
|
line.long 0x00 "DIEP0CTL,Device Control IN Endpoint 0 Control Register"
|
|
eventfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No clear,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,Handshake" "No handshake,Handshake"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "0,?..."
|
|
bitfld.long 0x00 17. " NAKSTS ,NAK status" "No-NAK handshakes,NAK handshakes"
|
|
rbitfld.long 0x00 15. " USBACTEP ,USB active endpoint" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " MPS ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
group.long 0xDE908++0x03
|
|
line.long 0x00 "DIEP0INT,Device IN Endpoint 0 Interrupt Register"
|
|
bitfld.long 0x00 13. " NAKINTRPT ,NAKINTRPT" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " BBLEERR ,NAK interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " PKTDRPSTS ,Packet drop status" "Not dropped,Dropped"
|
|
newline
|
|
bitfld.long 0x00 8. " TXFIFOUNDRN ,Fifo underrun" "No underrun,Underrun"
|
|
rbitfld.long 0x00 7. " TXFEMP ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " INEPNAKEFF ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " INTKNEPMIS ,IN token received with EP mismatch" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTKNTXFEMP ,IN token received when TxFIFO is empty" "Not empty,Empty"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Core has detected a timeout condition on the USB For the last IN token on this endpoint" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 2. " AHBERR ,AHB error" "No error,Error"
|
|
bitfld.long 0x00 1. " EPDISBLD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " XFERCOMPL ,Transfer completed interrupt" "No interrupt,Interrupt"
|
|
group.long 0xDE910++0x07
|
|
line.long 0x00 "DIEP0TSIZ,Device IN Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 19.--20. " PKTCNT ,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFERSIZE ,Transfer size"
|
|
line.long 0x04 "DIEP0DMAADDR,Device IN Endpoint 0 DMA Address Register"
|
|
rgroup.long 0xDE918++0x03
|
|
line.long 0x00 "DIEP0TXFSTS,Device IN Endpoint Transmit FIFO Status Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPCAVAIL ,IN endpoint TxFIFO space avail"
|
|
if (((per.l(ad:0x40022000+0xDE920))&0xC0000)==(0x80000||0xC0000))
|
|
group.long 0xDE920++0x03
|
|
line.long 0x00 "DIEP0_CTL,Device Control IN Endpoint 1 Control Register"
|
|
eventfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SETD1PIDOF ,Set DATA1 PID" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 28. " SETD0PIDEF ,Set DATA0 PID" "Even,Odd"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No set,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No clear,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x00 21. " STALL ,Handshake" "Not stalled,Stalled"
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0/Even,DATA1/Odd"
|
|
bitfld.long 0x00 15. " USBACTEP ,USB active endpoint" "Inactive,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
else
|
|
group.long 0xDE920++0x03
|
|
line.long 0x00 "DIEP0_CTL,Device Control IN Endpoint 1 Control Register"
|
|
eventfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No clear,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x00 21. " STALL ,Handshake" "Not stalled,Stalled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes"
|
|
bitfld.long 0x00 15. " USBACTEP ,USB active endpoint" "Inactive,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
endif
|
|
group.long 0xDE928++0x03
|
|
line.long 0x00 "DIEP0_INT,Device IN Endpoint 1 Interrupt Register"
|
|
bitfld.long 0x00 13. " NAKINTRPT ,NAKINTRPT" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " BBLEERR ,NAK interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " PKTDRPSTS ,Packet drop status" "Not dropped,Dropped"
|
|
newline
|
|
bitfld.long 0x00 8. " TXFIFOUNDRN ,Fifo underrun" "No underrun,Underrun"
|
|
rbitfld.long 0x00 7. " TXFEMP ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " INEPNAKEFF ,IN endpoint NAK effective interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " INTKNEPMIS ,IN token received with EP mismatch interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTKNTXFEMP ,IN token received when TxFIFO is empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Timeout condition on the USB For the last IN token on this endpoint" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 2. " AHBERR ,AHB error" "No error,Error"
|
|
bitfld.long 0x00 1. " EPDISBLD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " XFERCOMPL ,Transfer completed interrupt" "No interrupt,Interrupt"
|
|
group.long 0xDE930++0x07
|
|
line.long 0x00 "DIEP0_TSIZ,Device IN Endpoint 1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MC ,MC" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFERSIZE ,Transfer size"
|
|
line.long 0x04 "DIEP0_DMAADDR,Device IN Endpoint 1 DMA Address Register"
|
|
rgroup.long 0xDE938++0x03
|
|
line.long 0x00 "DIEP0_DTXFSTS,Device IN Endpoint Transmit FIFO Status Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPCAVAIL ,IN endpoint TxFIFO space avail"
|
|
group.long 0xDEB00++0x03
|
|
line.long 0x00 "DOEP0CTL,Device Control OUT Endpoint 0 Control Register"
|
|
eventfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No clear,Clear"
|
|
eventfld.long 0x00 21. " STALL ,Handshake" "Not stalled,Stalled"
|
|
bitfld.long 0x00 20. " SNP ,Snoop mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "0,?..."
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes"
|
|
rbitfld.long 0x00 15. " USBACTEP ,USB active endpoint" "Inactive,Active"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " MPS ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
group.long 0xDEB08++0x03
|
|
line.long 0x00 "DOEP0INT,Device OUT Endpoint 0 Interrupt Register"
|
|
bitfld.long 0x00 15. " STUPPKTRCVD ,STUPPKTRCVD" "0,1"
|
|
bitfld.long 0x00 13. " NAKINTRPT ,NAKINTRPT" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " BBLEERR ,NAK interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " PKTDRPSTS ,Packet drop status" "Not dropped,Dropped"
|
|
bitfld.long 0x00 8. " OUTPKTERR ,OUT packet error" "No error,Error"
|
|
bitfld.long 0x00 6. " BACK2BACKSETUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x00 5. " STSPHSERCVD ,Status phase received for control write interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " OUTTKNEPDIS ,OUT token received when endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " SETUP ,Phase done" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 2. " AHBERR ,AHB error" "No error,Error"
|
|
bitfld.long 0x00 1. " EPDISBLD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " XFERCOMPL ,Transfer completed interrupt" "No interrupt,Interrupt"
|
|
group.long 0xDEB10++0x07
|
|
line.long 0x00 "DOEP0TSIZ,Device OUT Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " SUPCNT ,SETUP packet count" ",1 packet,2 packets,3 packets"
|
|
bitfld.long 0x00 19. " PKTCNT ,Packet count" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFERSIZE ,Transfer size"
|
|
line.long 0x04 "DOEP0DMAADDR,Device OUT Endpoint 0 DMA Address Register"
|
|
if (((per.l(ad:0x40022000+0xDE920))&0xC0000)==(0x80000||0xC0000))
|
|
group.long 0xDEB20++0x03
|
|
line.long 0x00 "DOEP0_CTL,Device Control OUT Endpoint 1 Control Register"
|
|
eventfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SETD1PIDOF ,Set DATA1 PID" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 28. " SETD0PIDEF ,Set DATA0 PID" "Even,Odd"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not set,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No clear,Clear"
|
|
newline
|
|
eventfld.long 0x00 21. " STALL ,Handshake" "Not stalled,Stalled"
|
|
bitfld.long 0x00 20. " SNP ,Snoop mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBACTEP ,USB active endpoint" "Inactive,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
else
|
|
group.long 0xDEB20++0x03
|
|
line.long 0x00 "DOEP0_CTL,Device Control OUT Endpoint 1 Control Register"
|
|
eventfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No clear,Clear"
|
|
eventfld.long 0x00 21. " STALL ,Handshake" "Not stalled,Stalled"
|
|
bitfld.long 0x00 20. " SNP ,Snoop mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes"
|
|
bitfld.long 0x00 15. " USBACTEP ,USB active endpoint" "Inactive,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPS ,Maximum packet size"
|
|
endif
|
|
group.long 0xDEB28++0x03
|
|
line.long 0x00 "DOEP0_INT,Device OUT Endpoint 1 Interrupt Register"
|
|
bitfld.long 0x00 15. " STUPPKTRCVD ,STUPPKTRCVD" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " NAKINTRPT ,NAKINTRPT" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " BBLEERR ,NAK interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " PKTDRPSTS ,Packet drop status" "Not dropped,Dropped"
|
|
bitfld.long 0x00 8. " OUTPKTERR ,OUT packet error" "No error,Error"
|
|
bitfld.long 0x00 6. " BACK2BACKSETUP ,Back-to-back SETUP packets received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " STSPHSERCVD ,Status phase received for control write interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " OUTTKNEPDIS ,OUT token received when endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " SETUP ,Phase done interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 2. " AHBERR ,AHB error" "No error,Error"
|
|
bitfld.long 0x00 1. " EPDISBLD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " XFERCOMPL ,Transfer completed interrupt" "No interrupt,Interrupt"
|
|
group.long 0xDEB30++0x07
|
|
line.long 0x00 "DOEP0_TSIZ,Device OUT Endpoint 1 Transfer Size Register"
|
|
rbitfld.long 0x00 29.--30. " RXDPID ,RXDPID" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " PKTCNT ,Transfer size"
|
|
line.long 0x04 "DOEP0_DMAADDR,Device OUT Endpoint 1 DMA Address Register"
|
|
newline
|
|
else
|
|
hgroup.long 0xDE800++0x03
|
|
hide.long 0x00 "DCFG,Device Configuration Register"
|
|
hgroup.long 0xDE804++0x03
|
|
hide.long 0x00 "DCTL,Device Control Register"
|
|
hgroup.long 0xDE808++0x03
|
|
hide.long 0x00 "DSTS,Device Status Register"
|
|
hgroup.long 0xDE810++0x03
|
|
hide.long 0x00 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
|
|
hgroup.long 0xDE814++0x03
|
|
hide.long 0x00 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
|
|
hgroup.long 0xDE818++0x03
|
|
hide.long 0x00 "DAINT,Device All Endpoints Interrupt Register"
|
|
hgroup.long 0xDE81C++0x03
|
|
hide.long 0x00 "DAINTMSK,Device All Endpoints Interrupt Mask Register"
|
|
hgroup.long 0xDE828++0x03
|
|
hide.long 0x00 "DVBUSDIS,Device VBUS Discharge Time Register"
|
|
hgroup.long 0xDE82C++0x03
|
|
hide.long 0x00 "DVBUSPULSE,Device VBUS Pulsing Time Register"
|
|
hgroup.long 0xDE830++0x03
|
|
hide.long 0x00 "DTHRCTL,Device Threshold Control Register"
|
|
hgroup.long 0xDE834++0x03
|
|
hide.long 0x00 "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
hgroup.long 0xDE908++0x03
|
|
hide.long 0x00 "DIEP0INT,Device IN Endpoint 0 Interrupt Register"
|
|
hgroup.long 0xDE910++0x03
|
|
hide.long 0x00 "DIEP0TSIZ,Device IN Endpoint 0 Transfer Size Register"
|
|
hgroup.long 0xDE914++0x03
|
|
hide.long 0x00 "DIEP0DMAADDR,Device IN Endpoint 0 DMA Address Register"
|
|
hgroup.long 0xDE918++0x03
|
|
hide.long 0x00 "DIEP0TXFSTS,Device IN Endpoint Transmit FIFO Status Register 0"
|
|
hgroup.long 0xDE920++0x03
|
|
hide.long 0x00 "DIEP0_CTL,Device Control IN Endpoint 1 Control Register"
|
|
hgroup.long 0xDE928++0x03
|
|
hide.long 0x00 "DIEP0_INT,Device IN Endpoint 1 Interrupt Register"
|
|
hgroup.long 0xDE930++0x03
|
|
hide.long 0x00 "DIEP0_TSIZ,Device IN Endpoint 1 Transfer Size Register"
|
|
hgroup.long 0xDE934++0x03
|
|
hide.long 0x00 "DIEP0_DMAADDR,Device IN Endpoint 1 DMA Address Register"
|
|
hgroup.long 0xDE938++0x03
|
|
hide.long 0x00 "DIEP0_DTXFSTS,Device IN Endpoint Transmit FIFO Status Register 1"
|
|
hgroup.long 0xDEB00++0x03
|
|
hide.long 0x00 "DOEP0CTL,Device Control OUT Endpoint 0 Control Register"
|
|
hgroup.long 0xDEB08++0x03
|
|
hide.long 0x00 "DOEP0INT,Device OUT Endpoint 0 Interrupt Register"
|
|
hgroup.long 0xDEB10++0x03
|
|
hide.long 0x00 "DOEP0TSIZ,Device OUT Endpoint 0 Transfer Size Register"
|
|
hgroup.long 0xDEB14++0x03
|
|
hide.long 0x00 "DOEP0DMAADDR,Device OUT Endpoint 0 DMA Address Register"
|
|
hgroup.long 0xDEB20++0x03
|
|
hide.long 0x00 "DOEP0_CTL,Device Control OUT Endpoint 1 Control Register"
|
|
hgroup.long 0xDEB28++0x03
|
|
hide.long 0x00 "DOEP0_INT,Device OUT Endpoint 1 Interrupt Register"
|
|
hgroup.long 0xDEB30++0x03
|
|
hide.long 0x00 "DOEP0_TSIZ,Device OUT Endpoint 1 Transfer Size Register"
|
|
hgroup.long 0xDEB34++0x03
|
|
hide.long 0x00 "DOEP0_DMAADDR,Device OUT Endpoint 1 DMA Address Register"
|
|
newline
|
|
endif
|
|
group.long 0xDEE00++0x03
|
|
line.long 0x00 "PCGCCTL,Power And Clock Gating Control Register"
|
|
rbitfld.long 0x00 8. " RESETAFTERSUSP ,RESETAFTERSUSP" "Not suspended,Suspended"
|
|
rbitfld.long 0x00 7. " L1SUSPENDED ,L1SUSPENDED" "Not suspended,Suspended"
|
|
rbitfld.long 0x00 6. " PHYSLEEP ,PHYSLEEP" "No sleep,Sleep"
|
|
newline
|
|
bitfld.long 0x00 3. " RSTPDWNMODULE ,Reset power-down modules" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PWRCLMP ,Power clamp" "Turned off,Turned on"
|
|
bitfld.long 0x00 1. " GATEHCLK ,Gate Hclk" "Not gated,Gated"
|
|
newline
|
|
bitfld.long 0x00 0. " STOPPCLK ,Stop Pclk" "Not stopped,Stopped"
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x20)==0x00)
|
|
group.long 0xDF000++0x03
|
|
line.long 0x00 "FIFO0D0,Device EP 0/Host Channel 0 FIFO"
|
|
group.long 0xE0000++0x03
|
|
line.long 0x00 "FIFO1D0,Device EP 1/Host Channel 1 FIFO"
|
|
group.long 0xE1000++0x03
|
|
line.long 0x00 "FIFO2D0,Device EP 2/Host Channel 2 FIFO"
|
|
group.long 0xE2000++0x03
|
|
line.long 0x00 "FIFO3D0,Device EP 3/Host Channel 3 FIFO"
|
|
group.long 0xE3000++0x03
|
|
line.long 0x00 "FIFO4D0,Device EP 4/Host Channel 4 FIFO"
|
|
group.long 0xE4000++0x03
|
|
line.long 0x00 "FIFO5D0,Device EP 5/Host Channel 5 FIFO"
|
|
group.long 0xE5000++0x03
|
|
line.long 0x00 "FIFO6D0,Device EP 6/Host Channel 6 FIFO"
|
|
else
|
|
hgroup.long 0xDF000++0x03
|
|
hide.long 0x00 "FIFO0D0,Device EP 0/Host Channel 0 FIFO"
|
|
hgroup.long 0xE0000++0x03
|
|
hide.long 0x00 "FIFO1D0,Device EP 1/Host Channel 1 FIFO"
|
|
hgroup.long 0xE1000++0x03
|
|
hide.long 0x00 "FIFO2D0,Device EP 2/Host Channel 2 FIFO"
|
|
hgroup.long 0xE2000++0x03
|
|
hide.long 0x00 "FIFO3D0,Device EP 3/Host Channel 3 FIFO"
|
|
hgroup.long 0xE3000++0x03
|
|
hide.long 0x00 "FIFO4D0,Device EP 4/Host Channel 4 FIFO"
|
|
hgroup.long 0xE4000++0x03
|
|
hide.long 0x00 "FIFO5D0,Device EP 5/Host Channel 5 FIFO"
|
|
hgroup.long 0xE5000++0x03
|
|
hide.long 0x00 "FIFO6D0,Device EP 6/Host Channel 6 FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40022000+0xDE000))&0x200000)==0x200000)
|
|
if (((per.l(ad:0x40022000+0xDE008))&0x20)==0x00)
|
|
group.long 0xE6000++0x03
|
|
line.long 0x00 "FIFO7D0,Host Channel 7 FIFO"
|
|
group.long 0xE7000++0x03
|
|
line.long 0x00 "FIFO8D0,Host Channel 8 FIFO"
|
|
group.long 0xE8000++0x03
|
|
line.long 0x00 "FIFO9D0,Host Channel 9 FIFO"
|
|
group.long 0xE9000++0x03
|
|
line.long 0x00 "FIFO10D0,Host Channel 10 FIFO"
|
|
group.long 0xEA000++0x03
|
|
line.long 0x00 "FIFO11D0,Host Channel 11 FIFO"
|
|
group.long 0xEB000++0x03
|
|
line.long 0x00 "FIFO12D0,Host Channel 12 FIFO"
|
|
group.long 0xEC000++0x03
|
|
line.long 0x00 "FIFO13D0,Host Channel 13 FIFO"
|
|
else
|
|
hgroup.long 0xE6000++0x03
|
|
hide.long 0x00 "FIFO7D0,Host Channel 7 FIFO"
|
|
hgroup.long 0xE7000++0x03
|
|
hide.long 0x00 "FIFO8D0,Host Channel 8 FIFO"
|
|
hgroup.long 0xE8000++0x03
|
|
hide.long 0x00 "FIFO9D0,Host Channel 9 FIFO"
|
|
hgroup.long 0xE9000++0x03
|
|
hide.long 0x00 "FIFO10D0,Host Channel 10 FIFO"
|
|
hgroup.long 0xEA000++0x03
|
|
hide.long 0x00 "FIFO11D0,Host Channel 11 FIFO"
|
|
hgroup.long 0xEB000++0x03
|
|
hide.long 0x00 "FIFO12D0,Host Channel 12 FIFO"
|
|
hgroup.long 0xEC000++0x03
|
|
hide.long 0x00 "FIFO13D0,Host Channel 13 FIFO"
|
|
endif
|
|
else
|
|
hgroup.long 0xE6000++0x03
|
|
hide.long 0x00 "FIFO7D0,Host Channel 7 FIFO"
|
|
hgroup.long 0xE7000++0x03
|
|
hide.long 0x00 "FIFO8D0,Host Channel 8 FIFO"
|
|
hgroup.long 0xE8000++0x03
|
|
hide.long 0x00 "FIFO9D0,Host Channel 9 FIFO"
|
|
hgroup.long 0xE9000++0x03
|
|
hide.long 0x00 "FIFO10D0,Host Channel 10 FIFO"
|
|
hgroup.long 0xEA000++0x03
|
|
hide.long 0x00 "FIFO11D0,Host Channel 11 FIFO"
|
|
hgroup.long 0xEB000++0x03
|
|
hide.long 0x00 "FIFO12D0,Host Channel 12 FIFO"
|
|
hgroup.long 0xEC000++0x03
|
|
hide.long 0x00 "FIFO13D0,Host Channel 13 FIFO"
|
|
endif
|
|
group.long 0xFE000++0x03
|
|
line.long 0x00 "FIFORAM0,Direct Access To Data FIFO RAM For Debugging"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDIO (SDIO Host Controller)"
|
|
base ad:0x400F1000
|
|
width 15.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SDMASYSADDR,SDMA System Address Register"
|
|
line.long 0x04 "BLKSIZE,Block Size And Block Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKSCNTFORCURRTFR ,Blocks count for current transfer"
|
|
bitfld.long 0x04 12.--14. " HSTSDMABUFSIZE ,Host SDMA buffer size" "4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB"
|
|
hexmask.long.word 0x04 0.--11. 1. " TFRBLKSIZE ,Transfer block size, specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53"
|
|
line.long 0x08 "CMDARG1,SD Command Argument Register"
|
|
if (((per.l(ad:0x400F1000+0x0C))&0x20)==0x20)
|
|
if (((per.l(ad:0x400F1000+0x40))&0x400000)==0x400000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TFRMODE,Transfer Mode and Command Register"
|
|
bitfld.long 0x00 24.--29. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. " CMDTYPE ,Command type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x00 21. " DATPRESSEL ,Data present select" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 20. " CMDINDXCHKEN ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMDCRCCHKEN ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " RESPTYPESEL ,Response type select" "NORESP,RESP136,RESP48,BUSYAFTRESP"
|
|
newline
|
|
bitfld.long 0x00 5. " MULTSINGBLKSEL ,Multiple or single block data transfer selection" "Single,Multi"
|
|
bitfld.long 0x00 4. " DATDIRSEL ,Data transfer direction select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " AUTOCMDEN ,Auto command enable" "Disabled,CMD12 Enabled,CMD23 Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " BLKCNTEN ,Block count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TFRMODE,Transfer Mode and Command Register"
|
|
bitfld.long 0x00 24.--29. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. " CMDTYPE ,Command type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x00 21. " DATPRESSEL ,Data present select" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 20. " CMDINDXCHKEN ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMDCRCCHKEN ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " RESPTYPESEL ,Response type select" "NORESP,RESP136,RESP48,BUSYAFTRESP"
|
|
newline
|
|
bitfld.long 0x00 5. " MULTSINGBLKSEL ,Multiple or single block data transfer selection" "Single,Multi"
|
|
bitfld.long 0x00 4. " DATDIRSEL ,Data transfer direction select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " AUTOCMDEN ,Auto command enable" "Disabled,CMD12 Enabled,CMD23 Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " BLKCNTEN ,Block count enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400F1000+0x40))&0x400000)==0x400000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TFRMODE,Transfer Mode and Command Register"
|
|
bitfld.long 0x00 24.--29. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. " CMDTYPE ,Command type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x00 21. " DATPRESSEL ,Data present select" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 20. " CMDINDXCHKEN ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMDCRCCHKEN ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " RESPTYPESEL ,Response type select" "NORESP,RESP136,RESP48,BUSYAFTRESP"
|
|
newline
|
|
bitfld.long 0x00 5. " MULTSINGBLKSEL ,Multiple or single block data transfer selection" "Single,Multi"
|
|
bitfld.long 0x00 4. " DATDIRSEL ,Data transfer direction select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " AUTOCMDEN ,Auto command enable" "Disabled,CMD12 Enabled,CMD23 Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TFRMODE,Transfer Mode and Command Register"
|
|
bitfld.long 0x00 24.--29. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. " CMDTYPE ,Command type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x00 21. " DATPRESSEL ,Data present select" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 20. " CMDINDXCHKEN ,Command index check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMDCRCCHKEN ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " RESPTYPESEL ,Response type select" "NORESP,RESP136,RESP48,BUSYAFTRESP"
|
|
newline
|
|
bitfld.long 0x00 5. " MULTSINGBLKSEL ,Multiple or single block data transfer selection" "Single,Multi"
|
|
bitfld.long 0x00 4. " DATDIRSEL ,Data transfer direction select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " AUTOCMDEN ,Auto command enable" "Disabled,CMD12 Enabled,CMD23 Enabled,?..."
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RESP0,Response0 And Response1 Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RESP2,Response2 And Response3 Register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RESP4,Response4 And Response5 Register"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RESP6,Response6 And Response7 Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BUFDATPORT,Buffer Data Register"
|
|
newline
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 28. " DAT7TO4SIGLVL[3] ,DAT[7] line signal level" "Low,High"
|
|
bitfld.long 0x00 27. " [2] ,DAT[6] line signal level" "Low,High"
|
|
bitfld.long 0x00 26. " [1] ,DAT[5] line signal level" "Low,High"
|
|
bitfld.long 0x00 25. " [0] ,DAT[4] line signal level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " CMDSIGLVL ,Command line signal level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " DAT3TO0SIGLVL[3] ,DAT[3] line signal level" "Low,High"
|
|
bitfld.long 0x00 22. " [2] ,DAT[2] line signal level" "Low,High"
|
|
bitfld.long 0x00 21. " [1] ,DAT[1] line signal level" "Low,High"
|
|
bitfld.long 0x00 20. " [0] ,DAT[0] line signal level" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " WRPROTSWPINLVL ,Write protect switch pin level" "Write protected,Write enabled"
|
|
bitfld.long 0x00 18. " CARDDETPINLVL ,Card detect pin level" "Write protected,Write enabled"
|
|
bitfld.long 0x00 17. " CARDSTATESTABLE ,Card state stable status" "Not stable,Stable"
|
|
bitfld.long 0x00 16. " CARDINS ,Card inserted status" "Removed,Inserted"
|
|
newline
|
|
bitfld.long 0x00 11. " BUFRDEN ,Buffer read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BUFFERWRITEENABLE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RDTRANACT ,Read transfer active" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " WRTRANACT ,Write transfer active" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 3. " RETUNINGREQ ,Re-tuning request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " DATLINEACTIVE ,DAT line active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " CMDINHIBITDAT ,Command inhibit" "Inactive,Active"
|
|
bitfld.long 0x00 0. " CMDINHIBITCMD ,Command inhibit" "Inactive,Active"
|
|
newline
|
|
if (((per.l(ad:0x400F1000+0x28))&0xE00)==(0x00||0x02||0x04||0x06||0x08))
|
|
if (((per.l(ad:0x400F1000+0x28))&0x02)==0x02)
|
|
if (((per.l(ad:0x400F1000+0x40))&0x200000)==0x200000)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " INTATBLKGAP ,Interrupt at block gap" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detect signal detection" "SDCD,TSTLVL"
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
newline
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
bitfld.long 0x00 2. " HSEN ,High speed enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " INTATBLKGAP ,Interrupt at block gap" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detect signal detection" "SDCD,TSTLVL"
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
newline
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400F1000+0x40))&0x200000)==0x200000)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detetct signal detection" "SDCD,TSTLVL"
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
newline
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
bitfld.long 0x00 2. " HSEN ,High speed enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detetct signal detection" "SDCD,TSTLVL"
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
newline
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400F1000+0x28))&0x02)==0x02)
|
|
if (((per.l(ad:0x400F1000+0x40))&0x200000)==0x200000)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " INTATBLKGAP ,Interrupt at block gap" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBUSPOWER ,SD bus power" "Powered off,Powered on"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detetct signal detection" "SDCD,TSTLVL"
|
|
newline
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
newline
|
|
bitfld.long 0x00 2. " HSEN ,High speed enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " INTATBLKGAP ,Interrupt at block gap" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBUSPOWER ,SD bus power" "Powered off,Powered on"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detetct signal detection" "SDCD,TSTLVL"
|
|
newline
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400F1000+0x40))&0x200000)==0x200000)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detetct signal detection" "SDCD,TSTLVL"
|
|
newline
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
newline
|
|
bitfld.long 0x00 2. " HSEN ,High speed enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HOSTCTRL1,Host Control1 Power Block Gap And Wakeup-Up Control Register"
|
|
bitfld.long 0x00 26. " WKUPEVNTENONCRM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WKUPEVNTENONCINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WKUPEVNTENONCARDINT ,Wakeup event enable on card interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " BOOTACKCHK ,Boot ack check" "No check,Check"
|
|
bitfld.long 0x00 22. " ALTBOOTEN ,Alternate boot enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOTEN ,Boot enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " SPIMODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RDWAITCTRL ,Read wait control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTINUEREQ ,Continue request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " STOPATBLKGAPREQ ,Stop at block gap request" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HRDRST ,Hardware reset signal" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " SDBUSVOLTSEL ,SD bus voltage select" ",,,,,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 7. " CDSIGDET ,Card detetct signal detection" "SDCD,TSTLVL"
|
|
newline
|
|
bitfld.long 0x00 6. " CDTSTLVL ,Card detect test level" "No card,Card inserted"
|
|
bitfld.long 0x00 5. " EXTDATTRANWD ,Extended data transfer width" "8-bit,DATXFR"
|
|
bitfld.long 0x00 3.--4. " DMASEL ,DMA select" "SDMA,32-bit ADMA1,32-bit ADMA2,64-bit ADMA2"
|
|
newline
|
|
bitfld.long 0x00 1. " DATTRANWD ,Data transfer width 1-bit or 4-bit mode" "1-bit,4-bit"
|
|
bitfld.long 0x00 0. " LEDCTRL ,LED control" "Off,On"
|
|
endif
|
|
endif
|
|
endif
|
|
newline
|
|
group.long 0x2C++0x13
|
|
line.long 0x00 "CLOCKCTRL,Clock Control Timeout Control And Software Register"
|
|
bitfld.long 0x00 26. " SFTRSTDAT ,Software reset for DAT line" "No reset,Reset"
|
|
bitfld.long 0x00 25. " SFTRSTCMD ,Software reset for CMD line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SFTRSTA ,Software reset for all" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DATTOUTCNTVAL ,Data timeout counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFREQSEL ,SD_CLK frequency select"
|
|
bitfld.long 0x00 6.--7. " UPPSDCLKFRE ,Upper bits of SD_CLK frequency select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. " CLKGENSEL ,Clock generator select" "0,1"
|
|
bitfld.long 0x00 2. " SDCLKEN ,SDIO_CLK pin clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " INTCLKSTABLE ,Internal clock stable" "Not stable,Stable"
|
|
newline
|
|
bitfld.long 0x00 0. " INTCLKEN ,Internal clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "IFCR,Normal And Error Interrupt Status Register"
|
|
eventfld.long 0x04 28. " TARGETRESP ,Specific error STAT" "No error,Error"
|
|
eventfld.long 0x04 25. " ADMAERR ,ADMA error" "No error,Error"
|
|
eventfld.long 0x04 24. " AUTOCMDERR ,Auto CMD error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 23. " CURRENTLIMITERR ,Current limit error" "No error,Error"
|
|
eventfld.long 0x04 22. " DATENDBITERR ,Data end bit error" "No error,Error"
|
|
eventfld.long 0x04 21. " DATCRCERR ,Data CRC error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 20. " DATTOUTERR ,Data time-out error" "No error,Error"
|
|
eventfld.long 0x04 19. " CMDINDEXERR ,Command index error" "No error,Error"
|
|
eventfld.long 0x04 18. " CMDENDBITERR ,Command end bit error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " CMDCRCERR ,CMD CRC error" "No error,Error"
|
|
eventfld.long 0x04 16. " CMDTOUTERR ,Command timeout error" "No error,Error"
|
|
rbitfld.long 0x04 15. " ERRINT ,Error interrupt" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 14. " BOOTTERMINATE ,Boot terminate interrupt" "Not terminated,Terminated"
|
|
eventfld.long 0x04 13. " BOOTACKRCV ,Boot ack received" "Not received,Received"
|
|
rbitfld.long 0x04 12. " RETUNINGEVT ,Re-tunning event" "Not required,Required"
|
|
newline
|
|
rbitfld.long 0x04 8. " CARDINT ,Card interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 7. " CARDRM ,Card removal" "Not removed,Removed"
|
|
eventfld.long 0x04 6. " CARDINS ,Card insertion" "Not inserted,Inserted"
|
|
newline
|
|
eventfld.long 0x04 5. " BFRRDRDY ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x04 4. " BFRWRRDY ,Buffer write ready" "Not ready,Ready"
|
|
eventfld.long 0x04 3. " DMAINT ,DMA interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 2. " BLKGAPEVT ,Block gap event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 1. " TRANCOM ,Transfer complete" "Not completed,Completed"
|
|
eventfld.long 0x04 0. " CMDCOM ,Command complete" "Not completed,Completed"
|
|
line.long 0x08 "IFENC,Normal And Error Interrupt Status Enable Register"
|
|
bitfld.long 0x08 28. " TARGETRESPEN ,Target response/host error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " TUNINGERREN ,Tuning error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " ADMAERREN ,ADMA error status enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 24. " AUTOCMDERREN ,Auto CMD12 error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CURRENTLIMITERREN ,Current limit error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " DATENDBITERREN ,Data end bit error status enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " DATCRCERREN ,Data CRC error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " DATTOUTERREN ,Data timeout error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CMDINDEXERREN ,Command index error status enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " CMDENDBITERREN ,Command end bit error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CMDCRCERREN ,Command CRC error status enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " CMDTOUTERREN ,Command time-out error status enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " BOOTTERMINATEEN ,Boot terminate interrupt signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " BOOTACKRCVEN ,Boot ack received signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " RETUNINGEVTEN ,Re-tunning event signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 8. " CARDINTEN ,Card interrupt signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CARDRMEN ,Card removal signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CARDINSEN ,Card insertion signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " BUFRDRDYEN ,Buffer read ready signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " BUFWRRDYEN ,Buffer write ready signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " DMAINTEN ,DMA interrupt signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " BLKGAPEVTEN ,Block gap event signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TRANCOMEN ,Transfer complete signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CMDCOMEN ,Command complete signal enable" "Disabled,Enabled"
|
|
line.long 0x0C "IEN,Normal And Error Interrupt Signal Enable Register"
|
|
bitfld.long 0x0C 28. " TARGETRESPERRSEN ,Target response error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " TUNINGERRSIGNALENABLE ,Tuning error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " ADMAERRSEN ,ADMA error signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 24. " AUTOCMDERRSEN ,Auto CMD12 error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " CURRENTLIMITERRSEN ,Current limit error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " DATENDBITERRSEN ,Data end bit error signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " DATCRCERRSEN ,Data CRC error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " DATTOUTERRSEN ,Data timeout error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " CMDINDEXERRSEN ,Command index error signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 18. " CMDENDBITERRSEN ,Command end bit error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " CMDCRCERRSEN ,Command CRC error signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " CMDTOUTERRSEN ,Command timeout error signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " BOOTTERMINATESEN ,Boot terminate interrupt signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " BOOTACKRCVSEN ,Boot ack received signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " RETUNINGEVTSEN ,Re-tuning event signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. " CARDINTSEN ,Card interrupt signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " CARDREMSEN ,Card removal signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " CARDINSSEN ,Card insertion signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " BUFRDRDYSEN ,Buffer read ready signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " BUFWRRDYSEN ,Buffer write ready signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " DMAINTSEN ,DMA interrupt signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " BLKGAPEVTSEN ,Block gap event signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " TRANCOMSEN ,Transfer complete signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " CMDCOMSEN ,Command complete signal enable" "Disabled,Enabled"
|
|
line.long 0x10 "AC12ERRSTAT,AUTO CMD12 Error Status And Host Control2 Register"
|
|
bitfld.long 0x10 31. " PRSTVALEN ,Preset value enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ASYNCINTEN ,Asynchronous interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " SAMPCLKSEL ,Sampling clock select" "Fixed clock,Tuned clock"
|
|
newline
|
|
bitfld.long 0x10 22. " EXETUNING ,Execute tuning" "Not executed,Executed"
|
|
bitfld.long 0x10 20.--21. " DRVSTNSEL ,Driver strength select" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x10 19. " SIGEN1P8V ,Voltage 1.8V signal enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 16.--18. " UHSMODESEL ,UHS mode select" "SDR12,SDR25,SDR50,SDR104,DDR50,?..."
|
|
rbitfld.long 0x10 7. " CNIBAC12ERR ,Command not issued by auto CMD12 error" "Issued,Not issued"
|
|
rbitfld.long 0x10 4. " AC12INDEXERR ,Auto CMD index error" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x10 3. " AC12INDEXERR ,Auto CMD index error" "No error,Error"
|
|
rbitfld.long 0x10 2. " AC12CRCERR ,Auto CMD CRC error" "No error,Error"
|
|
rbitfld.long 0x10 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x10 0. " AC12NOTEXE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
if (((per.l(ad:0x400F1000+0x40))&0x80)==0x80)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CAPAB0,Capabilities Register to Hold Bits 31:0"
|
|
bitfld.long 0x00 30.--31. " IFSLOTTYPE ,Interface card slot type" "Removable,Embedded,Shared,?..."
|
|
bitfld.long 0x00 29. " ASYNCINTSUP ,Asynchronous interrupt support" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " SYSBUS64BSUP ,System bus 64-bit support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 26. " VOLTSUP1P8V ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VOLTSUP3P0V ,Voltage support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VOLTSUP3P3V ,Voltage support 3.3V" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 23. " SUSRESSUP ,Suspend/Resume support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " SDMASUP ,SDMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSSUP ,High speed support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 19. " ADMA2SUP ,ADMA2 support" "Not supported,Supported"
|
|
bitfld.long 0x00 18. " EXTMEDIABUSSUP ,Extended media bus support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--17. " MAXBLOCKLEN ,Maximum block length" "512 byte,1024 byte,2048 byte,4096 byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASECLKFREQSD ,Base clock frequency for SD_CLK"
|
|
bitfld.long 0x00 7. " TMOUTCLKUNIT ,Timeout clock unit" "kHz,Mhz"
|
|
bitfld.long 0x00 0.--5. " TMOUTCLKFREQ ,Timeout clock frequency" ",1 MHz,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,51 MHz,52 MHz,53 MHz,54 MHz,55 MHz,56 MHz,57 MHz,58 MHz,59 MHz,60 MHz,61 MHz,62 MHz,63 MHz"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CAPAB0,Capabilities Register to Hold Bits 31:0"
|
|
bitfld.long 0x00 30.--31. " IFSLOTTYPE ,Interface card slot type" "Removable,Embedded,Shared,?..."
|
|
bitfld.long 0x00 29. " ASYNCINTSUP ,Asynchronous interrupt support" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " SYSBUS64BSUP ,System bus 64-bit support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 26. " VOLTSUP1P8V ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VOLTSUP3P0V ,Voltage support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VOLTSUP3P3V ,Voltage support 3.3V" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 23. " SUSRESSUP ,Suspend/Resume support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " SDMASUP ,SDMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSSUP ,High speed support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 19. " ADMA2SUP ,ADMA2 support" "Not supported,Supported"
|
|
bitfld.long 0x00 18. " EXTMEDIABUSSUP ,Extended media bus support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--17. " MAXBLOCKLEN ,Maximum block length" "512 byte,1024 byte,2048 byte,4096 byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASECLKFREQSD ,Base clock frequency for SD_CLK"
|
|
bitfld.long 0x00 7. " TMOUTCLKUNIT ,Timeout clock unit" "kHz,Mhz"
|
|
bitfld.long 0x00 0.--5. " TMOUTCLKFREQ ,Timeout clock frequency" ",1 kHz,2 kHz,3 kHz,4 kHz,5 kHz,6 kHz,7 kHz,8 kHz,9 kHz,10 kHz,11 kHz,12 kHz,13 kHz,14 kHz,15 kHz,16 kHz,17 kHz,18 kHz,19 kHz,20 kHz,21 kHz,22 kHz,23 kHz,24 kHz,25 kHz,26 kHz,27 kHz,28 kHz,29 kHz,30 kHz,31 kHz,32 kHz,33 kHz,34 kHz,35 kHz,36 kHz,37 kHz,38 kHz,39 kHz,40 kHz,41 kHz,42 kHz,43 kHz,44 kHz,45 kHz,46 kHz,47 kHz,48 kHz,49 kHz,50 kHz,51 kHz,52 kHz,53 kHz,54 kHz,55 kHz,56 kHz,57 kHz,58 kHz,59 kHz,60 kHz,61 kHz,62 kHz,63 kHz"
|
|
endif
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "CAPAB2,Capabilities Register to Hold Bits 63:32"
|
|
bitfld.long 0x00 25. " SPIBLOCKMODE ,SPI block mode support" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " SPIMODE ,SPI mode support" "Not supported,Supported"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLOCKKMUL ,Clock multiplier"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RETUNEMODES ,Re-tuning modes" "Mode 1,Mode 2,Mode 3,?..."
|
|
bitfld.long 0x00 13. " USETUNSDR50 ,Use tuning for SDR50" "Not used,Used"
|
|
bitfld.long 0x00 8.--11. " TIMCNTRETUN ,Timer count for re-tuning" ",1 sec,2 sec,4 sec,8 sec,16 sec,32 sec,64 sec,128 sec,256 sec,512 sec,1024 sec,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " DRVTYPDSUP ,Driver type D support" "Not supported,Supported"
|
|
bitfld.long 0x00 5. " DRVTYPCSUP ,Driver type C support" "Not supported,Supported"
|
|
bitfld.long 0x00 4. " DRVTYPASUP ,Driver type A support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 2. " DDR50SUP ,DDR50 support" "Not supported,Supported"
|
|
bitfld.long 0x00 1. " SDR104SUP ,SDR104 support" "Not supported,Supported"
|
|
bitfld.long 0x00 0. " SDR50SUP ,SDR50 support" "Not supported,Supported"
|
|
line.long 0x04 "MAXCURCAPAB,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MAXCUR1P8VAL ,Maximum current for 1.8V"
|
|
hexmask.long.byte 0x04 8.--15. 1. " MAXCUR3P0VAL ,Maximum current for 3.0V"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MAXCUR3P3VAL ,Maximum current for 3.3V"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FEVTERRSTAT,Force Event Register For Auto CMD Error Status"
|
|
rbitfld.long 0x00 28.--31. " VENSPECE ,Force event for vendox specific error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 26. " TUNINGE ,Force event for tuning error" "No error,Error"
|
|
bitfld.long 0x00 25. " ADMAE ,Force event for ADMA error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 24. " AC12E ,Force event for auto CMD error" "No error,Error"
|
|
bitfld.long 0x00 23. " CURLIMITE ,Force event for current limit error" "No error,Error"
|
|
bitfld.long 0x00 22. " DATEBE ,Force event for data end bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 21. " DATCRCE ,Force event for data CRC error" "No error,Error"
|
|
bitfld.long 0x00 20. " DATTOE ,Force event for data timeout error" "No error,Error"
|
|
bitfld.long 0x00 19. " CMDINDXE ,Force event for command index error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CMDEBE ,Force event for command end bit error" "No error,Error"
|
|
bitfld.long 0x00 17. " CMDCRCE ,Force event for command CRC error" "No error,Error"
|
|
bitfld.long 0x00 16. " CMDTOE ,Force event for command timeout error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Force event for command not issued by auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " AC12INDXE ,Force event for auto CMD index error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12EBE ,Force event for auto CMD end bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " AC12CRCE ,Force event for auto CMD CRC error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Force event for auto CMD timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NEX ,Force event for command not issued by auto CM12 not executed" "No error,Error"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
newline
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "PRSTVAL0,Preset Value for Initialization And Default Speed Mode"
|
|
bitfld.long 0x00 30.--31. " DSPDRVSTVAL ,Driver strength select value for default speed" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x00 26. " DSPCLKGENVAL ,Clock generator select value for default speed" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x00 16.--25. 1. " DSPSDCLKFREQVAL ,SD_CLK frequency select value for default speed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " INITDRVSTVAL ,Driver strength select value for initialization" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x00 10. " INITCLCKGENVAL ,Clock generator select value for initialization" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x00 0.--9. 1. " INITSDCLKFREQVAL ,SD_CLK frequency select value for initialization"
|
|
line.long 0x04 "PRSTVAL2,Preset Value For High Speed And SDR12 Modes"
|
|
bitfld.long 0x04 30.--31. " SDR12DRVSTVAL ,Driver strength select value for SDR12" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x04 26. " SDR12CLKGENVAL ,Clock generator select value for SDR12" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x04 16.--25. 1. " SDR12SDCLKFREQVAL ,SD_CLK frequency select value for SDR12"
|
|
newline
|
|
bitfld.long 0x04 14.--15. " HSPDRVSTVAL ,Driver strength select value for high speed" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x04 10. " HSPCLKGENVAL ,Clock generator select value for high speed" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x04 0.--9. 1. " HSPSDCLKFREQVAL ,SD_CLK frequency select value for high speed"
|
|
line.long 0x08 "PRSTVAL4,Preset Value For SDR25 And SDR50 Modes"
|
|
bitfld.long 0x08 30.--31. " SDR50DRVSTVAL ,Driver strength select value for SDR50" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x08 26. " SDR50CLCKGENVAL ,Clock generator select value for SDR50" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x08 16.--25. 1. " SDR50SDCLKFREQVAL ,SD_CLK frequency select value for SDR50"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " SDR25DRVSTVAL ,Driver strength select value for SDR25" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x08 10. " SDR25CLKGENVAL ,Clock generator select value for SDR25" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x08 0.--9. 1. " SDR25SDCLKFREQVAL ,SD_CLK frequency select value for SDR25"
|
|
line.long 0x0C "PRSTVAL6,Preset Value for SDR104 and DDR50 Modes"
|
|
bitfld.long 0x0C 30.--31. " DDR50DRVSTVAL ,Driver strength select value for DDR50" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x0C 26. " DDR50CLKGENVAL ,Clock generator select value for DDR50" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DDR50SDCLKFREQVAL ,SD_CLK frequency select value for DDR50"
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " SDR104DRVSTVAL ,Driver strength select value for SDR104" "TYPEB,TYPEA,TYPEC,TYPED"
|
|
bitfld.long 0x0C 10. " SDR104CLKGENVAL ,Clock generator select value for SDR104" "Host controller clock generator,Programmable clock"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDR104SDCLKFREQVAL ,SD_CLK frequency select value for SDR104"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BOOTTOCTRL,Boot Timeout Control Register"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "SLOTINTSTAT,Slot Interrupt Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VENDVERNUM ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SPECVERNUM ,Host controller compliant spec version number"
|
|
bitfld.long 0x00 0. " INTSLOT0 ,Interrupt signal for slot#0" "No interrupt,Interrupt"
|
|
group.long 0x800++0x27
|
|
line.long 0x00 "CTRL,Core Control Signals Register"
|
|
bitfld.long 0x00 16.--17. " TXDLYMUXSEL ,TX delay mux selection" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " OTAPDLYSEL ,Selects one of 32 taps on the SDIO_CLK Pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " OTAPDLYEN ,Selective tap delay line enable on SDIO_CLK pin" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " ITAPCHGWIN ,Gating signal for tap delay change" "Not asserted,Asserted"
|
|
bitfld.long 0x00 1.--5. " ITAPDLYSEL ,Selects one of 32 taps on the Rxclk_in Line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " ITAPDLYEN ,Selective tap delay line enable on Rxclk_in" "Disabled,Enabled"
|
|
line.long 0x04 "CFG0,Core Configuration 0"
|
|
bitfld.long 0x04 30. " C1P8VSUP ,1P8V support" "Not supported,Supported"
|
|
bitfld.long 0x04 29. " C3P0VSUP ,3P0V support" "Not supported,Supported"
|
|
bitfld.long 0x04 28. " C3P3VSUP ,Core 3P3V support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x04 27. " CSUSPRESSUP ,Suspend/Resume support" "Not supported,Supported"
|
|
bitfld.long 0x04 26. " CSDMASUP ,SDMA mode support" "Not supported,Supported"
|
|
bitfld.long 0x04 25. " CHSSUP ,High speed mode support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x04 24. " CADMA2SUP ,ADMA2 mode support" "Not supported,Supported"
|
|
bitfld.long 0x04 23. " C8BITSUP ,8-bit interface support" "Not supported,Supported"
|
|
bitfld.long 0x04 21.--22. " MAXBLKLEN ,MAX block length of transfer" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
newline
|
|
hexmask.long.byte 0x04 13.--20. 1. " BASECLKFREQ ,Base clock frequency for SD_CLK"
|
|
bitfld.long 0x04 12. " TOUTCLKUNIT ,Timeout clock unit in kHz or MHz" "kHz,MHz"
|
|
bitfld.long 0x04 6.--11. " TOUTCLKFREQ ,Timeout clock frequency" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--5. " TUNINGCNT ,Tuning counter value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "CFG1,Core Configuration 1"
|
|
bitfld.long 0x08 18. " ASYNCWKUPEN ,Asynchronous wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " SPISUP ,SPI support" "Not supported,Supported"
|
|
bitfld.long 0x08 14.--15. " RETUNMODES ,Retuning modes" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 13. " TUNSDR50 ,Tuning for SDR50" "0,1"
|
|
bitfld.long 0x08 9.--12. " RETUNTMRCTL ,Retuning timer control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8. " CDRVDSUP ,Support type D driver" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x08 7. " CDRVCSUP ,Support type C driver" "Not supported,Supported"
|
|
bitfld.long 0x08 6. " CDRVASUP ,Support type A driver" "Not supported,Supported"
|
|
bitfld.long 0x08 5. " CDDR50SUP ,Support DDR50" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x08 4. " CSDR104SUP ,Support SDR104" "Not supported,Supported"
|
|
bitfld.long 0x08 3. " CSDR50SUP ,Core support SDR50" "Not supported,Supported"
|
|
bitfld.long 0x08 1.--2. " SLOTTYPE ,Slot type" "RMSDSLOT,EMSDSLOT,SHBUSSLOT,?..."
|
|
newline
|
|
bitfld.long 0x08 0. " ASYNCINTRSUP ,Asynchronous interrupt support" "Not supported,Supported"
|
|
line.long 0x0C "CFGPRESETVAL0,Core Configuration Preset Value 0"
|
|
bitfld.long 0x0C 27.--28. " DSPDRVST ,Default speed drive strength" "0,1,2,3"
|
|
bitfld.long 0x0C 26. " DSPCLKGENEN ,Default speed clock gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSPSDCLKFREQ ,Preset value for default speed of SD_CLK"
|
|
newline
|
|
bitfld.long 0x0C 11.--12. " INITDRVST ,Initial drive strength" "0,1,2,3"
|
|
bitfld.long 0x0C 10. " INITCLKGENEN ,Initial clock gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 0.--9. 1. " INITSDCLKFREQ ,Initial SD_CLK frequency"
|
|
line.long 0x10 "CFGPRESETVAL1,Core Configuration Preset Value 1"
|
|
bitfld.long 0x10 27.--28. " SDR12DRVST ,SDR12 speed drive strength" "0,1,2,3"
|
|
bitfld.long 0x10 26. " SDR12CLKGENEN ,SDR12 speed clock gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 16.--25. 1. " SDR12SDCLKFREQ ,Preset value for SDR12 speed of SD_CLK"
|
|
newline
|
|
bitfld.long 0x10 11.--12. " HSPDRVST ,High speed SD drive strength" "0,1,2,3"
|
|
bitfld.long 0x10 10. " HSPCLKGENEN ,High speed SD_CLK gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 0.--9. 1. " HSPSDCLKFREQ ,High speed SD_CLK frequency"
|
|
line.long 0x14 "CFGPRESETVAL2,Core Configuration Preset Value 2"
|
|
bitfld.long 0x14 27.--28. " SDR50DRVST ,SDR50 speed drive strength" "0,1,2,3"
|
|
bitfld.long 0x14 26. " SDR50CLKGENEN ,SDR50 speed clock gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 16.--25. 1. " SDR50SDCLKFREQ ,Preset value for SDR50 speed of SD_CLK"
|
|
newline
|
|
bitfld.long 0x14 11.--12. " SDR25DRVST ,SDR25 SD drive strength" "0,1,2,3"
|
|
bitfld.long 0x14 10. " SDR25CLKGENEN ,SDR25 SD_CLK gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 0.--9. 1. " SDR25SDCLKFREQ ,SDR25 SD_CLK frequency"
|
|
line.long 0x18 "CFGPRESETVAL3,Core Configuration Preset Value 3"
|
|
bitfld.long 0x18 27.--28. " DDR50DRVST ,DDR50 speed drive strength" "0,1,2,3"
|
|
bitfld.long 0x18 26. " DDR50CLKGENEN ,DDR50 speed clock gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x18 16.--25. 1. " DDR50SDCLKFREQ ,Preset value for DDR50 speed of SD_CLK"
|
|
newline
|
|
bitfld.long 0x18 11.--12. " SDR104DRVST ,SDR104 SD drive strength" "0,1,2,3"
|
|
bitfld.long 0x18 10. " SDR104CLKGENEN ,SDR104 SD_CLK gen enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x18 0.--9. 1. " SDR104SDCLKFREQ ,SDR104 SD_CLK frequency"
|
|
line.long 0x1C "ROUTELOC0,I/O Location Register"
|
|
bitfld.long 0x1C 24.--29. " CLKLOC ,I/O location for CLK" "LOC0,LOC1,?..."
|
|
bitfld.long 0x1C 16.--21. " WPLOC ,I/O location for WP" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x1C 8.--13. " CDLOC ,I/O location for CD" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " CDLOC ,I/O location for D0-7 pins" "LOC0,LOC1,?..."
|
|
line.long 0x20 "ROUTELOC1,I/O Location 1 Register"
|
|
bitfld.long 0x20 0.--5. " CMDLOC ,I/O location for CMD pin" "LOC0,LOC1,?..."
|
|
line.long 0x24 "ROUTEPEN,I/O Location Enable Register"
|
|
bitfld.long 0x24 9. " D7PEN ,Data7 I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 8. " D6PEN ,Dat6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 7. " D5PEN ,Dat5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 6. " D4PEN ,Dat4 I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " D3PEN ,Dat3 I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " D2PEN ,Dat2 I/O enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 3. " D1PEN ,Dat1 I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " D0PEN ,Dat0 I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " CMDPEN ,CMD I/O enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 0. " CLKPEN ,CLK I/O enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ETH (Ethernet)"
|
|
base ad:0x40024000
|
|
width 21.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "NETWORKCTRL,Network Control Register"
|
|
bitfld.long 0x00 25. " PFCCTRL ,Enable multiple PFC pause quantums one per pause priority" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ONESTEPSYNCMODE ,1588 one step sync mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " STOREUDPOFFSET ,Store UDP / TCP offset to memory" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 20. " PTPUNICASTEN ,Enable detection of unicast PTP unicast frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TXLPIEN ,Enable LPI transmission when set LPI is immediately transmitted" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FLUSHRXPKT ,Flush the next packet from the external RX DPRAM" "No flush,Flush"
|
|
newline
|
|
bitfld.long 0x00 17. " TXPFCPRIORPFRM ,Write a one to transmit PFC priority based pause frame" "No transmit,Transmit"
|
|
bitfld.long 0x00 16. " PFCENB ,Enable PFC priority based pause reception capabilities" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " STORERXTS ,Store receive time stamp to memory" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 12. " TXPFRMZERO ,Transmit zero quantum pause frame" "No transmit,Transmit"
|
|
bitfld.long 0x00 11. " TXPFRMREQ ,Transmit pause frame" "No transmit,Transmit"
|
|
bitfld.long 0x00 10. " TXHALT ,Transmit halt" "No halt,Halt"
|
|
newline
|
|
bitfld.long 0x00 9. " TXSTRT ,Start transmission" "No start,Start"
|
|
bitfld.long 0x00 8. " BACKPRESSURE ,Back pressure will force collisions on all received frames" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " STATSWREN ,Write enable for statistics registers" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " INCALLSTATSREGS ,Incremental statistics registers" "No increment,Increment"
|
|
bitfld.long 0x00 5. " CLRALLSTATSREGS ,Clear statistics registers" "No clear,Clear"
|
|
bitfld.long 0x00 4. " MANPORTEN ,Management port enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " ENBTX ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENBRX ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LOOPBACKLOCAL ,Assert loopback local signal" "Not asserted,Asserted"
|
|
line.long 0x04 "NETWORKCFG,Network Configuration Register"
|
|
bitfld.long 0x04 30. " IGNOREIPGRXER ,Ignore IPG rx_er" "Not ignored,Ignored"
|
|
bitfld.long 0x04 29. " NSPCHANGE ,Receive bad preamble" "Not received,Received"
|
|
bitfld.long 0x04 28. " IPGSTRTCHEN ,IPG stretch enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " IGNORERXFCS ,Ignore RX FCS" "Not ignored,Ignored"
|
|
bitfld.long 0x04 25. " ENHALFDUPLEXRX ,Enable frames to be received in half-duplex mode while transmitting" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " RXCHKSUMOFFLOADEN ,Receive checksum offload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " DISCOPYOFPFRAMES ,Disable copy of pause frames" "No,Yes"
|
|
bitfld.long 0x04 18.--20. " MDCCLKDIV ,MDC clock division" "DIVBY8,DIVBY16,DIVBY32,DIVBY48,DIVBY64,DIVBY96,DIVBY128,DIVBY224"
|
|
bitfld.long 0x04 17. " FCSREMOVE ,FCS remove" "Not removed,Removed"
|
|
newline
|
|
bitfld.long 0x04 16. " LENFIELDERRFRMDISCRD ,Length field error frame discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 14.--15. " RXBUFFOFFSET ,Receive buffer offset" "0,1,2,3"
|
|
bitfld.long 0x04 13. " PAUSEEN ,Pause enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 12. " RETRYTEST ,Retry test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RX1536BYTEFRAMES ,Receive 1536 byte frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " UNICASTHASHEN ,Unicast hash enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " MULTICASTHASHEN ,Multicast hash enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NOBROADCAST ,Broadcast disable" "No,Yes"
|
|
bitfld.long 0x04 4. " COPYALLFRAMES ,Copy all frames" "Not copy,Copy"
|
|
newline
|
|
bitfld.long 0x04 3. " JUMBOFRAMES ,Jumbo frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DISCRDNONVLANFRAMES ,Discard non-VLAN frames" "Not discarded,Discarded"
|
|
bitfld.long 0x04 1. " FULLDUPLEX ,Full duplex enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " SPEED ,Speed" "10Mbps,100Mbps"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "NETWORKSTATUS,Network Status Register"
|
|
bitfld.long 0x00 7. " LPIINDICATE ,Low power idle detected on receive" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " PFCNEGOTIATE ,Set when PFC priority based pause has been negotiated" "Not negotiated,Negotiated"
|
|
bitfld.long 0x00 2. " MANDONE ,PHY management logic idle" "Not idle,Idle"
|
|
newline
|
|
bitfld.long 0x00 1. " MDIOIN ,Returns status of the mdio_in pin" "Low,High"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 29. " TXBDEXTENDMODEEN ,Enable TX extended BD mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RXBDEXTNDMODEEN ,Enable RX extended BD mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FRCMAXAMBABRSTTX ,Force max length bursts on TX" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x00 25. " FRCMAXAMBABRSTRX ,Force max length bursts on RX" "Not forced,Forced"
|
|
bitfld.long 0x00 24. " FRCDISCARDONERR ,Enable auto discard RX pkts during lack of resource" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXBUFSIZE ,DMA receive buffer size in external AMBA system memory"
|
|
newline
|
|
bitfld.long 0x00 12. " INFLASTDBUFSIZEEN ,Forces the DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of infinite size" "Not forced,Forced"
|
|
bitfld.long 0x00 11. " TXPBUFTCPEN ,Transmitter IP TCP and UDP checksum generation offload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXPBUFSIZE ,Transmitter packet buffer memory size select" "2 Kb,4 Kb"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " RXPBUFSIZE ,Receiver packet buffer memory size select" "0.5 Kb,1 Kb,2 Kb,4 Kb"
|
|
bitfld.long 0x00 5. " HDRDATASPLITEN ,Enable header data splitting" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " AMBABRSTLEN ,Burst length to use on the AMBA when transferring frame data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TXSTATUS,Transmit Status Register"
|
|
eventfld.long 0x04 8. " RESPNOTOK ,DMA block sees bresp/hresp not OK" "Ok,Not ok"
|
|
eventfld.long 0x04 7. " LATECOLOCCRD ,Late collision occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " TXUNDERRUN ,Transmit under run" "No under run,Under run"
|
|
newline
|
|
eventfld.long 0x04 5. " TXCMPLT ,Transmit complete" "Not completed,Completed"
|
|
eventfld.long 0x04 4. " AMBAERR ,Transmit frame corruption due to AMBA errors" "Not transmitted,Transmitted"
|
|
rbitfld.long 0x04 3. " TXGO ,Transmit go" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x04 2. " RETRYLMTEXCD ,Retry limit exceeded" "Not exceeded,Exceeded"
|
|
eventfld.long 0x04 1. " COLOCCRD ,Collision occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " USEDBITREAD ,Used bit read" "Not used,Used"
|
|
line.long 0x08 "RXQPTR,Start Address Of The Receive Buffer Queue Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DMARXQPTR ,Receive buffer queue base address"
|
|
line.long 0x0C "TXQPTR,Start Address Of The Transmit Buffer Queue Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMATXQPTR ,Transmit buffer queue base address"
|
|
line.long 0x10 "RXSTATUS,Receive Status Register"
|
|
eventfld.long 0x10 3. " RESPNOTOK ,DMA block sees bresp/hresp not OK" "Ok,Not ok"
|
|
eventfld.long 0x10 2. " RXOVERRUN ,Receive overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 1. " FRMRX ,Frame received" "Not received,Received"
|
|
newline
|
|
eventfld.long 0x10 0. " BUFFNOTAVAIL ,Buffer not available" "Available,Not available"
|
|
line.long 0x14 "IFCR_SET/CLR,Interrupt Status Set/Clear Register"
|
|
setclrfld.long 0x14 29. 0x18 29. 0x1C 29. " TSUTIMERCOMP ,TSU timer comparison interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 28. 0x18 28. 0x1C 28. " WOLEVNTRX ,WOL event received interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 27. 0x18 27. 0x1C 27. " RXLPIINDC ,Receive LPI indication status bit change interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 26. 0x18 26. 0x1C 26. " TSUSECREGINCR ,TSU seconds register increment interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 25. 0x18 25. 0x1C 25. " PTPPDLYRESPFRMTX ,PTP pdelay_resp frame transmitted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 24. 0x18 24. 0x1C 24. " PTPPDLYREQFRMTX ,PTP pdelay_req frame transmitted interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 23. 0x18 23. 0x1C 23. " PTPPDLYRESPFRMRX ,PTP pdelay_resp frame received interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 22. 0x18 22. 0x1C 22. " PTPPDLYREQFRMRX ,PTP pdelay_req frame received interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 21. 0x18 21. 0x1C 21. " PTPSYNCFRMTX ,PTP sync frame transmitted interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 20. 0x18 20. 0x1C 20. " PTPDLYREQFRMTX ,PTP delay_req frame transmitted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 19. 0x18 19. 0x1C 19. " PTPSYNCFRMRX ,PTP sync frame received interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 18. 0x18 18. 0x1C 18. " PTPDLYREQFRMRX ,PTP delay_req frame received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 14. 0x18 14. 0x1C 14. " PFRMTX ,Pause frame transmitted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 13. 0x18 13. 0x1C 13. " PAUSETIMEZERO ,Pause time zero interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 12. 0x18 12. 0x1C 12. " NONZEROPFRMQUANT ,Pause frame with non-zero pause quantum received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 11. 0x18 11. 0x1C 11. " RESPNOTOK ,DMA block sees bresp/hresp not OK interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 10. 0x18 10. 0x1C 10. " RXOVERRUN ,Receive overrun interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 7. 0x18 7. 0x1C 7. " TXCMPLT ,Transmit complete interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 6. 0x18 6. 0x1C 6. " AMBAERR ,Transmit frame corruption due to AMBA (AHB) error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 5. 0x18 5. 0x1C 5. " RTRYLMTORLATECOL ,Retry limit exceeded or late collision interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 4. 0x18 4. 0x1C 4. " TXUNDERRUN ,Transmit under run interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 3. 0x18 3. 0x1C 3. " TXUSEDBITREAD ,TX used bit read interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 2. 0x18 2. 0x1C 2. " RXUSEDBITREAD ,RX used bit read interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x14 1. 0x18 1. 0x1C 1. " RXCMPLT ,Receive complete interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x14 0. 0x18 0. 0x1C 0. " MNGMNTDONE ,Management frame sent interrupt" "No interrupt,Interrupt"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "IENRO,Interrupt Mask Register"
|
|
bitfld.long 0x00 29. " TSUTIMERCOMP ,TSU timer comparison interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " WOLEVNTRX ,WOL event received interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " RXLPIINDC ,Receive LPI indication mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 26. " TSUSECREGINCR ,TSU seconds register increment mask" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " PTPPDLYRESPFRMTX ,PTP pdelay_resp frame transmitted mask" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PTPPDLYREQFRMTX ,PTP pdelay_req frame transmitted mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 23. " PTPPDLYRESPFRMRX ,PTP pdelay_resp frame received mask" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PTPPDLYREQFRMRX ,PTP pdelay_req frame received mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " PTPSYNCFRMTX ,PTP sync frame transmitted mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 20. " PTPDLYREQFRMTX ,PTP delay_req frame transmitted mask" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " PTPSYNCFRMRX ,PTP sync frame received mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PTPDLYREQFRMRX ,PTP delay_req frame received mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 14. " PFRMTX ,Pause frame transmitted interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " PAUSETIMEZERO ,Pause time zero interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " NONZEROPFRMQUANT ,Pause frame with non-zero pause quantum interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " RESPNOTOK ,DMA block sees bresp/hresp not OK interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " RXOVERRUN ,Receive overrun interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TXCMPLT ,Transmit complete interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " AMBAERR ,Transmit frame corruption due to AMBA (AHB) error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " RTRYLMTORLATECOL ,Retry limit exceeded or late collision interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TXUNDERRUN ,Transmit under run interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " TXUSEDBITREAD ,TX used bit read interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " RXUSEDBITREAD ,RX used bit read interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " RXCMPLT ,Receive complete interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 0. " MNGMNTDONE ,Management frame sent interrupt mask" "Not masked,Masked"
|
|
line.long 0x04 "PHYMNGMNT,PHY Management Register"
|
|
bitfld.long 0x04 30. " WRITE1 ,Written to 1 for valid clause 22 frame and to 0 for a valid clause 45 frame" "0,1"
|
|
bitfld.long 0x04 28.--29. " OPERATION ,Operation for clause 45/22" "ADDR/-,Write/Write,Post read inc/Read,Read frame/-"
|
|
hexmask.long.word 0x04 23.--27. 0x80 " PHYADDR ,PHY address"
|
|
newline
|
|
hexmask.long.byte 0x04 18.--22. 0x04 " REGADDR ,Register address - specifies the register in the PHY to access"
|
|
bitfld.long 0x04 16.--17. " WRITE10 ,Must be written with 10" ",,2,?..."
|
|
hexmask.long.word 0x04 0.--15. 1. " PHYRWDATA ,PHY read write data"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RXPAUSEQUANT,Received Pause Quantum Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " QUANT ,Received pause quantum"
|
|
group.long 0x3C++0x0F
|
|
line.long 0x00 "TXPAUSEQUANT,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " QUANTP1 ,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " QUANT ,Transmit pause quantum"
|
|
line.long 0x04 "PBUFTXCUTTHRU,TX Partial Store And Forward"
|
|
bitfld.long 0x04 31. " DMATXCUTTHRU ,Enable TX partial store and forward operation" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--9. 1. " DMATXCUTTHRUTHR ,Watermark value"
|
|
line.long 0x08 "PBUFRXCUTTHRU,RX Partial Store And Forward"
|
|
bitfld.long 0x08 31. " DMARXCUTTHRU ,Enable RX partial store and forward operation" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--9. 1. " DMARXCUTTHRUTHR ,Watermark value"
|
|
line.long 0x0C "JUMBOMAXLEN,Maximum Jumbo Frame Size"
|
|
hexmask.long.word 0x0C 0.--13. 1. " JUMBOMAXLEN ,Maximum jumbo frame size"
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "IMOD,Interrupt Moderation Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXINTMOD ,Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXINTMOD ,Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received"
|
|
line.long 0x04 "SYSWAKETIME,System Wake Time Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " SYSWAKETIME ,Count of 64ns 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "HASHBOTTOM,Hash Register Bottom Register"
|
|
line.long 0x04 "HASHTOP,Hash Register Top Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "SPECADDR1BOTTOM,Specific Address 1 Bottom Register"
|
|
line.long 0x04 "SPECADDR1TOP,Specific Address 1 Top Register"
|
|
bitfld.long 0x04 29. " FILTERBYTEMASK[5] ,Filter last byte received mask" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " [4] ,Filter fifth byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [3] ,Filter fourth byte mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,Filter third byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " [1] ,Filter second byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [0] ,Filter first byte received mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " FILTERTYPE ,MAC SA or DA selection" "DA,SA"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " ADDR ,Specific address 1 MSB"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "SPECADDR2BOTTOM,Specific Address 2 Bottom Register"
|
|
line.long 0x04 "SPECADDR2TOP,Specific Address 2 Top Register"
|
|
bitfld.long 0x04 29. " FILTERBYTEMASK[5] ,Filter last byte received mask" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " [4] ,Filter fifth byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [3] ,Filter fourth byte mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,Filter third byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " [1] ,Filter second byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [0] ,Filter first byte received mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " FILTERTYPE ,MAC SA or DA selection" "DA,SA"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " ADDR ,Specific address 2 MSB"
|
|
group.long 0x98++0x07
|
|
line.long 0x00 "SPECADDR3BOTTOM,Specific Address 3 Bottom Register"
|
|
line.long 0x04 "SPECADDR3TOP,Specific Address 3 Top Register"
|
|
bitfld.long 0x04 29. " FILTERBYTEMASK[5] ,Filter last byte received mask" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " [4] ,Filter fifth byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [3] ,Filter fourth byte mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,Filter third byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " [1] ,Filter second byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [0] ,Filter first byte received mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " FILTERTYPE ,MAC SA or DA selection" "DA,SA"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " ADDR ,Specific address 3 MSB"
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "SPECADDR4BOTTOM,Specific Address 4 Bottom Register"
|
|
line.long 0x04 "SPECADDR4TOP,Specific Address 4 Top Register"
|
|
bitfld.long 0x04 29. " FILTERBYTEMASK[5] ,Filter last byte received mask" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " [4] ,Filter fifth byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [3] ,Filter fourth byte mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,Filter third byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " [1] ,Filter second byte mask" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [0] ,Filter first byte received mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " FILTERTYPE ,MAC SA or DA selection" "DA,SA"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " ADDR ,Specific address 4 MSB"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "SPECTYPE1,Type ID Match 1 Register"
|
|
bitfld.long 0x00 31. " ENBCOPY ,Enable copying of type ID match 1 matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match 1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "SPECTYPE2,Type ID Match 2 Register"
|
|
bitfld.long 0x00 31. " ENBCOPY ,Enable copying of type ID match 2 matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match 2"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SPECTYPE3,Type ID Match 3 Register"
|
|
bitfld.long 0x00 31. " ENBCOPY ,Enable copying of type ID match 3 matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match 3"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "SPECTYPE4,Type ID Match 4 Register"
|
|
bitfld.long 0x00 31. " ENBCOPY ,Enable copying of type ID match 4 matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match 4"
|
|
group.long 0xB8++0x17
|
|
line.long 0x00 "WOLREG,Wake On LAN Register"
|
|
bitfld.long 0x00 19. " WOLMASK3 ,Wake on LAN multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " WOLMASK2 ,Wake on LAN specific address register 1 event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " WOLMASK1 ,Wake on LAN ARP request event enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " WOLMASK0 ,Wake on LAN magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Wake on LAN ARP request IP address"
|
|
line.long 0x04 "STRETCHRATIO,IPG Stretch Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " IPGSTRETCH ,IPG stretch"
|
|
line.long 0x08 "STACKEDVLAN,Stacked VLAN Register"
|
|
bitfld.long 0x08 31. " ENBPROCESSING ,Enable stacked VLAN processing mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,User defined VLAN_TYPE field"
|
|
line.long 0x0C "TXPFCPAUSE,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " VECTOR ,Priority vector pause size"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " VECTORENB ,Priority vector enable"
|
|
line.long 0x10 "MASKADD1BOTTOM,Specific Address Mask 1 Bottom 31:0 Register"
|
|
line.long 0x14 "MASKADD1TOP,Specific Address Mask 1 Top 47:32 Register"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " ADDRMASK ,Specific address mask"
|
|
group.long 0xD4++0x13
|
|
line.long 0x00 "RXPTPUNICAST,PTP RX Unicast IP Destination Address Register"
|
|
line.long 0x04 "TXPTPUNICAST,PTP TX Unicast IP Destination Address Register"
|
|
line.long 0x08 "TSUNSECCMP,TSU Timer Comparison Value Nanoseconds Register"
|
|
hexmask.long.tbyte 0x08 0.--21. 1. " COMPVAL ,TSU timer comparison value"
|
|
line.long 0x0C "TSUSECCMP,TSU Timer Comparison Value Seconds Register [31:0]"
|
|
line.long 0x10 "TSUMSBSECCM,TSU Timer Comparison Value Seconds Register [47:32]"
|
|
hexmask.long.word 0x10 0.--15. 1. " COMPVAL ,TSU timer comparison value"
|
|
rgroup.long 0xE8++0x0F
|
|
line.long 0x00 "TSUPTPTXMSBSEC,PTP Event Frame Transmitted Seconds Register 47:32"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMERSEC ,PTP event frame TX seconds"
|
|
line.long 0x04 "TSUPTPRXMSBSEC,PTP Event Frame Received Seconds Register 47:32"
|
|
hexmask.long.word 0x04 0.--15. 1. " TIMERSEC ,PTP event frame TX seconds"
|
|
line.long 0x08 "TSUPEERTXMSBSEC,PTP Peer Event Frame Transmitted Seconds Register 47:32"
|
|
hexmask.long.word 0x08 0.--15. 1. " TIMERSEC ,PTP peer event frame TX seconds"
|
|
line.long 0x0C "TSUPEERRXMSBSEC,PTP Peer Event Frame Received Seconds Register 47:32"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TIMERSEC ,PTP peer event frame RX seconds"
|
|
group.long 0x100++0xB7
|
|
line.long 0x00 "OCTETSTXEDBOTTOM,Octets Transmitted 31:0 Register"
|
|
line.long 0x04 "OCTETSTXEDTOP,Octets Transmitted 47:32 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Transmitted octets in frame without errors [47:32]"
|
|
line.long 0x08 "FRAMESTXEDOK,Frames Transmitted Register"
|
|
line.long 0x0C "BROADCASTTXED,Broadcast Frames Transmitted Register"
|
|
line.long 0x10 "MULTICASTTXED,Multicast Frames Transmitted Register"
|
|
line.long 0x14 "PFRAMESTXED,Pause Frames Transmitted Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT ,Transmitted pause frames"
|
|
line.long 0x18 "FRAMESTXED64,64 Byte Frames Transmitted Register"
|
|
line.long 0x1C "FRAMESTXED65,65 to 127 Byte Frames Transmitted Register"
|
|
line.long 0x20 "FRAMESTXED128,128 to 255 Byte Frames Transmitted Register"
|
|
line.long 0x24 "FRAMESTXED256,256 to 511 Byte Frames Transmitted Register"
|
|
line.long 0x28 "FRAMESTXED512,512 to 1023 Byte Frames Transmitted Register"
|
|
line.long 0x2C "FRAMESTXED1024,1024 to 1518 Byte Frames Transmitted Register"
|
|
line.long 0x30 "FRAMESTXED1519,Greater Than 1518 Byte Frames Transmitted Register"
|
|
line.long 0x34 "TXUNDERRUNS,Transmit Under Runs Register"
|
|
hexmask.long.word 0x34 0.--9. 1. " COUNT ,Transmit under runs"
|
|
line.long 0x38 "SINGLECOLS,Single Collision Frames Register"
|
|
hexmask.long.tbyte 0x38 0.--17. 1. " COUNT ,Single collision frames"
|
|
line.long 0x3C "MULTICOLS,Multiple Collision Frames Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " COUNT ,Multiple collision frames"
|
|
line.long 0x40 "EXCESSCOLS,Excessive Collisions Register"
|
|
hexmask.long.word 0x40 0.--9. 1. " COUNT ,Excessive collisions"
|
|
line.long 0x44 "LATECOLS,Late Collisions Register"
|
|
hexmask.long.word 0x44 0.--9. 1. " COUNT ,Late collisions"
|
|
line.long 0x48 "DEFERREDFRAMES,Deferred Transmission Frames Register"
|
|
hexmask.long.tbyte 0x48 0.--17. 1. " COUNT ,Deferred transmission frames"
|
|
line.long 0x4C "CRSERRS,Carrier Sense Errors Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. " COUNT ,Carrier sense errors"
|
|
line.long 0x50 "OCTETSRXEDBOTTOM,Octets Received 31:0 Register"
|
|
line.long 0x54 "OCTETSRXEDTOP,Octets Received 47:32 Register"
|
|
hexmask.long.word 0x54 0.--15. 1. " COUNT ,Received octets in frame without errors"
|
|
line.long 0x58 "FRAMESRXEDOK,Frames Received Register"
|
|
line.long 0x5C "BROADCASTRXED,Broadcast Frames Received Register"
|
|
line.long 0x60 "MULTICASTRXED,Multicast Frames Received Register"
|
|
line.long 0x64 "PFRAMESRXED,Pause Frames Received Register"
|
|
hexmask.long.word 0x64 0.--15. 1. " COUNT ,Received pause frames"
|
|
line.long 0x68 "FRAMESRXED64,64 Byte Frames Received Register"
|
|
line.long 0x6C "FRAMESRXED65,65 to 127 Byte Frames Received Register"
|
|
line.long 0x70 "FRAMESRXED128,128 to 255 Byte Frames Received Register"
|
|
line.long 0x74 "FRAMESRXED256,256 to 511 Byte Frames Received Register"
|
|
line.long 0x78 "FRAMESRXED512,512 to 1023 Byte Frames Received Register"
|
|
line.long 0x7C "FRAMESRXED1024,1024 to 1518 Byte Frames Received Register"
|
|
line.long 0x80 "FRAMESRXED1519,1519 to Maximum Byte Frames Received Register"
|
|
line.long 0x84 "UNDERSIZEFRAMES,Undersized Frames Received Register"
|
|
hexmask.long.word 0x84 0.--9. 1. " COUNT ,Undersize frames received"
|
|
line.long 0x88 "EXCESSIVERXLEN,Oversize Frames Received Register"
|
|
hexmask.long.word 0x88 0.--9. 1. " COUNT ,Oversize frames received"
|
|
line.long 0x8C "RXJABBERS,Jabbers Received Register"
|
|
hexmask.long.word 0x8C 0.--9. 1. " COUNT ,Jabbers received"
|
|
line.long 0x90 "FCSERRS,Frame Check Sequence Errors Register"
|
|
hexmask.long.word 0x90 0.--9. 1. " COUNT ,Frame check sequence errors"
|
|
line.long 0x94 "RXLENERRS,Length Field Frame Errors Register"
|
|
hexmask.long.word 0x94 0.--9. 1. " COUNT ,Length field frame errors"
|
|
line.long 0x98 "RXSYMBOLERRS,Receive Symbol Errors Register"
|
|
hexmask.long.word 0x98 0.--9. 1. " COUNT ,Receive symbol errors"
|
|
line.long 0x9C "ALIGNERRS,Alignment Errors Register"
|
|
hexmask.long.word 0x9C 0.--9. 1. " COUNT ,Alignment errors"
|
|
line.long 0xA0 "RXRESOURCEERRS,Receive Resource Errors Register"
|
|
hexmask.long.tbyte 0xA0 0.--17. 1. " COUNT ,Receive resource errors"
|
|
line.long 0xA4 "RXOVERRUNS,Receive Overruns Register"
|
|
hexmask.long.word 0xA4 0.--9. 1. " COUNT ,Receive overruns"
|
|
line.long 0xA8 "RXIPCKERRS,IP Header Checksum Errors Register"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " COUNT ,IP header checksum errors"
|
|
line.long 0xAC "RXTCPCKERRS,TCP Checksum Errors Register"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " COUNT ,TCP checksum errors"
|
|
line.long 0xB0 "RXUDPCKERRS,UDP Checksum Errors Register"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " COUNT ,UDP checksum errors"
|
|
line.long 0xB4 "AUTOFLUSHEDPKTS,Receive DMA Flushed Packets Register"
|
|
hexmask.long.word 0xB4 0.--15. 1. " COUNT ,Flushed RX pkts counter"
|
|
group.long 0x1BC++0x07
|
|
line.long 0x00 "TSUTIMERINCRSUBNSEC,1588 Timer Increment Register Subscript Nsec Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SUBNSINCRLSB ,LSB [7:0] of the subscript-ns value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SUBNSINCR ,MSB [23:8] of the subscript-ns value"
|
|
line.long 0x04 "TSUTIMERMSBSEC,1588 Timer Seconds Register 47:32 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TIMER ,MSB 16 bits of seconds timer count"
|
|
group.long 0x1D0++0x07
|
|
line.long 0x00 "TSUTIMERSEC,1588 Timer Seconds Register 31:0 Register"
|
|
line.long 0x04 "TSUTIMERNSEC,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x04 0.--29. 1. " TIMER ,Timer count in nanoseconds"
|
|
wgroup.long 0x1D8++0x03
|
|
line.long 0x00 "TSUTIMERADJUST,TSU Timer Adjust Register"
|
|
bitfld.long 0x00 31. " ADDSUBTRACT ,Write as one to subtract from the 1588 timer" "No add,Add"
|
|
hexmask.long 0x00 0.--29. 1. " INCREMENTVAL ,Timer increment value"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TSUTIMERINCR,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NUMINCS ,Number of incs before alt inc"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALTNSINCR ,Alternative nanoseconds count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NSINCREMENT ,A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle"
|
|
rgroup.long 0x1E0++0x1F
|
|
line.long 0x00 "TSUPTPTXSEC,PTP Event Frame Transmitted Seconds Register 31:0"
|
|
line.long 0x04 "TSUPTPTXNSEC,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x04 0.--29. 1. " TIMER ,PTP event frame transmitted nanoseconds"
|
|
line.long 0x08 "TSUPTPRXSEC,PTP Event Frame Received Seconds Register 31:0"
|
|
line.long 0x0C "TSUPTPRXNSEC,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x0C 0.--29. 1. " TIMER ,PTP event frame received nanoseconds"
|
|
line.long 0x10 "TSUPEERTXSEC,PTP Peer Event Frame Transmitted Seconds Register 31:0"
|
|
line.long 0x14 "TSUPEERTXNSEC,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. " TIMER ,PTP peer event frame transmitted nanoseconds"
|
|
line.long 0x18 "TSUPEERRXSEC,PTP Peer Event Frame Received Seconds Register 31:0"
|
|
line.long 0x1C "TSUPEERRXNSEC,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. " TIMER ,PTP peer event frame received nanoseconds"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TXPAUSEQUANT1,Transmit Pause Quantum Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " QUANTP3 ,Transmit pause quantum (pause frame transmission of priority 3)"
|
|
hexmask.long.word 0x00 0.--15. 1. " QUANTP2 ,Transmit pause quantum (pause frame transmission of priority 2)"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "TXPAUSEQUANT2,Transmit Pause Quantum Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " QUANTP5 ,Transmit pause quantum (pause frame transmission of priority 5)"
|
|
hexmask.long.word 0x00 0.--15. 1. " QUANTP4 ,Transmit pause quantum (pause frame transmission of priority 4)"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "TXPAUSEQUANT3,Transmit Pause Quantum Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " QUANTP7 ,Transmit pause quantum (pause frame transmission of priority 7)"
|
|
hexmask.long.word 0x00 0.--15. 1. " QUANTP6 ,Transmit pause quantum (pause frame transmission of priority 6)"
|
|
group.long 0x270++0x0F
|
|
line.long 0x00 "RXLPI,Received LPI Transitions Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count of RX LPI transitions"
|
|
line.long 0x04 "RXLPITIME,Received LPI Time Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " LPITIME ,Time in LPI"
|
|
line.long 0x08 "TXLPI,Transmit LPI Transitions Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Count of LPI transitions"
|
|
line.long 0x0C "TXLPITIME,Transmit LPI Time Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " LPITIME ,Time in LPI"
|
|
group.long 0x4CC++0x07
|
|
line.long 0x00 "TXBDCTRL,1TX BD Control Register"
|
|
bitfld.long 0x00 4.--5. " TXBDTSMODE ,TX descriptor timestamp insertion mode" "Disabled,PTP event frames only,All PTP frames only,All frames"
|
|
line.long 0x04 "RXBDCTRL,RX BD Control Register"
|
|
bitfld.long 0x04 4.--5. " RXBDTSMODE ,RX descriptor timestamp insertion mode" "Disabled,PTP event frames only,All PTP frames only,All frames"
|
|
group.long 0xC00++0x07
|
|
line.long 0x00 "ROUTEPEN,I/O Route Enable Register"
|
|
bitfld.long 0x00 5. " TSUTMRTOGPEN ,TSU_TMR_CNT_SEC output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RMIIPEN ,RMII I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MIIPEN ,MII I/O enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MIIRXERPEN ,MII RX ER I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MIITXERPEN ,MII TX ER I/O enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDIOPEN ,MDIO I/O enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTELOC0,I/O Route Location Register 0"
|
|
bitfld.long 0x04 24.--29. " MIICOLLOC ,Location of the MII COL pin" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x04 16.--21. " MIICRSLOC ,Location of the MII CRS pin" "LOC0,LOC1,LOC2,?..."
|
|
bitfld.long 0x04 8.--13. " MIIRXLOC ,Location of the RXDn, RX CLK and RX_DV pins" "LOC0,LOC1,LOC2,?..."
|
|
newline
|
|
bitfld.long 0x04 0.--5. " MIITXLOC ,Location of the TXDn, TX_CLK and TX_PEN pins" "LOC0,LOC1,?..."
|
|
group.long 0xC0C++0x07
|
|
line.long 0x00 "ROUTELOC1,I/O Route Location Register 1"
|
|
bitfld.long 0x00 24.--29. " RMIILOC ,Location of the RMII pins" "LOC0,LOC1,?..."
|
|
bitfld.long 0x00 16.--21. " MDIOLOC ,Location of the MDIO and MDC pins" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
bitfld.long 0x00 8.--13. " TSUTMRTOGLOC ,Location of the TSU_TMR_CNT_SEC pin" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. " TSUEXTCLKLOC ,Location of the TSU_EXT_CLK pin" "LOC0,LOC1,LOC2,LOC3,?..."
|
|
line.long 0x04 "CTRL,Ethernet Control Register"
|
|
bitfld.long 0x04 10. " TXREFCLKSEL ,REFCLK source select for RMII_TXD and RMII_TX_EN" "REFCLKINT,REFCLKPIN"
|
|
bitfld.long 0x04 9. " GBLCLKEN ,Global clock enable signal for ethernet clocks tsu_clk, tx_clk, rx_clk and ref_clk" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " MIISEL ,MII select signal" "RMII,MII"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " TSUPRESC ,Clock division factor of TSUPRESC+1" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--2. " TSUCLKSEL ,TSU clock selection value" "NOCLOCK,PLL,RXCLK,REFCLK,TSUEXTCLK,?..."
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "CSEN (Capacitive Sense Module)"
|
|
base ad:0x4008E000
|
|
width 15.
|
|
if (((per.l(ad:0x4008E000))&0x2000000)==0x00)
|
|
if (((per.l(ad:0x4008E000))&0x30)==(0x00||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 28. " CPACCURACY ,Charge pump accuracy" "Low accuracy,High accuracy"
|
|
bitfld.long 0x00 27. " LOCALSENS ,Local sensing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WARMUPMODE ,Warmup mode enable for CSEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " EMACMPEN ,Greater and less than comparison using the exponential moving average (EMA) enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MXUC ,CSEN mux disconnect" "Connected,Disconnected"
|
|
bitfld.long 0x00 23. " AUTOGND ,CSEN automatic ground enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " CHOPEN ,CSEN chop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONVSEL ,CSEN converter select" "SAR,DM"
|
|
bitfld.long 0x00 20. " DMAEN ,CSEN DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DRSF ,CSEN disable right-shift" "No,Yes"
|
|
bitfld.long 0x00 18. " CMPEN ,CSEN digital comparator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MCEN ,CSEN multiple channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " STM ,Start trigger select" "PRS,Timer,Start,?..."
|
|
bitfld.long 0x00 12.--14. " ACU ,CSEN accumulator mode select" "ACC1,ACC2,ACC4,ACC8,ACC16,ACC32,ACC64,?..."
|
|
bitfld.long 0x00 8.--9. " SARCR ,SAR conversion resolution" "CLK10,CLK12,CLK14,CLK16"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " CM ,CSEN conversion mode select" "SGL,SCAN,CONTSGL,CONTSCAN"
|
|
bitfld.long 0x00 2. " CMPPOL ,CSEN digital comparator polarity select" "GT,LTE"
|
|
bitfld.long 0x00 1. " EN ,CSEN enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 28. " CPACCURACY ,Charge pump accuracy" "Low accuracy,High accuracy"
|
|
bitfld.long 0x00 27. " LOCALSENS ,Local sensing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WARMUPMODE ,Warmup mode enable for CSEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " EMACMPEN ,Greater and less than comparison using the exponential moving average (EMA) enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MXUC ,CSEN mux disconnect" "Connected,Disconnected"
|
|
bitfld.long 0x00 23. " AUTOGND ,CSEN automatic ground enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " CHOPEN ,CSEN chop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONVSEL ,CSEN converter select" "SAR,DM"
|
|
bitfld.long 0x00 20. " DMAEN ,CSEN DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DRSF ,CSEN disable right-shift" "No,Yes"
|
|
bitfld.long 0x00 18. " CMPEN ,CSEN digital comparator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " STM ,Start trigger select" "PRS,Timer,Start,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. " ACU ,CSEN accumulator mode select" "ACC1,ACC2,ACC4,ACC8,ACC16,ACC32,ACC64,?..."
|
|
bitfld.long 0x00 8.--9. " SARCR ,SAR conversion resolution" "CLK10,CLK12,CLK14,CLK16"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " CM ,CSEN conversion mode select" "SGL,SCAN,CONTSGL,CONTSCAN"
|
|
bitfld.long 0x00 2. " CMPPOL ,CSEN digital comparator polarity select" "GT,LTE"
|
|
bitfld.long 0x00 1. " EN ,CSEN enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4008E000))&0x30)==(0x00||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 28. " CPACCURACY ,Charge pump accuracy" "Low accuracy,High accuracy"
|
|
bitfld.long 0x00 27. " LOCALSENS ,Local sensing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WARMUPMODE ,Warmup mode enable for CSEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " EMACMPEN ,Greater and less than comparison using the exponential moving average (EMA) enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MXUC ,CSEN mux disconnect" "Connected,Disconnected"
|
|
bitfld.long 0x00 23. " AUTOGND ,CSEN automatic ground enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " CHOPEN ,CSEN chop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONVSEL ,CSEN converter select" "SAR,DM"
|
|
bitfld.long 0x00 20. " DMAEN ,CSEN DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DRSF ,CSEN disable right-shift" "No,Yes"
|
|
bitfld.long 0x00 15. " MCEN ,CSEN multiple channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " STM ,Start trigger select" "PRS,Timer,Start,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. " ACU ,CSEN accumulator mode select" "ACC1,ACC2,ACC4,ACC8,ACC16,ACC32,ACC64,?..."
|
|
bitfld.long 0x00 8.--9. " SARCR ,SAR conversion resolution" "CLK10,CLK12,CLK14,CLK16"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " CM ,CSEN conversion mode select" "SGL,SCAN,CONTSGL,CONTSCAN"
|
|
bitfld.long 0x00 2. " CMPPOL ,CSEN digital comparator polarity select" "GT,LTE"
|
|
bitfld.long 0x00 1. " EN ,CSEN enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 28. " CPACCURACY ,Charge pump accuracy" "Low accuracy,High accuracy"
|
|
bitfld.long 0x00 27. " LOCALSENS ,Local sensing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WARMUPMODE ,Warmup mode enable for CSEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " EMACMPEN ,Greater and less than comparison using the exponential moving average (EMA) enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MXUC ,CSEN mux disconnect" "Connected,Disconnected"
|
|
bitfld.long 0x00 23. " AUTOGND ,CSEN automatic ground enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " CHOPEN ,CSEN chop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CONVSEL ,CSEN converter select" "SAR,DM"
|
|
bitfld.long 0x00 20. " DMAEN ,CSEN DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DRSF ,CSEN disable right-shift" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " STM ,Start trigger select" "PRS,Timer,Start,?..."
|
|
bitfld.long 0x00 12.--14. " ACU ,CSEN accumulator mode select" "ACC1,ACC2,ACC4,ACC8,ACC16,ACC32,ACC64,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " SARCR ,SAR conversion resolution" "CLK10,CLK12,CLK14,CLK16"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " CM ,CSEN conversion mode select" "SGL,SCAN,CONTSGL,CONTSCAN"
|
|
bitfld.long 0x00 2. " CMPPOL ,CSEN digital comparator polarity select" "GT,LTE"
|
|
bitfld.long 0x00 1. " EN ,CSEN enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TIMCTRL,Timing Control Register"
|
|
bitfld.long 0x00 16.--17. " WARMUPCNT ,Warmup period counter" "3 CSEN clk,4 CSEN clk,5 CSEN clk,6 CSEN clk"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PCTOP ,Period counter top value"
|
|
bitfld.long 0x00 0.--2. " PCPRESC ,Period counter prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CMD,Command Register"
|
|
bitfld.long 0x00 0. " START ,Start software-triggered conversions" "No effect,Trigger"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 0. " CSENBUSY ,Busy flag" "Idle,Busy"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "PRSSEL,PRS Select Register"
|
|
bitfld.long 0x00 0.--4. " PRSSEL ,PRS channel select" "PRSCH0,PRSCH1,PRSCH2,PRSCH3,PRSCH4,PRSCH5,PRSCH6,PRSCH7,PRSCH8,PRSCH9,PRSCH10,PRSCH11,PRSCH12,PRSCH13,PRSCH14,PRSCH15,PRSCH16,PRSCH17,PRSCH18,PRSCH19,PRSCH20,PRSCH21,PRSCH22,PRSCH23,?..."
|
|
newline
|
|
line.long 0x04 "DATA,Output Data Register"
|
|
line.long 0x08 "SCANMASK0,Scan Channel Mask 0 Register"
|
|
bitfld.long 0x08 31. " SCANINPUTEN[31] ,Scan channel 31 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 30. " [30] ,Scan channel 30 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 29. " [29] ,Scan channel 29 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 28. " [28] ,Scan channel 28 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 27. " [27] ,Scan channel 27 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " [26] ,Scan channel 26 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 25. " [25] ,Scan channel 25 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " [24] ,Scan channel 24 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 23. " [23] ,Scan channel 23 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 22. " [22] ,Scan channel 22 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 21. " [21] ,Scan channel 21 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 20. " [20] ,Scan channel 20 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Scan channel 19 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 18. " [18] ,Scan channel 18 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 17. " [17] ,Scan channel 17 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 16. " [16] ,Scan channel 16 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 15. " [15] ,Scan channel 15 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Scan channel 14 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Scan channel 13 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 12. " [12] ,Scan channel 12 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,Scan channel 11 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Scan channel 10 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " [9] ,Scan channel 9 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Scan channel 8 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Scan channel 7 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [6] ,Scan channel 6 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [5] ,Scan channel 5 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Scan channel 4 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Scan channel 3 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Scan channel 2 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " [1] ,Scan channel 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [0] ,Scan channel 0 mask" "Not masked,Masked"
|
|
newline
|
|
line.long 0x0C "SCANINPUTSEL0,Scan Input Selection 0 Register"
|
|
bitfld.long 0x0C 24.--27. " INPUT24TO31SEL ,CSEN_INPUT24-31 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
bitfld.long 0x0C 16.--19. " INPUT16TO23SEL ,CSEN_INPUT16-23 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
bitfld.long 0x0C 8.--11. " INPUT8TO15SEL ,CSEN_INPUT8-15 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. " INPUT0TO7SEL ,CSEN_INPUT0-7 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
newline
|
|
line.long 0x10 "SCANMASK1,Scan Channel Mask 1 Register"
|
|
bitfld.long 0x10 31. " SCANINPUTEN[63] ,Scan channel 63 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 30. " [62] ,Scan channel 62 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 29. " [61] ,Scan channel 61 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 28. " [60] ,Scan channel 60 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 27. " [59] ,Scan channel 59 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 26. " [58] ,Scan channel 58 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 25. " [57] ,Scan channel 57 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 24. " [56] ,Scan channel 56 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 23. " [55] ,Scan channel 55 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 22. " [54] ,Scan channel 54 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 21. " [53] ,Scan channel 53 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 20. " [52] ,Scan channel 52 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 19. " [51] ,Scan channel 51 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 18. " [50] ,Scan channel 50 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 17. " [49] ,Scan channel 49 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 16. " [48] ,Scan channel 48 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 15. " [47] ,Scan channel 47 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 14. " [46] ,Scan channel 46 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 13. " [45] ,Scan channel 45 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 12. " [44] ,Scan channel 44 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 11. " [43] ,Scan channel 43 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 10. " [42] ,Scan channel 42 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 9. " [41] ,Scan channel 41 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 8. " [40] ,Scan channel 40 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [39] ,Scan channel 39 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 6. " [38] ,Scan channel 38 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 5. " [37] ,Scan channel 37 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 4. " [36] ,Scan channel 36 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 3. " [35] ,Scan channel 35 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 2. " [34] ,Scan channel 34 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 1. " [33] ,Scan channel 33 mask" "Not masked,Masked"
|
|
bitfld.long 0x10 0. " [32] ,Scan channel 32 mask" "Not masked,Masked"
|
|
newline
|
|
line.long 0x14 "SCANINPUTSEL1,Scan Input Selection 1 Register"
|
|
bitfld.long 0x14 24.--27. " INPUT56TO63SEL ,CSEN_INPUT56-63 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
bitfld.long 0x14 16.--19. " INPUT48TO55SEL ,CSEN_INPUT48-55 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
bitfld.long 0x14 8.--11. " INPUT40TO47SEL ,CSEN_INPUT40-47 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
newline
|
|
bitfld.long 0x14 0.--3. " INPUT32TO39SEL ,CSEN_INPUT32-39 select" ",,,,APORT1CH0TO7,APORT1CH8TO15,APORT1CH16TO23,APORT1CH24TO31,,,,,APORT3CH0TO7,APORT3CH8TO15,APORT3CH16TO23,APORT3CH24TO31"
|
|
newline
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "APORTREQ,APORT Request Status Register"
|
|
bitfld.long 0x00 9. " APORT4YREQ ,Bus connected to APORT4Y requested from the APORT" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " APORT4XREQ ,Bus connected to APORT4X requested from the APORT" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " APORT3YREQ ,Bus connected to APORT3Y requested from the APORT" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 6. " APORT3XREQ ,Bus connected to APORT3X requested from the APORT" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " APORT2YREQ ,Bus connected to APORT2Y requested from the APORT" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " APORT2XREQ ,Bus connected to APORT2X requested from the APORT" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " APORT1YREQ ,Bus connected to APORT1Y requested from the APORT" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " APORT1XREQ ,Bus connected to APORT1X requested from the APORT" "Not requested,Requested"
|
|
line.long 0x04 "APORTCONFLICT,APORT Request Conflict Register"
|
|
bitfld.long 0x04 9. " APORT4YCONFLICT ,APORT4Y also requested by another peripheral" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " APORT4XCONFLICT ,APORT4X also requested by another peripheral" "Not requested,Requested"
|
|
bitfld.long 0x04 7. " APORT3YCONFLICT ,APORT3Y also requested by another peripheral" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 6. " APORT3XCONFLICT ,APORT3X also requested by another peripheral" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " APORT2YCONFLICT ,APORT2Y also requested by another peripheral" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " APORT2XCONFLICT ,APORT2X also requested by another peripheral" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " APORT1YCONFLICT ,APORT1Y also requested by another peripheral" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " APORT1XCONFLICT ,APORT1X also requested by another peripheral" "Not requested,Requested"
|
|
group.long 0x30++0x1B
|
|
line.long 0x00 "CMPTHR,Comparator Threshold Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMPTHR ,Comparator threshold"
|
|
line.long 0x04 "EMA,Exponential Moving Average Register"
|
|
hexmask.long.tbyte 0x04 0.--21. 1. " EMA ,Calculated exponential moving average"
|
|
line.long 0x08 "EMACTRL,Exponential Moving Average Control Register"
|
|
bitfld.long 0x08 0.--2. " EMASAMPLE ,EMA sample weight" "W1,W2,W4,W8,W16,W32,W64,?..."
|
|
line.long 0x0C "SINGLECTRL,Single Conversion Control Register"
|
|
hexmask.long.byte 0x0C 4.--10. 1. " SINGLESEL ,Single channel input select"
|
|
line.long 0x10 "DMBASELINE,Delta Modulation Baseline Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " BASELINEDN ,Delta modulator integrator initial value"
|
|
hexmask.long.word 0x10 0.--15. 1. " BASELINEUP ,Delta modulator integrator initial value"
|
|
line.long 0x14 "DMCFG,Delta Modulation Configuration Register"
|
|
bitfld.long 0x14 28. " DMGRDIS ,Delta modulation gain step reduction disable" "No,Yes"
|
|
bitfld.long 0x14 20.--21. " CRMODE ,Delta modulator conversion resolution" "10-bit,12-bit,14-bit,16-bit"
|
|
bitfld.long 0x14 16.--19. " DMCR ,Delta modulator conversion rate" "16 cycles,?..."
|
|
newline
|
|
bitfld.long 0x14 8.--11. " DMR ,Delta modulator gain reduction interval" "64 tests,4 tests,8 tests,12 tests,16 tests,20 tests,24 tests,28 tests,32 tests,36 tests,40 tests,44 tests,48 tests,52 tests,56 tests,60 tests"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DMG ,Delta modulator gain step"
|
|
line.long 0x18 "ANACTRL,Analog Control Register"
|
|
bitfld.long 0x18 20.--22. " TRSTPROG ,Reset timing" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 8.--10. " IDACIREFS ,Current DAC and reference current scale" "Max,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x18 4.--6. " IREFPROG ,Reference current control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "IF_SET/CLR,Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " APORTCONFLICT ,APORT conflict interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DMAOF ,DMA overflow interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " EOS ,End of scan interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CONV ,Conversion done interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CMP ,Digital comparator interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " APORTCONFLICT ,APORTCONFLICT interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " DMAOF ,DMAOF interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " EOS ,EOS interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " CONV ,CONV interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CMP ,CMP interrupt enable" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN0"
|
|
base ad:0x40004000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 7. " TEST ,Test mode enable write access to the test register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,Module interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " INIT ,CAN initialize" "Disabled,Enabled"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "STATUS,Status Register"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ERRCNT,Error Count Register"
|
|
bitfld.long 0x00 15. " RECERRP ,Receive error passive level" "Not reached,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit error counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BITTIMING,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization jump width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INTID,Interrupt Identification Register"
|
|
bitfld.long 0x00 15. " INTSTAT ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0.--5. " INTID ,Interrupt identifier" "No interrupt,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TEST,Test Register"
|
|
rbitfld.long 0x00 7. " RX ,Actual CAN_RX pin value" "Dominant,Recessive"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Core,SAMPT,Low,High"
|
|
bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
line.long 0x04 "BRPE,BRP Extension Register"
|
|
bitfld.long 0x04 0.--3. " BRPE ,Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "TRANSREQ,Transmission Request Register"
|
|
bitfld.long 0x00 31. " TXRQSTOUT[31] ,Transmission request bit 31" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Transmission request bit 30" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Transmission request bit 29" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Transmission request bit 28" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Transmission request bit 27" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " [26] ,Transmission request bit 26" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Transmission request bit 25" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Transmission request bit 24" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Transmission request bit 23" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Transmission request bit 22" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Transmission request bit 21" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Transmission request bit 20" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Transmission request bit 19" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Transmission request bit 18" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Transmission request bit 17" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Transmission request bit 16" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Transmission request bit 15" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Transmission request bit 14" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Transmission request bit 13" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Transmission request bit 12" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Transmission request bit 11" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Transmission request bit 10" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Transmission request bit 9" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Transmission request bit 8" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Transmission request bit 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Transmission request bit 6" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Transmission request bit 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Transmission request bit 4" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Transmission request bit 3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission request bit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Transmission request bit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission request bit 0" "Not requested,Requested"
|
|
line.long 0x04 "MESSAGEDATA,New Data Register"
|
|
bitfld.long 0x04 31. " VALID[31] ,Message object 31 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 30. " [30] ,Message object 30 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 29. " [29] ,Message object 29 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 28. " [28] ,Message object 28 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Message object 27 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 26. " [26] ,Message object 26 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 25. " [25] ,Message object 25 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 24. " [24] ,Message object 24 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Message object 23 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 22. " [22] ,Message object 22 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 21. " [21] ,Message object 21 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 20. " [20] ,Message object 20 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Message object 19 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 18. " [18] ,Message object 18 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 17. " [17] ,Message object 17 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 16. " [16] ,Message object 16 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Message object 15 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 14. " [14] ,Message object 14 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 13. " [13] ,Message object 13 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 12. " [12] ,Message object 12 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Message object 11 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 10. " [10] ,Message object 10 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 9. " [9] ,Message object 9 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 8. " [8] ,Message object 8 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Message object 7 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 6. " [6] ,Message object 6 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 5. " [5] ,Message object 5 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 4. " [4] ,Message object 4 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Message object 3 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 2. " [2] ,Message object 2 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 1. " [1] ,Message object 1 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 0. " [0] ,Message object 0 data portion update" "Not updated,Updated"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "MESSAGESTATE,Message Valid Register"
|
|
bitfld.long 0x00 31. " VALID[31] ,Message object 31 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " [30] ,Message object 30 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 29. " [29] ,Message object 29 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 28. " [28] ,Message object 28 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Message object 27 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 26. " [26] ,Message object 26 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 25. " [25] ,Message object 25 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 24. " [24] ,Message object 24 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Message object 23 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 22. " [22] ,Message object 22 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 21. " [21] ,Message object 21 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 20. " [20] ,Message object 20 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Message object 19 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " [18] ,Message object 18 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " [17] ,Message object 17 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " [16] ,Message object 16 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Message object 15 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " [14] ,Message object 14 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " [13] ,Message object 13 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 12. " [12] ,Message object 12 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Message object 11 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " [10] ,Message object 10 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " [9] ,Message object 9 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 8. " [8] ,Message object 8 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Message object 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " [6] ,Message object 6 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " [5] ,Message object 5 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " [4] ,Message object 4 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Message object 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " [2] ,Message object 2 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " [1] ,Message object 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " [0] ,Message object 0 valid" "Not valid,Valid"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "CONFIG,Configuration Register"
|
|
bitfld.long 0x00 15. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
line.long 0x04 "IF0IF_SET/CLR,Message Object Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 31. 0x08 31. 0x0C 31. " MESSAGE[31] ,Message object 31 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x08 30. 0x0C 30. " [30] ,Message object 30 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x08 29. 0x0C 29. " [29] ,Message object 29 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x08 28. 0x0C 28. " [28] ,Message object 28 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 27. 0x08 27. 0x0C 27. " [27] ,Message object 27 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x08 26. 0x0C 26. " [26] ,Message object 26 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x08 25. 0x0C 25. " [25] ,Message object 25 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 24. 0x08 24. 0x0C 24. " [24] ,Message object 24 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " [23] ,Message object 23 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Message object 22 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Message object 21 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Message object 20 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,Message object 19 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,Message object 18 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,Message object 17 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,Message object 16 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,Message object 15 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,Message object 14 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,Message object 13 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,Message object 12 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,Message object 11 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,Message object 10 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x08 9. 0x0C 9. " [9] ,Message object 9 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x08 8. 0x0C 8. " [8] ,Message object 8 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " [7] ,Message object 7 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " [6] ,Message object 6 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " [5] ,Message object 5 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " [4] ,Message object 4 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " [3] ,Message object 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " [2] ,Message object 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " [1] ,Message object 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " [0] ,Message object 0 interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IF0IEN,Message Object Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " MESSAGE[31] ,Message 31 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Message 30 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Message 29 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Message 28 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Message 27 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Message 26 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Message 25 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Message 24 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Message 23 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Message 22 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Message 21 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Message 20 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Message 19 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Message 18 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Message 17 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Message 16 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Message 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Message 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Message 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Message 12 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Message 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Message 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Message 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Message 8 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Message 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Message 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Message 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Message 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Message 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Message 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Message 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Message 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF1IF_SET/CLR,Status Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " STATUS ,Status interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IF1IEN,Status Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " STATUS ,Status interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTE,I/O Routing Register"
|
|
bitfld.long 0x04 8.--13. " TXLOC ,TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x04 2.--7. " RXLOC ,RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x04 0. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "MIR0_CMDMASK,Interface Command Mask Register"
|
|
bitfld.long 0x00 7. " WRRD ,Write/Read RAM" "Read,Write"
|
|
bitfld.long 0x00 6. " MASKACC ,Access mask bits" "No access,Access"
|
|
bitfld.long 0x00 5. " ARBACC ,Access arbitration bits" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 4. " CONTROL ,Access control bits" "No access,Access"
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " TXRQSTNEWDAT ,Transmission request bit/New data bit" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAA ,Access data bytes 0-3" "No access,Access"
|
|
bitfld.long 0x00 0. " DATAB ,CC channel mode" "Disabled,Enabled"
|
|
line.long 0x04 "MIR0_MASK,Interface Mask Register"
|
|
bitfld.long 0x04 31. " MXTD ,Mask extended identifier" "0,1"
|
|
bitfld.long 0x04 30. " MDIR ,Mask message direction" "RX,TX"
|
|
hexmask.long 0x04 0.--28. 1. " MASK ,Identifier mask"
|
|
if (((per.l(ad:0x40004000+0x60+0x08))&0x40000000)==0x40000000)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "MIR0_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. " MASK ,Message identifier"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "MIR0_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long.word 0x00 18.--28. 1. " MASK ,Message identifier"
|
|
endif
|
|
if (((per.l(ad:0x40004000+0x60+0x08))&0x20000000)==0x00)
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "MIR0_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " MESSAGEOF ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0B,1B,2B,3B,4B,5B,6B,7B,8B,8B,8B,8B,8B,8B,8B,8B"
|
|
else
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "MIR0_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x60+0x10)++0x0B
|
|
line.long 0x00 "MIR0_DATAL,Interface Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Fourth byte of CAN data frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Third byte of CAN data frame"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Second byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,First byte of CAN data frame"
|
|
line.long 0x04 "MIR0_DATAH,Interface Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Eight byte of CAN data frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Seventh byte of CAN data frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Sixth byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Fifth byte of CAN data frame"
|
|
line.long 0x08 "MIR0_CMDREQ,Interface Command Request Register"
|
|
rbitfld.long 0x08 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x08 0.--5. " MSGNUM ,Message number" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "MIR1_CMDMASK,Interface Command Mask Register"
|
|
bitfld.long 0x00 7. " WRRD ,Write/Read RAM" "Read,Write"
|
|
bitfld.long 0x00 6. " MASKACC ,Access mask bits" "No access,Access"
|
|
bitfld.long 0x00 5. " ARBACC ,Access arbitration bits" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 4. " CONTROL ,Access control bits" "No access,Access"
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " TXRQSTNEWDAT ,Transmission request bit/New data bit" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAA ,Access data bytes 0-3" "No access,Access"
|
|
bitfld.long 0x00 0. " DATAB ,CC channel mode" "Disabled,Enabled"
|
|
line.long 0x04 "MIR1_MASK,Interface Mask Register"
|
|
bitfld.long 0x04 31. " MXTD ,Mask extended identifier" "0,1"
|
|
bitfld.long 0x04 30. " MDIR ,Mask message direction" "RX,TX"
|
|
hexmask.long 0x04 0.--28. 1. " MASK ,Identifier mask"
|
|
if (((per.l(ad:0x40004000+0x80+0x08))&0x40000000)==0x40000000)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "MIR1_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. " MASK ,Message identifier"
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "MIR1_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long.word 0x00 18.--28. 1. " MASK ,Message identifier"
|
|
endif
|
|
if (((per.l(ad:0x40004000+0x80+0x08))&0x20000000)==0x00)
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "MIR1_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " MESSAGEOF ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0B,1B,2B,3B,4B,5B,6B,7B,8B,8B,8B,8B,8B,8B,8B,8B"
|
|
else
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "MIR1_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x80+0x10)++0x0B
|
|
line.long 0x00 "MIR1_DATAL,Interface Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Fourth byte of CAN data frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Third byte of CAN data frame"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Second byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,First byte of CAN data frame"
|
|
line.long 0x04 "MIR1_DATAH,Interface Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Eight byte of CAN data frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Seventh byte of CAN data frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Sixth byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Fifth byte of CAN data frame"
|
|
line.long 0x08 "MIR1_CMDREQ,Interface Command Request Register"
|
|
rbitfld.long 0x08 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x08 0.--5. " MSGNUM ,Message number" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x40004400
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 7. " TEST ,Test mode enable write access to the test register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,Module interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " INIT ,CAN initialize" "Disabled,Enabled"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "STATUS,Status Register"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ERRCNT,Error Count Register"
|
|
bitfld.long 0x00 15. " RECERRP ,Receive error passive level" "Not reached,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit error counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BITTIMING,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization jump width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INTID,Interrupt Identification Register"
|
|
bitfld.long 0x00 15. " INTSTAT ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0.--5. " INTID ,Interrupt identifier" "No interrupt,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TEST,Test Register"
|
|
rbitfld.long 0x00 7. " RX ,Actual CAN_RX pin value" "Dominant,Recessive"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Core,SAMPT,Low,High"
|
|
bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
line.long 0x04 "BRPE,BRP Extension Register"
|
|
bitfld.long 0x04 0.--3. " BRPE ,Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "TRANSREQ,Transmission Request Register"
|
|
bitfld.long 0x00 31. " TXRQSTOUT[31] ,Transmission request bit 31" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Transmission request bit 30" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Transmission request bit 29" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Transmission request bit 28" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Transmission request bit 27" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " [26] ,Transmission request bit 26" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Transmission request bit 25" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Transmission request bit 24" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Transmission request bit 23" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Transmission request bit 22" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Transmission request bit 21" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Transmission request bit 20" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Transmission request bit 19" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Transmission request bit 18" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Transmission request bit 17" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Transmission request bit 16" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Transmission request bit 15" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Transmission request bit 14" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Transmission request bit 13" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Transmission request bit 12" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Transmission request bit 11" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Transmission request bit 10" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Transmission request bit 9" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Transmission request bit 8" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Transmission request bit 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Transmission request bit 6" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Transmission request bit 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Transmission request bit 4" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Transmission request bit 3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission request bit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Transmission request bit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission request bit 0" "Not requested,Requested"
|
|
line.long 0x04 "MESSAGEDATA,New Data Register"
|
|
bitfld.long 0x04 31. " VALID[31] ,Message object 31 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 30. " [30] ,Message object 30 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 29. " [29] ,Message object 29 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 28. " [28] ,Message object 28 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Message object 27 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 26. " [26] ,Message object 26 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 25. " [25] ,Message object 25 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 24. " [24] ,Message object 24 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Message object 23 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 22. " [22] ,Message object 22 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 21. " [21] ,Message object 21 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 20. " [20] ,Message object 20 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Message object 19 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 18. " [18] ,Message object 18 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 17. " [17] ,Message object 17 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 16. " [16] ,Message object 16 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Message object 15 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 14. " [14] ,Message object 14 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 13. " [13] ,Message object 13 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 12. " [12] ,Message object 12 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Message object 11 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 10. " [10] ,Message object 10 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 9. " [9] ,Message object 9 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 8. " [8] ,Message object 8 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Message object 7 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 6. " [6] ,Message object 6 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 5. " [5] ,Message object 5 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 4. " [4] ,Message object 4 data portion update" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Message object 3 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 2. " [2] ,Message object 2 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 1. " [1] ,Message object 1 data portion update" "Not updated,Updated"
|
|
bitfld.long 0x04 0. " [0] ,Message object 0 data portion update" "Not updated,Updated"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "MESSAGESTATE,Message Valid Register"
|
|
bitfld.long 0x00 31. " VALID[31] ,Message object 31 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " [30] ,Message object 30 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 29. " [29] ,Message object 29 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 28. " [28] ,Message object 28 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Message object 27 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 26. " [26] ,Message object 26 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 25. " [25] ,Message object 25 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 24. " [24] ,Message object 24 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Message object 23 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 22. " [22] ,Message object 22 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 21. " [21] ,Message object 21 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 20. " [20] ,Message object 20 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Message object 19 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 18. " [18] ,Message object 18 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 17. " [17] ,Message object 17 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " [16] ,Message object 16 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Message object 15 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " [14] ,Message object 14 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " [13] ,Message object 13 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 12. " [12] ,Message object 12 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Message object 11 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " [10] ,Message object 10 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " [9] ,Message object 9 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 8. " [8] ,Message object 8 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Message object 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " [6] ,Message object 6 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " [5] ,Message object 5 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " [4] ,Message object 4 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Message object 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " [2] ,Message object 2 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " [1] ,Message object 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " [0] ,Message object 0 valid" "Not valid,Valid"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "CONFIG,Configuration Register"
|
|
bitfld.long 0x00 15. " DBGHALT ,Debug halt" "Not halted,Halted"
|
|
line.long 0x04 "IF0IF_SET/CLR,Message Object Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x04 31. 0x08 31. 0x0C 31. " MESSAGE[31] ,Message object 31 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x08 30. 0x0C 30. " [30] ,Message object 30 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x08 29. 0x0C 29. " [29] ,Message object 29 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x08 28. 0x0C 28. " [28] ,Message object 28 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 27. 0x08 27. 0x0C 27. " [27] ,Message object 27 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x08 26. 0x0C 26. " [26] ,Message object 26 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x08 25. 0x0C 25. " [25] ,Message object 25 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 24. 0x08 24. 0x0C 24. " [24] ,Message object 24 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " [23] ,Message object 23 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Message object 22 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Message object 21 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Message object 20 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,Message object 19 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,Message object 18 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,Message object 17 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,Message object 16 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,Message object 15 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,Message object 14 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,Message object 13 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,Message object 12 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,Message object 11 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,Message object 10 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x08 9. 0x0C 9. " [9] ,Message object 9 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x08 8. 0x0C 8. " [8] ,Message object 8 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " [7] ,Message object 7 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " [6] ,Message object 6 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " [5] ,Message object 5 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " [4] ,Message object 4 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " [3] ,Message object 3 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " [2] ,Message object 2 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " [1] ,Message object 1 interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " [0] ,Message object 0 interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IF0IEN,Message Object Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " MESSAGE[31] ,Message 31 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Message 30 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Message 29 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Message 28 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Message 27 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Message 26 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Message 25 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Message 24 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Message 23 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Message 22 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Message 21 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Message 20 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Message 19 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Message 18 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Message 17 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Message 16 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Message 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Message 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Message 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Message 12 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Message 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Message 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Message 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Message 8 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Message 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Message 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Message 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Message 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Message 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Message 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Message 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Message 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IF1IF_SET/CLR,Status Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " STATUS ,Status interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "IF1IEN,Status Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " STATUS ,Status interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ROUTE,I/O Routing Register"
|
|
bitfld.long 0x04 8.--13. " TXLOC ,TX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x04 2.--7. " RXLOC ,RX pin location" "LOC0,LOC1,LOC2,LOC3,LOC4,LOC5,LOC6,LOC7,?..."
|
|
bitfld.long 0x04 0. " TXPEN ,TX pin enable" "Disabled,Enabled"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "MIR0_CMDMASK,Interface Command Mask Register"
|
|
bitfld.long 0x00 7. " WRRD ,Write/Read RAM" "Read,Write"
|
|
bitfld.long 0x00 6. " MASKACC ,Access mask bits" "No access,Access"
|
|
bitfld.long 0x00 5. " ARBACC ,Access arbitration bits" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 4. " CONTROL ,Access control bits" "No access,Access"
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " TXRQSTNEWDAT ,Transmission request bit/New data bit" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAA ,Access data bytes 0-3" "No access,Access"
|
|
bitfld.long 0x00 0. " DATAB ,CC channel mode" "Disabled,Enabled"
|
|
line.long 0x04 "MIR0_MASK,Interface Mask Register"
|
|
bitfld.long 0x04 31. " MXTD ,Mask extended identifier" "0,1"
|
|
bitfld.long 0x04 30. " MDIR ,Mask message direction" "RX,TX"
|
|
hexmask.long 0x04 0.--28. 1. " MASK ,Identifier mask"
|
|
if (((per.l(ad:0x40004400+0x60+0x08))&0x40000000)==0x40000000)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "MIR0_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. " MASK ,Message identifier"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "MIR0_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long.word 0x00 18.--28. 1. " MASK ,Message identifier"
|
|
endif
|
|
if (((per.l(ad:0x40004400+0x60+0x08))&0x20000000)==0x00)
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "MIR0_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " MESSAGEOF ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0B,1B,2B,3B,4B,5B,6B,7B,8B,8B,8B,8B,8B,8B,8B,8B"
|
|
else
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "MIR0_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x60+0x10)++0x0B
|
|
line.long 0x00 "MIR0_DATAL,Interface Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Fourth byte of CAN data frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Third byte of CAN data frame"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Second byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,First byte of CAN data frame"
|
|
line.long 0x04 "MIR0_DATAH,Interface Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Eight byte of CAN data frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Seventh byte of CAN data frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Sixth byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Fifth byte of CAN data frame"
|
|
line.long 0x08 "MIR0_CMDREQ,Interface Command Request Register"
|
|
rbitfld.long 0x08 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x08 0.--5. " MSGNUM ,Message number" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "MIR1_CMDMASK,Interface Command Mask Register"
|
|
bitfld.long 0x00 7. " WRRD ,Write/Read RAM" "Read,Write"
|
|
bitfld.long 0x00 6. " MASKACC ,Access mask bits" "No access,Access"
|
|
bitfld.long 0x00 5. " ARBACC ,Access arbitration bits" "No access,Access"
|
|
newline
|
|
bitfld.long 0x00 4. " CONTROL ,Access control bits" "No access,Access"
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " TXRQSTNEWDAT ,Transmission request bit/New data bit" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAA ,Access data bytes 0-3" "No access,Access"
|
|
bitfld.long 0x00 0. " DATAB ,CC channel mode" "Disabled,Enabled"
|
|
line.long 0x04 "MIR1_MASK,Interface Mask Register"
|
|
bitfld.long 0x04 31. " MXTD ,Mask extended identifier" "0,1"
|
|
bitfld.long 0x04 30. " MDIR ,Mask message direction" "RX,TX"
|
|
hexmask.long 0x04 0.--28. 1. " MASK ,Identifier mask"
|
|
if (((per.l(ad:0x40004400+0x80+0x08))&0x40000000)==0x40000000)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "MIR1_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. " MASK ,Message identifier"
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "MIR1_ARB,Interface Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit ID,29-bit ID"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "RX,TX"
|
|
newline
|
|
hexmask.long.word 0x00 18.--28. 1. " MASK ,Message identifier"
|
|
endif
|
|
if (((per.l(ad:0x40004400+0x80+0x08))&0x20000000)==0x00)
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "MIR1_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " MESSAGEOF ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0B,1B,2B,3B,4B,5B,6B,7B,8B,8B,8B,8B,8B,8B,8B,8B"
|
|
else
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "MIR1_CTRL,Interface Message Control Register"
|
|
bitfld.long 0x00 15. " DATAVALID ,New data" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x80+0x10)++0x0B
|
|
line.long 0x00 "MIR1_DATAL,Interface Data A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Fourth byte of CAN data frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Third byte of CAN data frame"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Second byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,First byte of CAN data frame"
|
|
line.long 0x04 "MIR1_DATAH,Interface Data B Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Eight byte of CAN data frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Seventh byte of CAN data frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Sixth byte of CAN data frame"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Fifth byte of CAN data frame"
|
|
line.long 0x08 "MIR1_CMDREQ,Interface Command Request Register"
|
|
rbitfld.long 0x08 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x08 0.--5. " MSGNUM ,Message number" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
; tree "DBG (Debug Interface)"
|
|
; base ad:0x0
|
|
; %include efm32lgxxx/dbg.ph
|
|
; tree.end
|
|
newline
|