14150 lines
1.1 MiB
14150 lines
1.1 MiB
; --------------------------------------------------------------------------------
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; @Title: CC26XX On-Chip Peripherals
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; @Props: Released
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; @Author: ZUO, JRK, TPP
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; @Changelog: 2016-06-03 MMK
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; @Manufacturer: TI - Texas Instruments
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; @Doc: swcu117d-1.pdf (Rev.D 2015-09)
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; cc2630.pdf (Rev. 2015-02), cc2640.pdf (Rev. 2015-02), cc2650.pdf (Rev. 2015-02)
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; @Core: Cortex-M3
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; @Chip: CC2630F128, CC2640F128, CC2650F128
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: percc26xx.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; Known problems
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; MODULE REGISTER DESCRIPTION
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; AUX_ADI4 ADCREF1 no description how to calculate the value of VTRIM
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; AUX_WUC AUXCTL register missing
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; UARTS IMSC inverted mask definition in bitfields' description
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; SSI IMSC inverted mask definition in bitfields' description
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "EVENT (Event Fabric)"
|
|
tree "AON_EVENT (Always On Event Fabric)"
|
|
base ad:0x40093000
|
|
width 12.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MCUWUSEL,Wake-up Selector For MCU"
|
|
bitfld.long 0x00 24.--29. " WU3_EV ,MCU Wakeup Source #3" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
bitfld.long 0x00 16.--21. " WU2_EV ,MCU Wakeup Source #2" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " WU1_EV ,MCU Wakeup Source #1" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
bitfld.long 0x00 0.--5. " WU0_EV ,MCU Wakeup Source #0" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
line.long 0x04 "AUXWUSEL,Wake-up Selector For AUX"
|
|
bitfld.long 0x04 16.--21. " WU2_EV ,MCU Wakeup Source #2" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
bitfld.long 0x04 8.--13. " WU1_EV ,MCU Wakeup Source #1" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " WU0_EV ,MCU Wakeup Source #0" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
line.long 0x08 "EVTOMCUSEL,Event Selector For MCU Event Fabric"
|
|
bitfld.long 0x08 16.--21. " AON_PROG2_EV ,Event selector for AON_PROG2 event" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
bitfld.long 0x08 8.--13. " AON_PROG1_EV ,Event selector for AON_PROG2 event" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--5. " AON_PROG0_EV ,Event selector for AON_PROG2 event" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
line.long 0x0C "RTCSEL,RTC Capture Event Selector For AON_RTC"
|
|
bitfld.long 0x0C 0.--5. " RTC_CH1_CAPT_EV ,AON Event Source id# for RTCSEL event which is fed to AON_RTC" "Edge detect on PAD0,Edge detect on PAD1,Edge detect on PAD2,Edge detect on PAD3,Edge detect on PAD4,Edge detect on PAD5,Edge detect on PAD6,Edge detect on PAD7,Edge detect on PAD8,Edge detect on PAD9,Edge detect on PAD10,Edge detect on PAD11,Edge detect on PAD12,Edge detect on PAD13,Edge detect on PAD14,Edge detect on PAD15,Edge detect on PAD16,Edge detect on PAD17,Edge detect on PAD18,Edge detect on PAD19,Edge detect on PAD20,Edge detect on PAD21,Edge detect on PAD22,Edge detect on PAD23,Edge detect on PAD24,Edge detect on PAD25,Edge detect on PAD26,Edge detect on PAD27,Edge detect on PAD28,Edge detect on PAD29,Edge detect on PAD30,Edge detect on PAD31,Edge detect on any PAD,,,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick,JTAG generated event,AUX Software triggered event #0,AUX Software triggered event #1,AUX Software triggered event #2,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,Timer 0 event,Timer 1 event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered,Comparator B not triggered,No event (always low),?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "EVENT (MCU Event Fabric)"
|
|
base ad:0x40083000
|
|
width 15.
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 " CPUIRQSEL0 ,Output Selection for CPU Interrupt 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 " CPUIRQSEL1 ,Output Selection for CPU Interrupt 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 " CPUIRQSEL2 ,Output Selection for CPU Interrupt 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 " CPUIRQSEL4 ,Output Selection for CPU Interrupt 4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 " CPUIRQSEL5 ,Output Selection for CPU Interrupt 5"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 " CPUIRQSEL6 ,Output Selection for CPU Interrupt 6"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 " CPUIRQSEL7 ,Output Selection for CPU Interrupt 7"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 " CPUIRQSEL8 ,Output Selection for CPU Interrupt 8"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 " CPUIRQSEL9 ,Output Selection for CPU Interrupt 9"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 " CPUIRQSEL10 ,Output Selection for CPU Interrupt 10"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 " CPUIRQSEL11 ,Output Selection for CPU Interrupt 11"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 " CPUIRQSEL12 ,Output Selection for CPU Interrupt 12"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 " CPUIRQSEL13 ,Output Selection for CPU Interrupt 13"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 " CPUIRQSEL14 ,Output Selection for CPU Interrupt 14"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 " CPUIRQSEL15 ,Output Selection for CPU Interrupt 15"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 " CPUIRQSEL16 ,Output Selection for CPU Interrupt 16"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 " CPUIRQSEL17 ,Output Selection for CPU Interrupt 17"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 " CPUIRQSEL18 ,Output Selection for CPU Interrupt 18"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 " CPUIRQSEL19 ,Output Selection for CPU Interrupt 19"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 " CPUIRQSEL20 ,Output Selection for CPU Interrupt 20"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 " CPUIRQSEL21 ,Output Selection for CPU Interrupt 21"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 " CPUIRQSEL22 ,Output Selection for CPU Interrupt 22"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 " CPUIRQSEL23 ,Output Selection for CPU Interrupt 23"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 " CPUIRQSEL24 ,Output Selection for CPU Interrupt 24"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 " CPUIRQSEL25 ,Output Selection for CPU Interrupt 25"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 " CPUIRQSEL26 ,Output Selection for CPU Interrupt 26"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 " CPUIRQSEL27 ,Output Selection for CPU Interrupt 27"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 " CPUIRQSEL28 ,Output Selection for CPU Interrupt 28"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 " CPUIRQSEL29 ,Output Selection for CPU Interrupt 29"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 " CPUIRQSEL30 ,Output Selection for CPU Interrupt 30"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 " CPUIRQSEL31 ,Output Selection for CPU Interrupt 31"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 " CPUIRQSEL32 ,Output Selection for CPU Interrupt 32"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 " CPUIRQSEL33 ,Output Selection for CPU Interrupt 33"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 " RFCSEL0 ,Output Selection for RFC Event 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 " RFCSEL1 ,Output Selection for RFC Event 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 " RFCSEL2 ,Output Selection for RFC Event 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 " RFCSEL3 ,Output Selection for RFC Event 3"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 " RFCSEL4 ,Output Selection for RFC Event 4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 " RFCSEL5 ,Output Selection for RFC Event 5"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 " RFCSEL6 ,Output Selection for RFC Event 6"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 " RFCSEL7 ,Output Selection for RFC Event 7"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 " RFCSEL8 ,Output Selection for RFC Event 8"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 " RFCSEL9 ,Output Selection for RFC Event 9"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 " GPT0ACAPTSEL ,Output Selection for GPT0 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " GPT0BCAPTSEL ,Output Selection for GPT0 1"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 " GPT1ACAPTSEL ,Output Selection for GPT1 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " GPT1BCAPTSEL ,Output Selection for GPT1 1"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x400++0x07
|
|
line.long 0x00 " GPT2ACAPTSEL ,Output Selection for GPT2 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " GPT2BCAPTSEL ,Output Selection for GPT2 1"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
rgroup.long 0x508++0x07
|
|
line.long 0x00 " UDMACH1SSEL ,Output Selection for DMA Channel 1 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH1BSEL ,Output Selection for DMA Channel 1 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x510++0x07
|
|
line.long 0x00 " UDMACH2SSEL ,Output Selection for DMA Channel 2 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH2BSEL ,Output Selection for DMA Channel 2 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x518++0x07
|
|
line.long 0x00 " UDMACH3SSEL ,Output Selection for DMA Channel 3 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH3BSEL ,Output Selection for DMA Channel 3 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x520++0x07
|
|
line.long 0x00 " UDMACH4SSEL ,Output Selection for DMA Channel 4 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH4BSEL ,Output Selection for DMA Channel 4 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x538++0x07
|
|
line.long 0x00 " UDMACH7SSEL ,Output Selection for DMA Channel 7 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH7BSEL ,Output Selection for DMA Channel 7 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x540++0x07
|
|
line.long 0x00 " UDMACH8SSEL ,Output Selection for DMA Channel 8 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH8BSEL ,Output Selection for DMA Channel 8 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
group.long 0x548++0x07
|
|
line.long 0x00 " UDMACH9SSEL ,Output Selection for DMA Channel 9 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " UDMACH9BSEL ,Output Selection for DMA Channel 9 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x550++0x07
|
|
line.long 0x00 " UDMACH10SSEL ,Output Selection for DMA Channel 10 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " UDMACH10BSEL ,Output Selection for DMA Channel 10 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x558++0x07
|
|
line.long 0x00 " UDMACH11SSEL ,Output Selection for DMA Channel 11 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " UDMACH11BSEL ,Output Selection for DMA Channel 11 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x560++0x07
|
|
line.long 0x00 " UDMACH12SSEL ,Output Selection for DMA Channel 12 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " UDMACH12BSEL ,Output Selection for DMA Channel 12 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
rgroup.long (0x568+0x04)++0x03
|
|
line.long 0x00 " UDMACH13BSEL ,Output Selection for DMA Channel 13 REQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
group.long (0x570+0x04)++0x03
|
|
line.long 0x00 " UDMACH14BSEL ,Output Selection for DMA Channel 14 REQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
rgroup.long (0x578+0x04)++0x03
|
|
line.long 0x00 " UDMACH15BSEL ,Output Selection for DMA Channel 15 REQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x580++0x07
|
|
line.long 0x00 " UDMACH16SSEL ,Output Selection for DMA Channel 16 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH16BSEL ,Output Selection for DMA Channel 16 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x588++0x07
|
|
line.long 0x00 " UDMACH17SSEL ,Output Selection for DMA Channel 17 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH17BSEL ,Output Selection for DMA Channel 17 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x5A8++0x07
|
|
line.long 0x00 " UDMACH21SSEL ,Output Selection for DMA Channel 21 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH21BSEL ,Output Selection for DMA Channel 21 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x5B0++0x07
|
|
line.long 0x00 " UDMACH22SSEL ,Output Selection for DMA Channel 22 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH22BSEL ,Output Selection for DMA Channel 22 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x5B8++0x07
|
|
line.long 0x00 " UDMACH23SSEL ,Output Selection for DMA Channel 23 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH23BSEL ,Output Selection for DMA Channel 23 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
rgroup.long 0x5C0++0x07
|
|
line.long 0x00 " UDMACH24SSEL ,Output Selection for DMA Channel 24 SREQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
line.long 0x04 " UDMACH24BSEL ,Output Selection for DMA Channel 24 REQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read only selection value"
|
|
group.long 0x600++0x07
|
|
line.long 0x00 " GPT3ACAPTSEL ,Output Selection for GPT3 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
line.long 0x04 " GPT3BCAPTSEL ,Output Selection for GPT3 1"
|
|
hexmask.long.byte 0x04 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 " AUXSEL0 ,Output Selection for AUX Subscriber 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 " CM3NMISEL0 ,Output Selection for NMI Subscriber 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read only selection value"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 " I2SSTMPSEL0 ,Output Selection for I2S Subscriber 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 " FRZSEL0 ,Output Selection for FRZ Subscriber 0"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EV ,Read/Write selection value"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 " SWEV ,Set or Clear Software Events"
|
|
bitfld.long 0x00 24. " SWEV3 ,Software 3 event trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 16. " SWEV3 ,Software 2 event trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SWEV3 ,Software 1 event trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " SWEV3 ,Software 0 event trigger" "Not triggered,Triggered"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PRCM (Power, Reset and Clock Management)"
|
|
base ad:0x40082000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "INFRCLKDIVR,Infrastructure Clock Division Factor For Run Mode"
|
|
bitfld.long 0x00 0.--1. " RATIO ,Division rate" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x04 "INFRCLKDIVS,Infrastructure Clock Division Factor For Sleep Mode"
|
|
bitfld.long 0x04 0.--1. " RATIO ,Division rate" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x08 "INFRCLKDIVDS,Infrastructure Clock Division Factor For DeepSleep Mode"
|
|
bitfld.long 0x08 0.--1. " RATIO ,Division rate" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x0C "VDCTL,MCU Voltage Domain Control"
|
|
bitfld.long 0x0C 2. " MCU_VD ,Request WUC to power down the MCU voltage domain" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " ULDO ,Request WUC to switch to uLDO" "Not requested,Requested"
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CLKLOADCTL,Clock Load Control"
|
|
rbitfld.long 0x00 1. " LOAD_DONE ,Status of LOAD" "Not done,Done"
|
|
bitfld.long 0x00 0. " LOAD ,Load settings to CLKCTR" "No action,Load"
|
|
line.long 0x04 "RFCCLKG,RFC Clock Gate"
|
|
bitfld.long 0x04 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "VIMSCLKG,VIMS Clock Gate"
|
|
bitfld.long 0x08 0.--1. " CLK_EN ,Clock Enable" "Disabled,Disabled when SYSBUS clk disabled,,Enabled"
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "SECDMACLKGR,TRNG / CRYPTO / UDMA Clock Gate For Run Mode"
|
|
bitfld.long 0x00 8. " DMA_CLK_EN ,DMA Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TRNG_CLK_EN ,TRNG Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CRYPTO_CLK_EN ,CRYPTO Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SECDMACLKGS,TRNG / CRYPTO / UDMA Clock Gate For Sleep Mode"
|
|
bitfld.long 0x04 8. " DMA_CLK_EN ,DMA Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TRNG_CLK_EN ,TRNG Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CRYPTO_CLK_EN ,CRYPTO Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "SECDMACLKGDS,TRNG / CRYPTO / UDMA Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 8. " DMA_CLK_EN ,DMA Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TRNG_CLK_EN ,TRNG Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CRYPTO_CLK_EN ,CRYPTO Clock Enable" "Disabled,Enabled"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "GPIOCLKGR,GPIO Clock Gate For Run Mode"
|
|
bitfld.long 0x00 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPIOCLKGS,GPIO Clock Gate For Sleep Mode"
|
|
bitfld.long 0x04 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIOCLKGDS,GPIO Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "GPTCLKGR,GPT Clock Gate For Run Mode"
|
|
bitfld.long 0x00 3. " CLK_EN[3] ,GPT3 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CLK_EN[2] ,GPT2 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLK_EN[1] ,GPT1 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CLK_EN[0] ,GPT0 Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPTCLKGS,GPT Clock Gate For Sleep Mode"
|
|
bitfld.long 0x04 3. " CLK_EN[3] ,GPT3 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLK_EN[2] ,GPT2 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLK_EN[1] ,GPT1 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLK_EN[0] ,GPT0 Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPTCLKGDS,GPT Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 3. " CLK_EN[3] ,GPT3 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CLK_EN[2] ,GPT2 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CLK_EN[1] ,GPT1 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CLK_EN[0] ,GPT0 Clock Enable" "Disabled,Enabled"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "I2CCLKGR,I2C Clock Gate For Run Mode"
|
|
bitfld.long 0x00 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2CCLKGS,I2C Clock Gate For Sleep Mode"
|
|
bitfld.long 0x04 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "I2CCLKGDS,I2C Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
group.long 0x6C++0x0B
|
|
line.long 0x00 "UARTCLKGR,UART Clock Gate For Run Mode"
|
|
bitfld.long 0x00 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UARTCLKGS,UART Clock Gate For Sleep Modee"
|
|
bitfld.long 0x04 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "UARTCLKGDS,UART Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
group.long 0x78++0x0B
|
|
line.long 0x00 "SSICLKGR,SSI Clock Gate For Run Mode"
|
|
bitfld.long 0x00 0.--1. " CLK_EN ,Clock Enable" "Disabled,Enabled for SSI0,Enabled for SSI1,"
|
|
line.long 0x04 "SSICLKGS,SSI Clock Gate For Sleep Mode"
|
|
bitfld.long 0x04 0.--1. " CLK_EN ,Clock Enable" "Disabled,Enabled for SSI0,Enabled for SSI1,"
|
|
line.long 0x08 "SSICLKGDS,SSI Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 0.--1. " CLK_EN ,Clock Enable" "Disabled,Enabled for SSI0,Enabled for SSI1,"
|
|
group.long 0x84++0x0B
|
|
line.long 0x00 "I2SCLKGR,I2S Clock Gate For Run Mode"
|
|
bitfld.long 0x00 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2SCLKGR,I2S Clock Gate For Sleep Mode"
|
|
bitfld.long 0x04 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x08 "I2SCLKGR,I2S Clock Gate For Deep Sleep Mode"
|
|
bitfld.long 0x08 0. " CLK_EN ,Clock Enable" "Disabled,Enabled"
|
|
; Internal. Only to be used through TI provided API
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CPUCLKDIV ,CPU Clock Division Factor"
|
|
bitfld.long 0x00 0.--1. " RATIO ,Division rate (Internal, to be used through TI provided API)" "0,1,2,3"
|
|
textline " "
|
|
group.long 0xC8++0x17
|
|
line.long 0x00 "I2SBCLKSEL,I2S Clock Control"
|
|
bitfld.long 0x00 0. " SRC ,BCLK source selector" "External,Internal"
|
|
line.long 0x04 "GPTCLKDIV ,CPU Clock Division Factor"
|
|
bitfld.long 0x04 0.--3. " RATIO ,Division rate" "Divide by 1,Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256,?..."
|
|
line.long 0x08 "I2SCLKCTL,I2S Clock Control"
|
|
bitfld.long 0x08 3. " SMPL_ON_POSEDGE ,Data and WCLK Sampling and Clocking (Sampled on P/N Edge / Clocked out on P/N Edge)" "Negative/Positive,Positive/Negative"
|
|
bitfld.long 0x08 1.--2. " WCLK_PHASE ,WCLK Phase" "Single phase,Dual phase,User Defined,"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EN ,Enable the generation of MCLK, BCLK and WCLK" "Disabled,Enabled"
|
|
line.long 0x0C "I2SMCLKDIV,MCLK Division Ratio"
|
|
hexmask.long.word 0x0C 0.--9. 1. " MDIV ,An unsigned factor of the division ratio used to generate MCLK"
|
|
line.long 0x10 "I2SBCLKDIV,BCLK Division Ratio"
|
|
hexmask.long.word 0x10 0.--9. 1. " BDIV ,An unsigned factor of the division ratio used to generate I2S BCLK"
|
|
line.long 0x14 "I2SWCLKDIV,WCLK Division Ratio"
|
|
hexmask.long.word 0x14 0.--15. 1. " WDIV ,An unsigned factor of the division ratio used to generate WCLK"
|
|
textline " "
|
|
; Internal. Only to be used through TI provided API
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "SWRESET,SW Initiated Resets"
|
|
bitfld.long 0x00 2. " MCU ,MCU (Internal, to be used through TI provided API)" "0,1"
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "WARMRESET,WARM Reset Control And Status"
|
|
in
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "PDCTL0,Power Domain Control 0"
|
|
bitfld.long 0x00 2. " PERIPH_ON ,PERIPH Power domain" "OFF,ON"
|
|
bitfld.long 0x00 1. " SERIAL_ON ,SERIAL Power domain" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFC_ON ,RFC power domain" "OFF,ON"
|
|
line.long 0x04 "PDCTL0RFC,RFC Power Domain Control"
|
|
bitfld.long 0x04 0. " ON ,Alias for PDCTL0.RFC_ON" "OFF,ON"
|
|
line.long 0x08 "PDCTL0SERIAL,SERIAL Power Domain Control"
|
|
bitfld.long 0x08 0. " ON ,Alias for PDCTL0.SERIAL_ON" "OFF,ON"
|
|
line.long 0x0C "PDCTL0PERIPH,PERIPH Power Domain Control"
|
|
bitfld.long 0x0C 0. " ON ,Alias for PDCTL0.PERIPH_ON" "OFF,ON"
|
|
rgroup.long 0x140++0x0F
|
|
line.long 0x00 "PDSTAT0,Power Domain Status 0"
|
|
bitfld.long 0x00 2. " PERIPH_ON ,PERIPH Power domain" "May be DOWN,Guaranteed UP"
|
|
bitfld.long 0x00 1. " SERIAL_ON ,SERIAL Power domain" "May be DOWN,Guaranteed UP"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFC_ON ,RFC power domain" "May be DOWN,Guaranteed UP"
|
|
line.long 0x04 "PDSTAT0RFC,RFC Power Domain Status"
|
|
bitfld.long 0x04 0. " ON ,Alias for PDSTAT0.RFC_ON" "May be DOWN,Guaranteed UP"
|
|
line.long 0x08 "PDSTAT0SERIAL,SERIAL Power Domain Status"
|
|
bitfld.long 0x08 0. " ON ,Alias for PDSTAT0.SERIAL_ON" "May be DOWN,Guaranteed UP"
|
|
line.long 0x0C "PDSTAT0PERIPH,Power Domain Status"
|
|
bitfld.long 0x0C 0. " ON ,Alias for PDSTAT0.PERIPH_ON" "May be DOWN,Guaranteed UP"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PDCTL1,Power Domain Control 1"
|
|
bitfld.long 0x00 3. " VIMS_MODE ,VIMS Power domain mode (Powered Only when CPU is ON / Whenever the BUS is ON)" "CPU,BUS"
|
|
bitfld.long 0x00 2. " RFC_ON ,RFC Power domain" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CPU_ON ,CPU power domain (Power OFF when sys indicates Idle state / Initiate Power ON)" "OFF,ON"
|
|
group.long 0x184++0x0B
|
|
line.long 0x00 "PDCTL1CPU,CPU Power Domain Control"
|
|
bitfld.long 0x00 0. " ON ,Alias for PDCTL1.CPU_ON" "OFF,ON"
|
|
line.long 0x04 "PDCTL1RFC,RFC Power Domain Control"
|
|
bitfld.long 0x04 0. " ON ,Alias for PDCTL1.RFC_ON" "OFF,ON"
|
|
line.long 0x08 "PDCTL1VIMS,VIMS Power Domain Control"
|
|
bitfld.long 0x08 0. " ON ,Alias for PDCTL1.VIMS_MODE" "CPU,BUS"
|
|
rgroup.long 0x194++0x13
|
|
line.long 0x00 "PDSTAT1,Power Domain Status 1"
|
|
bitfld.long 0x00 4. " BUS_ON ,BUS domain accessibility" "Not accessible,Accessible"
|
|
bitfld.long 0x00 3. " VIMS_MODE ,VIMS domain accessibility" "Not accessible,Accessible"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFC_ON ,RFC domain accessibility" "Not accessible,Accessible"
|
|
bitfld.long 0x00 1. " CPU_ON ,CPU and BUS domain accessibility" "Not accessible,Accessible"
|
|
line.long 0x04 "PDSTAT1BUS,BUS Power Domain Status"
|
|
bitfld.long 0x04 0. " ON ,Alias for PDSTAT1.BUS_ON" "Not accessible,Accessible"
|
|
line.long 0x08 "PDSTAT1RFC,RFC Power Domain Status"
|
|
bitfld.long 0x08 0. " ON ,Alias for PDSTAT1.RFC_ON" "Not accessible,Accessible"
|
|
line.long 0x0C "PDSTAT1CPU,CPU Power Domain Status"
|
|
bitfld.long 0x0C 0. " ON ,Alias for PDSTAT1.CPU_ON" "Not accessible,Accessible"
|
|
line.long 0x10 "PDSTAT1VIMS,VIMS Power Domain Status"
|
|
bitfld.long 0x10 0. " ON ,Alias for PDSTAT1.VIMS_MODE" "Not accessible,Accessible"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "PDSTAT1,Selected RFC Mode"
|
|
bitfld.long 0x00 0.--2. " CURR ,RFC Mode selection" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMRETEN,Selected RFC Mode"
|
|
bitfld.long 0x00 2. " RFC ,Retention for RFC SRAM enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " VIMS ,Memory retention (TRAM/CRAM)" "Disabled,Disabled/enabled,,Enabled"
|
|
width 0x0B
|
|
tree "AON_SYSCTL (Always On System Control)"
|
|
base ad:0x40090000
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PWRCTL,Power Management"
|
|
bitfld.long 0x00 2. " DCDC_ACTIVE ,Regulator Usage for VDDR in active mode" "GLDO,DCDC"
|
|
rbitfld.long 0x00 1. " EXT_REG_MODE ,Status of source for VDDRsupply" "DCDC/GLDO,External"
|
|
bitfld.long 0x00 0. " DCDC_EN ,Regulator Usage during recharge of VDDR" "GLDO,DCDC"
|
|
line.long 0x04 "RESETCTL,Reset Management"
|
|
bitfld.long 0x04 31. " SYSRESET ,Cold system reset" "No effect,System reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " BOOT_DET_1_CLR ,BOOT_DET_1_CLR (Internal, to be used through TI provided API)" "0,1"
|
|
bitfld.long 0x04 24. " BOOT_DET_0_CLR ,BOOT_DET_0_CLR (Internal, to be used through TI provided API)" "0,1"
|
|
bitfld.long 0x04 17. " BOOT_DET_1_SET ,BOOT_DET_1_SET (Internal, to be used through TI provided API)" "0,1"
|
|
bitfld.long 0x04 16. " BOOT_DET_0_SET ,BOOT_DET_0_SET (Internal, to be used through TI provided API)" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x04 15. " WU_FROM_SD ,Wakeup occured from SHUTDOWN" "Not occurred,Occurred"
|
|
rbitfld.long 0x04 14. " GPIO_WU_FROM_SD ,Wakeup occured from SHUTDOWN from an IO event" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " BOOT_DET_1 ,BOOT_DET_1 (Internal, to be used through TI provided API)" "0,1"
|
|
bitfld.long 0x04 12. " BOOT_DET_0 ,BOOT_DET_0 (Internal, to be used through TI provided API)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " VDDS_LOSS_EN_OVR ,Override of VDDS_LOSS_EN" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VDDR_LOSS_EN_OVR ,Override of VDDR_LOSS_EN" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " VDD_LOSS_EN_OVR ,Override of VDD_LOSS_EN " "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " VDDS_LOSS_EN ,Controls reset generation in case VDDS is lost" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VDDR_LOSS_EN ,Controls reset generation in case VDDS is lost" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " VDD_LOSS_EN ,Controls reset generation in case VDD is lost" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CLK_LOSS_EN ,Controls reset generation in case CLK is lost" "Disabled,Enabled"
|
|
rbitfld.long 0x04 1.--3. " RESET_SRC ,Source of the last system reset" "Power on reset,Reset pin,VDDS brown out,VDD brown out,VDDR brown out,Clock loss,SYSRESET,PRCM warm reset"
|
|
line.long 0x08 "SLEEPCTL,Sleep Mode"
|
|
bitfld.long 0x08 0. " IO_PAD_SLEEP_DIS ,Pad sleep mode disable" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AON_WUC (Always On Wake up Controller)"
|
|
base ad:0x40091000
|
|
width 14.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "MCUCLK,MCU Clock Management"
|
|
bitfld.long 0x00 2. " RCOSC_HF_CAL_DONE ,RCOSC_HF calibration status" "Not calibrated,Calibrated"
|
|
bitfld.long 0x00 0.--1. " PWR_DWN_SRC ,Clock source while MCU is requesting powerdown" "No clock,SCLK_LF,?..."
|
|
line.long 0x04 "AUXCLK,AUX Clock Management"
|
|
bitfld.long 0x04 11.--12. " PWR_DWN_SRC ,Clock source selection during powerdown" "No clock,SCLK_LF,?..."
|
|
bitfld.long 0x04 8.--10. " SCLK_HF_DIV ,AUX clock divider for SCLK_HF NB selection" "Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256"
|
|
bitfld.long 0x04 0.--2. " SRC ,Clock source for AUX: NB selection" ",SCLK_HF,,,SCLK_LF,?..."
|
|
line.long 0x08 "MCUCFG,MCU Configuration"
|
|
bitfld.long 0x08 17. " VIRT_OFF ,VIRT_OFF (Internal, to be used through TI provided API)" "0,1"
|
|
bitfld.long 0x08 16. " FIXED_WU_EN ,Fixed Wake-up Enable (Internal, to be used through TI provided API)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " SRAM_RET_EN ,MCU SRAM retention during MCU power off" "Disabled,BANK0,,BANK[0-1],,,,BANK[0-2],,,,,,,,All Banks"
|
|
line.long 0x0C "AUXCFG,AUX Configuration"
|
|
bitfld.long 0x0C 0. " RAM_RET_EN ,AUX_RAM:BANK0 retention enable" "Disabled,Enabled"
|
|
line.long 0x10 "AUXCTL,AUX Control"
|
|
bitfld.long 0x10 31. " RESET_REQ ,Reset request for AUX" "No reset,Reset"
|
|
bitfld.long 0x10 2. " SCE_RUN_EN ,AUX_SCE execution enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " SWEV ,Software event" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 0. " AUX_FORCE_ON ,Force AUX domain into active mode" "Not forced,Forced"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PWRSTAT,Power Status"
|
|
bitfld.long 0x00 9. " AUX_PWR_DWN ,AUX powerdown" "Active mode,Powerdown"
|
|
bitfld.long 0x00 6. " JTAG_PD_ON ,JTAG power state" "Off,On"
|
|
bitfld.long 0x00 5. " AUX_PD_ON ,AUX power state (readiness to work)" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MCU_PD_ON ,MCU power state (readiness to work)" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " AUX_BUS_CONNECTED ,AUX Bus connection" "Not connected,Connected"
|
|
bitfld.long 0x00 1. " AUX_RESET_DONE ,Aux current reset state" "In progress,Done"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SHUTDOWN,Shutdown Control"
|
|
bitfld.long 0x00 0. " EN ,Shutdown request" "Not registered,Registered"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CTL0,Control 0"
|
|
bitfld.long 0x00 8. " PWR_DWN_DIS ,Power down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " AUX_SRAM_ERASE ,AUX SRAM Erase (Internal, to be used through TI provided API)" "Not erased,Erased"
|
|
bitfld.long 0x00 2. " MCU_SRAM_ERASE ,MCU SRAM Erase (Internal, to be used through TI provided API)" "Not erased,Erased"
|
|
line.long 0x04 "CTL1,Control 1"
|
|
eventfld.long 0x04 1. " MCU_RESET_SRC ,Source of last MCU Voltage Domain warm reset request" "MCU SW,JTAG"
|
|
eventfld.long 0x04 0. " MCU_WARM_RESET ,Type of last MCU Voltage Domain reset" "Not warm,Warm"
|
|
textline " "
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RECHARGECFG,Recharge Controller Configuration"
|
|
bitfld.long 0x00 31. " ADAPTIVE_EN ,Enable adaptive recharge" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " C2 ,Gain factor for adaptive recharge algorithm [period_new = period * (1+/-(2^-C1+2^-C2))]" ",,2,3,4,5,6,7,8,9,10,?..."
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|
bitfld.long 0x00 16.--19. " C1 ,Gain factor for adaptive recharge algorithm [period_new = period * (1+/-(2^-C1+2^-C2))]" ",1,2,3,4,5,6,7,8,9,10,?..."
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|
bitfld.long 0x00 11.--15. " MAX_PER_M ,Maximum period that the recharge algorithm can take (Mantisa)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MAX_PER_E ,Maximum period that the recharge algorithm can take (Exponent)" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 3.--7. " PER_M ,Number of 32 KHz clocks between activation of recharge controller (Mantisa)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " PER_E ,Number of 32 KHz clocks between activation of recharge controller (Exponent)" "0,1,2,3,4,5,6,7"
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|
line.long 0x04 "RECHARGESTAT,Recharge Controller Status"
|
|
rbitfld.long 0x04 19. " VDDR_SMPLS[3] ,The last 4 VDDR samples - sample 3" "0,1"
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|
rbitfld.long 0x04 18. " VDDR_SMPLS[2] ,The last 4 VDDR samples - sample 2" "0,1"
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|
rbitfld.long 0x04 17. " VDDR_SMPLS[1] ,The last 4 VDDR samples - sample 1" "0,1"
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|
rbitfld.long 0x04 16. " VDDR_SMPLS[0] ,The last 4 VDDR samples - sample 0" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " MAX_USED_PER ,The maximum value of recharge period seen with VDDR>threshold"
|
|
line.long 0x08 "OSCCFG,Oscillator Configuration"
|
|
bitfld.long 0x08 3.--7. " PER_M ,Number of 32 KHz clocks between oscillator amplitude calibrations (Mantisa)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--2. " PER_E ,Number of 32 KHz clocks between oscillator amplitude calibrations (Exponent)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "JTAGCFG,JTAG Configuration"
|
|
bitfld.long 0x00 8. " JTAG_PD_FORCE_ON ,JTAG Power Domain forced ON" "Not forced,Forced"
|
|
line.long 0x04 "JTAGUSERCODE,32-bit JTAG USERCODE register feeding main JTAG TAP NB"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DDI0_OSC (Digital/Digital Interface, Oscillator control)"
|
|
base ad:0x400CA000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL0,Control 0"
|
|
bitfld.long 0x00 31. " XTAL_IS_24M ,XTAL IS 24M (Internal, to be used through TI API)" "48M,24M"
|
|
bitfld.long 0x00 29. " BYPASS_XOSC_LF_CLK_QUAL ,BYPASS XOSC LF CLK QUAL (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x00 28. " BYPASS_RCOSC_LF_CLK_QUAL ,BYPASS RCOSC LF CLK QUAL (Internal, to be used through TI API)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " DOUBLER_START_DURATION ,Doubler Start Duration (Internal, to be used through TI API)" "0,1,2,3"
|
|
bitfld.long 0x00 25. " DOUBLER_RESET_DURATION ,Doubler Reset Duration (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x00 22. " FORCE_KICKSTART_EN ,Force Kickstart Enable (Internal, to be used through TI API)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALLOW_SCLK_HF_SWITCHING ,Swtiching of sclk_hf source allowance" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " RCOSC_LF_TRIMMED ,RCOSC LF TRIMMED (Internal, to be used through TI API)" "No,Yes"
|
|
bitfld.long 0x00 11. " XOSC_HF_POWER_MODE ,XOSC_HF_POWER_MODE (Internal, to be used through TI API)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XOSC_LF_DIG_BYPASS ,XOSC_LF Bypass (use the digital input clock from AON for thexosc_lf clock)" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 9. " CLK_LOSS_EN ,Clock loss circuit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--8. " ACLK_TDC_SRC_SE ,Source select for aclk_tdc" "RCOSC_HF(48MHz),RCOSC_HF(24MHz),XOSC_HF(24MHz),?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " ACLK_REF_SRC_SEL ,Source select for aclk_ref" "LF from RCOSC_HF (31.25kHz),LF from XOSC_HF (31.25kHz),RCOSC_LF (32kHz),XOSC_LF (32.768kHz)"
|
|
bitfld.long 0x00 2.--3. " SCLK_LF_SRC_SEL ,Source select for sclk_lf" "LF from HF RCOSC,LF from HF XOSC,LF RCOSC,LF XOSC"
|
|
bitfld.long 0x00 1. " SCLK_MF_SRC_SEL ,Source select for sclk_mf" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCLK_HF_SRC_SEL ,Source select for sclk_hf" "Internal,MF from HF XOSC"
|
|
textline " "
|
|
width 15.
|
|
group.long 0x04++0x1B
|
|
line.long 0x00 "CTL1,Control 1"
|
|
bitfld.long 0x00 18.--22. " RCOSCHFCTRIMFRACT ,RCOSCHFCTRIMFRACT (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. " RCOSCHFCTRIMFRACT_EN ,RCOSCHFCTRIMFRACT_EN (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x00 0.--1. " XOSC_HF_FAST_START ,XOSC_HF_FAST_START (Internal, to be used through TI API)" "0,1,2,3"
|
|
line.long 0x04 "RADCEXTCFG,RADC External Configuration"
|
|
hexmask.long.word 0x04 22.--31. 1. " HPM_IBIAS_WAIT_CNT ,HPM_IBIAS_WAIT_CNT (Internal, to be used through TI API)"
|
|
bitfld.long 0x04 16.--21. " LPM_IBIAS_WAIT_CNT ,LPM_IBIAS_WAIT_CNT (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 12.--15. " IDAC_STEP ,IDAC_STEP (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 6.--11. " RADC_DAC_TH ,RADC_DAC_TH (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RADC_MODE_IS_SAR ,RADC_MODE_IS_SAR (Internal, to be used through TI API)" "0,1"
|
|
line.long 0x08 "AMPCOMPCTL,Amplitude Compensation Control"
|
|
bitfld.long 0x08 30. " AMPCOMP_REQ_MODE ,AMPCOMP_REQ_MODE (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x08 28.--29. " AMPCOMP_FSM_UPDATE_RATE ,AMPCOMP_FSM_UPDATE_RATE (Internal, to be used through TI API)" "2MHZ,1MHZ,500KHZ,250KHZ"
|
|
bitfld.long 0x08 27. " AMPCOMP_SW_CTRL ,AMPCOMP_SW_CTRL (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x08 26. " AMPCOMP_SW_EN ,AMPCOMP_SW_EN (Internal, to be used through TI API)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 20.--23. " IBIAS_OFFSET ,IBIAS_OFFSET (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " IBIAS_INIT ,IBIAS_INIT (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 8.--15. 1. " LPM_IBIAS_WAIT_CNT_FINAL ,LPM_IBIAS_WAIT_CNT_FINAL (Internal, to be used through TI API)"
|
|
bitfld.long 0x08 4.--7. " CAP_STEP ,CAP_STEP (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " IBIASCAP_HPTOLP_OL_CNT ,IBIASCAP_HPTOLP_OL_CNT (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "AMPCOMPTH1,Amplitude Compensation Threshold 1"
|
|
bitfld.long 0x0C 18.--23. " HPMRAMP3_LTH ,HPMRAMP3_LTH (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 10.--15. " HPMRAMP3_HTH ,HPMRAMP3_HTH (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 6.--9. " IBIASCAP_LPTOHP_OL_CNT ,IBIASCAP_LPTOHP_OL_CNT (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--5. " HPMRAMP1_TH ,HPMRAMP1_TH (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "AMPCOMPTH2,Amplitude Compensation Threshold 2"
|
|
bitfld.long 0x10 26.--31. " LPMUPDATE_LTH ,LPMUPDATE_LTH (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 18.--23. " LPMUPDATE_HTH ,LPMUPDATE_HTH (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 10.--15. " ADC_COMP_AMPTH_LPM ,ADC_COMP_AMPTH_LPM (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 2.--7. " ADC_COMP_AMPTH_HPM ,ADC_COMP_AMPTH_HPM (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "ANABYPASSVAL1,Analog Bypass Values 1"
|
|
bitfld.long 0x14 16.--19. " XOSC_HF_ROW_Q12 ,XOSC_HF_ROW_Q12 (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x14 0.--15. 1. " XOSC_HF_COLUMN_Q12 ,XOSC_HF_COLUMN_Q12 (Internal, to be used through TI API)"
|
|
line.long 0x18 "ANABYPASSVAL2,Analog Bypass Values 2"
|
|
hexmask.long.word 0x18 0.--13. 1. " XOSC_HF_IBIASTHERM ,XOSC_HF_IBIASTHERM (Internal, to be used through TI API)"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "ATESTCTL,Analog Test Control"
|
|
bitfld.long 0x00 29. " CLK_LF_AUX_EN ,Enable 32 kHz clock to AUX_COMPB." "Disabled,Enabled"
|
|
line.long 0x04 "ADCDOUBLERNANOAMPCTL,ADC Doubler Nanoamp Control"
|
|
bitfld.long 0x04 24. " NANOAMP_BIAS_ENABLE ,NANOAMP_BIAS_ENABLE (Internal, to be used through TI API)" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ADC_SH_MODE_EN ,ADC_SH Mode Enable (Internal, to be used through TI API)" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ADC_SH_VBUF_EN ,ADC_SH_VBUF Enable (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x04 0.--1. " ADC_IREF_CTRL ,ADC_IREF Control (Internal, to be used through TI API)" "0,1,2,3"
|
|
line.long 0x08 "XOSCHFCTL,XOSCHF Control"
|
|
bitfld.long 0x08 8.--9. " PEAK_DET_ITRIM ,PEAK_DET_ITRIM (Internal, to be used through TI API)" "0,1,2,3"
|
|
bitfld.long 0x08 6. " BYPASS ,BYPASS (Internal, to be used through TI API)" "0,1"
|
|
bitfld.long 0x08 2.--4. " HP_BUF_ITRIM ,HP_BUF_ITRIM (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--1. " LP_BUF_ITRIM ,LP_BUF_ITRIM (Internal, to be used through TI API)" "0,1,2,3"
|
|
line.long 0x0C "LFOSCCTL,Low Frequency Oscillator Control"
|
|
bitfld.long 0x0C 22.--23. " XOSCLF_REGULATOR_TRIM ,XOSCLF_REGULATOR_TRIM (Internal, to be used through TI API)" "0,1,2,3"
|
|
bitfld.long 0x0C 18.--21. " XOSCLF_CMIRRWR_RATIO ,XOSCLF_CMIRRWR_RATIO (Internal, to be used through TI API)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--9. " RCOSCLF_RTUNE_TRIM ,RCOSCLF_RTUNE_TRIM (Internal, to be used through TI API)" "7P5MEG,7P0MEG,6P5MEG,6P0MEG"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RCOSCLF_CTUNE_TRIM ,RCOSCLF_CTUNE_TRIM (Internal, to be used through TI API)"
|
|
line.long 0x10 "RCOSCHFCTL,RCOSCHF Control"
|
|
hexmask.long.byte 0x10 8.--15. 1. " RCOSCHF_CTRIM ,RCOSCHF_CTRIM (Internal, to be used through TI API)"
|
|
textline ""
|
|
width 7.
|
|
rgroup.long 0x34++0x0B
|
|
line.long 0x00 "STAT0,Status 0"
|
|
bitfld.long 0x00 29.--30. " SCLK_LF_SRC ,SCLK_LF Source" "LF from HF RCOSC,LF from HF XOSC,LF RCOSC,LF XOSC"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SCLK_HF_SRC ,SCLK_HF source" "HF RCOSC,HF XOSC"
|
|
bitfld.long 0x00 22. " RCOSC_HF_EN ,RCOSC_HF_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RCOSC_LF_EN ,RCOSC_LF_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " XOSC_LF_EN ,XOSC_LF_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLK_DCDC_RDY ,CLK_DCDC Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " CLK_DCDC_RDY_ACK ,CLK_DCDC_RDY_ACK" "No,Yes"
|
|
bitfld.long 0x00 17. " SCLK_HF_LOSS ,SCLK_HF Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 16. " SCLK_LF_LOSS ,SCLK_LF Lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x00 15. " XOSC_HF_EN ,XOSC_HF Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " XB_48M_CLK_EN ,48MHz clock from the DOUBLER Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " XOSC_HF_LP_BUF_EN ,XOSC High Frequency LP_BUF Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XOSC_HF_HP_BUF_EN ,XOSC High Frequency HP_BUF Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADC_THMET ,ADC_THMET" "0,1"
|
|
bitfld.long 0x00 7. " ADC_DATA_READY ,ADC Data Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 1.--6. " ADC_DATA ,ADC Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0. " PENDINGSCLKHFSWITCHING ,SCLK_HF is ready to be switched" "Not ready,Ready"
|
|
line.long 0x04 "STAT1,Status 1"
|
|
bitfld.long 0x04 28.--31. " RAMPSTATE ,AMPCOMP FSM State" "RESET,INITIALIZATION,HPM_RAMP1,HPM_RAMP2,HPM_RAMP3,HPM_UPDATE,IDAC_INCREMENT,IBIAS_CAP_UPDATE,IBIAS_DECREMENT_WITH_MEASURE,LPM_UPDATE,IBIAS_INCREMENT,IDAC_DECREMENT_WITH_MEASURE,DUMMY_TO_INIT_1,FAST_START,FAST_START_SETTLE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--27. " HMP_UPDATE_AMP ,OSC amplitude during HPM_UPDATE state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " LPM_UPDATE_AMP ,OSC amplitude during LPM_UPDATE state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15. " FORCE_RCOSC_HF ,FORCE HF RCOSC" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " SCLK_HF_EN ,SCLK_HF enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SCLK_MF_EN ,SCLK_MF enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " ACLK_ADC_EN ,ACLK_ADC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ACLK_TDC_EN ,ACLK_TDC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ACLK_REF_EN ,ACLK_REF enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLK_CHP_EN ,CLK_CHP enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLK_DCDC_EN ,CLK_DCDC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SCLK_HF_GOOD ,SCLK_HF_GOOD" "Not good,Good"
|
|
bitfld.long 0x04 6. " SCLK_MF_GOOD ,SCLK_MF_GOOD" "Not good,Good"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCLK_LF_GOOD ,SCLK_LF_GOOD" "Not good,Good"
|
|
bitfld.long 0x04 4. " ACLK_ADC_GOOD ,ACLK_ADC_GOOD" "Not good,Good"
|
|
bitfld.long 0x04 3. " ACLK_TDC_GOOD ,ACLK_TDC_GOOD" "Not good,Good"
|
|
bitfld.long 0x04 2. " ACLK_REF_GOOD ,ACLK_REF_GOOD" "Not good,Good"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLK_CHP_GOOD ,CLK_CHP_GOOD" "Not good,Good"
|
|
bitfld.long 0x04 0. " CLK_DCDC_GOOD ,CLK_DCDC_GOOD" "Not good,Good"
|
|
line.long 0x08 "STAT2,Status 2"
|
|
bitfld.long 0x08 26.--31. " ADC_DCBIAS ,DC Bias read by RADC during SAR mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 25. " HPM_RAMP1_THMET ,Threshhold is met for hpm_ramp1" "Not met,Met"
|
|
bitfld.long 0x08 24. " HPM_RAMP2_THMET ,Threshhold is met for hpm_ramp2" "Not met,Met"
|
|
bitfld.long 0x08 23. " HPM_RAMP3_THMET ,Threshhold is met for hpm_ramp3" "Not met,Met"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " RAMPSTATE ,AMPCOMP FSM State" "RESET,INITIALIZATION,HPM_RAMP1,HPM_RAMP2,HPM_RAMP3,HPM_UPDATE,IDAC_INCREMENT,IBIAS_CAP_UPDATE,IBIAS_DECREMENT_WITH_MEASURE,LPM_UPDATE,IBIAS_INCREMENT,IDAC_DECREMENT_WITH_MEASURE,DUMMY_TO_INIT_1,FAST_START,FAST_START_SETTLE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 3. " AMPCOMP_REQ ,AMPCOMP_REQ" "0,1"
|
|
bitfld.long 0x08 2. " XOSC_HF_AMPGOOD ,Amplitude of XOSC_HF is within the required threshold" "No,Yes"
|
|
bitfld.long 0x08 1. " XOSC_HF_FREQGOOD ,Frequency of XOSC_HF is good to use for the digital clocks" "Not good,Good"
|
|
bitfld.long 0x08 0. " XOSC_HF_RF_FREQGOOD ,XOSC_HF is good for radio operations" "Not good,Good"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "VIMS"
|
|
tree "VIMS"
|
|
base ad:0x40034000
|
|
width 6.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "STAT,Status"
|
|
bitfld.long 0x00 5. " IDCODE_LB_DIS ,Icode/Dcode flash line buffer disabled" "No,Yes"
|
|
bitfld.long 0x00 4. " SYSBUS_LB_DIS ,Sysbus flash line buffer disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " MODE_CHANGING ,VIMS mode change status" "Not changing,Changing"
|
|
bitfld.long 0x00 2. " INV ,Invalidation of the cache memory" "No invalidation,Invalidation"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE ,Current VIMS mode" "GPRAM,CACHE,Split cache,Off"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. " STATS_CLR ,Statistic counters clear" "No effect,Cleared"
|
|
bitfld.long 0x00 30. " STATS_EN ,Statistic counters enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DYN_CG_EN ,The in-built clock gate functionality enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IDCODE_LB_DIS ,Icode/Dcode flash line buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYSBUS_LB_DIS ,Sysbus flash line buffer disable" "No,Yes"
|
|
bitfld.long 0x00 3. " ARB_CFG ,Code/Dcode and sysbus arbitation scheme" "Static,Round-robin"
|
|
bitfld.long 0x00 2. " PREF_EN ,Tag prefetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MODE ,VIMS mode request" "GPRAM,CACHE,Split cache,Off"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FLASH"
|
|
base ad:0x40030000
|
|
width 20.
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STAT ,FMC and Efuse Status"
|
|
bitfld.long 0x00 15. " EFUSE_BLANK ,Efuse scanning detected if fuse ROM is blank" "Not blank,Blank"
|
|
bitfld.long 0x00 14. " EFUSE_TIMEOUT ,Efuse scanning resulted in timeout error" "No error,Error"
|
|
bitfld.long 0x00 13. " EFUSE_CRC_ERROR ,Efuse scanning resulted in scan chain CRC error" "No error,Error"
|
|
bitfld.long 0x00 8.--12. " EFUSE_ERRCODE ,Efuse error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SAMHOLD_DIS ,Flash sample and hold sequencing logic disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " BUSY ,Fast version of the FMC FMSTAT.BUSY bit" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " POWER_MODE ,Power state of the flash sub-system" "Active,Low-power"
|
|
; Following registers : "Internal. Only to be used through TI provided API"
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "CFG,Configuration"
|
|
bitfld.long 0x00 8. " STANDBY_MODE_SEL ,Standby mode selection" "0,1"
|
|
bitfld.long 0x00 6.--7. " STANDBY_PW_SEL ,Standby PW selection" "0,1,2,3"
|
|
bitfld.long 0x00 5. " DIS_EFUSECLK ,Disable EFUSECLK" "No,Yes"
|
|
bitfld.long 0x00 4. " DIS_READACCESS ,Disable READACCESS" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SWINTF ,ENABLE_SWINTF" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DIS_STANDBY ,Disable STANDBY" "No,Yes"
|
|
bitfld.long 0x00 0. " DIS_IDLE ,Disable IDLE" "No,Yes"
|
|
line.long 0x04 "SYSCODE_START,Syscode Start Address Offset Configuration"
|
|
bitfld.long 0x04 0.--4. " SYSCODE_START , SYSCODE START" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "FLASH_SIZE,Flash Size Configuration"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SECTORS ,SECTORS"
|
|
textline ""
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "FWLOCK,Firmware Lock"
|
|
bitfld.long 0x00 0.--2. " FWLOCK ,Firmware lock" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FWFLAG,Firmware Flags"
|
|
bitfld.long 0x04 0.--2. " FWFLAG ,Firmware Flags" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1000++0x13
|
|
line.long 0x00 "EFUSE,E-Fuse instruction register"
|
|
bitfld.long 0x00 24.--28. " INSTRUCTION ,INSTRUCTION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. " DUMPWORD ,DUMPWORD"
|
|
line.long 0x04 "EFUSEADDR,E-Fuse address register"
|
|
bitfld.long 0x04 11.--15. " BLOCK ,BLOCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x04 0.--10. 1. " ROW ,ROW"
|
|
line.long 0x08 "DATAUPPER,E-Fuse data register - upper"
|
|
bitfld.long 0x08 3.--7. " SPARE ,SPARE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 2. " P ,P" "0,1"
|
|
bitfld.long 0x08 1. " R ,R" "0,1"
|
|
bitfld.long 0x08 0. " EEN ,EEN" "0,1"
|
|
line.long 0x0C "DATALOWER,E-fuse data register - lower"
|
|
line.long 0x10 "EFUSECFG OCP,Standard system configuration register"
|
|
bitfld.long 0x10 8. " IDLEGATING ,Idle gating" "0,1"
|
|
bitfld.long 0x10 3.--4. " SLAVEPOWER ,Slave power" "0,1,2,3"
|
|
bitfld.long 0x10 0. " GATING ,GATING" "0,1"
|
|
rgroup.long 0x1014++0x07
|
|
line.long 0x00 "EFUSESTAT,System Status"
|
|
bitfld.long 0x00 2. " RESETDONE ,RESET DONE" "No,Yes"
|
|
line.long 0x04 "ACC,Arbitrary Instruction count"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " ACCUMULATOR ,ACCUMULATOR"
|
|
textline " "
|
|
group.long 0x101C++0x03
|
|
line.long 0x00 "BOUNDARY,Boundary test register to drive I/O"
|
|
bitfld.long 0x00 23. " DISROW0 ,DISROW0" "0,1"
|
|
bitfld.long 0x00 22. " SPARE ,SPARE" "0,1"
|
|
bitfld.long 0x00 21. " EFC_SELF_TEST_ERROR ,EFC Self Test Error" "No error,Error"
|
|
bitfld.long 0x00 20. " EFC_INSTRUCTION_INFO ,EFC Instruction Info" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EFC_INSTRUCTION_ERROR ,EFC Instructioon Error" "No error,Error"
|
|
bitfld.long 0x00 18. " EFC_AUTOLOAD_ERROR ,EFC Autoload Error" "No error,Error"
|
|
bitfld.long 0x00 14.--17. " OUTPUTENABLE ,Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13. " YS_ECC_SELF_TEST_EN ,YS_ECC Self Test Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SYS_ECC_OVERRIDE_EN ,SYS_ECC Override Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EFC_FDI ,EFC_FDI" "0,1"
|
|
bitfld.long 0x00 10. " SYS_DIEID_AUTOLOAD_EN ,SYS_DIEID Autoload Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " SYS_REPAIR_EN ,SYS Repair Enable" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SYS_WS_READ_STATES ,SYS_WS Read States" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " INPUTENABLE ,Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1020++0x03
|
|
line.long 0x00 "EFUSEFLAG,Efuse Key Loaded Flag"
|
|
bitfld.long 0x00 0. " KEY ,KEY" "0,1"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "EFUSEKEY,Efuse Key"
|
|
rgroup.long 0x1028++0x07
|
|
line.long 0x00 "EFUSERELEASE,Efuse Release"
|
|
hexmask.long.byte 0x00 25.--31. 1. " ODPYEAR ,ODP YEAR"
|
|
bitfld.long 0x00 21.--24. " ODPMONTH ,ODP MONTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 16.--20. " ODPDAY ,ODP DAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 9.--15. 1. " EFUSEYEAR ,EFUSE YEAR"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " EFUSEMONTH ,EFUSE MONTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 0.--4. " EFUSEDAY ,EFUSE DAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EFUSEPINS,Efuse Pins"
|
|
bitfld.long 0x04 15. " EFC_SELF_TEST_DONE ,EFC Self Test Done" "Not Done,Done"
|
|
bitfld.long 0x04 14. " EFC_SELF_TEST_ERROR ,EFC Self Test Error" "No error,Error"
|
|
bitfld.long 0x04 13. " SYS_ECC_SELF_TEST_EN ,SYS_ECC Self Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EFC_INSTRUCTION_INFO ,EFC Instruction Info" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EFC_INSTRUCTION_ERROR ,EFC Instruction Error" "No error,Error"
|
|
bitfld.long 0x04 10. " EFC_AUTOLOAD_ERROR ,EFC Autoload Error" "No error,Error"
|
|
bitfld.long 0x04 9. " SYS_ECC_OVERRIDE_EN ,SYS_ECC Override Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EFC_READY ,EFC Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EFC_FCLRZ ,EFC_FCLRZ" "0,1"
|
|
bitfld.long 0x04 6. " SYS_DIEID_AUTOLOAD_EN ,SYS_DIEID Autoload Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4.--5. " SYS_REPAIR_EN ,SYS Repair Enable" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " SYS_WS_READ_STATES ,SYS_WS Read States" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline ""
|
|
group.long 0x1030++0x0F
|
|
line.long 0x00 "EFUSECRA,Efuse Column Repair Address"
|
|
bitfld.long 0x00 0.--5. " DATA ,DATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "EFUSEREAD,Efuse Read"
|
|
bitfld.long 0x04 8.--9. " DATABIT ,DATABIT" "0,1,2,3"
|
|
bitfld.long 0x04 4.--7. " READCLOCK ,READCLOCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 3. " DEBUG ,DEBUG" "0,1"
|
|
bitfld.long 0x04 2. " SPARE ,SPARE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MARGIN ,MARGIN" "0,1,2,3"
|
|
line.long 0x08 "EFUSEPROGRAM,Efuse Program"
|
|
bitfld.long 0x08 30. " COMPAREDISABLE ,Compare disable" "No,Yes"
|
|
hexmask.long.word 0x08 14.--29. 1. " CLOCKSTALL ,CLOCKSTALL"
|
|
bitfld.long 0x08 13. " VPPTOVDD ,VPP TO VDD" "0,1"
|
|
bitfld.long 0x08 9.--12. " ITERATIONS ,ITERATIONS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--8. 1. " WRITECLOCK ,WRITE CLOCK"
|
|
line.long 0x0C "EFUSEERROR,Efuse Error"
|
|
bitfld.long 0x0C 5. " DONE ,DONE" "No,Yes"
|
|
bitfld.long 0x0C 0.--4. " CODE ,CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x1040++0x07
|
|
line.long 0x00 "SINGLEBIT,Single-Bit Error Status"
|
|
hexmask.long 0x00 1.--31. 1. " FROMN ,FROMN"
|
|
bitfld.long 0x00 0. " FROM0 ,FROM0" "0,1"
|
|
line.long 0x04 "TWOBIT,Two-Bit Error Status"
|
|
hexmask.long 0x04 1.--31. 1. " FROMN ,FROMN"
|
|
bitfld.long 0x04 0. " FROM0 ,FROM0" "0,1"
|
|
group.long 0x1048++0x07
|
|
line.long 0x00 "SELFTESTCYC,Self-Test Cycles"
|
|
line.long 0x04 "SELFTESTSIGN,Self-Test Signature"
|
|
group.long 0x2000++0x0B
|
|
line.long 0x00 "FRDCTL,FMC Read Control"
|
|
bitfld.long 0x00 8.--11. " RWAIT ,RWAIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RM ,RM"
|
|
line.long 0x04 "FSPRD FMC, Read Margin Control"
|
|
hexmask.long.word 0x04 16.--31. 1. " DIS_PREEMPT ,DIS_PREEMPT"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RMBSEM ,RMBSEM"
|
|
bitfld.long 0x04 1. " RM1 ,RM1" "0,1"
|
|
bitfld.long 0x04 0. " RM0 ,RM0" "0,1"
|
|
line.long 0x08 "FEDACCTL1,FMC Error Correction Control 1"
|
|
bitfld.long 0x08 24. " SUSP_IGNR ,SUSP_IGNR" "0,1"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " EDACEN ,EDACEN"
|
|
group.long 0x201C++0x03
|
|
line.long 0x00 "FEDACSTAT,FMC Error Status"
|
|
eventfld.long 0x00 25. " RVF_INT ,RVF_INT" "0,1"
|
|
eventfld.long 0x00 24. " FSM_DONE ,FSM DONE" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ERR_PRF_FLG ,ERR_PRF Flag"
|
|
group.long 0x2030++0x07
|
|
line.long 0x00 "FBPROT ,FMC Bank Protection"
|
|
bitfld.long 0x00 0. " PROTL1DIS ,PROTL1 Disable" "No,Yes"
|
|
line.long 0x04 "FBSE ,FMC Bank Sector Enable"
|
|
hexmask.long.word 0x04 0.--15. 1. " BSE ,BSE"
|
|
rgroup.long 0x2038++0x03
|
|
line.long 0x00 "FBBUSY,FMC Bank Busy"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BUSY ,BUSY"
|
|
group.long 0x203C++0x07
|
|
line.long 0x00 "FBAC,FMC Bank Access Control"
|
|
bitfld.long 0x00 16. " OTPPROTDIS ,OTPPROTDIS" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BAGP ,BAGP"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VREADS ,VREADS"
|
|
line.long 0x04 "FBFALLBACK,FMC Bank Fallback Power"
|
|
bitfld.long 0x04 24.--27. " FSM_PWRSAV ,FSM Power Saving" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " REG_PWRSAV ,REG Power Saving" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 14.--15. " BANKPWR7 ,Bank 7 Power" "0,1,2,3"
|
|
bitfld.long 0x04 12.--13. " BANKPWR6 ,Bank 6 Power" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " BANKPWR5 ,Bank 5 Power" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. " BANKPWR4 ,Bank 4 Power" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " BANKPWR3 ,Bank 3 Power" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BANKPWR2 ,Bank 2 Power" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " BANKPWR1 ,Bank 1 Power" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " BANKPWR0 ,Bank 0 Power" "0,1,2,3"
|
|
rgroup.long 0x2044++03
|
|
line.long 0x00 "FBPRDY,FMC Bank/Pump Ready"
|
|
bitfld.long 0x00 16. " BANKBUSY ,Bank ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " PUMPRDY ,Pump ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " BANKRDY ,Bank Ready" "Not ready,Ready"
|
|
textline " "
|
|
group.long 0x2048++0x0B
|
|
line.long 0x00 "FPAC1,FMC Pump Access Control 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " PSLEEPTDIS ,PSLEEPTDIS"
|
|
hexmask.long.word 0x00 4.--15. 1. " PUMPRESET_PW ,PUMPRESET_PW"
|
|
bitfld.long 0x00 0.--1. " PUMPPWR ,PUMPPWR" "0,1,2,3"
|
|
line.long 0x04 "FPAC2,FMC Pump Access Control 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " PAGP ,PAGP"
|
|
line.long 0x08 "FMAC,FMC Module Access Control"
|
|
bitfld.long 0x08 0.--2. " BANK , BANK" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2054++0x03
|
|
line.long 0x00 "FMSTAT,FMC Module Status"
|
|
bitfld.long 0x00 17. " RVSUSP ,RVSUSP" "0,1"
|
|
bitfld.long 0x00 16. " RDVER ,RDVER" "0,1"
|
|
bitfld.long 0x00 15. " RVF ,RVF" "0,1"
|
|
bitfld.long 0x00 14. " ILA ,ILA" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DBF ,DBF" "0,1"
|
|
bitfld.long 0x00 12. " PGV ,PGV" "0,1"
|
|
bitfld.long 0x00 11. " PCV ,PCV" "0,1"
|
|
bitfld.long 0x00 10. " EV ,EV" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CV ,CV" "0,1"
|
|
bitfld.long 0x00 8. " BUSY ,BUSY" "0,1"
|
|
bitfld.long 0x00 7. " ERS ,ERS" "0,1"
|
|
bitfld.long 0x00 6. " PGM ,PGM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INVDAT ,INVDAT" "0,1"
|
|
bitfld.long 0x00 4. " CSTAT ,CSTAT" "0,1"
|
|
bitfld.long 0x00 3. " VOLSTAT ,VOLSTAT" "0,1"
|
|
bitfld.long 0x00 2. " ESUSP ,ESUSP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PSUSP ,PSUSP" "0,1"
|
|
bitfld.long 0x00 0. " SLOCK ,SLOCK" "0,1"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "FLOCK,FMC Flash Lock"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENCOM ,ENCOM"
|
|
group.long 0x2080++0x2B
|
|
line.long 0x00 "FVREADCT,FMC VREADCT Trim"
|
|
bitfld.long 0x00 0.--3. " VREADCT ,VREADCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "FVHVCT1,FMC VHVCT1 Trim"
|
|
bitfld.long 0x04 20.--23. " TRIM13_E ,TRIM13_E" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " VHVCT_E ,VHVCT_E" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " TRIM13_PV ,TRIM13_PV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " VHVCT_PV ,VHVCT_PV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "FVHVCT2,FMC VHVCT2 Trim"
|
|
bitfld.long 0x08 20.--23. " TRIM13_P ,TRIM13_P" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " VHVCT_P ,VHVCT_P" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "FVHVCT3,FMC VHVCT3 Trim"
|
|
bitfld.long 0x0C 16.--19. " WCT ,WCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " VHVCT_READ ,VHVCT_READ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "FVNVCT,FMC VNVCT Trim"
|
|
bitfld.long 0x10 8.--12. " VCG2P5CT ,VCG2P5CT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--4. " VIN_CT ,VIN_CT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "FVSLP,FMC VSL_P Trim"
|
|
bitfld.long 0x14 12.--15. " VSL_P ,VSL_P" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "FVWLCT,FMC VWLCT Trim"
|
|
bitfld.long 0x18 0.--4. " VWLCT_P ,VWLCT_P" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "FEFUSECTL,FMC EFUSE Control"
|
|
bitfld.long 0x1C 24.--26. " CHAIN_SEL ,CHAIN_SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 17. " WRITE_EN ,WRITE Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " BP_SEL ,BP Select" "0,1"
|
|
bitfld.long 0x1C 8. " EF_CLRZ ,EF_CLRZ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EF_TEST ,EF TEST" "0,1"
|
|
bitfld.long 0x1C 0.--3. " EFUSE_EN ,EFUSE Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "FEFUSESTAT,FMC EFUSE Status"
|
|
eventfld.long 0x20 0. " SHIFT_DONE ,SHIFT DONE" "Not done,Done"
|
|
line.long 0x24 "FEFUSEDATA,FMC EFUSE Data"
|
|
line.long 0x28 "FSEQPMP,FMC Sequential Pump Information"
|
|
bitfld.long 0x28 24.--27. " RIM_3P4 ,RIM_3P4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 20.--21. " TRIM_1P7 ,TRIM_1P7" "0,1,2,3"
|
|
bitfld.long 0x28 16.--19. " TRIM_0P8 ,TRIM_0P8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 12.--14. " VIN_AT_X ,VIN_AT_X" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 8. " VIN_BY_PASS ,VIN_BY_PASS" "0,1"
|
|
hexmask.long.byte 0x28 0.--7. 1. " SEQ_PUMP ,SEQ_PUMP"
|
|
group.long 0x2100++0x17
|
|
line.long 0x00 "FBSTROBES,FMC Bank Signal Strobe"
|
|
bitfld.long 0x00 24. " ECBIT ,ECBIT" "0,1"
|
|
bitfld.long 0x00 18. " RWAIT2_FLCLK ,RWAIT2_FLCLK" "0,1"
|
|
bitfld.long 0x00 17. " RWAIT_FLCLK ,RWAIT_FLCLK" "0,1"
|
|
bitfld.long 0x00 16. " FLCLKEN ,FLCLKEN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CTRLENZ ,CTRLENZ" "0,1"
|
|
bitfld.long 0x00 6. " NOCOLRED ,NOCOLRED" "0,1"
|
|
bitfld.long 0x00 5. " PRECOL ,PRECOL" "0,1"
|
|
bitfld.long 0x00 4. " TI_OTP ,TI_OTP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OTP ,OTP" "0,1"
|
|
bitfld.long 0x00 2. " TEZ ,TEZ" "0,1"
|
|
line.long 0x04 "FPSTROBES,FMC Pump Signal Strobe"
|
|
bitfld.long 0x04 8. " EXECUTEZ ,EXECUTEZ" "0,1"
|
|
bitfld.long 0x04 1. " V3PWRDNZ ,V3PWRDNZ" "0,1"
|
|
bitfld.long 0x04 0. " V5PWRDNZ ,V5PWRDNZ" "0,1"
|
|
line.long 0x08 "FBMODE, FMC Bank and Pump Mode"
|
|
bitfld.long 0x08 0.--2. " MODE ,MODE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "FTCR,FMC Test Command Control"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " TCR ,TCR"
|
|
line.long 0x10 "FADDR,FMC Bank Address"
|
|
group.long 0x211C++0x03
|
|
line.long 0x00 "FTCTL,FMC Test Control"
|
|
bitfld.long 0x00 16. " WDATA_BLK_CLR ,WDATA_BLK_CLR" "0,1"
|
|
bitfld.long 0x00 1. " TEST_EN ,TEST_EN" "0,1"
|
|
width 20.
|
|
group.long 0x2120++0x23
|
|
line.long 0x00 "FWPWRITE0,FMC Flash Wide Programming Write Data 0"
|
|
line.long 0x04 "FWPWRITE1,FMC Flash Wide Programming Write Data 1"
|
|
line.long 0x08 "FWPWRITE2,FMC Flash Wide Programming Write Data 2"
|
|
line.long 0x0C "FWPWRITE3,FMC Flash Wide Programming Write Data 3"
|
|
line.long 0x10 "FWPWRITE4,FMC Flash Wide Programming Write Data 4"
|
|
line.long 0x14 "FWPWRITE5,FMC Flash Wide Programming Write Data 5"
|
|
line.long 0x18 "FWPWRITE6,FMC Flash Wide Programming Write Data 6"
|
|
line.long 0x1C "FWPWRITE7,FMC Flash Wide Programming Write Data 7"
|
|
line.long 0x20 "FWPWRITE_ECC,FMC Flash Wide Programming ECC"
|
|
hexmask.long.byte 0x20 24.--31. 1. " ECCBYTES07_00 ,ECCBYTES [07:00]"
|
|
hexmask.long.byte 0x20 16.--23. 1. " ECCBYTES15_08 ,ECCBYTES [15:08]"
|
|
hexmask.long.byte 0x20 8.--15. 1. " ECCBYTES23_16 ,ECCBYTES [23:16]"
|
|
hexmask.long.byte 0x20 0.--7. 1. " ECCBYTES31_24 ,ECCBYTES [31:24]"
|
|
rgroup.long 0x2144++0x03
|
|
line.long 0x00 "FSWSTAT,FMC Software Interface Status"
|
|
bitfld.long 0x00 0. " SAFELV ,SAFELV" "0,1"
|
|
rgroup.long 0x2200++0x0B
|
|
line.long 0x00 "FSM_GLBCTL,FMC FSM Global Control"
|
|
bitfld.long 0x00 0. " CLKSEL ,CLKSEL" "0,1"
|
|
line.long 0x04 "FSM_STATE,FMC FSM State Status"
|
|
bitfld.long 0x04 11. " CTRLENZ ,CTRLENZ" "0,1"
|
|
bitfld.long 0x04 10. " EXECUTEZ ,EXECUTEZ" "0,1"
|
|
bitfld.long 0x04 8. " FSM_ACT ,FSM_ACT" "0,1"
|
|
bitfld.long 0x04 7. " TIOTP_ACT ,TIOTP_ACT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OTP_ACT ,OTP_ACT" "0,1"
|
|
line.long 0x08 "FSM_STAT,FMC FSM Status"
|
|
bitfld.long 0x08 2. " NON_OP ,NON_OP" "0,1"
|
|
bitfld.long 0x08 1. " OVR_PUL_CNT ,OVR_PUL_CNT" "0,1"
|
|
bitfld.long 0x08 0. " INV_DAT ,INV_DAT" "0,1"
|
|
group.long 0x220C++0x23
|
|
line.long 0x00 "FSM_CMD,FMC FSM Command"
|
|
bitfld.long 0x00 0.--5. " FSMCMD ,FSM Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "FSM_PE_OSU,FMC FSM Program/Erase Operation Setup"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PGM_OSU ,PGM_OSU"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ERA_OSU ,ERA_OSU"
|
|
line.long 0x08 "FSM_VSTAT,FMC FSM Voltage Status Setup"
|
|
bitfld.long 0x08 12.--15. " VSTAT_CNT ,VSTAT_CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "FSM_PE_VSU,FMC FSM Program/Erase Verify Setup"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PGM_VSU ,PGM_VSU"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ERA_VSU ,ERA_VSU"
|
|
line.long 0x10 "FSM_CMP_VSU,FMC FSM Compare Verify Setup"
|
|
bitfld.long 0x10 12.--15. " ADD_EXZ ,ADD_EXZ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "FSM_EX_VAL,FMC FSM EXECUTEZ to Valid Data"
|
|
hexmask.long.byte 0x14 8.--15. 1. " ADD_EXZ ,ADD_EXZ"
|
|
hexmask.long.byte 0x14 0.--7. 1. " EXE_VALD ,EXE_VALD"
|
|
line.long 0x18 "FSM_RD_H,FMC FSM Read Mode Hold"
|
|
hexmask.long.byte 0x18 0.--7. 1. " RD_H ,RD_H"
|
|
line.long 0x1C "FSM_P_OH,FMC FSM Program Hold"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PGM_OH ,PGM_OH"
|
|
line.long 0x20 "FSM_ERA_OH,FMC FSM Erase Operation Hold"
|
|
hexmask.long.word 0x20 0.--15. 1. " ERA_OH ,ERA_OH"
|
|
rgroup.long 0x2230++0x03
|
|
line.long 0x00 "FSM_SAV_PPUL,FMC FSM Saved Program Pulses"
|
|
hexmask.long.word 0x00 0.--11. 1. " SAV_P_PUL ,SAV_P_PUL"
|
|
group.long 0x2234++0x03
|
|
line.long 0x00 "FSM_PE_VH,FMC FSM Program/Erase Verify Hold"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PGM_VH ,PGM_VH"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERA_VH ,ERA_VH"
|
|
group.long 0x2240++0x07
|
|
line.long 0x00 "FSM_PRG_PW,FMC FSM Program Pulse Width"
|
|
hexmask.long.word 0x00 0.--15. 1. " PROG_PUL_WIDTH ,PROG_PUL_WIDTH"
|
|
line.long 0x04 "FSM_ERA_PW,FMC FSM Erase Pulse Width"
|
|
rgroup.long 0x2254++0x13
|
|
line.long 0x00 "FSM_SAV_ERA_PUL,FMC FSM Saved Erased Pulses"
|
|
hexmask.long.word 0x00 0.--11. 1. " SAV_ERA_PUL ,SAV_ERA_PUL"
|
|
line.long 0x04 "FSM_TIMER,FMC FSM Timer"
|
|
line.long 0x08 "FSM_MODE,FMC FSM MODE"
|
|
bitfld.long 0x08 18.--19. " RDV_SUBMODE ,RDV_SUBMODE" "0,1,2,3"
|
|
bitfld.long 0x08 16.--17. " PGM_SUBMODE ,PGM_SUBMODE" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " ERA_SUBMODE ,ERA_SUBMODE" "0,1,2,3"
|
|
bitfld.long 0x08 12.--13. " SUBMODE ,SUBMODE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 9.--11. " SAV_PGM_CMD ,SAV_PGM_CMD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 6.--8. " SAV_ERA_MODE ,SAV_ERA_MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 3.--5. " MODE ,MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--2. " CMD ,CMD" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "FSM_PGM,FMC FSM Program Bits"
|
|
bitfld.long 0x0C 23.--25. " PGM_BANK ,PGM_BANK" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x0C 0.--22. 1. " PGM_ADDR ,PGM_ADDR"
|
|
line.long 0x10 "FSM_ERA,FMC FSM Erase Bits"
|
|
bitfld.long 0x10 23.--25. " ERA_BANK ,ERA_BANK" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x10 0.--22. 1. " ERA_ADDR ,ERA_ADDR"
|
|
group.long 0x2268++0x0B
|
|
line.long 0x00 "FSM_PRG_PUL,FMC FSM Maximum Programming Pulses"
|
|
bitfld.long 0x00 16.--19. " BEG_EC_LEVEL ,BEG_EC_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " MAX_PRG_PUL ,MAX_PRG_PUL"
|
|
line.long 0x04 "FSM_ERA_PUL,FMC FSM Maximum Erase Pulses"
|
|
bitfld.long 0x04 16.--19. " MAX_EC_LEVEL ,MAX_EC_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX_ERA_PUL ,MAX_ERA_PUL"
|
|
line.long 0x08 "FSM_STEP_SIZE,FMC FSM EC Step Size"
|
|
hexmask.long.word 0x08 16.--24. 1. " EC_STEP_SIZE ,EC_STEP_SIZE"
|
|
rgroup.long 0x2274++0x03
|
|
line.long 0x00 "FSM_PUL_CNTR,FMC FSM Pulse Counter"
|
|
hexmask.long.word 0x00 16.--24. 1. " CUR_EC_LEVEL ,Current EC Level"
|
|
hexmask.long.word 0x00 0.--11. 1. " PUL_CNTR ,PUL_CNTR"
|
|
group.long 0x2278++0x0B
|
|
line.long 0x00 "FSM_EC_STEP_HEIGHT,FMC FSM EC Step Height"
|
|
bitfld.long 0x00 0.--3. " EC_STEP_HEIGHT ,EC Step Height" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "FSM_ST_MACHINE,FMC FSM_ST_MACHINE"
|
|
bitfld.long 0x04 23. " DO_PRECOND ,DO_PRECOND" "0,1"
|
|
bitfld.long 0x04 22. " FSM_INT_EN ,FSM_INT_EN" "0,1"
|
|
bitfld.long 0x04 21. " ALL_BANKS ,ALL_BANKS" "0,1"
|
|
bitfld.long 0x04 20. " CMPV_ALLOWED ,CMPV_ALLOWED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RANDOM ,RANDOM" "0,1"
|
|
bitfld.long 0x04 18. " RV_SEC_EN ,RV_SEC_EN" "0,1"
|
|
bitfld.long 0x04 17. " RV_RES ,RV_RES" "0,1"
|
|
bitfld.long 0x04 16. " RV_INT_EN ,RV_INT_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 14. " ONE_TIME_GOOD ,ONE_TIME_GOOD" "0,1"
|
|
bitfld.long 0x04 11. " DO_REDU_COL ,DO_REDU_COL" "0,1"
|
|
bitfld.long 0x04 7.--10. " DBG_SHORT_ROW ,DBG_SHORT_ROW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 5. " PGM_SEC_COF_EN ,PGM_SEC_COF_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PREC_STOP_EN ,PREC_STOP_EN" "0,1"
|
|
bitfld.long 0x04 3. " DIS_TST_EN ,DIS_TST_EN" "0,1"
|
|
bitfld.long 0x04 2. " CMD_EN ,CMD_EN" "0,1"
|
|
bitfld.long 0x04 1. " INV_DATA ,INV_DATA" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OVERRIDE ,OVERRIDE" "0,1"
|
|
line.long 0x08 "FSM_FLES,FMC FLES Memory Control Bits"
|
|
bitfld.long 0x08 8.--11. " BLK_TIOTP ,BLK_TIOTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 0.--7. 1. " BLK_OTP ,BLK_OTP"
|
|
group.long 0x2288++0x03
|
|
line.long 0x00 "FSM_WR_ENA,FMC FSM Register Write Enable"
|
|
bitfld.long 0x00 0.--2. " WR_ENA ,Write Enable" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x228C++0x07
|
|
line.long 0x00 "FSM_ACC_PP,FMC FSM Accumulate Program Pulses"
|
|
line.long 0x04 "FSM_ACC_EP,FMC FSM Accumulate Erase Pulses"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACC_EP ,Accumulate Erase Pulses"
|
|
rgroup.long 0x22A0++0x03
|
|
line.long 0x00 "FSM_ADDR,FMC FSM Address"
|
|
bitfld.long 0x00 28.--30. " BANK ,BANK" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--27. 1. " CUR_ADDR ,Current Address"
|
|
group.long 0x22A4++0x13
|
|
line.long 0x00 "FSM_SECTOR,FMC Sectors Erased"
|
|
hexmask.long.word 0x00 16.--31. 1. " SECT_ERASED ,Sectors Erased"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FSM_SECTOR_EXTENSION ,FSM Sector Extention"
|
|
rbitfld.long 0x00 4.--7. " SECTOR ,SECTOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " SEC_OUT ,SEC_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x22A8++0x0F
|
|
line.long 0x00 "FMC_REV_ID,FMC Revision Identification"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " MOD_VERSION ,MOD Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " CONFIG_CRC ,CONFIG_CRC"
|
|
line.long 0x04 "FSM_ERR_ADDR,FSM Error Address"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " FSM_ERR_ADDR ,FSM Error Address"
|
|
bitfld.long 0x04 0.--3. " FSM_ERR_BANK ,FSM Error Bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "FSM_PGM_MAXPUL,FMC FSM Maximum Program Pulse"
|
|
hexmask.long.word 0x08 0.--11. 1. " FSM_PGM_MAXPUL ,FSM Maximum program pulse"
|
|
line.long 0x0C "FSM_EXECUTE,FMC FSM Command Execute"
|
|
bitfld.long 0x0C 16.--19. " SUSPEND_NOW ,SUSPEND_NOW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--4. " FSMEXECUTE ,FSMEXECUTE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x22C0++0x07
|
|
line.long 0x00 "FSM_SECTOR1,FMC FSM Sector Erased 1"
|
|
line.long 0x04 "FSM_SECTOR2,FMC FSM Sector Erased 2"
|
|
group.long 0x22E0++0x07
|
|
line.long 0x00 "FSM_BSLE0,FMC FSM Bank Sector Lock Erase 0"
|
|
line.long 0x04 "FSM_BSLE1,FMC FSM Bank Sector Lock Erase 1"
|
|
group.long 0x22F0++0x07
|
|
line.long 0x00 "FSM_BSLP0,FMC FSM Bank Sector Lock Program 0"
|
|
line.long 0x04 "FSM_BSLP1,FMC FSM Bank Sector Lock Program 1"
|
|
rgroup.long 0x2400++0x0B
|
|
line.long 0x00 "FCFG_BANK,FMC Flash Configuration Bank"
|
|
hexmask.long.word 0x00 20.--31. 1. " EE_BANK_WIDTH ,EE Bank Width"
|
|
bitfld.long 0x00 16.--19. " EE_NUM_BANK ,EE_NUM_BANK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " MAIN_BANK_WIDTH ,Main Bank Width"
|
|
bitfld.long 0x00 0.--3. " MAIN_NUM_BANK ,MAIN_NUM_BANK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "FCFG_WRAPPER,FMC Flash Wrapper Configuration"
|
|
hexmask.long.byte 0x04 24.--31. 1. " FAMILY_TYPE ,FAMILY_TYPE"
|
|
bitfld.long 0x04 20. " MEM_MAP ,MEM_MAP" "0,1"
|
|
bitfld.long 0x04 16.--19. " CPU2 ,CPU2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 12.--15. " EE_IN_MAIN ,EE_IN_MAIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ROM ,ROM" "0,1"
|
|
bitfld.long 0x04 10. " IFLUSH ,IFLUSH" "0,1"
|
|
bitfld.long 0x04 9. " SIL3 ,SIL3" "0,1"
|
|
bitfld.long 0x04 8. " ECCA ,ECCA" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " AUTO_SUSP ,AUTO_SUSP" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " UERR ,UERR" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " CPU_TYPE1 ,CPU_TYPE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "FCFG_BNK_TYPE,FMC Flash Bank Type"
|
|
bitfld.long 0x08 28.--31. " B7_TYPE ,B7 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " B6_TYPE ,B6 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " B5_TYPE ,B5 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " B4_TYPE ,B4 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " B3_TYPE ,B3 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " B2_TYPE ,B2_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " B1_TYPE ,B1 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " B0_TYPE ,B0 TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x2410++0x03
|
|
line.long 0x00 "FCFG_B0_START,FMC Flash Bank 0 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B0_MAX_SECTOR ,Flash Bank 0 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B0_MUX_FACTOR ,Flash Bank 0 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B0_START_ADDR ,Flash Bank 0 Starting Address"
|
|
rgroup.long 0x2414++0x03
|
|
line.long 0x00 "FCFG_B1_START,FMC Flash Bank 1 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B1_MAX_SECTOR ,Flash Bank 1 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B1_MUX_FACTOR ,Flash Bank 1 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B1_START_ADDR ,Flash Bank 1 Starting Address"
|
|
rgroup.long 0x2418++0x03
|
|
line.long 0x00 "FCFG_B2_START,FMC Flash Bank 2 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B2_MAX_SECTOR ,Flash Bank 2 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B2_MUX_FACTOR ,Flash Bank 2 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B2_START_ADDR ,Flash Bank 2 Starting Address"
|
|
rgroup.long 0x241C++0x03
|
|
line.long 0x00 "FCFG_B3_START,FMC Flash Bank 3 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B3_MAX_SECTOR ,Flash Bank 3 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B3_MUX_FACTOR ,Flash Bank 3 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B3_START_ADDR ,Flash Bank 3 Starting Address"
|
|
rgroup.long 0x2420++0x03
|
|
line.long 0x00 "FCFG_B4_START,FMC Flash Bank 4 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B4_MAX_SECTOR ,Flash Bank 4 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B4_MUX_FACTOR ,Flash Bank 4 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B4_START_ADDR ,Flash Bank 4 Starting Address"
|
|
rgroup.long 0x2424++0x03
|
|
line.long 0x00 "FCFG_B5_START,FMC Flash Bank 5 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B5_MAX_SECTOR ,Flash Bank 5 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B5_MUX_FACTOR ,Flash Bank 5 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B5_START_ADDR ,Flash Bank 5 Starting Address"
|
|
rgroup.long 0x2428++0x03
|
|
line.long 0x00 "FCFG_B6_START,FMC Flash Bank 6 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B6_MAX_SECTOR ,Flash Bank 6 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B6_MUX_FACTOR ,Flash Bank 6 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B6_START_ADDR ,Flash Bank 6 Starting Address"
|
|
rgroup.long 0x242C++0x03
|
|
line.long 0x00 "FCFG_B7_START,FMC Flash Bank 7 Starting Address"
|
|
bitfld.long 0x00 28.--31. " B7_MAX_SECTOR ,Flash Bank 7 MAX sector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " B7_MUX_FACTOR ,Flash Bank 7 MUX Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " B7_START_ADDR ,Flash Bank 7 Starting Address"
|
|
rgroup.long 0x2430++0x03
|
|
line.long 0x00 "FCFG_B0_SSIZE0,FMC Flash Bank 0 Sector Size 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " B0_NUM_SECTORS ,B0_NUM_SECTORS"
|
|
bitfld.long 0x00 0.--3. " B0_SECT_SIZE ,Bank 0 Sector Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DEVCFG (Device configuration)"
|
|
tree "CCFG (Consumer Configuration)"
|
|
base ad:0x50003000
|
|
width 20.
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "EXT_LF_CLK,Extern LF Clock Configuration"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DIO ,DIO used to supply external 32kHz clock for SCLK_LF"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTC_INCREMENT ,Increment value (2^38 / InputClockFrequency)"
|
|
if ((d.l(ad:0x50003000+0xFB0)&0x03)==0x00)
|
|
group.long 0xFAC++0x03
|
|
line.long 0x00 "MODE_CONF_1 ,Mode Configuration 1"
|
|
bitfld.long 0x00 20.--23. " ALT_DCDC_VMIN ,Minimum voltage for when DC/DC should be used" "1.75,1.8125,1.875,1.9375,2,2.0625,2.125,2.1875,2.25,2.3125,2.375,2.4375,2.5,2.5625,2.625,2.6875"
|
|
bitfld.long 0x00 19. " ALT_DCDC_DITHER_EN ,Enable DC/DC dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " ALT_DCDC_IPEAK ,Inductor peak current" "31mA,35mA,39mA,43mA,47mA,51mA,55mA,59mA"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELTA_IBIAS_INIT ,Signed delta value for IBIAS_INIT" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
bitfld.long 0x00 8.--11. " DELTA_IBIAS_OFFSET ,Signed delta value for IBIAS_OFFSET" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XOSC_MAX_START ,Unsigned value of maximum XOSC startup time (worst case) in units of 100us"
|
|
elif ((d.l(ad:0x50003000+0xFB0)&0x03)==0x01)
|
|
group.long 0xFAC++0x03
|
|
line.long 0x00 "MODE_CONF_1 ,Mode Configuration 1"
|
|
bitfld.long 0x00 20.--23. " ALT_DCDC_VMIN ,Minimum voltage for when DC/DC should be used" "1.75,1.8125,1.875,1.9375,2,2.0625,2.125,2.1875,2.25,2.3125,2.375,2.4375,2.5,2.5625,2.625,2.6875"
|
|
bitfld.long 0x00 19. " ALT_DCDC_DITHER_EN ,Enable DC/DC dithering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " ALT_DCDC_IPEAK ,Inductor peak current" "31mA,35mA,39mA,43mA,47mA,51mA,55mA,59mA"
|
|
elif ((d.l(ad:0x50003000+0xFB0)&0x03)==0x02)
|
|
group.long 0xFAC++0x03
|
|
line.long 0x00 "MODE_CONF_1 ,Mode Configuration 1"
|
|
bitfld.long 0x00 12.--15. " DELTA_IBIAS_INIT ,Signed delta value for IBIAS_INIT" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
bitfld.long 0x00 8.--11. " DELTA_IBIAS_OFFSET ,Signed delta value for IBIAS_OFFSET" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XOSC_MAX_START ,Unsigned value of maximum XOSC startup time (worst case) in units of 100us"
|
|
else
|
|
hgroup.long 0xFAC++0x03
|
|
hide.long 0x00 "MODE_CONF_1 ,Mode Configuration 1"
|
|
endif
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "SIZE_AND_DIS_FLAGS ,CCFG Size and Disable Flags"
|
|
hexmask.long.word 0x00 16.--31. 1. " SIZE_OF_CCFG ,Total size of CCFG in bytes"
|
|
bitfld.long 0x00 1. " DIS_ALT_DCDC_SETTING ,Disable alternate DC/DC settings" "No,Yes"
|
|
bitfld.long 0x00 0. " DIS_XOSC_OVR ,Disable XOSC override functionality" "No,Yes"
|
|
if ((d.l(ad:0x50003000+0xFB4)&0x20000)==0x20000)
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "MODE_CONF ,Mode Configuration 0"
|
|
bitfld.long 0x00 28.--31. " VDDR_TRIM_SLEEP_DELTA ,Signed delta value to apply to the VDDR_TRIM_SLEEP target" "1,2,3,4,5,6,7,8,-7,-6,-5,-4,-3,-2,-1,0"
|
|
bitfld.long 0x00 27. " DCDC_RECHARGE ,DC/DC Usage during recharge in powerdown" "Used,Not used"
|
|
bitfld.long 0x00 26. " DCDC_ACTIVE ,DC/DC Usage in active mode" "Used,Not used"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VDDS_BOD_LEVEL ,VDDS BOD level" "2.0V,1.8V"
|
|
bitfld.long 0x00 22.--23. " SCLK_LF_OPTION ,Select source for SCLK_LF" "XOSC_HF_DLF,EXTERNAL,XOSC_LF,RCOSC_LF"
|
|
bitfld.long 0x00 17. " XOSC_CAP_MOD ,XOSC cap-array modification (cap-array delta appliance)" "Apply,Do not apply"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XOSC_CAPARRAY_DELTA ,Directly modifying trimmed XOSC cap-array step TA value (Signed 8-bit value)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VDDR_CAP ,Minimum decoupling capacitance (worst case) on VDDR in units of 100nF (Unsigned 8-bit integer)"
|
|
else
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "MODE_CONF ,Mode Configuration 0"
|
|
bitfld.long 0x00 28.--31. " VDDR_TRIM_SLEEP_DELTA ,Signed delta value to apply to the VDDR_TRIM_SLEEP target" "1,2,3,4,5,6,7,8,-7,-6,-5,-4,-3,-2,-1,0"
|
|
bitfld.long 0x00 27. " DCDC_RECHARGE ,DC/DC Usage during recharge in powerdown" "Not used,Used"
|
|
bitfld.long 0x00 26. " DCDC_ACTIVE ,DC/DC Usage in active mode" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VDDS_BOD_LEVEL ,VDDS BOD level" "2.0V,1.8V"
|
|
bitfld.long 0x00 22.--23. " SCLK_LF_OPTION ,Select source for SCLK_LF" "XOSC_HF_DLF,EXTERNAL,XOSC_LF,RCOSC_LF"
|
|
bitfld.long 0x00 17. " XOSC_CAP_MOD ,XOSC cap-array modification (cap-array delta appliance)" "Apply,Do not apply"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VDDR_CAP ,Minimum decoupling capacitance (worst case) on VDDR in units of 100nF (Unsigned 8-bit integer)"
|
|
endif
|
|
; Reserved:
|
|
; line.long 0x0C "VOLT_LOAD_0 ,Voltage Load 0"
|
|
; line.long 0x10 "VOLT_LOAD_1 ,Voltage Load 1"
|
|
; line.long 0x14 "RTC_OFFSET ,Real Time Clock Offset"
|
|
; line.long 0x18 "FREQ_OFFSET ,Frequency Offset"
|
|
group.long 0xFC8++0x0F
|
|
line.long 0x00 "IEEE_MAC_0 ,IEEE MAC Address 0"
|
|
line.long 0x04 "IEEE_MAC_1 ,IEEE MAC Address 1"
|
|
line.long 0x08 "IEEE_BLE_0 ,IEEE BLE Address 0"
|
|
line.long 0x0C "IEEE_BLE_1 ,IEEE BLE Address 1"
|
|
if ((d.l(ad:0x50003000+0xFD8)&0xFF)==0xC5)
|
|
group.long 0xFD8++0x03
|
|
line.long 0x00 "BL_CONFIG ,Bootloader Configuration"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BOOTLOADER_ENABLE ,Bootloader enable (0xC5: Enabled)"
|
|
bitfld.long 0x00 16. " BL_LEVEL ,Sets the active level of the selected pin" "Active low,Avtive high"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BL_PIN_NUMBER ,DIO number that is level checked "
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BL_ENABLE ,Boot loader backdoor enable (0xC5: Enabled)"
|
|
else
|
|
group.long 0xFD8++0x03
|
|
line.long 0x00 "BL_CONFIG ,Bootloader Configuration"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BOOTLOADER_ENABLE ,Bootloader enable (0xC5: Enabled)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BL_ENABLE ,Boot loader backdoor enable (0xC5: Enabled)"
|
|
endif
|
|
group.long 0xFDC++0x23
|
|
line.long 0x00 "ERASE_CONF ,Erase Configuration"
|
|
bitfld.long 0x00 8. " CHIP_ERASE_DIS_N ,Chip erase" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BANK_ERASE_DIS_N ,Bank erase" "Disabled,Enabled"
|
|
line.long 0x04 "CCFG_TI_OPTIONS ,TI Options"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TI_FA_ENABLE ,TI Failure Analysis (0xC5: Enabled)"
|
|
line.long 0x08 "CCFG_TAP_DAP_0 ,Test Access Points Enable 0"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CPU_DAP_ENABLE ,Enable CPU DAP (0xC5: Enabled)"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRCM_TAP_ENABLE ,Enable PRCM TAP (0xC5: Enabled)"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TEST_TAP_ENABLE ,Enable Test TAP (0xC5: Enabled)"
|
|
line.long 0x0C "CCFG_TAP_DAP_1 ,Test Access Points Enable 1"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PBIST2_TAP_ENABLE ,Enable PBIST2 TAP (0xC5: Enabled)"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PBIST1_TAP_ENABLE ,Enable PBIST1 TAP (0xC5: Enabled)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " WUC_TAP_ENABLE ,Enable WUC TAP (0xC5: Enabled)"
|
|
line.long 0x10 "IMAGE_VALID_CONF ,Image Valid"
|
|
line.long 0x14 "CCFG_PROT_31_0 ,Protect Sectors 0-31"
|
|
bitfld.long 0x14 31. " WRT_PROT_SEC[31] ,Sector 31 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 30. " [30] ,Sector 30 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 29. " [29] ,Sector 29 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 28. " [28] ,Sector 28 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 27. " [27] ,Sector 27 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 26. " [26] ,Sector 26 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 25. " [25] ,Sector 25 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 24. " [24] ,Sector 24 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 23. " [23] ,Sector 23 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 22. " [22] ,Sector 22 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 21. " [21] ,Sector 21 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 20. " [20] ,Sector 20 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 19. " [19] ,Sector 19 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 18. " [18] ,Sector 18 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 17. " [17] ,Sector 17 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 16. " [16] ,Sector 16 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 15. " [15] ,Sector 15 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 14. " [14] ,Sector 14 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 13. " [13] ,Sector 13 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 12. " [12] ,Sector 12 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 11. " [11] ,Sector 11 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 10. " [10] ,Sector 10 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 9. " [9] ,Sector 9 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 8. " [8] ,Sector 8 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 7. " [7] ,Sector 7 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 6. " [6] ,Sector 6 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 5. " [5] ,Sector 5 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 4. " [4] ,Sector 4 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x14 3. " [3] ,Sector 3 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 2. " [2] ,Sector 2 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 1. " [1] ,Sector 1 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x14 0. " [0] ,Sector 0 Write Protection" "Protected,Not protected"
|
|
line.long 0x18 "CCFG_PROT_63_32 ,Protect Sectors 32-63"
|
|
bitfld.long 0x18 31. " WRT_PROT_SEC[63] ,Sector 63 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 30. " [62] ,Sector 62 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 29. " [61] ,Sector 61 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 28. " [60] ,Sector 60 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 27. " [59] ,Sector 59 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 26. " [58] ,Sector 58 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 25. " [57] ,Sector 57 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 24. " [56] ,Sector 56 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 23. " [55] ,Sector 55 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 22. " [54] ,Sector 54 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 21. " [53] ,Sector 53 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 20. " [52] ,Sector 52 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 19. " [51] ,Sector 51 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 18. " [50] ,Sector 50 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 17. " [49] ,Sector 49 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 16. " [48] ,Sector 48 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 15. " [47] ,Sector 47 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 14. " [46] ,Sector 46 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 13. " [45] ,Sector 45 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 12. " [44] ,Sector 44 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 11. " [43] ,Sector 43 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 10. " [42] ,Sector 42 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 9. " [41] ,Sector 41 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 8. " [40] ,Sector 40 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 7. " [39] ,Sector 39 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 6. " [38] ,Sector 38 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 5. " [37] ,Sector 37 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 4. " [36] ,Sector 36 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x18 3. " [35] ,Sector 35 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 2. " [34] ,Sector 34 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 1. " [33] ,Sector 33 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x18 0. " [32] ,Sector 32 Write Protection" "Protected,Not protected"
|
|
line.long 0x1C "CCFG_PROT_95_64 ,Protect Sectors 64-95"
|
|
bitfld.long 0x1C 31. " WRT_PROT_SEC[95] ,Sector 95 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 30. " [94] ,Sector 94 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 29. " [93] ,Sector 93 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 28. " [92] ,Sector 92 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " [91] ,Sector 91 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 26. " [90] ,Sector 90 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 25. " [89] ,Sector 89 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 24. " [88] ,Sector 88 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " [87] ,Sector 87 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 22. " [86] ,Sector 86 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 21. " [85] ,Sector 85 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 20. " [84] ,Sector 84 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " [83] ,Sector 83 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 18. " [82] ,Sector 82 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 17. " [81] ,Sector 81 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 16. " [80] ,Sector 80 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " [79] ,Sector 79 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 14. " [78] ,Sector 78 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 13. " [77] ,Sector 77 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 12. " [76] ,Sector 76 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " [75] ,Sector 75 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 10. " [74] ,Sector 74 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 9. " [73] ,Sector 73 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 8. " [72] ,Sector 72 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " [71] ,Sector 71 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 6. " [70] ,Sector 70 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 5. " [69] ,Sector 69 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 4. " [68] ,Sector 68 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " [67] ,Sector 67 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 2. " [66] ,Sector 66 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 1. " [65] ,Sector 65 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x1C 0. " [64] ,Sector 64 Write Protection" "Protected,Not protected"
|
|
line.long 0x20 "CCFG_PROT_127_96 ,Protect Sectors 96-127"
|
|
bitfld.long 0x20 31. " WRT_PROT_SEC[127] ,Sector 127 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 30. " [126] ,Sector 126 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 29. " [125] ,Sector 125 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 28. " [124] ,Sector 124 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 27. " [123] ,Sector 123 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 26. " [122] ,Sector 122 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 25. " [121] ,Sector 121 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 24. " [120] ,Sector 120 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 23. " [119] ,Sector 119 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 22. " [118] ,Sector 118 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 21. " [117] ,Sector 117 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 20. " [116] ,Sector 116 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 19. " [115] ,Sector 115 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 18. " [114] ,Sector 114 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 17. " [113] ,Sector 113 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 16. " [112] ,Sector 112 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 15. " [111] ,Sector 111 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 14. " [110] ,Sector 110 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 13. " [109] ,Sector 109 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 12. " [108] ,Sector 108 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 11. " [107] ,Sector 107 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 10. " [106] ,Sector 106 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 9. " [105] ,Sector 105 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 8. " [104] ,Sector 104 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 7. " [103] ,Sector 103 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 6. " [102] ,Sector 102 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 5. " [101] ,Sector 101 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 4. " [100] ,Sector 100 Write Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x20 3. " [99] ,Sector 99 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 2. " [98] ,Sector 98 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 1. " [97] ,Sector 97 Write Protection" "Protected,Not protected"
|
|
bitfld.long 0x20 0. " [96] ,Sector 96 Write Protection" "Protected,Not protected"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FCFG (Factory Configuration)"
|
|
base ad:0x50001000
|
|
width 26.
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "MISC_CONF_1,Misc Configurations"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DEVICE_MINOR_REV ,HW minor revision number"
|
|
sif cpuis("CC1310*")
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CONFIG_RF_FRONTEND_DIV5,Configuration of RF Frontend in Divide-by-5 Mode"
|
|
bitfld.long 0x00 28.--31. " IFAMP_IB ,ADI_0_RF:IFAMPCTL3.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LNA_IB ,ADI_0_RF:LNACTL2.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " IFAMP_TRIM ,ADI_0_RF:IFAMPCTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CTL_PA0_TRIM , ADI_0_RF:PACTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RFLDO_TRIM_OUTPUT ,ADI_0_RF:RFLDO1.TRIM_OUT trim value"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "CONFIG_RF_FRONTEND_DIV6,Configuration of RF Frontend in Divide-by-6 Mode"
|
|
bitfld.long 0x00 28.--31. " IFAMP_IB ,ADI_0_RF:IFAMPCTL3.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LNA_IB ,ADI_0_RF:LNACTL2.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " IFAMP_TRIM ,ADI_0_RF:IFAMPCTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CTL_PA0_TRIM , ADI_0_RF:PACTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RFLDO_TRIM_OUTPUT ,ADI_0_RF:RFLDO1.TRIM_OUT trim value"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "CONFIG_RF_FRONTEND_DIV10,Configuration of RF Frontend in Divide-by-10 Mode"
|
|
bitfld.long 0x00 28.--31. " IFAMP_IB ,ADI_0_RF:IFAMPCTL3.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LNA_IB ,ADI_0_RF:LNACTL2.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " IFAMP_TRIM ,ADI_0_RF:IFAMPCTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CTL_PA0_TRIM , ADI_0_RF:PACTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RFLDO_TRIM_OUTPUT ,ADI_0_RF:RFLDO1.TRIM_OUT trim value"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "CONFIG_RF_FRONTEND_DIV12,Configuration of RF Frontend in Divide-by-12 Mode"
|
|
bitfld.long 0x00 28.--31. " IFAMP_IB ,ADI_0_RF:IFAMPCTL3.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LNA_IB ,ADI_0_RF:LNACTL2.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " IFAMP_TRIM ,ADI_0_RF:IFAMPCTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CTL_PA0_TRIM , ADI_0_RF:PACTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RFLDO_TRIM_OUTPUT ,ADI_0_RF:RFLDO1.TRIM_OUT trim value"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "CONFIG_RF_FRONTEND_DIV15,Configuration of RF Frontend in Divide-by-15 Mode"
|
|
bitfld.long 0x00 28.--31. " IFAMP_IB ,ADI_0_RF:IFAMPCTL3.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LNA_IB ,ADI_0_RF:LNACTL2.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. " IFAMP_TRIM ,ADI_0_RF:IFAMPCTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 14.--18. " CTL_PA0_TRIM , ADI_0_RF:PACTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x00 0.--6. 1. " RFLDO_TRIM_OUTPUT ,ADI_0_RF:RFLDO1.TRIM_OUT trim value"
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|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "CONFIG_RF_FRONTEND_DIV30,Configuration of RF Frontend in Divide-by-30 Mode"
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|
bitfld.long 0x00 28.--31. " IFAMP_IB ,ADI_0_RF:IFAMPCTL3.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. " LNA_IB ,ADI_0_RF:LNACTL2.IB trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19.--23. " IFAMP_TRIM ,ADI_0_RF:IFAMPCTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 14.--18. " CTL_PA0_TRIM , ADI_0_RF:PACTL0.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x00 0.--6. 1. " RFLDO_TRIM_OUTPUT ,ADI_0_RF:RFLDO1.TRIM_OUT trim value"
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|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV5,Configuration of Synthesizer in Divide-by-5 Mode"
|
|
hexmask.long.word 0x00 12.--27. 1. " RFC_MDM_DEMIQMC0 ,RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR trim value"
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|
bitfld.long 0x00 6.--11. " LDOVCO_TRIM_OUTPUT ,ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 0.--5. " SLDO_TRIM_OUTPUT ,ADI_1_SYNTH:SLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV6,Configuration of Synthesizer in Divide-by-6 Mode"
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|
hexmask.long.word 0x00 12.--27. 1. " RFC_MDM_DEMIQMC0 ,RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR trim value"
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|
bitfld.long 0x00 6.--11. " LDOVCO_TRIM_OUTPUT ,ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. " SLDO_TRIM_OUTPUT ,ADI_1_SYNTH:SLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV10,Configuration of Synthesizer in Divide-by-10 Mode"
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hexmask.long.word 0x00 12.--27. 1. " RFC_MDM_DEMIQMC0 ,RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR trim value"
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bitfld.long 0x00 6.--11. " LDOVCO_TRIM_OUTPUT ,ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. " SLDO_TRIM_OUTPUT ,ADI_1_SYNTH:SLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0xE8++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV12,Configuration of Synthesizer in Divide-by-12 Mode"
|
|
hexmask.long.word 0x00 12.--27. 1. " RFC_MDM_DEMIQMC0 ,RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR trim value"
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bitfld.long 0x00 6.--11. " LDOVCO_TRIM_OUTPUT ,ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. " SLDO_TRIM_OUTPUT ,ADI_1_SYNTH:SLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV15,Configuration of Synthesizer in Divide-by-15 Mode"
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|
hexmask.long.word 0x00 12.--27. 1. " RFC_MDM_DEMIQMC0 ,RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR trim value"
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bitfld.long 0x00 6.--11. " LDOVCO_TRIM_OUTPUT ,ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 0.--5. " SLDO_TRIM_OUTPUT ,ADI_1_SYNTH:SLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV30,Configuration of Synthesizer in Divide-by-30 Mode"
|
|
hexmask.long.word 0x00 12.--27. 1. " RFC_MDM_DEMIQMC0 ,RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR trim value"
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bitfld.long 0x00 6.--11. " LDOVCO_TRIM_OUTPUT ,ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. " SLDO_TRIM_OUTPUT ,ADI_1_SYNTH:SLDOCTL1.TRIM_OUT trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "CONFIG_MISC_ADC_DIV5,Configuration of IFADC in Divide-by-5 Mode"
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|
hexmask.long.byte 0x00 9.--16. 1. " RSSI_OFFSET ,RSSI value measured in production test"
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|
bitfld.long 0x00 6.--8. " QUANTCTLTHRES ,ADI_0_RF:IFADCQUANT0.TH trim value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--5. " DACTRIM , ADI_0_RF:IFADCDAC.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0xF8++0x03
|
|
line.long 0x00 "CONFIG_MISC_ADC_DIV6,Configuration of IFADC in Divide-by-6 Mode"
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|
hexmask.long.byte 0x00 9.--16. 1. " RSSI_OFFSET ,RSSI value measured in production test"
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|
bitfld.long 0x00 6.--8. " QUANTCTLTHRES ,ADI_0_RF:IFADCQUANT0.TH trim value" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 0.--5. " DACTRIM , ADI_0_RF:IFADCDAC.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0xFC++0x03
|
|
line.long 0x00 "CONFIG_MISC_ADC_DIV10,Configuration of IFADC in Divide-by-10 Mode"
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|
hexmask.long.byte 0x00 9.--16. 1. " RSSI_OFFSET ,RSSI value measured in production test"
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|
bitfld.long 0x00 6.--8. " QUANTCTLTHRES ,ADI_0_RF:IFADCQUANT0.TH trim value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--5. " DACTRIM , ADI_0_RF:IFADCDAC.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x100++0x03
|
|
line.long 0x00 "CONFIG_MISC_ADC_DIV12,Configuration of IFADC in Divide-by-12 Mode"
|
|
hexmask.long.byte 0x00 9.--16. 1. " RSSI_OFFSET ,RSSI value measured in production test"
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bitfld.long 0x00 6.--8. " QUANTCTLTHRES ,ADI_0_RF:IFADCQUANT0.TH trim value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--5. " DACTRIM , ADI_0_RF:IFADCDAC.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x104++0x03
|
|
line.long 0x00 "CONFIG_MISC_ADC_DIV15,Configuration of IFADC in Divide-by-15 Mode"
|
|
hexmask.long.byte 0x00 9.--16. 1. " RSSI_OFFSET ,RSSI value measured in production test"
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bitfld.long 0x00 6.--8. " QUANTCTLTHRES ,ADI_0_RF:IFADCQUANT0.TH trim value" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 0.--5. " DACTRIM , ADI_0_RF:IFADCDAC.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x108++0x03
|
|
line.long 0x00 "CONFIG_MISC_ADC_DIV30,Configuration of IFADC in Divide-by-30 Mode"
|
|
hexmask.long.byte 0x00 9.--16. 1. " RSSI_OFFSET ,RSSI value measured in production test"
|
|
bitfld.long 0x00 6.--8. " QUANTCTLTHRES ,ADI_0_RF:IFADCQUANT0.TH trim value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " DACTRIM , ADI_0_RF:IFADCDAC.TRIM trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
endif
|
|
rgroup.long 0x118++0x0F
|
|
line.long 0x00 "SHDW_DIE_ID_0,EFUSE:DIE_ID_0 Shadow"
|
|
line.long 0x04 "SHDW_DIE_ID_1,EFUSE:DIE_ID_1 Shadow"
|
|
line.long 0x08 "SHDW_DIE_ID_2,EFUSE:DIE_ID_2 Shadow"
|
|
line.long 0x0C "SHDW_DIE_ID_3,EFUSE:DIE_ID_3 Shadow"
|
|
rgroup.long 0x138++0x07
|
|
line.long 0x00 "SHDW_OSC_BIAS_LDO_TRIM,EFUSE:OSC_BIAS_LDO_TRIM Shadow"
|
|
bitfld.long 0x00 27.--28. " ET_RCOSC_HF_COARSE_RESISTOR ,EFUSE:OSC_BIAS_LDO_TRIM.SET_RCOSC_HF_COARSE_RESISTOR shadow value" "0,1,2,3"
|
|
bitfld.long 0x00 23.--26. " TRIMMAG ,EFUSE:OSC_BIAS_LDO_TRIM.TRIMMAG shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--22. " TRIMIREF ,EFUSE:OSC_BIAS_LDO_TRIM.TRIMIREF shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 16.--17. " ITRIM_DIG_LDO ,EFUSE:OSC_BIAS_LDO_TRIM.ITRIM_DIG_LDO shadow value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " VTRIM_DIG ,EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_DIG shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. " VTRIM_COARSE ,EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_COARSE shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.byte 0x00 0.--7. 1. " RCOSCHF_CTRIM ,EFUSE:OSC_BIAS_LDO_TRIM.RCOSCHF_CTRIM shadow value"
|
|
line.long 0x04 "SHDW_ANA_TRIM,EFUSE:ANA_TRIM Shadow"
|
|
bitfld.long 0x04 25.--26. " BOD_BANDGAP_TRIM_CNF ,EFUSE:ANA_TRIM.BOD_BANDGAP_TRIM_CNF shadow value" "0,1,2,3"
|
|
bitfld.long 0x04 24. " VDDR_ENABLE_PG1 ,EFUSE:ANA_TRIM.VDDR_ENABLE_PG1 shadow value" "0,1"
|
|
bitfld.long 0x04 23. " VDDR_OK_HYS ,EFUSE:ANA_TRIM.VDDR_OK_HYS shadow value" "0,1"
|
|
bitfld.long 0x04 21.--22. " IPTAT_TRIM ,EFUSE:ANA_TRIM.IPTAT_TRIM shadow value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 16.--20. " VDDR_TRIM ,EFUSE:ANA_TRIM.VDDR_TRIM shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x04 11.--15. " TRIMBOD_INTMODE ,EFUSE:ANA_TRIM.TRIMBOD_INTMODE shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x04 6.--10. " TRIMBOD_EXTMODE ,EFUSE:ANA_TRIM.TRIMBOD_EXTMODE shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--5. " TRIMTEMP ,EFUSE:ANA_TRIM.TRIMTEMP shadow value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "FLASH_NUMBER,FLASH Lot Number Register"
|
|
rgroup.long 0x16C++0x2F
|
|
line.long 0x00 "FLASH_COORDINATE,FLASH Wafer Coordinate Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XCOORDINATE ,X coordinate of this unit on the wafer"
|
|
hexmask.long.word 0x00 0.--15. 1. " YCOORDINATE ,Y coordinate of this unit on the wafer"
|
|
line.long 0x04 "FLASH_E_P,Flash Erase and Program Setup Time Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PSU ,Program setup time"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ESU ,Erase setup time"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PVSU ,Program verify setup time"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EVSU ,Erase verify setup time"
|
|
line.long 0x08 "FLASH_C_E_P_R,Flash Compaction, Execute, Program and Read Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RVSU ,Repeat verify setup time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PV_ACCESS ,Program verify EXECUTEZ->data valid time"
|
|
bitfld.long 0x08 12.--15. " A_EXEZ_SETUP ,Address->EXECUTEZ setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x08 0.--11. 1. " CVSU ,Compaction verify setup time"
|
|
line.long 0x0C "FLASH_P_R_PV,Flash Program, Read, and Program Verify Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PH ,Program hold time after SAFELV low"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " RH ,Read hold/mode transition time"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PVH ,Program verify hold time after SAFELV low"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PVH2 ,Program verify row switch time"
|
|
line.long 0x10 "FLASH_EH_SEQ,Flash Erase Hold and Sequence Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " EH ,Erase hold time after SAFELV low"
|
|
hexmask.long.byte 0x10 16.--23. 1. " SEQ ,Pump sequence control"
|
|
bitfld.long 0x10 12.--15. " VSTAT ,Pump brown-out max number of HCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.word 0x10 0.--11. 1. " SM_FREQUENCY ,Program, erase, and verify reads max FCLK frequency"
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|
line.long 0x14 "FLASH_VHV_E,Flash VHV Erase Register"
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|
hexmask.long.word 0x14 16.--31. 1. " VHV_E_START ,Starting VHV-Erase CT for stairstep erase"
|
|
hexmask.long.word 0x14 0.--15. 1. " VHV_E_STEP_HIGHT ,Number of VHV CTs to step after each erase pulse"
|
|
line.long 0x18 "FLASH_PP,Flash Program Pulse Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PUMP_SU ,Pump read->non-read mode transition time"
|
|
hexmask.long.word 0x18 0.--15. 1. " MAX_PP ,Max program pulse limit per program operation"
|
|
line.long 0x1C "FLASH_PROG_EP,Flash Program and Erase Pulse Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " MAX_EP ,Max erase pulse limit per erase operation"
|
|
hexmask.long.word 0x1C 0.--15. 1. " PROGRAM_PW ,Program pulse width"
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|
line.long 0x20 "FLASH_ERA_PW,Flash Erase Pulse Width Register"
|
|
line.long 0x24 "FLASH_VHV,Flash VHV Register"
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|
bitfld.long 0x24 24.--27. " TRIM13_P ,Erase/program operation initiation FLASH:FVHVCT2.TRIM13_P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. " VHV_P ,Erase/program operation initiation FLASH:FVHVCT2.VHVCT_P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x24 8.--11. " TRIM13_E ,Erase/program operation initiation FLASH:FVHVCT1.TRIM13_E value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x24 0.--3. " VHV_E ,Erase/program operation initiation FLASH:FVHVCT1.VHVCT_E value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x28 "FLASH_VHV_PV,Flash VHV Program Verify Register"
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|
bitfld.long 0x28 24.--27. " TRIM13_PV ,Erase/program operation initiation FLASH:FVHVCT1.TRIM13_PV value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. " VHV_PV ,Erase/program operation initiation FLASH:FVHVCT1.VHVCT_PV value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.byte 0x28 8.--15. 1. " VCG2P5 ,Control gate voltage for read/read margin/erase verify"
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|
hexmask.long.byte 0x28 0.--7. 1. " VINH ,Inhibit voltage applied to unselected columns during programming"
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|
line.long 0x2C "FLASH_V,Flash Voltages Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " VSL_P ,Sourceline voltage applied to the selected block during programming"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " VWL_P ,Wordline voltage applied to the selected half-row during programming"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " V_READ ,Wordline voltage applied to the selected block during reads and verifies"
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|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "USER_ID,User Identification Register"
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|
bitfld.long 0x00 28.--31. " PG_REV ,PG revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 26.--27. " VER ,Version number" "0,1,2,3"
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|
bitfld.long 0x00 19.--22. " SEQUENCE ,Sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--18. " PKG ,Package type" "4x4mm,5x5mm,7x7mm,?..."
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|
textline " "
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|
bitfld.long 0x00 12.--15. " PROTOCOL ,Supported protocol" ",BLE,RF4CE,BLE/RF4CE,Zigbee/6lowpan,BLE/Zigbee/6lowpan,RF4CE/Zigbee/6lowpan,BLE/RF4CE/Zigbee/6lowpan,Proprietary,BLE/Proprietary,R4FCE/Proprietary,BLE/RF4CE/Proprietary,Zigbee/6lowpan/Proprietary,BLE/Zigbee/6lowpan/Proprietary,RF4CE/Zigbee/6lowpan/Proprietary,BLE/RF4CE/Zigbee/6lowpan/Proprietary"
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rgroup.long 0x2B0++0x0B
|
|
line.long 0x00 "FLASH_OTP_DATA3,Flash OTP Data 3 Register"
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hexmask.long.word 0x00 23.--31. 1. " EC_STEP_SIZE ,Erase/program operation initiation FLASH:FSM_STEP_SIZE.EC_STEP_SIZE value"
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|
bitfld.long 0x00 22. " DO_PRECOND ,Erase/program operation initiation FLASH:FSM_ST_MACHINE.DO_PRECOND value" "0,1"
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|
bitfld.long 0x00 18.--21. " MAX_EC_LEVEL ,Erase/program operation initiation FLASH:FSM_ERA_PUL.MAX_EC_LEVEL value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--17. " TRIM_1P7 ,Erase/program operation initiation FLASH:FSEQPMP.TRIM_1P7 value" "0,1,2,3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " FLASH_SIZE ,Safe Zone Boot FW written FLASH:FLASH_SIZE.SECTORS value"
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hexmask.long.byte 0x00 0.--7. 1. " WAIT_SYSCODE ,Safe Zone Boot FW written FLASH:WAIT_SYSCODE.WAIT_SYSCODE value"
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line.long 0x04 "ANA2_TRIM,Misc Analog Trim Register"
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bitfld.long 0x04 31. " RCOSCHFCTRIMFRACT_EN ,Safe Zone Boot FW written DDI_0_OSC:CTL1.RCOSCHFCTRIMFRACT_EN value" "0,1"
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bitfld.long 0x04 26.--30. " RCOSCHFCTRIMFRACT ,Safe Zone Boot FW written DDI_0_OSC:CTL1.RCOSCHFCTRIMFRACT value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 23.--24. " SET_RCOSC_HF_FINE_RESISTOR ,Safe Zone Boot FW written DDI_0_OSC:ATESTCTL.SET_RCOSC_HF_FINE_RESISTOR value" "0,1,2,3"
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|
bitfld.long 0x04 22. " ATESTLF_UDIGLDO_IBIAS_TRIM ,Safe Zone Boot FW written DDI_0_OSC:ATESTCTL.ATESTLF_UDIGLDO_IBIAS_TRIM value" "0,1"
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|
textline " "
|
|
bitfld.long 0x04 16.--21. " NANOAMP_RES_TRIM ,Safe Zone Boot FW written DDI_0_OSC:ADCDOUBLERNANOAMPCTL.NANOAMP_RES_TRIM value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 11. " DITHER_EN ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL5.DITHER_EN value" "0,1"
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|
bitfld.long 0x04 8.--10. " DCDC_IPEAK ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL5.IPEAK value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 6.--7. " DEAD_TIME_TRIM ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL4.DEADTIME_TRIM value" "0,1,2,3"
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textline " "
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bitfld.long 0x04 3.--5. " DCDC_LOW_EN_SEL ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL4.LOW_EN_SEL value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--2. " DCDC_HIGH_EN_SEL ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL4.HIGH_EN_SEL value" "0,1,2,3,4,5,6,7"
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line.long 0x08 "LDO_TRIM,LDO Trim Register"
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|
bitfld.long 0x08 24.--28. " VDDR_TRIM_SLEEP ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL1.VDDR_TRIM_SLEEP value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 16.--18. " GLDO_CURSRC ,Safe Zone Boot FW written ADI_3_REFSYS:DCDCCTL0.GLDO_ISRC value" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x08 11.--12. " ITRIM_DIGLDO_LOAD ,Safe Zone Boot FW written ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO_LOAD value" "0,1,2,3"
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|
bitfld.long 0x08 8.--10. " ITRIM_UDIGLDO ,Safe Zone Boot FW written ADI_2_REFSYS:SOCLDOCTL3.ITRIM_UDIGLDO value" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x08 0.--2. " VTRIM_DELTA ,Safe Zone Boot FW written ADI_2_REFSYS:SOCLDOCTL2.VTRIM_DELTA value" "0,1,2,3,4,5,6,7"
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|
sif !cpuis("CC2630*")&&!cpuis("CC2620*")&&!cpuis("CC1310*")
|
|
rgroup.long 0x2E8++0x07
|
|
line.long 0x00 "MAC_BLE_0,MAC BLE Address Register 0"
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|
line.long 0x04 "MAC_BLE_1,MAC BLE Address Register 1"
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endif
|
|
sif !cpuis("CC2640*")
|
|
rgroup.long 0x2F0++0x07
|
|
line.long 0x00 "MAC_15_4_0,MAC IEEE 802.15.4 Address Register 0"
|
|
line.long 0x04 "MAC_15_4_1,MAC IEEE 802.15.4 Address Register 1"
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endif
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textline " "
|
|
rgroup.long 0x308++0x0B
|
|
line.long 0x00 "FLASH_OTP_DATA4,Flash OTP Data 4 Register"
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|
bitfld.long 0x00 31. " STANDBY_MODE_SEL_INT_WRT ,Flash write operation initiation FLASH:CFG.STANDBY_MODE_SEL value" "0,1"
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|
bitfld.long 0x00 29.--30. " STANDBY_PW_SEL_INT_WRT ,Flash write operation initiation FLASH:CFG.STANDBY_PW_SEL value" "0,1,2,3"
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bitfld.long 0x00 28. " DIS_STANDBY_INT_WRT ,Flash write operation initiation FLASH:CFG.DIS_STANDBY value" "0,1"
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|
textline " "
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bitfld.long 0x00 27. " DIS_IDLE_INT_WRT ,Flash write operation initiation FLASH:CFG.DIS_IDLE value" "0,1"
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bitfld.long 0x00 24.--26. " VIN_AT_X_INT_WRT ,Flash write operation initiation FLASH:FSEQPMP.VIN_AT_X value" "0,1,2,3,4,5,6,7"
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|
textline " "
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bitfld.long 0x00 23. " STANDBY_MODE_SEL_EXT_WRT ,Flash write operation initiation FLASH:CFG.STANDBY_MODE_SEL value" "0,1"
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bitfld.long 0x00 21.--22. " STANDBY_PW_SEL_EXT_WRT ,Flash write operation initiation FLASH:CFG.STANDBY_PW_SEL value" "0,1,2,3"
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bitfld.long 0x00 20. " DIS_STANDBY_EXT_WRT ,Flash write operation initiation FLASH:CFG.DIS_STANDBY value" "0,1"
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|
textline " "
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bitfld.long 0x00 19. " DIS_IDLE_EXT_WRT ,Flash write operation initiation FLASH:CFG.DIS_IDLE value" "0,1"
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bitfld.long 0x00 16.--18. " VIN_AT_X_EXT_WRT ,Flash write operation initiation FLASH:FSEQPMP.VIN_AT_X value" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 15. " STANDBY_MODE_SEL_INT_RD ,Flash write operation initiation FLASH:CFG.STANDBY_MODE_SEL value" "0,1"
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|
bitfld.long 0x00 13.--14. " STANDBY_PW_SEL_INT_RD ,Flash write operation initiation FLASH:CFG.STANDBY_PW_SEL value" "0,1,2,3"
|
|
bitfld.long 0x00 12. " DIS_STANDBY_INT_RD ,Flash write operation initiation FLASH:CFG.DIS_STANDBY value" "0,1"
|
|
textline " "
|
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bitfld.long 0x00 11. " DIS_IDLE_INT_RD ,Flash write operation initiation FLASH:CFG.DIS_IDLE value" "0,1"
|
|
bitfld.long 0x00 8.--10. " VIN_AT_X_INT_RD ,Flash write operation initiation FLASH:FSEQPMP.VIN_AT_X value" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 7. " STANDBY_MODE_SEL_EXT_RD ,Flash write operation initiation FLASH:CFG.STANDBY_MODE_SEL value" "0,1"
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|
bitfld.long 0x00 5.--6. " STANDBY_PW_SEL_EXT_RD ,Flash write operation initiation FLASH:CFG.STANDBY_PW_SEL value" "0,1,2,3"
|
|
bitfld.long 0x00 4. " DIS_STANDBY_EXT_RD ,Flash write operation initiation FLASH:CFG.DIS_STANDBY value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIS_IDLE_EXT_RD ,Flash write operation initiation FLASH:CFG.DIS_IDLE value" "0,1"
|
|
bitfld.long 0x00 0.--2. " VIN_AT_X_EXT_RD ,Flash write operation initiation FLASH:FSEQPMP.VIN_AT_X value" "0,1,2,3,4,5,6,7"
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line.long 0x04 "MISC_TRIM,Miscellaneous Trim Parameters Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TEMPVSLOPE ,TEMP slope with battery voltage (deg C / V)"
|
|
line.long 0x08 "RCOSC_HF_TEMPCOMP,RCOSC HF Temperature Compensation Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " FINE_RESISTOR ,Change in FINE_RESISTOR trim"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CTRIM ,Change in CTRIM trim"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CTRIMFRACT_QUAD ,Temp compensation quadratic CTRIMFRACT"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " CTRIMFRACT_SLOPE ,Number of CTRIMFRACT codes per 20 degrees C from default temperature"
|
|
rgroup.long 0x318++0xB
|
|
line.long 0x00 "ICEPICK_DEVICE_ID,IcePick Device Identification Register"
|
|
bitfld.long 0x00 28.--31. " PG_REV ,Device silicon revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--27. 1. " WAFER_ID ,Silicon die identifier"
|
|
hexmask.long.word 0x00 0.--11. 1. " MANUFACTURER_ID ,Manufacturer code"
|
|
line.long 0x04 "FCFG1_REVISION,Factory Configuration (FCFG1) Revision Register"
|
|
line.long 0x08 "MISC_OTP_DATA,Misc OTP Data Register"
|
|
bitfld.long 0x08 28.--31. " RCOSC_HF_ITUNE ,Trim value for DDI_0_OSC:RCOSCHFCTL.RCOSCHF_ITUNE_TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 20.--27. 1. " RCOSC_HF_CRIM ,Trim value for DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM"
|
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bitfld.long 0x08 15.--19. " PER_M ,Trim value for AON_WUC:OSCCFG.PER_M" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " PER_E ,Trim value for AON_WUC:OSCCFG.PER_E" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x08 8.--11. " PO_TAIL_RES_TRIM ,Trim value for DLO_DTX:PLLCTL1.PO_TAIL_RES_TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.byte 0x08 0.--7. 1. " TEST_PROGRAM_REV ,The revision of the test program used in the production process"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "IOCONF,IO Configuration Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " GPIO_CNT ,Safe Zone boot FW written IOC:CFG.GPIO_CNT value"
|
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rgroup.long 0x34C++0x0F
|
|
line.long 0x00 "CONFIG_IF_ADC,Configuration of IF_ADC"
|
|
bitfld.long 0x00 28.--31. " FF2ADJ ,Trim value for ADI_0_RF:IFADCLFCFG1.FF2ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. " FF3ADJ ,Trim value for ADI_0_RF:IFADCLFCFG1.FF3ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 20.--23. " INT3ADJ ,Trim value for ADI_0_RF:IFADCLFCFG0.INT3ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " FF1ADJ ,Trim value for ADI_0_RF:IFADCLFCFG0.FF1ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 14.--15. " AAFCAP ,Trim value for ADI_0_RF:IFADCCTL0.AAFCAP" "0,1,2,3"
|
|
bitfld.long 0x00 10.--13. " INT2ADJ ,Trim value for Trim value for ADI_0_RF:IFADCCTL0.INT2ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. " IFDIGLDO_TRIM_OUTPUT ,Trim value for ADI_0_RF:IFDLDO2.TRIM_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 0.--4. " IFANALDO_TRIM_OUTPUT ,Trim value for ADI_0_RF:IFALDO2.TRIM_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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line.long 0x04 "CONFIG_OSC_TOP,OSC Configuration Register"
|
|
bitfld.long 0x04 26.--29. " XOSC_HF_ROW_Q12 ,Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_ROW_Q12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x04 10.--25. 1. " XOSC_HF_COLUMN_Q12 ,Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_COLUMN_Q12"
|
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hexmask.long.byte 0x04 2.--9. 1. " RCOSCLF_CTUNE_TRIM ,Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_CTUNE_TRIM"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " RCOSCLF_RTUNE_TRIM ,Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_RTUNE_TRIM" "0,1,2,3"
|
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line.long 0x08 "CONFIG_RF_FRONTEND,Divide-by-2 Mode RF Frontend Configuration Register"
|
|
bitfld.long 0x08 28.--31. " IFAMP_IB ,Trim value for ADI_0_RF:IFAMPCTL3.IB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x08 24.--27. " LNA_IB ,Trim value for ADI_0_RF:LNACTL2.IB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 19.--23. " IFAMP_TRIM ,Trim value for ADI_0_RF:IFAMPCTL0.TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 14.--18. " CTL_PA0_TRIM ,Trim value for ADI_0_RF:PACTL0.TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 13. " PATRIMCOMPLETE_N ,Status of PA trim" "Trimmed,Not trimmed"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RFLDO_TRIM_OUTPUT ,Trim value for ADI_0_RF:RFLDO1.TRIM_OUT"
|
|
line.long 0x0C "CONFIG_SYNTH,Divide-by-2 Mode Synthesizer Configuration Register"
|
|
hexmask.long.word 0x0C 12.--27. 1. " RFC_MDM_DEMIQMC0 ,Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR"
|
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bitfld.long 0x0C 6.--11. " LDOVCO_TRIM_OUTPUT ,Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x0C 0.--5. " SLDO_TRIM_OUTPUT ,Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline ""
|
|
width 35.
|
|
rgroup.long 0x35C++0x07
|
|
line.long 0x00 "SOC_ADC_ABS_GAIN,Absolute Reference Mode AUX_ADC Gain Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SOC_ADC_ABS_GAIN_TEMP1 ,SOC_ADC gain in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REL_GAIN,Relative Reference Mode AUX_ADC Gain Register"
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|
hexmask.long.word 0x04 0.--15. 1. " SOC_ADC_REL_GAIN_TEMP1 ,SOC_ADC gain in relative reference mode at temperature 1 (30C)"
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|
rgroup.long 0x368++0x07
|
|
line.long 0x00 "SOC_ADC_OFFSET_INT,Absolute Reference Mode AUX_ADC Temperature Offsets Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SOC_ADC_REL_OFFSET_TEMP1 ,SOC_ADC offset in relative reference mode at temperature 1 (30C)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SOC_ADC_ABS_OFFSET_TEMP1 ,SOC_ADC offset in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REF_TRIM_AND_OFFSET_EXT,External Reference Mode AUX_ADC Reference Trim and Offset Register"
|
|
bitfld.long 0x04 0.--5. " SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 ,Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 1 (30C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline ""
|
|
width 18.
|
|
rgroup.long 0x370++0x13
|
|
line.long 0x00 "AMPCOMP_TH1,Ampltude Compensation Threshold 1 Register"
|
|
bitfld.long 0x00 18.--23. " HPMRAMP3_LTH ,HPM Ramp3 low amplitude threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. " HPMRAMP3_HTH ,HPM Ramp3 high amplitude threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 6.--9. " IBIASCAP_LPTOHP_OL_CNT ,XOSC mode transition CAP and IBIAS trim modification value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
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|
bitfld.long 0x00 0.--5. " HPMRAMP1_TH ,XOSC mode transition CAP and IBIAS trim modification value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x04 "AMPCOMP_TH2,Ampltude Compensation Threshold 2"
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|
bitfld.long 0x04 26.--31. " LPMUPDATE_LTH ,LPM Update low amplitude threshhold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x04 18.--23. " LPMUPDATE_HTM ,LPM Update high amplitude threshhold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x04 10.--15. " ADC_COMP_AMPTH_LPM ,LPM_UPDATE mode OPAMP's threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline " "
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bitfld.long 0x04 2.--7. " ADC_COMP_AMPTH_HPM ,HPM_UPDATE mode OPAMP's threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
line.long 0x08 "AMPCOMP_CTRL1,Amplitude Compensation Control Register"
|
|
bitfld.long 0x08 30. " AMPCOMP_REQ_MODE ,Trim value for DDI_0_OSC:AMPCOMPCTL.AMPCOMP_REQ_MODE" "0,1"
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|
bitfld.long 0x08 20.--23. " IBIAS_OFFSET ,Offset values of XOSC IBIAS trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. " IBIAS_INIT ,Initial value of XOSC IBIAS trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " LPM_IBIAS_WAIT_CNT_FINAL ,XTAL slow response compensation wait count"
|
|
bitfld.long 0x08 4.--7. " CAP_STEP ,Step size of XOSC CAP trim (both Q1 and Q2) during XOSC mode transition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x08 0.--3. " IBIASCAP_HPTOLP_OL_CNT ,HPM to LPM transition CAP and IBIAS trim modification value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x0C "ANABYPASS_VALUE2,OSC Analog Bypass Value Register"
|
|
hexmask.long.word 0x0C 0.--13. 1. " XOSC_HF_IBIASTHERM ,Value of XOSC_HF_IBIASTHERM when OSCDIG is bypassed"
|
|
line.long 0x10 "CONFIG_MISC_ADC,Divide-by-2 Mode IFADC Configuration Register"
|
|
bitfld.long 0x10 17. " RSSITRIMCOMPLETE_N ,Status of RSSI trim" "Trimmed,Not trimmed"
|
|
hexmask.long.byte 0x10 9.--16. 1. " RSSI_OFFSET ,Value for RSSI measured in production test"
|
|
bitfld.long 0x10 6.--8. " QUANTCTLTHRES ,Trim value for ADI_0_RF:IFADCQUANT0.TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 0.--5. " DACTRIM ,Trim value for ADI_0_RF:IFADCDAC.TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0x388++0x07
|
|
line.long 0x00 "VOLT_TRIM,Voltage Trim Register"
|
|
bitfld.long 0x00 24.--28. " VDDR_TRIM_HH ,Trim value for 1.94V VDDR found in production test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VDDR_TRIM_H ,Trim value for 1.85V VDDR found in production test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--12. " VDDR_TRIM_SLEEP_H ,Trim value for 1.75V VDDR recharge target found in production test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " TRIMBOD_H ,Trim value for 2.0V VDDS BOD target found in production test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "OSC_CONF,OSC Configuration Register"
|
|
bitfld.long 0x04 29. " ADC_SH_VBUF_EN ,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN" "0,1"
|
|
bitfld.long 0x04 28. " ADC_SH_MODE_EN ,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN" "0,1"
|
|
bitfld.long 0x04 27. " ATESTLF_RCOSCLF_IBIAS_TRIM ,Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25.--26. " XOSCLF_REGULATOR_TRIM ,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM" "0,1,2,3"
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|
bitfld.long 0x04 21.--24. " XOSCLF_CMIRRWR_RATIO ,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 19.--20. " XOSC_HF_FAST_START ,Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 18. " XOSC_OPTION ,XOSC HF Available" "Not available,Available"
|
|
group.long 0x394++0x07
|
|
line.long 0x00 "CAP_TRIM,Capacitor Trim Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FLUX_CAP_0P28_TRIM ,Reserved storage of measurement value on 0.28um pitch FLUX CAP"
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|
hexmask.long.word 0x00 0.--15. 1. " FLUX_CAP_0P4_TRIM ,Reserved storage of measurement value on 0.4um pitch FLUX CAP"
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|
line.long 0x04 "MISC_OTP_DATA_1,Misc OSC Control Register"
|
|
bitfld.long 0x04 27.--28. " PEAK_DET_ITRIM ,Trim value for DDI_0_OSC:XOSCHFCTL.PEAK_DET_ITRIM" "0,1,2,3"
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|
bitfld.long 0x04 24.--26. " HP_BUF_ITRIM ,Trim value for DDI_0_OSC:XOSCHFCTL.HP_BUF_ITRIM" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 22.--23. " LP_BUF_ITRIM ,Trim value for DDI_0_OSC:XOSCHFCTL.LP_BUF_ITRIM" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " DBLR_LOOP_FILTER_RESET_VOLTAGE ,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.DBLR_LOOP_FILTER_RESET_VOLTAGE" "0,1,2,3"
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hexmask.long.word 0x04 10.--19. 1. " HPM_IBIAS_WAIT_CNT ,Trim value for DDI_0_OSC:RADCEXTCFG.HPM_IBIAS_WAIT_CNT"
|
|
textline " "
|
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bitfld.long 0x04 4.--9. " LPM_IBIAS_WAIT_CNT ,Trim value for DDI_0_OSC:RADCEXTCFG.LPM_IBIAS_WAIT_CNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--3. " IDAC_STEP ,Trim value for DDI_0_OSC:RADCEXTCFG.IDAC_STEP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
group.long 0x39C++0x03
|
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line.long 0x00 "PWD_CURR_20C,Power Down Current Control 20C Register"
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
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hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
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hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
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group.long 0x3A0++0x03
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line.long 0x00 "PWD_CURR_35C,Power Down Current Control 35C Register"
|
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
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hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
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group.long 0x3A4++0x03
|
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line.long 0x00 "PWD_CURR_50C,Power Down Current Control 50C Register"
|
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
|
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
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hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
|
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group.long 0x3A8++0x03
|
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line.long 0x00 "PWD_CURR_65C,Power Down Current Control 65C Register"
|
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
|
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
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hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
|
|
group.long 0x3AC++0x03
|
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line.long 0x00 "PWD_CURR_80C,Power Down Current Control 80C Register"
|
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
|
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
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hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
|
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group.long 0x3B0++0x03
|
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line.long 0x00 "PWD_CURR_95C,Power Down Current Control 95C Register"
|
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
|
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
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hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
|
|
group.long 0x3B4++0x03
|
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line.long 0x00 "PWD_CURR_110C,Power Down Current Control 110C Register"
|
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hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
|
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hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
|
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group.long 0x3B8++0x03
|
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line.long 0x00 "PWD_CURR_125C,Power Down Current Control 125C Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DELTA_CACHE_REF ,Additional maximum current, in units of 1uA, with cache retention"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DELTA_RFMEM_RET ,Additional maximum current, in 1uA units, with RF memory retention"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DELTA_XOSC_LPM ,Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASELINE ,Worst-case baseline maximum powerdown current, in units of 0.5uA"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CRYPTO (Cryptography)"
|
|
base ad:0x40024000
|
|
width 15.
|
|
tree "DMA registers"
|
|
group.long 0x00++0x07
|
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line.long 0x00 "DMACH0CTL,DMA Channel 0 Control Register"
|
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bitfld.long 0x00 1. " PRIO ,Channel priority" "Low,High"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMACH0EXTADDR,DMA Channel 0 External Address Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMACH0LEN,DMA Channel 0 Length Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEN ,DMA transfer length"
|
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rgroup.long 0x18++0x03
|
|
line.long 0x00 "DMASTAT,DMA Controller Status Register"
|
|
bitfld.long 0x00 17. " PORT_ERR ,Transfer error on AHB bus" "No error,Error"
|
|
bitfld.long 0x00 1. " CH1_ACTIVE ,DMA channel 1 active" "Not active,Active"
|
|
bitfld.long 0x00 0. " CH0_ACTIVE ,DMA channel 0 active" "Not active,Active"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DMASWRESET,DMA Controller Software Reset Register"
|
|
bitfld.long 0x00 0. " RESET ,Software reset enable" "Disabled,Enabled"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DMACH1CTL,DMA Channel 1 Control Register"
|
|
bitfld.long 0x00 1. " PRIO ,Channel priority" "Low,High"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMACH1EXTADDR,DMA Channel 1 External Address Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMACH1LEN,DMA Channel 1 Length Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEN ,DMA transfer length"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DMABUSCFG,DMA Controller Master Configuration Register"
|
|
bitfld.long 0x00 12.--15. " AHB_MST1_BURST_SIZE ,AHB bus maximum burst size" ",,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,?..."
|
|
bitfld.long 0x00 11. " AHB_MST1_IDLE_EN ,Idle transfer insertion between AHB burst transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " AHB_MST1_INCR_EN ,AHB transfer burst length type" "Unspecified length,Fixed length"
|
|
bitfld.long 0x00 9. " AHB_MST1_LOCK_EN ,AHB transfer lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AHB_MST1_BIGEND ,AHB master endianness" "Little endian,Big endian"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "DMAPORTERR,DMA Controller Port Error Register"
|
|
bitfld.long 0x00 12. " AHB_ERR ,AHB bus error" "No error,Error"
|
|
bitfld.long 0x00 9. " LAST_CH ,AHB master port last serviced channel" "Channel 0,Channel 1"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "DMAHWVER,DMA Controller Version Register"
|
|
bitfld.long 0x00 24.--27. " HW_MAJOR_VER ,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " HW_MINOR_VER ,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " HW_PATCH_LVL ,Patch level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VER_NUM_COMPL ,VER_NUM field bits Bit-by-bit complement"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VER_NUM ,DMA Controller version number"
|
|
group.long 0x700++0x07
|
|
line.long 0x00 "ALGSEL,Master Algorithm Select"
|
|
bitfld.long 0x00 31. " TAG ,DMA operations TAG include" "Not included,Included"
|
|
bitfld.long 0x00 1. " AES ,DMA AES data load select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " KEY_STORE ,DMA Key Store load select" "Not selected,Selected"
|
|
line.long 0x04 "DMAPROTCTL,Master Protection Control"
|
|
bitfld.long 0x04 0. " EN ,AHB transfer protection control for DMA transfers using the key store area as destination" "USER,PRIVILEDGED"
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "SWRESET,Software Reset Register"
|
|
eventfld.long 0x00 0. " RESET ,Software Reset" "No effect,Reset"
|
|
tree.end
|
|
width 16.
|
|
tree "Key registers"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "KEYWRITEAREA,Key Write Area Register"
|
|
bitfld.long 0x00 7. " RAM_AREA[7] ,RAM area 7 write select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,RAM area 6 write select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,RAM area 5 write select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,RAM area 4 write select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,RAM area 3 write select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,RAM area 2 write select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,RAM area 1 write select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,RAM area 0 write select" "Not selected,Selected"
|
|
textline " "
|
|
line.long 0x04 "KEYWRITTENAREA,Key Written Area Register"
|
|
eventfld.long 0x04 7. " RAM_AREA_WRITTEN[7] ,RAM area 7 written status" "Not written,Written"
|
|
eventfld.long 0x04 6. " [6] ,RAM area 6 written status" "Not written,Written"
|
|
eventfld.long 0x04 5. " [5] ,RAM area 5 written status" "Not written,Written"
|
|
eventfld.long 0x04 4. " [4] ,RAM area 4 written status" "Not written,Written"
|
|
textline " "
|
|
eventfld.long 0x04 3. " [3] ,RAM area 3 written status" "Not written,Written"
|
|
eventfld.long 0x04 2. " [2] ,RAM area 2 written status" "Not written,Written"
|
|
eventfld.long 0x04 1. " [1] ,RAM area 1 written status" "Not written,Written"
|
|
eventfld.long 0x04 0. " [0] ,RAM area 0 written status" "Not written,Written"
|
|
textline " "
|
|
line.long 0x08 "KEYSIZE,Key Size Register"
|
|
bitfld.long 0x08 0.--1. " SIZE ,Key size" ",128 bits,?..."
|
|
line.long 0x0C "KEYREADAREA,Key Read Area Register"
|
|
rbitfld.long 0x0C 31. " BUSY ,Key store operation busy status flag" "Not busy,Busy"
|
|
bitfld.long 0x0C 0.--3. " RAM_AREA ,Key store RAM area read/write select" "RAM area 0,RAM area 1,RAM area 2,RAM area 3,RAM area 4,RAM area 5,RAM area 6,RAM area 7,No RAM,?..."
|
|
wgroup.long 0x500++0x0F
|
|
line.long 0x00 "AESKEY2_0,Clear AES KEY2/GHASH Register 0"
|
|
line.long 0x04 "AESKEY2_1,Clear AES KEY2/GHASH Register 1"
|
|
line.long 0x08 "AESKEY2_2,Clear AES KEY2/GHASH Register 2"
|
|
line.long 0x0C "AESKEY2_3,Clear AES KEY2/GHASH Register 3"
|
|
wgroup.long 0x510++0x0F
|
|
line.long 0x00 "AESKEY3_0,Clear AES KEY3 Register 0"
|
|
line.long 0x04 "AESKEY3_1,Clear AES KEY3 Register 1"
|
|
line.long 0x08 "AESKEY3_2,Clear AES KEY3 Register 2"
|
|
line.long 0x0C "AESKEY3_3,Clear AES KEY3 Register 3"
|
|
group.long 0x540++0x0F
|
|
line.long 0x00 "AESIV_0,AES Initialization Vector 0"
|
|
line.long 0x04 "AESIV_1,AES Initialization Vector 1"
|
|
line.long 0x08 "AESIV_2,AES Initialization Vector 2"
|
|
line.long 0x0C "AESIV_3,AES Initialization Vector 3"
|
|
width 16.
|
|
if (((d.l(ad:0x40024000+0x550))&0x44)==0x44)
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "AESCTL,AES Input/Output Buffer Control Register"
|
|
rbitfld.long 0x00 31. " CONTEXT_RDY ,Context data registers overwrite ready" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " SAVED_CONTEXT_RDY ,AES auth TAG or IV blocks ready to retrieve" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " SAVE_CONTEXT ,Save context" "No effect,Save"
|
|
bitfld.long 0x00 22.--24. " CCM_M ,CCM operations authentication field length" "1,3,5,7,9,11,13,15"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " CCM_L ,CCM operations length field width" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 18. " CCM ,AES-CCM mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CBC_MAC ,MAC mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--8. " CTR_WIDTH ,AES-CTR counter width" "32 bits,64 bits,96 bits,128 bits"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CTR ,AES-CTR mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CBC ,CBC mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--4. " KEY_SIZE ,Key size" ",128 bits,?..."
|
|
bitfld.long 0x00 2. " DIR ,Direction" "Decryption,Encryption"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INPUT_RDY ,AES input buffer ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " OUTPUT_RDY ,AES output block ready" "Not ready,Ready"
|
|
elif (((d.l(ad:0x40024000+0x550))&0x44)==0x4)
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "AESCTL,AES Input/Output Buffer Control Register"
|
|
rbitfld.long 0x00 31. " CONTEXT_RDY ,Context data registers overwrite ready" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " SAVED_CONTEXT_RDY ,AES auth TAG or IV blocks ready to retrieve" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " SAVE_CONTEXT ,Save context" "No effect,Save"
|
|
bitfld.long 0x00 22.--24. " CCM_M ,CCM operations authentication field length" "1,3,5,7,9,11,13,15"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " CCM_L ,CCM operations length field width" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 18. " CCM ,AES-CCM mode enable" "Disabled,?..."
|
|
bitfld.long 0x00 15. " CBC_MAC ,MAC mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--8. " CTR_WIDTH ,AES-CTR counter width" "32 bits,64 bits,96 bits,128 bits"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CTR ,AES-CTR mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CBC ,CBC mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--4. " KEY_SIZE ,Key size" ",128 bits,?..."
|
|
bitfld.long 0x00 2. " DIR ,Direction" "Decryption,Encryption"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INPUT_RDY ,AES input buffer ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " OUTPUT_RDY ,AES output block ready" "Not ready,Ready"
|
|
elif (((d.l(ad:0x40024000+0x550))&0x44)==0x40)
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "AESCTL,AES Input/Output Buffer Control Register"
|
|
rbitfld.long 0x00 31. " CONTEXT_RDY ,Context data registers overwrite ready" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " SAVED_CONTEXT_RDY ,AES auth TAG or IV blocks ready to retrieve" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " SAVE_CONTEXT ,Save context" "No effect,Save"
|
|
bitfld.long 0x00 22.--24. " CCM_M ,CCM operations authentication field length" "1,3,5,7,9,11,13,15"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " CCM_L ,CCM operations length field width" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 18. " CCM ,AES-CCM mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CBC_MAC ,MAC mode enable" "Disabled,?..."
|
|
bitfld.long 0x00 7.--8. " CTR_WIDTH ,AES-CTR counter width" "32 bits,64 bits,96 bits,128 bits"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CTR ,AES-CTR mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CBC ,CBC mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--4. " KEY_SIZE ,Key size" ",128 bits,?..."
|
|
bitfld.long 0x00 2. " DIR ,Direction" "Decryption,Encryption"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INPUT_RDY ,AES input buffer ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " OUTPUT_RDY ,AES output block ready" "Not ready,Ready"
|
|
else
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "AESCTL,AES Input/Output Buffer Control Register"
|
|
rbitfld.long 0x00 31. " CONTEXT_RDY ,Context data registers overwrite ready" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " SAVED_CONTEXT_RDY ,AES auth TAG or IV blocks ready to retrieve" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " SAVE_CONTEXT ,Save context" "No effect,Save"
|
|
bitfld.long 0x00 22.--24. " CCM_M ,CCM operations authentication field length" "1,3,5,7,9,11,13,15"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " CCM_L ,CCM operations length field width" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 18. " CCM ,AES-CCM mode enable" "Disabled,?..."
|
|
bitfld.long 0x00 15. " CBC_MAC ,MAC mode enable" "Disabled,?..."
|
|
bitfld.long 0x00 7.--8. " CTR_WIDTH ,AES-CTR counter width" "32 bits,64 bits,96 bits,128 bits"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CTR ,AES-CTR mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CBC ,CBC mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--4. " KEY_SIZE ,Key size" ",128 bits,?..."
|
|
bitfld.long 0x00 2. " DIR ,Direction" "Decryption,Encryption"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INPUT_RDY ,AES input buffer ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " OUTPUT_RDY ,AES output block ready" "Not ready,Ready"
|
|
endif
|
|
wgroup.long 0x554++0x0B
|
|
line.long 0x00 "AESDATALEN0,Crypto Data Length LSW Register"
|
|
line.long 0x04 "AESDATALEN1,Crypto Data Length MSW Register"
|
|
hexmask.long 0x04 0.--28. 1. " LEN_MSW ,Combined data length [60:32]"
|
|
line.long 0x08 "AESAUTHLEN,AES Authentication Length Register"
|
|
tree.open "AES Data"
|
|
tree "AES Data Input"
|
|
rgroup.long 0x560++0x0F
|
|
line.long 0x00 "AESDATAOUT0,Data Output Register 0"
|
|
line.long 0x04 "AESDATAOUT1,Data Output Register 1"
|
|
line.long 0x08 "AESDATAOUT2,Data Output Register 2"
|
|
line.long 0x0C "AESDATAOUT3,Data Output Register 3"
|
|
tree.end
|
|
tree "AES Data Output"
|
|
wgroup.long 0x560++0x0F
|
|
line.long 0x00 "AESDATAIN0,Data input register 0"
|
|
line.long 0x04 "AESDATAIN1,Data input register 1"
|
|
line.long 0x08 "AESDATAIN2,Data input register 2"
|
|
line.long 0x0C "AESDATAIN3,Data input register 3"
|
|
tree.end
|
|
tree.end
|
|
textline ""
|
|
rgroup.long 0x570++0x0F
|
|
line.long 0x00 "AESTAGOUT0,AES Tag Output Register 0"
|
|
line.long 0x04 "AESTAGOUT1,AES Tag Output Register 1"
|
|
line.long 0x08 "AESTAGOUT2,AES Tag Output Register 2"
|
|
line.long 0x0C "AESTAGOUT3,AES Tag Output Register 3"
|
|
tree.end
|
|
width 9.
|
|
tree "Interrupt registers"
|
|
group.long 0x780++0x07
|
|
line.long 0x00 "IRQTYPE,Interrupt Configuration Register"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRQEN,Interrupt Enable Register"
|
|
bitfld.long 0x04 1. " DMA_IN_DONE ,DMA_IN_DONE interrupt source enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RESULT_AVAIL ,RESULT_AVAIL interrupt source enable" "Disabled,Enabled"
|
|
wgroup.long 0x788++0x03
|
|
line.long 0x00 "IRQCLR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " DMA_BUS_ERR ,DMA operation bus error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " KEY_ST_WR_ERR ,Key store memory DMA write error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " KEY_ST_RD_ERR ,Key store memory DMA read interrupt clear" "No effect,Clear"
|
|
group.long 0x790++0x03
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " DMA_BUS_ERR ,DMA operation bus error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " KEY_ST_WR_ERR ,Key store memory DMA write error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " KEY_ST_RD_ERR ,Key store memory DMA read interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DMA_IN_DONE_set/clr ,DMA data in done interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RESULT_AVAIL_set/clr ,Crypto peripheral result available interrupt flag" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 7.
|
|
tree "Hardware version registers"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "HWVER,CTRL Module Version Register"
|
|
bitfld.long 0x00 24.--27. " HW_MAJOR_VER ,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " HW_MINOR_VER ,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " HW_PATCH_LVL ,Patch level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VER_NUM_COMPL ,VER_NUM field bits Bit-by-bit complement"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VER_NUM ,Crypto peripheral version number"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I/O (Input/Output Control)"
|
|
tree "AON_IOC (Always On Input/Output Controller)"
|
|
base ad:0x40094000
|
|
width 11.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "IOSTRMIN,IO Drive Strength Minimum Register (Internal to be used through TI provided API)"
|
|
bitfld.long 0x00 0.--2. " GRAY_CODE ,GRAY_CODE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IOSTRMED,IO Drive Strength Medium Register (Internal to be used through TI provided API)"
|
|
bitfld.long 0x04 0.--2. " GRAY_CODE ,GRAY_CODE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "IOSTRMAX,IO Drive Strength Maximum Register (Internal to be used through TI provided API)"
|
|
bitfld.long 0x08 0.--2. " GRAY_CODE ,GRAY_CODE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "IOCLATCH,IO Latch Control Register"
|
|
bitfld.long 0x0C 0. " EN ,IO latch enable" "Enabled,Disabled"
|
|
line.long 0x10 "CLK32KCTL,SCLK_LF External Output Control Register"
|
|
bitfld.long 0x10 0. " OE_N ,External clock output enable active" "Active,Not active"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IOC (Input/Output Controller)"
|
|
base ad:0x40081000
|
|
width 9.
|
|
if ((((d.l(ad:0x40081000+0x0))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x0))&0x3F)>0x08))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "IOCFG0,Configuration of DIO0"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO0" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "IOCFG0,Configuration of DIO0"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO0" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x4))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x4))&0x3F)>0x08))
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "IOCFG1,Configuration of DIO1"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO1" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "IOCFG1,Configuration of DIO1"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO1" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x8))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x8))&0x3F)>0x08))
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "IOCFG2,Configuration of DIO2"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO2" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "IOCFG2,Configuration of DIO2"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO2" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0xC))&0x3F)==0x00)||(((d.l(ad:0x40081000+0xC))&0x3F)>0x08))
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "IOCFG3,Configuration of DIO3"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO3" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "IOCFG3,Configuration of DIO3"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO3" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x10))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x10))&0x3F)>0x08))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IOCFG4,Configuration of DIO4"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO4" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IOCFG4,Configuration of DIO4"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO4" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x14))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x14))&0x3F)>0x08))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IOCFG5,Configuration of DIO5"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO5" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IOCFG5,Configuration of DIO5"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO5" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x18))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x18))&0x3F)>0x08))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IOCFG6,Configuration of DIO6"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO6" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IOCFG6,Configuration of DIO6"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO6" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x1C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x1C))&0x3F)>0x08))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IOCFG7,Configuration of DIO7"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO7" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IOCFG7,Configuration of DIO7"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO7" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x20))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x20))&0x3F)>0x08))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IOCFG8,Configuration of DIO8"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO8" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IOCFG8,Configuration of DIO8"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO8" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x24))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x24))&0x3F)>0x08))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IOCFG9,Configuration of DIO9"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO9" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IOCFG9,Configuration of DIO9"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO9" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x28))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x28))&0x3F)>0x08))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IOCFG10,Configuration of DIO10"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO10" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IOCFG10,Configuration of DIO10"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO10" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x2C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x2C))&0x3F)>0x08))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IOCFG11,Configuration of DIO11"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO11" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IOCFG11,Configuration of DIO11"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO11" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x30))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x30))&0x3F)>0x08))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IOCFG12,Configuration of DIO12"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO12" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IOCFG12,Configuration of DIO12"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO12" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x34))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x34))&0x3F)>0x08))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IOCFG13,Configuration of DIO13"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO13" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IOCFG13,Configuration of DIO13"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO13" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x38))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x38))&0x3F)>0x08))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IOCFG14,Configuration of DIO14"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO14" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IOCFG14,Configuration of DIO14"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO14" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x3C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x3C))&0x3F)>0x08))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IOCFG15,Configuration of DIO15"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO15" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IOCFG15,Configuration of DIO15"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO15" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x40))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x40))&0x3F)>0x08))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IOCFG16,Configuration of DIO16"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO16" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IOCFG16,Configuration of DIO16"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO16" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x44))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x44))&0x3F)>0x08))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IOCFG17,Configuration of DIO17"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO17" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IOCFG17,Configuration of DIO17"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO17" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x48))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x48))&0x3F)>0x08))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IOCFG18,Configuration of DIO18"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO18" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IOCFG18,Configuration of DIO18"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO18" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x4C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x4C))&0x3F)>0x08))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IOCFG19,Configuration of DIO19"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO19" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IOCFG19,Configuration of DIO19"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO19" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x50))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x50))&0x3F)>0x08))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IOCFG20,Configuration of DIO20"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO20" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IOCFG20,Configuration of DIO20"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO20" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x54))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x54))&0x3F)>0x08))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "IOCFG21,Configuration of DIO21"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO21" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "IOCFG21,Configuration of DIO21"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO21" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x58))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x58))&0x3F)>0x08))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IOCFG22,Configuration of DIO22"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO22" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IOCFG22,Configuration of DIO22"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO22" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x5C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x5C))&0x3F)>0x08))
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IOCFG23,Configuration of DIO23"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO23" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IOCFG23,Configuration of DIO23"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO23" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x60))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x60))&0x3F)>0x08))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IOCFG24,Configuration of DIO24"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO24" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IOCFG24,Configuration of DIO24"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO24" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x64))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x64))&0x3F)>0x08))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "IOCFG25,Configuration of DIO25"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO25" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "IOCFG25,Configuration of DIO25"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO25" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x68))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x68))&0x3F)>0x08))
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IOCFG26,Configuration of DIO26"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO26" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IOCFG26,Configuration of DIO26"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO26" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x6C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x6C))&0x3F)>0x08))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "IOCFG27,Configuration of DIO27"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO27" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "IOCFG27,Configuration of DIO27"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO27" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x70))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x70))&0x3F)>0x08))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IOCFG28,Configuration of DIO28"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO28" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IOCFG28,Configuration of DIO28"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO28" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x74))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x74))&0x3F)>0x08))
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "IOCFG29,Configuration of DIO29"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO29" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "IOCFG29,Configuration of DIO29"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO29" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x78))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x78))&0x3F)>0x08))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "IOCFG30,Configuration of DIO30"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO30" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "IOCFG30,Configuration of DIO30"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO30" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
if ((((d.l(ad:0x40081000+0x7C))&0x3F)==0x00)||(((d.l(ad:0x40081000+0x7C))&0x3F)>0x08))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IOCFG31,Configuration of DIO31"
|
|
bitfld.long 0x00 30. " HYST_EN ,Input Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "No wakeup,No wakeup,Wakeup if Low,Wakeup if High"
|
|
bitfld.long 0x00 24.--26. " IOMODE ,IO Mode" "Normal,Inverted,,,Open Drain/Normal,Open Drain/Inverted,Open Source/Normal,Open Source/Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "None,Negative edge,Positive edge,Both edges"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO31" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IOCFG31,Configuration of DIO31"
|
|
bitfld.long 0x00 30. " HYST_EN ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE ,Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27.--28. " WU_CFG ,Wakeup Configuration" "Disabled,Disabled,Enabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EDGE_IRQ_EN ,Edge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EDGE_DET ,Enable generation of edge detection events on this IO" "No edge,Negative edge,Positive edge,Both edge"
|
|
bitfld.long 0x00 13.--14. " PULL_CTL ,Pull control" ",Down,Up,Disabled"
|
|
bitfld.long 0x00 12. " SLEW_RED ,Slew rate" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IOCURR ,Selects IO current in combination with IOSTR" "2 mA,4 mA,4 mA or 8mA,?..."
|
|
bitfld.long 0x00 8.--9. " IOSTR ,Select drive strength IO" "Automatic,Minimum,Medium,Maximum"
|
|
bitfld.long 0x00 0.--5. " PORT_ID ,Selects usage for DIO31" "GPIO,,,,,,,,AUX IO,SSI0_RX,SSI0_TX,SSI0_FSS,SSI0_CLK,I2C_MSSDA,I2C_MSSCL,UART0_RX,UART0_TX,UART0_CTS,UART0_RTS,,,,,PORT_EVENT0,PORT_EVENT1,PORT_EVENT2,PORT_EVENT3,PORT_EVENT4,PORT_EVENT5,PORT_EVENT6,PORT_EVENT7,,CPU_SWV,SSI1_RX,SSI1_TX,SSI1_FSS,SSI1_CLK,I2S_AD0,I2S_AD1,I2S_WCLK,I2S_BCLK,I2S_MCLK,,,,,RF Core Trace,RF Core Data Out 0,RF Core Data Out 1,RF Core Data Out 2,RF Core Data Out 3,RF Core Data In 0,RF Core Data In 1,RF Core SMI Data Link Out,RF Core SMI Data Link In,RF Core SMI Command Link Out,RF Core SMI Command Link In,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base ad:0x40022000
|
|
width 18.
|
|
wgroup.long 0x00++0x1F
|
|
line.long 0x00 "DOUT3_0,Data Out 0 to 3 Register"
|
|
bitfld.long 0x00 24. " DIO[3] ,Sets the state of the pin that is configured as DIO#3" "Low,High"
|
|
bitfld.long 0x00 16. " [2] ,Sets the state of the pin that is configured as DIO#2" "Low,High"
|
|
bitfld.long 0x00 8. " [1] ,Sets the state of the pin that is configured as DIO#1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Sets the state of the pin that is configured as DIO#0" "Low,High"
|
|
line.long 0x04 "DOUT7_4,Data Out 4 to 7 Register"
|
|
bitfld.long 0x04 24. " [7] ,Sets the state of the pin that is configured as DIO#7" "Low,High"
|
|
bitfld.long 0x04 16. " [6] ,Sets the state of the pin that is configured as DIO#6" "Low,High"
|
|
bitfld.long 0x04 8. " [5] ,Sets the state of the pin that is configured as DIO#5" "Low,High"
|
|
bitfld.long 0x04 0. " [4] ,Sets the state of the pin that is configured as DIO#4" "Low,High"
|
|
line.long 0x08 "DOUT11_8,Data Out 8 to 11 Register"
|
|
bitfld.long 0x08 24. " [11] ,Sets the state of the pin that is configured as DIO#11" "Low,High"
|
|
bitfld.long 0x08 16. " [10] ,Sets the state of the pin that is configured as DIO#10" "Low,High"
|
|
bitfld.long 0x08 8. " [9] ,Sets the state of the pin that is configured as DIO#9" "Low,High"
|
|
bitfld.long 0x08 0. " [8] ,Sets the state of the pin that is configured as DIO#8" "Low,High"
|
|
line.long 0x0C "DOUT15_12,Data Out 12 to 15 Register"
|
|
bitfld.long 0x0C 24. " [15] ,Sets the state of the pin that is configured as DIO#15" "Low,High"
|
|
bitfld.long 0x0C 16. " [14] ,Sets the state of the pin that is configured as DIO#14" "Low,High"
|
|
bitfld.long 0x0C 8. " [13] ,Sets the state of the pin that is configured as DIO#13" "Low,High"
|
|
bitfld.long 0x0C 0. " [12] ,Sets the state of the pin that is configured as DIO#12" "Low,High"
|
|
line.long 0x10 "DOUT19_16,Data Out 16 to 19 Register"
|
|
bitfld.long 0x10 24. " [19] ,Sets the state of the pin that is configured as DIO#19" "Low,High"
|
|
bitfld.long 0x10 16. " [18] ,Sets the state of the pin that is configured as DIO#18" "Low,High"
|
|
bitfld.long 0x10 8. " [17] ,Sets the state of the pin that is configured as DIO#17" "Low,High"
|
|
bitfld.long 0x10 0. " [16] ,Sets the state of the pin that is configured as DIO#16" "Low,High"
|
|
line.long 0x14 "DOUT23_20,Data Out 20 to 23 Register"
|
|
bitfld.long 0x14 24. " [23] ,Sets the state of the pin that is configured as DIO#23" "Low,High"
|
|
bitfld.long 0x14 16. " [22] ,Sets the state of the pin that is configured as DIO#22" "Low,High"
|
|
bitfld.long 0x14 8. " [21] ,Sets the state of the pin that is configured as DIO#21" "Low,High"
|
|
bitfld.long 0x14 0. " [20] ,Sets the state of the pin that is configured as DIO#20" "Low,High"
|
|
line.long 0x18 "DOUT27_24,Data Out 24 to 27 Register"
|
|
bitfld.long 0x18 24. " [27] ,Sets the state of the pin that is configured as DIO#27" "Low,High"
|
|
bitfld.long 0x18 16. " [26] ,Sets the state of the pin that is configured as DIO#26" "Low,High"
|
|
bitfld.long 0x18 8. " [25] ,Sets the state of the pin that is configured as DIO#25" "Low,High"
|
|
bitfld.long 0x18 0. " [24] ,Sets the state of the pin that is configured as DIO#24" "Low,High"
|
|
line.long 0x1C "DOUT28_31,Data Out 28 to 31 Register"
|
|
bitfld.long 0x1C 24. " [31] ,Sets the state of the pin that is configured as DIO#31" "Low,High"
|
|
bitfld.long 0x1C 16. " [30] ,Sets the state of the pin that is configured as DIO#30" "Low,High"
|
|
bitfld.long 0x1C 8. " [29] ,Sets the state of the pin that is configured as DIO#29" "Low,High"
|
|
bitfld.long 0x1C 0. " [28] ,Sets the state of the pin that is configured as DIO#28" "Low,High"
|
|
textline ""
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DOUT31_0_set/clr,Data Output for DIO 0 to 31 Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x20 31. " DIO[31] ,Data output for DIO 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x20 30. " [30] ,Data output for DIO 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x20 29. " [29] ,Data output for DIO 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x20 28. " [28] ,Data output for DIO 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x20 27. " [27] ,Data output for DIO 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x20 26. " [26] ,Data output for DIO 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x20 25. " [25] ,Data output for DIO 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x20 24. " [24] ,Data output for DIO 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x20 23. " [23] ,Data output for DIO 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x20 22. " [22] ,Data output for DIO 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x20 21. " [21] ,Data output for DIO 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x20 20. " [20] ,Data output for DIO 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x20 19. " [19] ,Data output for DIO 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x20 18. " [18] ,Data output for DIO 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x10 17. 0x20 17. " [17] ,Data output for DIO 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x20 16. " [16] ,Data output for DIO 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x20 15. " [15] ,Data output for DIO 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x20 14. " [14] ,Data output for DIO 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x20 13. " [13] ,Data output for DIO 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x20 12. " [12] ,Data output for DIO 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x20 11. " [11] ,Data output for DIO 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x20 10. " [10] ,Data output for DIO 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x20 9. " [9] ,Data output for DIO 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x20 8. " [8] ,Data output for DIO 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x20 7. " [7] ,Data output for DIO 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x20 6. " [6] ,Data output for DIO 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x20 5. " [5] ,Data output for DIO 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x20 4. " [4] ,Data output for DIO 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x20 3. " [3] ,Data output for DIO 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x20 2. " [2] ,Data output for DIO 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x20 1. " [1] ,Data output for DIO 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x20 0. " [0] ,Data output for DIO 0" "Low,High"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DOUTTGL31_0,Data Out Toggle for DIO 0 to 31 Register"
|
|
bitfld.long 0x00 31. " DIO[31] ,Invert the DIO31 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 30. " [30] ,Invert the DIO30 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 29. " [29] ,Invert the DIO29 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 28. " [28] ,Invert the DIO28 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Invert the DIO27 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 26. " [26] ,Invert the DIO26 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 25. " [25] ,Invert the DIO25 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 24. " [24] ,Invert the DIO24 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Invert the DIO23 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " [22] ,Invert the DIO22 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 21. " [21] ,Invert the DIO21 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 20. " [20] ,Invert the DIO20 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Invert the DIO19 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 18. " [18] ,Invert the DIO18 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " [17] ,Invert the DIO17 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " [16] ,Invert the DIO16 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Invert the DIO15 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " [14] ,Invert the DIO14 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " [13] ,Invert the DIO13 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " [12] ,Invert the DIO12 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Invert the DIO11 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " [10] ,Invert the DIO10 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 9. " [9] ,Invert the DIO9 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " [8] ,Invert the DIO8 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Invert the DIO7 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 6. " [6] ,Invert the DIO6 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " [5] ,Invert the DIO5 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " [4] ,Invert the DIO4 output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Invert the DIO3 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " [2] ,Invert the DIO2 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 1. " [1] ,Invert the DIO1 output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " [0] ,Invert the DIO0 output" "Not inverted,Inverted"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "DIN31_0,Data Input from DIO 0 to 31 Register"
|
|
bitfld.long 0x00 31. " DIO[31] ,Data Input from DIO31" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Data Input from DIO30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Data Input from DIO29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Data Input from DIO28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Data Input from DIO27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Data Input from DIO26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Data Input from DIO25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Data Input from DIO24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Data Input from DIO23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Data Input from DIO22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Data Input from DIO21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Data Input from DIO20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Data Input from DIO19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Data Input from DIO18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Data Input from DIO17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Data Input from DIO16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Data Input from DIO15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Data Input from DIO14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Data Input from DIO13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Data Input from DIO12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Data Input from DIO11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Data Input from DIO10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Data Input from DIO9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Data Input from DIO8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Data Input from DIO7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Data Input from DIO6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Data Input from DIO5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Data Input from DIO4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Data Input from DIO3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Data Input from DIO2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Data Input from DIO1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Data Input from DIO0" "Low,High"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DOE31_0,Data Output Enable for DIO 0 to 31 Register"
|
|
bitfld.long 0x00 31. " DIO[31] ,Data Output Enable DIO31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Data Output Enable DIO30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Data Output Enable DIO29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Data Output Enable DIO28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Data Output Enable DIO27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Data Output Enable DIO26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Data Output Enable DIO25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Data Output Enable DIO24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Data Output Enable DIO23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Data Output Enable DIO22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Data Output Enable DIO21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Data Output Enable DIO20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Data Output Enable DIO19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Data Output Enable DIO18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Data Output Enable DIO17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Data Output Enable DIO16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Data Output Enable DIO15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Data Output Enable DIO14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Data Output Enable DIO13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Data Output Enable DIO12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Data Output Enable DIO11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Data Output Enable DIO10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Data Output Enable DIO9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Data Output Enable DIO8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Data Output Enable DIO7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Data Output Enable DIO6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Data Output Enable DIO5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Data Output Enable DIO4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Data Output Enable DIO3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Data Output Enable DIO2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Data Output Enable DIO1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Data Output Enable DIO0" "Disabled,Enabled"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "EVFLAGS31_0,Event Register for DIO 0 to 31"
|
|
eventfld.long 0x00 30. " DIO[31] ,Event for DIO31" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " [30] ,Event for DIO30" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " [29] ,Event for DIO29" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " [28] ,Event for DIO28" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Event for DIO27" "Not occurred,Occurred"
|
|
eventfld.long 0x00 26. " [26] ,Event for DIO26" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " [25] ,Event for DIO25" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " [24] ,Event for DIO24" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Event for DIO23" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " [22] ,Event for DIO22" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " [21] ,Event for DIO21" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " [20] ,Event for DIO20" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Event for DIO19" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " [18] ,Event for DIO18" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " [17] ,Event for DIO17" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " [16] ,Event for DIO16" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Event for DIO15" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " [14] ,Event for DIO14" "Not occurred,Occurred"
|
|
eventfld.long 0x00 13. " [13] ,Event for DIO13" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " [12] ,Event for DIO12" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Event for DIO11" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " [10] ,Event for DIO10" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " [9] ,Event for DIO9" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " [8] ,Event for DIO8" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Event for DIO7" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " [6] ,Event for DIO6" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " [5] ,Event for DIO5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " [4] ,Event for DIO4" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Event for DIO3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " [2] ,Event for DIO2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Event for DIO1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " [0] ,Event for DIO0" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "uDMA (Micro Direct Memory Access)"
|
|
base ad:0x40020000
|
|
width 25.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 28.--31. " TEST ,Integration Test Logic" "Not included,Included,?..."
|
|
bitfld.long 0x00 16.--20. " TOTALCHANNELS ,Available uDMA Channels" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels,9 channels,10 channels,11 channels,12 channels,13 channels,14 channels,15 channels,16 channels,17 channels,18 channels,19 channels,20 channels,21 channels,22 channels,23 channels,24 channels,25 channels,26 channels,27 channels,28 channels,29 channels,30 channels,31 channels,32 channels"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE ,Control State Machine Status" "Idle,Reading channel controller data,Reading source end pointer,Reading destination end pointer,Reading source data,Writing destination data,Waiting for uDMA request to clear,Writing channel controller data,Stalled,Done,Peripheral scatter-gather transition,?..."
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|
textline " "
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bitfld.long 0x00 0. " MASTERENABLE ,Controller Master Enable Status" "Disabled,Enabled"
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|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
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|
bitfld.long 0x00 7. " PRTOCTRL3 ,Protocol protection HProt3 (cacheable access)" "Low,High"
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|
bitfld.long 0x00 6. " PRTOCTRL2 ,Protocol protection HProt2 (bufferable access)" "Low,High"
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|
textline " "
|
|
bitfld.long 0x00 5. " PRTOCTRL1 ,Protocol protection HProt1 (privileged access)" "Low,High"
|
|
bitfld.long 0x00 0. " MASTERENABLE ,Controller Master Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,Channel Control Data Base Pointer Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x4 " BASEPTR ,Point to the base address"
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|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ALTCTRL,Channel Alternate Control Data Base Pointer Register"
|
|
textline ""
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|
rgroup.long 0x10++0x03
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|
line.long 0x00 "WAITONREQ,Channel Wait On Request Status Register"
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|
bitfld.long 0x00 31. " CHNLSTATUS[31] ,Channel [31] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 30. " [30] ,Channel [30] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 29. " [29] ,Channel [29] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 28. " [28] ,Channel [28] wait on request status" "Not waiting,Waiting"
|
|
textline " "
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|
bitfld.long 0x00 27. " [27] ,Channel [27] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 26. " [26] ,Channel [26] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 25. " [25] ,Channel [25] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 24. " [24] ,Channel [24] wait on request status" "Not waiting,Waiting"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel [23] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 22. " [22] ,Channel [22] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] wait on request status" "Not waiting,Waiting"
|
|
textline " "
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|
bitfld.long 0x00 19. " [19] ,Channel [19] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 18. " [18] ,Channel [18] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] wait on request status" "Not waiting,Waiting"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 14. " [14] ,Channel [14] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] wait on request status" "Not waiting,Waiting"
|
|
textline " "
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|
bitfld.long 0x00 11. " [11] ,Channel [11] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 10. " [10] ,Channel [10] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] wait on request status" "Not waiting,Waiting"
|
|
textline " "
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|
bitfld.long 0x00 7. " [7] ,Channel [7] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 6. " [6] ,Channel [6] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] wait on request status" "Not waiting,Waiting"
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|
bitfld.long 0x00 4. " [4] ,Channel [4] wait on request status" "Not waiting,Waiting"
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|
textline " "
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|
bitfld.long 0x00 3. " [3] ,Channel [3] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] wait on request status" "Not waiting,Waiting"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] wait on request status" "Not waiting,Waiting"
|
|
textline ""
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "SOFTREQ,Channel Software Request Register"
|
|
bitfld.long 0x00 31. " CHNLS[31] ,Channel [31] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 30. " [30] ,Channel [30] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 29. " [29] ,Channel [29] Software Request" "Do not generate,Generate"
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|
bitfld.long 0x00 28. " [28] ,Channel [28] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel [27] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 26. " [26] ,Channel [26] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 25. " [25] ,Channel [25] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 24. " [24] ,Channel [24] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel [23] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] Software Request" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] Software Request" "Do not generate,Generate"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] Software Request" "Do not generate,Generate"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SETBURST_set/clr,Channel Set/clear UseBurst Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CHNLS[31] ,Channel [31] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Channel [30] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Channel [29] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Channel [28] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Channel [27] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Channel [26] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Channel [25] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Channel [24] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Channel [23] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Channel [22] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Channel [21] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Channel [20] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Channel [19] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Channel [18] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Channel [17] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Channel [16] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Channel [15] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Channel [14] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Channel [13] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Channel [12] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Channel [11] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Channel [10] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Channel [9] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Channel [8] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Channel [7] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Channel [6] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Channel [5] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Channel [4] Useburst" "Single or Burst Request,Burst Request"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Channel [3] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Channel [2] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Channel [1] Useburst" "Single or Burst Request,Burst Request"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Channel [0] Useburst" "Single or Burst Request,Burst Request"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SETREQMASK_set/clr,Channel Set/Clear Request Mask Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CHNLS[31] ,Burst and single request mask status for channel [31]" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Burst and single request mask status for channel [30]" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Burst and single request mask status for channel [29]" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Burst and single request mask status for channel [28]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Burst and single request mask status for channel [27]" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Burst and single request mask status for channel [26]" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Burst and single request mask status for channel [25]" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Burst and single request mask status for channel [24]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Burst and single request mask status for channel [23]" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Burst and single request mask status for channel [22]" "Not masked,Masked"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Burst and single request mask status for channel [21]" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Burst and single request mask status for channel [20]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Burst and single request mask status for channel [19]" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Burst and single request mask status for channel [18]" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Burst and single request mask status for channel [17]" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Burst and single request mask status for channel [16]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Burst and single request mask status for channel [15]" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Burst and single request mask status for channel [14]" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Burst and single request mask status for channel [13]" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Burst and single request mask status for channel [12]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Burst and single request mask status for channel [11]" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Burst and single request mask status for channel [10]" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Burst and single request mask status for channel [9]" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Burst and single request mask status for channel [8]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Burst and single request mask status for channel [7]" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Burst and single request mask status for channel [6]" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Burst and single request mask status for channel [5]" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Burst and single request mask status for channel [4]" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Burst and single request mask status for channel [3]" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Burst and single request mask status for channel [2]" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Burst and single request mask status for channel [1]" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Burst and single request mask status for channel [0]" "Not masked,Masked"
|
|
textline ""
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SETCHANNELEN_set/clr,Set/Clear Channel Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CHNLS[31] ,Channel [31] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Channel [30] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Channel [29] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Channel [28] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Channel [27] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Channel [26] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Channel [25] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Channel [24] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Channel [23] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Channel [22] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Channel [21] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Channel [20] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Channel [19] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Channel [18] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Channel [17] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Channel [16] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Channel [15] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Channel [14] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Channel [13] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Channel [12] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Channel [11] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Channel [10] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Channel [9] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Channel [8] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Channel [7] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Channel [6] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Channel [5] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Channel [4] Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Channel [3] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Channel [2] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Channel [1] Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Channel [0] Enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SETCHNLPRIALT_set/clr,Channel Set/Clear Primary Alternate Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CHNLS[31] ,Channel [31] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Channel [30] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Channel [29] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Channel [28] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Channel [27] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Channel [26] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Channel [25] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Channel [24] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Channel [23] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Channel [22] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Channel [21] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Channel [20] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Channel [19] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Channel [18] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Channel [17] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Channel [16] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Channel [15] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Channel [14] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Channel [13] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Channel [12] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Channel [11] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Channel [10] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Channel [9] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Channel [8] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Channel [7] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Channel [6] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Channel [5] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Channel [4] control data structure" "Primary,Alternate"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Channel [3] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Channel [2] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Channel [1] control data structure" "Primary,Alternate"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Channel [0] control data structure" "Primary,Alternate"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SETCHNLPRIORITY_set/clr,Set/Clear Channel Priority Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CHNLS[31] ,Channel [31] Priority" "Default,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Channel [30] Priority" "Default,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Channel [29] Priority" "Default,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Channel [28] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Channel [27] Priority" "Default,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Channel [26] Priority" "Default,High"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Channel [25] Priority" "Default,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Channel [24] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Channel [23] Priority" "Default,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Channel [22] Priority" "Default,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Channel [21] Priority" "Default,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Channel [20] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Channel [19] Priority" "Default,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Channel [18] Priority" "Default,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Channel [17] Priority" "Default,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Channel [16] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Channel [15] Priority" "Default,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Channel [14] Priority" "Default,High"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Channel [13] Priority" "Default,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Channel [12] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Channel [11] Priority" "Default,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Channel [10] Priority" "Default,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Channel [9] Priority" "Default,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Channel [8] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Channel [7] Priority" "Default,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Channel [6] Priority" "Default,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Channel [5] Priority" "Default,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Channel [4] Priority" "Default,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Channel [3] Priority" "Default,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Channel [2] Priority" "Default,High"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Channel [1] Priority" "Default,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Channel [0] Priority" "Default,High"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ERROR,Error Status and Clear Register"
|
|
eventfld.long 0x00 0. " STATUS ,Status of bus error flag" "No error,Error"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "REQDONE,Channel Request Done Register"
|
|
eventfld.long 0x00 31. " CHNLS[31] ,Channel [31] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 30. " [30] ,Channel [30] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 29. " [29] ,Channel [29] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 28. " [28] ,Channel [28] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Channel [27] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 26. " [26] ,Channel [26] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 25. " [25] ,Channel [25] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 24. " [24] ,Channel [24] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,Channel [23] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 22. " [22] ,Channel [22] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 21. " [21] ,Channel [21] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 20. " [20] ,Channel [20] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Channel [19] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 18. " [18] ,Channel [18] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " [17] ,Channel [17] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 16. " [16] ,Channel [16] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,Channel [15] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 14. " [14] ,Channel [14] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 13. " [13] ,Channel [13] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 12. " [12] ,Channel [12] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Channel [11] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 10. " [10] ,Channel [10] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 9. " [9] ,Channel [9] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 8. " [8] ,Channel [8] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Channel [7] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 6. " [6] ,Channel [6] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " [5] ,Channel [5] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 4. " [4] ,Channel [4] uDMA done status" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Channel [3] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " [2] ,Channel [2] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 1. " [1] ,Channel [1] uDMA done status" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " [0] ,Channel [0] uDMA done status" "Not completed,Completed"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "DONEMASK,Channel Request Done Mask Register"
|
|
bitfld.long 0x00 31. " CHNLS[31] ,Channel [31] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Channel [30] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Channel [29] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " [28] ,Channel [28] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel [27] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Channel [26] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " [25] ,Channel [25] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Channel [24] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel [23] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " [22] ,Channel [22] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Channel [21] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Channel [20] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel [19] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Channel [18] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Channel [17] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " [16] ,Channel [16] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel [15] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Channel [14] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Channel [13] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Channel [12] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel [11] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Channel [10] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Channel [9] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Channel [8] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel [7] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Channel [6] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Channel [5] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Channel [4] Request Done Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel [3] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Channel [2] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Channel [1] Request Done Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Channel [0] Request Done Mask" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "GPT (General-Purpose Timers)"
|
|
tree "Timer 0"
|
|
base ad:0x40010000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
|
|
bitfld.long 0x00 0.--2. " CFG ,GPT Configuration" "32 bit timer,32 bit real-time,,,16 bit timer,?..."
|
|
if (((d.l(ad:0x40010000+0x04))&0x0B)==0x0A)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40010000+0x04))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40010000+0x04))&0x0B)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
if (((d.l(ad:0x40010000+0x08))&0x0B)==0x0A)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40010000+0x08))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40010000+0x08))&0x0B)==0x02)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 14. " TBPWML ,GPT Timer B PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--11. " TBEVENT ,GPT Timer B Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 9. " TBSTALL ,GPT Timer B Stall Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBEN ,GPT Timer B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAPWML ,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " RTCEN ,GPT RTC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TAEVENT ,GPT Timer A Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 1. " TASTALL ,GPT Timer A Stall Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TAEN ,GPT Timer A Enable" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SYNC,Synch Register"
|
|
bitfld.long 0x00 6.--7. " SYNC3 ,Synchronize GPT Timer 3" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 4.--5. " SYNC2 ,Synchronize GPT Timer 2" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 2.--3. " SYNC1 ,Synchronize GPT Timer 1" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 0.--1. " SYNC0 ,Synchronize GPT Timer 0" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 16. " WUMIS ,GPT Write Update Error interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " DMABIM ,GPT Timer B DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TBMIM ,GPT Timer B Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " CBEIM ,GPT Timer B Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMIM ,GPT Timer B Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TBTOIM ,GPT Timer B Time-out interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " DMAAIM ,GPT Timer A DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " TAMIM ,GPT Timer A Match interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCIM ,GPT RTC interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " CAEIM ,GPT Timer A Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CAMIM ,GPT Timer A Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TATOIM ,GPT Timer A Time-out interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 16. " WURIS ,GPT Write Update Error Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " DMABRIS ,GPT Timer B DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TBMRIS ,GPT Timer B Match Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CBERIS ,GPT Timer B Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMRIS ,GPT Timer B Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TBTORIS ,GPT Timer B Time-out Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " DMAARIS ,GPT Timer A DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " TAMRIS ,GPT Timer A Match Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCRIS ,GPT RTC Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAERIS ,GPT Timer A Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAMRIS ,GPT Timer A Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " TATORIS ,GPT Timer A Time-out Raw interrupt" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 16. " WUMIS ,GPT Write Update Error Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 13. " DMABMIS ,GPT Timer B DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 11. " TBMMIS ,GPT Timer B Match Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 10. " CBEMIS ,GPT Timer B Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CBMMIS ,GPT Timer B Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 8. " TBTOMIS ,GPT Timer B Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 5. " DMAAMIS ,GPT Timer A DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 4. " TAMMIS ,GPT Timer A Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RTCMIS ,GPT RTC Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 2. " CAEMIS ,GPT Timer A Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 1. " CAMMIS ,GPT Timer A Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 0. " TATOMIS ,GPT Timer A Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline ""
|
|
group.long 0x24++0x23
|
|
line.long 0x00 "ICLR,Interrupt Clear Register"
|
|
eventfld.long 0x00 16. " WUECINT ,GPT Write Update Error interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 13. " DMABINT ,GPT Timer B DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 11. " TBMCINT ,GPT Timer B Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CBECINT ,GPT Timer B Capture Mode Event interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 9. " CBMCINT ,GPT Timer B Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 8. " TBTOCINT ,GPT Timer B Time-out interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 5. " DMAAINT ,GPT Timer A DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 4. " TAMCINT ,GPT Timer A Match interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RTCCINT ,GPT RTC interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CAECINT ,GPT Timer A Capture Mode Event interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CAMCINT ,GPT Timer A Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 0. " TATOCINT ,GPT Timer A Time-out interrupt clear" "No effect,Clear"
|
|
line.long 0x04 "TAILR,Timer A Interval Load Register"
|
|
line.long 0x08 "TBILR,Timer B Interval Load Register"
|
|
line.long 0x0C "TAMATCHR,Timer A Match Register"
|
|
line.long 0x10 "TBMATCHR,Timer B Match Register"
|
|
line.long 0x14 "TAPR,Timer A Pre-scale Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " TAPSR ,Timer A Pre-scale"
|
|
line.long 0x18 "TBPR,Timer B Pre-scale Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " TBPSR ,Timer B Pre-scale"
|
|
line.long 0x1C "TAPMR,Timer A Pre-scale Match Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " TAPSMR ,Timer A Pre-scale Match"
|
|
line.long 0x20 "TBPMR,Timer B Pre-scale Match Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " TBPSMR ,Timer B Pre-scale Match"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "TAR,Timer A Register"
|
|
line.long 0x04 "TBR,Timer B Register"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "TAV,Timer A Value Register"
|
|
line.long 0x04 "TBV,Timer B Value Register"
|
|
rgroup.long 0x58++0x13
|
|
line.long 0x00 "RTCPD,RTC Pre-divide Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTCPD ,GPT RTC Pre-divider"
|
|
line.long 0x04 "TAPS,Timer A Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x08 "TBPS,Timer B Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x0C "TAPV,Timer A Pre-scale Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PSV ,GPT Timer A Pre-scaler Value"
|
|
line.long 0x10 "TBPV,Timer B Pre-scale Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " PSV ,GPT Timer B Pre-scaler Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DMAEV,DMA Event Register"
|
|
bitfld.long 0x00 11. " TBMDMAEN ,GPT Timer B Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CBEDMAEN ,GPT Timer B Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CBMDMAEN ,GPT Timer B Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBTODMAEN ,GPT Timer B Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TAMDMAEN ,GPT Timer A Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RTCDMAEN ,GPT RTC Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAEDMAEN ,GPT Timer A Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAMDMAEN ,GPT Timer A Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TATODMAEN ,GPT Timer A Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "VERSION,Peripheral Version Register"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "ANDCCP,Combined CCP Output Register"
|
|
bitfld.long 0x00 0. " CCP_AND_EN ,CPP output AND operation for timer A and B Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 1"
|
|
base ad:0x40011000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
|
|
bitfld.long 0x00 0.--2. " CFG ,GPT Configuration" "32 bit timer,32 bit real-time,,,16 bit timer,?..."
|
|
if (((d.l(ad:0x40011000+0x04))&0x0B)==0x0A)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40011000+0x04))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40011000+0x04))&0x0B)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
if (((d.l(ad:0x40011000+0x08))&0x0B)==0x0A)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40011000+0x08))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40011000+0x08))&0x0B)==0x02)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 14. " TBPWML ,GPT Timer B PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--11. " TBEVENT ,GPT Timer B Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 9. " TBSTALL ,GPT Timer B Stall Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBEN ,GPT Timer B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAPWML ,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " RTCEN ,GPT RTC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TAEVENT ,GPT Timer A Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 1. " TASTALL ,GPT Timer A Stall Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TAEN ,GPT Timer A Enable" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SYNC,Synch Register"
|
|
bitfld.long 0x00 6.--7. " SYNC3 ,Synchronize GPT Timer 3" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 4.--5. " SYNC2 ,Synchronize GPT Timer 2" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 2.--3. " SYNC1 ,Synchronize GPT Timer 1" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 0.--1. " SYNC0 ,Synchronize GPT Timer 0" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 16. " WUMIS ,GPT Write Update Error interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " DMABIM ,GPT Timer B DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TBMIM ,GPT Timer B Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " CBEIM ,GPT Timer B Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMIM ,GPT Timer B Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TBTOIM ,GPT Timer B Time-out interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " DMAAIM ,GPT Timer A DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " TAMIM ,GPT Timer A Match interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCIM ,GPT RTC interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " CAEIM ,GPT Timer A Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CAMIM ,GPT Timer A Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TATOIM ,GPT Timer A Time-out interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 16. " WURIS ,GPT Write Update Error Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " DMABRIS ,GPT Timer B DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TBMRIS ,GPT Timer B Match Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CBERIS ,GPT Timer B Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMRIS ,GPT Timer B Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TBTORIS ,GPT Timer B Time-out Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " DMAARIS ,GPT Timer A DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " TAMRIS ,GPT Timer A Match Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCRIS ,GPT RTC Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAERIS ,GPT Timer A Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAMRIS ,GPT Timer A Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " TATORIS ,GPT Timer A Time-out Raw interrupt" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 16. " WUMIS ,GPT Write Update Error Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 13. " DMABMIS ,GPT Timer B DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 11. " TBMMIS ,GPT Timer B Match Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 10. " CBEMIS ,GPT Timer B Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CBMMIS ,GPT Timer B Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 8. " TBTOMIS ,GPT Timer B Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 5. " DMAAMIS ,GPT Timer A DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 4. " TAMMIS ,GPT Timer A Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RTCMIS ,GPT RTC Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 2. " CAEMIS ,GPT Timer A Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 1. " CAMMIS ,GPT Timer A Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 0. " TATOMIS ,GPT Timer A Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline ""
|
|
group.long 0x24++0x23
|
|
line.long 0x00 "ICLR,Interrupt Clear Register"
|
|
eventfld.long 0x00 16. " WUECINT ,GPT Write Update Error interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 13. " DMABINT ,GPT Timer B DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 11. " TBMCINT ,GPT Timer B Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CBECINT ,GPT Timer B Capture Mode Event interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 9. " CBMCINT ,GPT Timer B Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 8. " TBTOCINT ,GPT Timer B Time-out interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 5. " DMAAINT ,GPT Timer A DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 4. " TAMCINT ,GPT Timer A Match interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RTCCINT ,GPT RTC interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CAECINT ,GPT Timer A Capture Mode Event interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CAMCINT ,GPT Timer A Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 0. " TATOCINT ,GPT Timer A Time-out interrupt clear" "No effect,Clear"
|
|
line.long 0x04 "TAILR,Timer A Interval Load Register"
|
|
line.long 0x08 "TBILR,Timer B Interval Load Register"
|
|
line.long 0x0C "TAMATCHR,Timer A Match Register"
|
|
line.long 0x10 "TBMATCHR,Timer B Match Register"
|
|
line.long 0x14 "TAPR,Timer A Pre-scale Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " TAPSR ,Timer A Pre-scale"
|
|
line.long 0x18 "TBPR,Timer B Pre-scale Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " TBPSR ,Timer B Pre-scale"
|
|
line.long 0x1C "TAPMR,Timer A Pre-scale Match Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " TAPSMR ,Timer A Pre-scale Match"
|
|
line.long 0x20 "TBPMR,Timer B Pre-scale Match Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " TBPSMR ,Timer B Pre-scale Match"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "TAR,Timer A Register"
|
|
line.long 0x04 "TBR,Timer B Register"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "TAV,Timer A Value Register"
|
|
line.long 0x04 "TBV,Timer B Value Register"
|
|
rgroup.long 0x58++0x13
|
|
line.long 0x00 "RTCPD,RTC Pre-divide Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTCPD ,GPT RTC Pre-divider"
|
|
line.long 0x04 "TAPS,Timer A Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x08 "TBPS,Timer B Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x0C "TAPV,Timer A Pre-scale Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PSV ,GPT Timer A Pre-scaler Value"
|
|
line.long 0x10 "TBPV,Timer B Pre-scale Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " PSV ,GPT Timer B Pre-scaler Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DMAEV,DMA Event Register"
|
|
bitfld.long 0x00 11. " TBMDMAEN ,GPT Timer B Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CBEDMAEN ,GPT Timer B Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CBMDMAEN ,GPT Timer B Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBTODMAEN ,GPT Timer B Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TAMDMAEN ,GPT Timer A Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RTCDMAEN ,GPT RTC Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAEDMAEN ,GPT Timer A Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAMDMAEN ,GPT Timer A Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TATODMAEN ,GPT Timer A Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "VERSION,Peripheral Version Register"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "ANDCCP,Combined CCP Output Register"
|
|
bitfld.long 0x00 0. " CCP_AND_EN ,CPP output AND operation for timer A and B Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 2"
|
|
base ad:0x40012000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
|
|
bitfld.long 0x00 0.--2. " CFG ,GPT Configuration" "32 bit timer,32 bit real-time,,,16 bit timer,?..."
|
|
if (((d.l(ad:0x40012000+0x04))&0x0B)==0x0A)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40012000+0x04))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40012000+0x04))&0x0B)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
if (((d.l(ad:0x40012000+0x08))&0x0B)==0x0A)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40012000+0x08))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40012000+0x08))&0x0B)==0x02)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 14. " TBPWML ,GPT Timer B PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--11. " TBEVENT ,GPT Timer B Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 9. " TBSTALL ,GPT Timer B Stall Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBEN ,GPT Timer B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAPWML ,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " RTCEN ,GPT RTC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TAEVENT ,GPT Timer A Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 1. " TASTALL ,GPT Timer A Stall Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TAEN ,GPT Timer A Enable" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SYNC,Synch Register"
|
|
bitfld.long 0x00 6.--7. " SYNC3 ,Synchronize GPT Timer 3" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 4.--5. " SYNC2 ,Synchronize GPT Timer 2" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 2.--3. " SYNC1 ,Synchronize GPT Timer 1" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 0.--1. " SYNC0 ,Synchronize GPT Timer 0" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 16. " WUMIS ,GPT Write Update Error interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " DMABIM ,GPT Timer B DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TBMIM ,GPT Timer B Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " CBEIM ,GPT Timer B Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMIM ,GPT Timer B Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TBTOIM ,GPT Timer B Time-out interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " DMAAIM ,GPT Timer A DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " TAMIM ,GPT Timer A Match interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCIM ,GPT RTC interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " CAEIM ,GPT Timer A Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CAMIM ,GPT Timer A Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TATOIM ,GPT Timer A Time-out interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 16. " WURIS ,GPT Write Update Error Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " DMABRIS ,GPT Timer B DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TBMRIS ,GPT Timer B Match Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CBERIS ,GPT Timer B Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMRIS ,GPT Timer B Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TBTORIS ,GPT Timer B Time-out Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " DMAARIS ,GPT Timer A DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " TAMRIS ,GPT Timer A Match Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCRIS ,GPT RTC Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAERIS ,GPT Timer A Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAMRIS ,GPT Timer A Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " TATORIS ,GPT Timer A Time-out Raw interrupt" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 16. " WUMIS ,GPT Write Update Error Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 13. " DMABMIS ,GPT Timer B DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 11. " TBMMIS ,GPT Timer B Match Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 10. " CBEMIS ,GPT Timer B Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CBMMIS ,GPT Timer B Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 8. " TBTOMIS ,GPT Timer B Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 5. " DMAAMIS ,GPT Timer A DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 4. " TAMMIS ,GPT Timer A Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RTCMIS ,GPT RTC Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 2. " CAEMIS ,GPT Timer A Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 1. " CAMMIS ,GPT Timer A Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 0. " TATOMIS ,GPT Timer A Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline ""
|
|
group.long 0x24++0x23
|
|
line.long 0x00 "ICLR,Interrupt Clear Register"
|
|
eventfld.long 0x00 16. " WUECINT ,GPT Write Update Error interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 13. " DMABINT ,GPT Timer B DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 11. " TBMCINT ,GPT Timer B Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CBECINT ,GPT Timer B Capture Mode Event interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 9. " CBMCINT ,GPT Timer B Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 8. " TBTOCINT ,GPT Timer B Time-out interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 5. " DMAAINT ,GPT Timer A DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 4. " TAMCINT ,GPT Timer A Match interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RTCCINT ,GPT RTC interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CAECINT ,GPT Timer A Capture Mode Event interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CAMCINT ,GPT Timer A Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 0. " TATOCINT ,GPT Timer A Time-out interrupt clear" "No effect,Clear"
|
|
line.long 0x04 "TAILR,Timer A Interval Load Register"
|
|
line.long 0x08 "TBILR,Timer B Interval Load Register"
|
|
line.long 0x0C "TAMATCHR,Timer A Match Register"
|
|
line.long 0x10 "TBMATCHR,Timer B Match Register"
|
|
line.long 0x14 "TAPR,Timer A Pre-scale Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " TAPSR ,Timer A Pre-scale"
|
|
line.long 0x18 "TBPR,Timer B Pre-scale Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " TBPSR ,Timer B Pre-scale"
|
|
line.long 0x1C "TAPMR,Timer A Pre-scale Match Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " TAPSMR ,Timer A Pre-scale Match"
|
|
line.long 0x20 "TBPMR,Timer B Pre-scale Match Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " TBPSMR ,Timer B Pre-scale Match"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "TAR,Timer A Register"
|
|
line.long 0x04 "TBR,Timer B Register"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "TAV,Timer A Value Register"
|
|
line.long 0x04 "TBV,Timer B Value Register"
|
|
rgroup.long 0x58++0x13
|
|
line.long 0x00 "RTCPD,RTC Pre-divide Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTCPD ,GPT RTC Pre-divider"
|
|
line.long 0x04 "TAPS,Timer A Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x08 "TBPS,Timer B Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x0C "TAPV,Timer A Pre-scale Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PSV ,GPT Timer A Pre-scaler Value"
|
|
line.long 0x10 "TBPV,Timer B Pre-scale Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " PSV ,GPT Timer B Pre-scaler Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DMAEV,DMA Event Register"
|
|
bitfld.long 0x00 11. " TBMDMAEN ,GPT Timer B Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CBEDMAEN ,GPT Timer B Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CBMDMAEN ,GPT Timer B Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBTODMAEN ,GPT Timer B Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TAMDMAEN ,GPT Timer A Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RTCDMAEN ,GPT RTC Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAEDMAEN ,GPT Timer A Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAMDMAEN ,GPT Timer A Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TATODMAEN ,GPT Timer A Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "VERSION,Peripheral Version Register"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "ANDCCP,Combined CCP Output Register"
|
|
bitfld.long 0x00 0. " CCP_AND_EN ,CPP output AND operation for timer A and B Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 3"
|
|
base ad:0x40013000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
|
|
bitfld.long 0x00 0.--2. " CFG ,GPT Configuration" "32 bit timer,32 bit real-time,,,16 bit timer,?..."
|
|
if (((d.l(ad:0x40013000+0x04))&0x0B)==0x0A)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40013000+0x04))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TAPWMIE ,GPT Timer A PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40013000+0x04))&0x0B)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TAMR,Timer A Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TACINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TAPLO ,Legacy PWM operation" "Legacy,CCP set to 1 on time-out"
|
|
bitfld.long 0x00 10. " TAMRSU ,Timer A Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TAILD ,GPT Timer A PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TASNAPS ,GPT Timer A Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TAWOT ,Timer A Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMIE ,GPT Timer A Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TACDIR ,GPT Timer A Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TAAMS ,GPT Timer A Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TACM ,GPT Timer A Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer A Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
if (((d.l(ad:0x40013000+0x08))&0x0B)==0x0A)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40013000+0x08))&0x0B)==(0x08||0x09||0x0B))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TBPWMIE ,GPT Timer B PWM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
elif (((d.l(ad:0x40013000+0x08))&0x0B)==0x02)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TBMR,Timer B Mode Register"
|
|
bitfld.long 0x00 13.--15. " TCACT ,Timer Compare Action Select" "Disable compare,Toggle state on time-out,Clear CCP on time-out,Set CCP on time-out,Set CCP immediately and toggle on time-out,Clear CCP immediately and toggle on time-out,Set CCP immediately and clear on time-out,Clear CCP immediately and clear on time-out"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TBCINTD ,One-Shot/Periodic Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " TBPLO ,Legacy PWM operation" "Legacy,CCP output as 1 on time-out"
|
|
bitfld.long 0x00 10. " TBMRSU ,Timer B Match Register Update mode" "Next cycle,Next time-out"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBILD ,GPT Timer B PWM Interval Load Write" "Next cycle,Next time-out"
|
|
bitfld.long 0x00 7. " TBSNAPS ,GPT Timer B Snap-Shot Mode" "Disabled,"
|
|
bitfld.long 0x00 6. " TBWOT ,Timer B Wait-On-Trigger" "Immediately,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TBMIE ,GPT Timer B Match Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TBCDIR ,GPT Timer B Count Direction" "Down,Up"
|
|
bitfld.long 0x00 3. " TBAMS ,GPT Timer B Alternate Mode" "Capture/Compare,PWM"
|
|
bitfld.long 0x00 2. " TBCM ,GPT Timer B Capture Mode" "Edge-Count,Edge-Time"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TAMR ,GPT Timer B Mode" ",One-Shot Timer,Periodic Timer,Capture"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 14. " TBPWML ,GPT Timer B PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--11. " TBEVENT ,GPT Timer B Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 9. " TBSTALL ,GPT Timer B Stall Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TBEN ,GPT Timer B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TAPWML ,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " RTCEN ,GPT RTC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TAEVENT ,GPT Timer A Event Mode" "Positive,Negative,,Both"
|
|
bitfld.long 0x00 1. " TASTALL ,GPT Timer A Stall Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TAEN ,GPT Timer A Enable" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SYNC,Synch Register"
|
|
bitfld.long 0x00 6.--7. " SYNC3 ,Synchronize GPT Timer 3" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 4.--5. " SYNC2 ,Synchronize GPT Timer 2" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 2.--3. " SYNC1 ,Synchronize GPT Timer 1" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
bitfld.long 0x00 0.--1. " SYNC0 ,Synchronize GPT Timer 0" "No Sync,Timer A,Timer B,Timer A and Timer B"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 16. " WUMIS ,GPT Write Update Error interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " DMABIM ,GPT Timer B DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " TBMIM ,GPT Timer B Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " CBEIM ,GPT Timer B Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMIM ,GPT Timer B Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " TBTOIM ,GPT Timer B Time-out interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " DMAAIM ,GPT Timer A DMA Done interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " TAMIM ,GPT Timer A Match interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCIM ,GPT RTC interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " CAEIM ,GPT Timer A Capture Mode Event interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CAMIM ,GPT Timer A Capture Mode Match interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " TATOIM ,GPT Timer A Time-out interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 16. " WURIS ,GPT Write Update Error Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " DMABRIS ,GPT Timer B DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TBMRIS ,GPT Timer B Match Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CBERIS ,GPT Timer B Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBMRIS ,GPT Timer B Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TBTORIS ,GPT Timer B Time-out Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " DMAARIS ,GPT Timer A DMA Done Raw interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " TAMRIS ,GPT Timer A Match Raw interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RTCRIS ,GPT RTC Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAERIS ,GPT Timer A Capture Mode Event Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAMRIS ,GPT Timer A Capture Mode Match Raw interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " TATORIS ,GPT Timer A Time-out Raw interrupt" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 16. " WUMIS ,GPT Write Update Error Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 13. " DMABMIS ,GPT Timer B DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 11. " TBMMIS ,GPT Timer B Match Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 10. " CBEMIS ,GPT Timer B Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CBMMIS ,GPT Timer B Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 8. " TBTOMIS ,GPT Timer B Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 5. " DMAAMIS ,GPT Timer A DMA Done Masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 4. " TAMMIS ,GPT Timer A Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RTCMIS ,GPT RTC Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 2. " CAEMIS ,GPT Timer A Capture Mode Event Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 1. " CAMMIS ,GPT Timer A Capture Mode Match Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 0. " TATOMIS ,GPT Timer A Time-out Masked interrupt" "No interrupt or disabled,Interrupt"
|
|
textline ""
|
|
group.long 0x24++0x23
|
|
line.long 0x00 "ICLR,Interrupt Clear Register"
|
|
eventfld.long 0x00 16. " WUECINT ,GPT Write Update Error interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 13. " DMABINT ,GPT Timer B DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 11. " TBMCINT ,GPT Timer B Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CBECINT ,GPT Timer B Capture Mode Event interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 9. " CBMCINT ,GPT Timer B Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 8. " TBTOCINT ,GPT Timer B Time-out interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 5. " DMAAINT ,GPT Timer A DMA Done interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 4. " TAMCINT ,GPT Timer A Match interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RTCCINT ,GPT RTC interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CAECINT ,GPT Timer A Capture Mode Event interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CAMCINT ,GPT Timer A Capture Mode Match interrupt clear" "No effect,Clear"
|
|
eventfld.long 0x00 0. " TATOCINT ,GPT Timer A Time-out interrupt clear" "No effect,Clear"
|
|
line.long 0x04 "TAILR,Timer A Interval Load Register"
|
|
line.long 0x08 "TBILR,Timer B Interval Load Register"
|
|
line.long 0x0C "TAMATCHR,Timer A Match Register"
|
|
line.long 0x10 "TBMATCHR,Timer B Match Register"
|
|
line.long 0x14 "TAPR,Timer A Pre-scale Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " TAPSR ,Timer A Pre-scale"
|
|
line.long 0x18 "TBPR,Timer B Pre-scale Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " TBPSR ,Timer B Pre-scale"
|
|
line.long 0x1C "TAPMR,Timer A Pre-scale Match Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " TAPSMR ,Timer A Pre-scale Match"
|
|
line.long 0x20 "TBPMR,Timer B Pre-scale Match Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " TBPSMR ,Timer B Pre-scale Match"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "TAR,Timer A Register"
|
|
line.long 0x04 "TBR,Timer B Register"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "TAV,Timer A Value Register"
|
|
line.long 0x04 "TBV,Timer B Value Register"
|
|
rgroup.long 0x58++0x13
|
|
line.long 0x00 "RTCPD,RTC Pre-divide Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTCPD ,GPT RTC Pre-divider"
|
|
line.long 0x04 "TAPS,Timer A Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x08 "TBPS,Timer B Pre-scale Snap-shot Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PSS ,GPT Timer A Pre-scaler"
|
|
line.long 0x0C "TAPV,Timer A Pre-scale Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PSV ,GPT Timer A Pre-scaler Value"
|
|
line.long 0x10 "TBPV,Timer B Pre-scale Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " PSV ,GPT Timer B Pre-scaler Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DMAEV,DMA Event Register"
|
|
bitfld.long 0x00 11. " TBMDMAEN ,GPT Timer B Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CBEDMAEN ,GPT Timer B Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CBMDMAEN ,GPT Timer B Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TBTODMAEN ,GPT Timer B Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TAMDMAEN ,GPT Timer A Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RTCDMAEN ,GPT RTC Match DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAEDMAEN ,GPT Timer A Capture Event DMA Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAMDMAEN ,GPT Timer A Capture Match DMA Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TATODMAEN ,GPT Timer A Time-Out DMA Trigger Enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "VERSION,Peripheral Version Register"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "ANDCCP,Combined CCP Output Register"
|
|
bitfld.long 0x00 0. " CCP_AND_EN ,CPP output AND operation for timer A and B Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "AON RTC (Always On Real-Time Clock)"
|
|
base ad:0x40092000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 16.--18. " COMB_EV_MASK ,Event mask selecting which delayed events that form the combined event" "No event,Channel 0,Channel 1,,Channel 2,?..."
|
|
bitfld.long 0x00 8.--11. " EV_DELAY ,Number of SCLK_LF clock cycles waited before generating delayed events" "0,1,2,4,8,16,32,48,64,80,96,112,128,144,?..."
|
|
eventfld.long 0x00 7. " RESET ,RTC Counter reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RTC_4KHZ_EN ,RTC_4KHZ signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTC_UPD_EN ,RTC_UPD signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable RTC counter" "Disabled,Enabled"
|
|
if (((d.l(ad:0x40092000+0x14))&0x10101)==0x10101)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,1"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,1"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,1"
|
|
elif (((d.l(ad:0x40092000+0x14))&0x10101)==0x10100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,1"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,1"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,"
|
|
elif (((d.l(ad:0x40092000+0x14))&0x10101)==0x10001)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,1"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,1"
|
|
elif (((d.l(ad:0x40092000+0x14))&0x10101)==0x10000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,1"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,"
|
|
elif (((d.l(ad:0x40092000+0x14))&0x10101)==0x00101)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,1"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,1"
|
|
elif (((d.l(ad:0x40092000+0x14))&0x10101)==0x00100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,1"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,"
|
|
elif (((d.l(ad:0x40092000+0x14))&0x10101)==0x000001)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EVFLAGS,Event Flags Register"
|
|
eventfld.long 0x00 16. " CH2 ,Channel 2 event flag" "0,"
|
|
eventfld.long 0x00 8. " CH1 ,Channel 1 event flag" "0,"
|
|
eventfld.long 0x00 0. " CH0 ,Channel 0 event flag" "0,"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SEC,Second Counter Value (Integer Part) Register"
|
|
in
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SUBSEC,Second Counter Value (Fractional Part) Register"
|
|
in
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SUBSECINC,Subseconds Increment Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUEINC ,Increment Value"
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "CHCTL,Channel Configuration Register"
|
|
bitfld.long 0x00 18. " CH2_CONT_EN ,Channel 2 Continuous Operation mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CH2_EN ,RTC Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CH1_CAPT_EN ,Channel 1 Capture mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH1_EN ,RTC Channel 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CH0_EN ,RTC Channel 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH0CMP,Channel 0 Compare Value Register"
|
|
line.long 0x08 "CH1CMP,Channel 1 Compare Value Register"
|
|
line.long 0x0C "CH2CMP,Channel 2 Compare Value Register"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH2CMPINC,Channel 2 Compare Value Auto-increment Register"
|
|
if (((d.l(ad:0x40092000+0x14))&0x300)==0x300)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CH1CAPT,Channel 1 Capture Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SEC ,Second Counter Value (Integer Part)[15:0] Capture Time"
|
|
hexmask.long.word 0x00 0.--15. 1. " SUBSEC ,Second Counter Value (Fractional Part)[31:16] Capture Time"
|
|
else
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "CH1CAPT,Channel 1 Capture Value Register"
|
|
endif
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SYNC,AON Synchronization Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40080000
|
|
width 10.
|
|
if (((d.l(ad:0x40080000+0xC00))&0xFFFFFFFF)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LOAD,Configuration Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "VALUE,Current Count Value Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 2. " INTTYPE ,WDT Interrupt Type" "Maskable,Non-maskable"
|
|
bitfld.long 0x00 1. " RESEN ,WDT Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTEN ,WDT Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 0. " WDTRIS ,WDT Raw Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 0. " WDTMIS ,WDT Masked Interrupt Status" "No interrupt,Interrupt"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "TEST,Test Mode Register"
|
|
bitfld.long 0x00 8. " STALL ,WDT Stall Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEST_EN ,Test mode Enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x40080000+0x418))&0x01)==0x01)
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "INT_CAUS,Interrupt Cause Test Mode Register"
|
|
bitfld.long 0x00 1. " CAUSE_RESET ,Interrupt Cause Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CAUSE_INTR ,WDT Raw Interrupt Status" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "INT_CAUS,Interrupt Cause Test Mode Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "LOAD,Configuration Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "VALUE,Current Count Value Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 2. " INTTYPE ,WDT Interrupt Type" "Maskable,Non-maskable"
|
|
bitfld.long 0x00 1. " RESEN ,WDT Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTEN ,WDT Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "ICR,Interrupt Clear Register"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 0. " WDTRIS ,WDT Raw Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 0. " WDTMIS ,WDT Masked Interrupt Status" "No interrupt,Interrupt"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "TEST,Test Mode Register"
|
|
rbitfld.long 0x00 8. " STALL ,WDT Stall Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEST_EN ,Test mode Enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x40080000+0x418))&0x01)==0x01)
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "INT_CAUS,Interrupt Cause Test Mode Register"
|
|
bitfld.long 0x00 1. " CAUSE_RESET ,Interrupt Cause Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CAUSE_INTR ,WDT Raw Interrupt Status" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "INT_CAUS,Interrupt Cause Test Mode Register"
|
|
endif
|
|
endif
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LOCK,Lock Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40028000
|
|
width 13.
|
|
hgroup.long 0x00++0x07
|
|
hide.long 0x00 "OUT0,Random Number Lower Word Readout Value Register"
|
|
in
|
|
hide.long 0x04 "OUT1,Random Number Upper Word Readout Value Register"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IRQFLAGSTAT,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " NEED_CLOCK ,TRNG operating status" "Idle,Busy"
|
|
bitfld.long 0x00 1. " SHUTDOWN_OVF ,The number of FROs shut down has exceeded threshold" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 0. " RDY ,Data availability" "Not available,Available"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IRQFLAGMASK,Interrupt Mask Register"
|
|
bitfld.long 0x00 1. " SHUTDOWN_OVF ,The number of FROs shut down has exceeded threshold interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RDY ,Data availability interrupt mask" "Masked,Not masked"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "IRQFLAGCLR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 1. " SHUTDOWN_OVF ,The number of FROs shut down has exceeded threshold interrupt clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RDY ,Data availability interrupt clear flag" "No effect,Clear"
|
|
if (((d.l(ad:0x40028000+0x14))&0x02)==0x02)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " STARTUP_CYCLES ,Number of samples taken to gather entropy from the FROs during startup"
|
|
bitfld.long 0x00 10. " TRNG_EN ,TRNG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NO_LFSR_FB ,Remove XNOR feedback from main LFSR" "Not removed,Removed"
|
|
bitfld.long 0x00 1. " TEST_MODE ,Test mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " STARTUP_CYCLES ,Number of samples taken to gather entropy from the FROs during startup"
|
|
bitfld.long 0x00 10. " TRNG_EN ,TRNG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NO_LFSR_FB ,Remove XNOR feedback from main LFSR" "Not removed,"
|
|
bitfld.long 0x00 1. " TEST_MODE ,Test mode enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x40028000+0x14))&0x400)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CFG0,Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MAX_REFILL_CYCLES ,Maximum number of samples taken to re-generate entropy"
|
|
bitfld.long 0x00 8.--11. " SMPL_DIV ,Number of clock cycles between samples taken from the FROs" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MIN_REFILL_CYCLES ,Minimum number of samples taken to re-generate entropy"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CFG0,Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MAX_REFILL_CYCLES ,Maximum number of samples taken to re-generate entropy"
|
|
bitfld.long 0x00 8.--11. " SMPL_DIV ,Number of clock cycles between samples taken from the FROs" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MIN_REFILL_CYCLES ,Minimum number of samples taken to re-generate entropy"
|
|
endif
|
|
group.long 0x1C++0x13
|
|
line.long 0x00 "ALARMCNT,Alarm Control Register"
|
|
rbitfld.long 0x00 24.--29. " SHUTDOWN_CNT ,Number of bits set in ALARMSTOP register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
bitfld.long 0x00 16.--20. " SHUTDOWN_THR ,Threshold setting for generating shut down interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ALARM_THR ,Alarm detection threshold for the repeating pattern detectors on each FRO"
|
|
textline " "
|
|
line.long 0x04 "FROEN,FRO Enable Register"
|
|
bitfld.long 0x04 23. " FRO_MASK_[23] ,FRO23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,FRO22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,FRO21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,FRO20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,FRO19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,FRO18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,FRO17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [16] ,FRO16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [15] ,FRO15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,FRO14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,FRO13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,FRO12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,FRO11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,FRO10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,FRO9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,FRO8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,FRO7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,FRO6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,FRO5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,FRO4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,FRO3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,FRO2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,FRO1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,FRO0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FRODETUNE,FRO De-tune Register"
|
|
bitfld.long 0x08 23. " FRO_MASK_[23] ,De-tune for FRO23" "Normal,5% Faster"
|
|
bitfld.long 0x08 22. " [22] ,De-tune for FRO22" "Normal,5% Faster"
|
|
bitfld.long 0x08 21. " [21] ,De-tune for FRO21" "Normal,5% Faster"
|
|
bitfld.long 0x08 20. " [20] ,De-tune for FRO20" "Normal,5% Faster"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,De-tune for FRO19" "Normal,5% Faster"
|
|
bitfld.long 0x08 18. " [18] ,De-tune for FRO18" "Normal,5% Faster"
|
|
bitfld.long 0x08 17. " [17] ,De-tune for FRO17" "Normal,5% Faster"
|
|
bitfld.long 0x08 16. " [16] ,De-tune for FRO16" "Normal,5% Faster"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,De-tune for FRO15" "Normal,5% Faster"
|
|
bitfld.long 0x08 14. " [14] ,De-tune for FRO14" "Normal,5% Faster"
|
|
bitfld.long 0x08 13. " [13] ,De-tune for FRO13" "Normal,5% Faster"
|
|
bitfld.long 0x08 12. " [12] ,De-tune for FRO12" "Normal,5% Faster"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,De-tune for FRO11" "Normal,5% Faster"
|
|
bitfld.long 0x08 10. " [10] ,De-tune for FRO10" "Normal,5% Faster"
|
|
bitfld.long 0x08 9. " [9] ,De-tune for FRO9" "Normal,5% Faster"
|
|
bitfld.long 0x08 8. " [8] ,De-tune for FRO8" "Normal,5% Faster"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,De-tune for FRO7" "Normal,5% Faster"
|
|
bitfld.long 0x08 6. " [6] ,De-tune for FRO6" "Normal,5% Faster"
|
|
bitfld.long 0x08 5. " [5] ,De-tune for FRO5" "Normal,5% Faster"
|
|
bitfld.long 0x08 4. " [4] ,De-tune for FRO4" "Normal,5% Faster"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,De-tune for FRO3" "Normal,5% Faster"
|
|
bitfld.long 0x08 2. " [2] ,De-tune for FRO2" "Normal,5% Faster"
|
|
bitfld.long 0x08 1. " [1] ,De-tune for FRO1" "Normal,5% Faster"
|
|
bitfld.long 0x08 0. " [0] ,De-tune for FRO0" "Normal,5% Faster"
|
|
line.long 0x0C "ALARMMASK,Alarm Event Register"
|
|
bitfld.long 0x0C 23. " FRO_MASK_[23] ,Alarm event for FRO23" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 22. " [22] ,Alarm event for FRO22" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 21. " [21] ,Alarm event for FRO21" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 20. " [20] ,Alarm event for FRO20" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [19] ,Alarm event for FRO19" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 18. " [18] ,Alarm event for FRO18" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 17. " [17] ,Alarm event for FRO17" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 16. " [16] ,Alarm event for FRO16" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [15] ,Alarm event for FRO15" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 14. " [14] ,Alarm event for FRO14" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 13. " [13] ,Alarm event for FRO13" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 12. " [12] ,Alarm event for FRO12" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [11] ,Alarm event for FRO11" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 10. " [10] ,Alarm event for FRO10" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 9. " [9] ,Alarm event for FRO9" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 8. " [8] ,Alarm event for FRO8" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [7] ,Alarm event for FRO7" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 6. " [6] ,Alarm event for FRO6" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 5. " [5] ,Alarm event for FRO5" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 4. " [4] ,Alarm event for FRO4" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [3] ,Alarm event for FRO3" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 2. " [2] ,Alarm event for FRO2" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 1. " [1] ,Alarm event for FRO1" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " [0] ,Alarm event for FRO0" "Not occurred,Occurred"
|
|
line.long 0x10 "ALARMSTOP,Alarm Shutdown Register"
|
|
bitfld.long 0x10 23. " FRO_FLAGS[23] ,Alarm Shutdown for FRO23" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 22. " [22] ,Alarm Shutdown for FRO22" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 21. " [21] ,Alarm Shutdown for FRO21" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 20. " [20] ,Alarm Shutdown for FRO20" "No shutdown,Shutdown"
|
|
textline " "
|
|
bitfld.long 0x10 19. " [19] ,Alarm Shutdown for FRO19" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 18. " [18] ,Alarm Shutdown for FRO18" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 17. " [17] ,Alarm Shutdown for FRO17" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 16. " [16] ,Alarm Shutdown for FRO16" "No shutdown,Shutdown"
|
|
textline " "
|
|
bitfld.long 0x10 15. " [15] ,Alarm Shutdown for FRO15" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 14. " [14] ,Alarm Shutdown for FRO14" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 13. " [13] ,Alarm Shutdown for FRO13" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 12. " [12] ,Alarm Shutdown for FRO12" "No shutdown,Shutdown"
|
|
textline " "
|
|
bitfld.long 0x10 11. " [11] ,Alarm Shutdown for FRO11" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 10. " [10] ,Alarm Shutdown for FRO10" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 9. " [9] ,Alarm Shutdown for FRO9" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 8. " [8] ,Alarm Shutdown for FRO8" "No shutdown,Shutdown"
|
|
textline " "
|
|
bitfld.long 0x10 7. " [7] ,Alarm Shutdown for FRO7" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 6. " [6] ,Alarm Shutdown for FRO6" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 5. " [5] ,Alarm Shutdown for FRO5" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 4. " [4] ,Alarm Shutdown for FRO4" "No shutdown,Shutdown"
|
|
textline " "
|
|
bitfld.long 0x10 3. " [3] ,Alarm Shutdown for FRO3" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 2. " [2] ,Alarm Shutdown for FRO2" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 1. " [1] ,Alarm Shutdown for FRO1" "No shutdown,Shutdown"
|
|
bitfld.long 0x10 0. " [0] ,Alarm Shutdown for FRO0" "No shutdown,Shutdown"
|
|
textline " "
|
|
if (((d.l(ad:0x40028000+0x14))&0x02)==0x02)
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "LFSR0,LFSR Readout Value[31:0]"
|
|
line.long 0x04 "LFSR1,LFSR Readout Value[63:32]"
|
|
line.long 0x08 "LFSR2,LFSR Readout Value[80:64]"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " LFSR_80_64 ,Bits [80:64] of the main entropy accumulation LFSR"
|
|
else
|
|
hgroup.long 0x30++0x0B
|
|
hide.long 0x00 "LFSR0,LFSR Readout Value[31:0]"
|
|
hide.long 0x04 "LFSR1,LFSR Readout Value[63:32]"
|
|
hide.long 0x08 "LFSR2,LFSR Readout Value[80:64]"
|
|
endif
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "HWOPT,TRNG Engine Options Information Register"
|
|
bitfld.long 0x00 6.--11. " NR_OF_FROS ,Number of FROs implemented in this TRNG" ",,,,,,,,,,,,,,,,,,,,,,,,24,?..."
|
|
line.long 0x04 "HWVER0,HW Version 0 EIP Number And Core Revision Register"
|
|
bitfld.long 0x04 24.--27. " HW_MAJOR_VER ,Major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " HW_MINOR_VER ,Minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " HW_PATCH_LVL ,Hardware patch level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " EIP_NUM_COMPL ,Module number complement"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EIP_NUM ,Module number"
|
|
rgroup.long 0x1FD8++0x03
|
|
line.long 0x00 "IRQSTATMASK,Interrupt Status After Masking Register"
|
|
bitfld.long 0x00 1. " SHUTDOWN_OVF ,Shutdown Overflow" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RDY ,New random value available" "No interrupt,Interrupt"
|
|
rgroup.long 0x1FE0++0x03
|
|
line.long 0x00 "HWVER1,HW Version 1 TRNG Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number"
|
|
group.long 0x1FF0++0x03
|
|
line.long 0x00 "SWRESET,SW Reset Control Register"
|
|
bitfld.long 0x00 0. " RESET ,Reset" "Not reset,Reset"
|
|
textline " "
|
|
rgroup.long 0x1FF8++0x03
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
bitfld.long 0x00 0. " STAT ,Status" "No data available and not overflowed,Data Available or overflowed"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "AUX (Sensor Controller with Digital and Analog Peripherals)"
|
|
tree "AIODIO_0 (Analog/Digital I/O 0)"
|
|
base ad:0x400C1000
|
|
width 13.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GPIODOUT,General Purpose Input/Output Data Out Register"
|
|
bitfld.long 0x00 7. " IO[7] ,Output values for AUXIO[7]" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Output value for AUXIO[6]" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Output value for AUXIO[5]" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,Output value for AUXIO[4]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Output value for AUXIO[3]" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Output value for AUXIO[2]" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Output value for AUXIO[1]" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Output value for AUXIO[0]" "0,1"
|
|
textline " "
|
|
line.long 0x04 "IOMODE,Input Output Mode Register"
|
|
bitfld.long 0x04 14.--15. " IO7 ,Selects mode for AUXIO7" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
bitfld.long 0x04 12.--13. " IO6 ,Selects mode for AUXIO6" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
bitfld.long 0x04 10.--11. " IO5 ,Selects mode for AUXIO5" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " IO4 ,Selects mode for AUXIO4" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
bitfld.long 0x04 6.--7. " IO3 ,Selects mode for AUXIO3" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
bitfld.long 0x04 4.--5. " IO2 ,Selects mode for AUXIO2" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " IO1 ,Selects mode for AUXIO1" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
bitfld.long 0x04 0.--1. " IO0 ,Selects mode for AUXIO0" "Output,Analog IO/Digital I,Open-drain,Open-source"
|
|
textline " "
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "GPIODIN,General Purpose Input Output Data In Register"
|
|
bitfld.long 0x00 7. " IO[7] ,Input value for AUXIO7" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Input value for AUXIO6" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Input value for AUXIO5" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,Input value for AUXIO4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Input value for AUXIO3" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Input value for AUXIO2" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Input value for AUXIO1" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Input value for AUXIO0" "0,1"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "GPIODOUTSET,General Purpose Input Output Data Out Set Register"
|
|
bitfld.long 0x00 7. " IO[7] ,Set IO[7] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,Set IO[6] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,Set IO[5] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,Set IO[4] in GPIODOUT" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Set IO[3] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,Set IO[2] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,Set IO[1] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,Set IO[0] in GPIODOUT" "No effect,Set"
|
|
line.long 0x04 "GPIODOUTCLR,General Purpose Input Output Data Out Clear Register"
|
|
bitfld.long 0x04 7. " IO[7] ,Clear IO[7] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Clear IO[6] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Clear IO[5] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [4] ,Clear IO[4] in GPIODOUT" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Clear IO[3] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Clear IO[2] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [1] ,Clear IO[1] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Clear IO[0] in GPIODOUT" "No effect,Clear"
|
|
line.long 0x08 "GPIODOUTTGL,General Purpose Input Output Data Out Toggle Register"
|
|
bitfld.long 0x08 7. " IO[7] ,Toggle IO[7] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [6] ,Toggle IO[6] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 5. " [5] ,Toggle IO[5] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [4] ,Toggle IO[4] in GPIODOUT" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Toggle IO[3] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [2] ,Toggle IO[2] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 1. " [1] ,Toggle IO[1] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [0] ,Toggle IO[0] in GPIODOUT" "No effect,Toggle"
|
|
line.long 0x0C "GPIODIE,General Purpose Input Output Input Enable Register"
|
|
bitfld.long 0x0C 7. " IO[7] ,AUXIO[7] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [6] ,AUXIO[6] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [5] ,AUXIO[5] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [4] ,AUXIO[4] Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [3] ,AUXIO[3] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [2] ,AUXIO[2] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [1] ,AUXIO[1] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [0] ,AUXIO[0] Input Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AIODIO_1 (Analog/Digital I/O 1)"
|
|
base ad:0x400C2000
|
|
width 13.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GPIODOUT,General Purpose Input/Output Data Out Register"
|
|
bitfld.long 0x00 7. " IO[15] ,Output value for AUXIO[15]" "0,1"
|
|
bitfld.long 0x00 6. " [14] ,Output value for AUXIO[14]" "0,1"
|
|
bitfld.long 0x00 5. " [13] ,Output value for AUXIO[13]" "0,1"
|
|
bitfld.long 0x00 4. " [12] ,Output value for AUXIO[12]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [11] ,Output value for AUXIO[11]" "0,1"
|
|
bitfld.long 0x00 2. " [10] ,Output values for AUXIO[10]" "0,1"
|
|
bitfld.long 0x00 1. " [9] ,Output value for AUXIO[9]" "0,1"
|
|
bitfld.long 0x00 0. " [8] ,Output value for AUXIO[8]" "0,1"
|
|
textline " "
|
|
line.long 0x04 "IOMODE,Input Output Mode Register"
|
|
bitfld.long 0x04 14.--15. " IO15 ,Selects mode for AUXIO15" "Output,Digital input,Open-drain,Open-source"
|
|
bitfld.long 0x04 12.--13. " IO14 ,Selects mode for AUXIO14" "Output,Digital input,Open-drain,Open-source"
|
|
bitfld.long 0x04 10.--11. " IO13 ,Selects mode for AUXIO13" "Output,Digital input,Open-drain,Open-source"
|
|
bitfld.long 0x04 8.--9. " IO12 ,Selects mode for AUXIO12" "Output,Digital input,Open-drain,Open-source"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " IO11 ,Selects mode for AUXIO11" "Output,Digital input,Open-drain,Open-source"
|
|
bitfld.long 0x04 4.--5. " IO10 ,Selects mode for AUXIO10" "Output,Digital input,Open-drain,Open-source"
|
|
bitfld.long 0x04 2.--3. " IO9 ,Selects mode for AUXIO9" "Output,Digital input,Open-drain,Open-source"
|
|
bitfld.long 0x04 0.--1. " IO8 ,Selects mode for AUXIO8" "Output,Digital input,Open-drain,Open-source"
|
|
textline " "
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "GPIODIN,General Purpose Input Output Data In Register"
|
|
bitfld.long 0x00 7. " IO[15] ,Input value for AUXIO15" "0,1"
|
|
bitfld.long 0x00 6. " [14] ,Input value for AUXIO14" "0,1"
|
|
bitfld.long 0x00 5. " [13] ,Input value for AUXIO13" "0,1"
|
|
bitfld.long 0x00 4. " [12] ,Input value for AUXIO12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [11] ,Input value for AUXIO11" "0,1"
|
|
bitfld.long 0x00 2. " [10] ,Input value for AUXIO10" "0,1"
|
|
bitfld.long 0x00 1. " [9] ,Input value for AUXIO9" "0,1"
|
|
bitfld.long 0x00 0. " [8] ,Input value for AUXIO8" "0,1"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "GPIODOUTSET,General Purpose Input Output Data Out Set Register"
|
|
bitfld.long 0x00 7. " IO[15] ,Set IO[15] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 6. " [14] ,Set IO[14] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 5. " [13] ,Set IO[13] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 4. " [12] ,Set IO[12] in GPIODOUT" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [11] ,Set IO[11] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 2. " [10] ,Set IO[10] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 1. " [9] ,Set IO[9] in GPIODOUT" "No effect,Set"
|
|
bitfld.long 0x00 0. " [8] ,Set IO[8] in GPIODOUT" "No effect,Set"
|
|
line.long 0x04 "GPIODOUTCLR,General Purpose Input Output Data Out Clear Register"
|
|
bitfld.long 0x04 7. " IO[15] ,Clear IO[15] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [14] ,Clear [14] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [13] ,Clear [13] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 4. " [12] ,Clear [12] in GPIODOUT" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [11] ,Clear [11] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [10] ,Clear [10] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 1. " [9] ,Clear [9] in GPIODOUT" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [8] ,Clear [8] in GPIODOUT" "No effect,Clear"
|
|
line.long 0x08 "GPIODOUTTGL,General Purpose Input Output Data Out Toggle Register"
|
|
bitfld.long 0x08 7. " IO[15] ,Toggle IO[15] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 6. " [14] ,Toggle IO[14] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 5. " [13] ,Toggle IO[13] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 4. " [12] ,Toggle IO[12] in GPIODOUT" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [11] ,Toggle [11] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 2. " [10] ,Toggle [10] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 1. " [9] ,Toggle [9] in GPIODOUT" "No effect,Toggle"
|
|
bitfld.long 0x08 0. " [8] ,Toggle [8] in GPIODOUT" "No effect,Toggle"
|
|
line.long 0x0C "GPIODIE,General Purpose Input Output Input Enable Register"
|
|
bitfld.long 0x0C 7. " IO[15] ,AUXIO[15] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [14] ,AUXIO[14] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [13] ,AUXIO[13] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [12] ,AUXIO[12] Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [11] ,AUXIO[11] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [10] ,AUXIO[10] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [9] ,AUXIO[9] Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [8] ,AUXIO[8] Input Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TDC (Time to Digital Converter)"
|
|
base ad:0x400C4000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 0.--1. " CMD ,TDC command strobes" "Clear SAT and DONE,TDC FSM Start Synchronously,TDC FSM Start/Stop Asynchronously,Force IDLE"
|
|
textline " "
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "STAT,Status Register"
|
|
bitfld.long 0x00 7. " SAT ,Saturation flag for TDC measurement" "Not saturated,Saturated"
|
|
bitfld.long 0x00 6. " DONE ,Measurement complete flag" "Not complete,Complete"
|
|
bitfld.long 0x00 0.--5. " STATE ,TDC internal state machine status" "TDC_STATE_WAIT_START,,,,TDC_STATE_WAIT_STARTSTOPCNTEN,,TDC_STATE_IDLE,TDC_STATE_CLRCNT,TDC_STATE_WAIT_STOP,,,,TDC_STATE_WAIT_STOPCNTDOWN,,TDC_STATE_GETRESULTS,TDC_STATE_POR,,,,,,,TDC_STATE_WAIT_CLRCNT_DONE,,,,,,,,TDC_WAIT_STARTFALL,,,,,,,,,,,,,,,,TDC_FORCESTOP,?..."
|
|
line.long 0x04 "RESULT,Result of last TDC conversion Register"
|
|
hexmask.long 0x04 0.--24. 1. " VALUE ,Result of the TDC conversion"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SATCFG,Saturation Configuration Register"
|
|
bitfld.long 0x00 0.--3. " LIMIT ,TDC time out limit" ",,,2^12,2^13,2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24"
|
|
if (d.l(ad:0x400C4000+0x04)&0x3F)==0x06
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "TRIGSRC,Trigger Source Register"
|
|
bitfld.long 0x00 13. " STOP_POL ,Polarity of stop signal" "High,Low"
|
|
bitfld.long 0x00 8.--12. " STOP_SRC ,Selects the asynchronous stop signal" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,ISRC_RESET,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO014,AUXIO15,ACLK_REF,MCU_EV,TDC_PRE"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START_POL ,Polarity of start signal" "High,Low"
|
|
bitfld.long 0x00 0.--4. " START_SRC ,Selects the asynchronous start signal" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,ISRC_RESET,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO014,AUXIO15,ACLK_REF,MCU_EV,TDC_PRE"
|
|
line.long 0x04 "TRIGCNT,Trigger Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter of stop events that will be ignored"
|
|
line.long 0x08 "TRIGCNTLOAD,Trigger Counter Load Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " CNT ,Counter of stop events that will be ignored by the TDC"
|
|
else
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "TRIGSRC,Trigger Source Register"
|
|
bitfld.long 0x00 13. " STOP_POL ,Polarity of stop signal" "High,Low"
|
|
bitfld.long 0x00 8.--12. " STOP_SRC ,Selects the asynchronous stop signal" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,ISRC_RESET,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO014,AUXIO15,ACLK_REF,MCU_EV,TDC_PRE"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START_POL ,Polarity of start signal" "High,Low"
|
|
bitfld.long 0x00 0.--4. " START_SRC ,Selects the asynchronous start signal" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,ISRC_RESET,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO014,AUXIO15,ACLK_REF,MCU_EV,TDC_PRE"
|
|
line.long 0x04 "TRIGCNT,Trigger Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNT ,Counter of stop events that will be ignored"
|
|
line.long 0x08 "TRIGCNTLOAD,Trigger Counter Load Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " CNT ,Counter of stop events that will be ignored by the TDC"
|
|
endif
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "TRIGCNTCFG,Trigger Counter Configuration Register"
|
|
bitfld.long 0x00 0. " EN ,Stop counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "PRECTL,Prescaler Control Register"
|
|
bitfld.long 0x04 7. " RESET_N ,Prescaler reset control" "Held in reset,Not in held reset"
|
|
bitfld.long 0x04 6. " RATIO ,Prescaler ratio" "/16,/64"
|
|
bitfld.long 0x04 0.--4. " SRC ,Prescaler event to use as input" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,ISRC_RESET,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO014,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
line.long 0x08 "PRECNT,Prescaler Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " CNT ,Prescaler counter"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EVCTL (Event Control)"
|
|
base ad:0x400C5000
|
|
width 17.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "VECCFG0,Vector Configuration 0 Register"
|
|
bitfld.long 0x00 14. " VEC1_POL ,Vector 1 trigger event polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 13. " VEC1_EN ,Vector 1 execution trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " VEC1_EV ,Vector 1 trigger source event" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VEC0_POL ,Vector 0 trigger event polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 5. " VEC0_EN ,Vector 0 execution trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " VEC0_EV ,Vector 0 trigger source event" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
line.long 0x04 "VECCFG1,Vector Configuration 1 Register"
|
|
bitfld.long 0x04 14. " VEC3_POL ,Vector 3 trigger event polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 13. " VEC3_EN ,Vector 3 execution trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--12. " VEC3_EV ,Vector 3 trigger source event" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VEC2_POL ,Vector 2 trigger event polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 5. " VEC2_EN ,Vector 2 execution trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--4. " VEC2_EV ,Vector 2 trigger source event" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
line.long 0x08 "SCEWEVSEL,Sensor Controller Engine Wait Event Selection Register"
|
|
bitfld.long 0x08 0.--4. " WEV7_EV ,Event source" "AON_RTC_CH2,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,ADC_DONE,ADC_FIFO_ALMOST_FULL,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
line.long 0x0C "EVTOAONFLAGS,Events To AON Domain Flags Register"
|
|
bitfld.long 0x0C 8. " TIMER1_EV ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 7. " TIMER0_EV ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 6. " TDC_DONE ,Event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ADC_DONE ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 4. " AUX_COMPB ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 3. " AUX_COMPA ,Event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SWEV2 ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 1. " SWEV1 ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " SWEV0 ,Event flag" "Not occurred,Occurred"
|
|
line.long 0x10 "EVTOAONPOL,Events To AON Domain Polarity Register"
|
|
bitfld.long 0x10 8. " TIMER1_EV ,Event source level" "High,Low"
|
|
bitfld.long 0x10 7. " TIMER0_EV ,Event source level" "High,Low"
|
|
bitfld.long 0x10 6. " TDC_DONE ,Event source level" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x10 5. " ADC_DONE ,Event source level" "High,Low"
|
|
bitfld.long 0x10 4. " AUX_COMPB ,Event source level" "High,Low"
|
|
bitfld.long 0x10 3. " AUX_COMPA ,Event source level" "High,Low"
|
|
line.long 0x14 "DMACTL,Direct Memory Access Control Register"
|
|
bitfld.long 0x14 2. " REQ_MODE ,DMA Request mode" "Burst,Single"
|
|
bitfld.long 0x14 1. " EN ,DMA interface" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " SEL ,Selection of FIFO watermark level" "Valid samples,Almost full"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "SWEVSET,Software Event Set Register"
|
|
bitfld.long 0x00 2. " SWEV2 ,Software Event 2 Set" "Not set,Set"
|
|
bitfld.long 0x00 1. " SWEV1 ,Software Event 1 Set" "Not set,Set"
|
|
bitfld.long 0x00 0. " SWEV0 ,Software Event 0 Set" "Not set,Set"
|
|
textline " "
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "EVSTAT0,Event Status 0 Register"
|
|
bitfld.long 0x00 15. " AUXIO2 ,Value of AUXIO2 event line" "0,1"
|
|
bitfld.long 0x00 14. " AUXIO1 ,Value of AUXIO1 event line" "0,1"
|
|
bitfld.long 0x00 13. " AUXIO0 ,Value of AUXIO0 event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AON_PROG_WU ,Value of OBSMUX3 event line" "0,1"
|
|
bitfld.long 0x00 11. " AON_SW ,Value of OBSMUX2 event line" "0,1"
|
|
bitfld.long 0x00 10. " OBSMUX1 ,Value of OBSMUX1 event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OBSMUX0 ,Value of OBSMUX0 event line" "0,1"
|
|
bitfld.long 0x00 8. " ADC_FIFO_ALMOST_FULL ,Value of ADC_FIFO_ALMOST_FULL event line" "0,1"
|
|
bitfld.long 0x00 7. " ADC_DONE ,Value of ADC_DONE event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SMPH_AUTOTAKE_DONE ,Value of SMPH_AUTOTAKE_DONE event line" "0,1"
|
|
bitfld.long 0x00 5. " TIMER1_EV ,Value of TIMER1_EV event line" "0,1"
|
|
bitfld.long 0x00 4. " TIMER0_EV ,Value of TIMER0_EV event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TDC_DONE ,Value of TDC_DONE event line" "0,1"
|
|
bitfld.long 0x00 2. " AUX_COMPB ,Value of AUX_COMPB event line" "0,1"
|
|
bitfld.long 0x00 1. " AUX_COMPA ,Value of AUX_COMPA event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AON_RTC_CH2 ,Value of AON_RTC_CH2 event line" "0,1"
|
|
line.long 0x04 "EVSTAT1,Event Status 1 Register"
|
|
bitfld.long 0x04 15. " ADC_IRQ ,Value of ADC_IRQ event line" "0,1"
|
|
bitfld.long 0x04 14. " MCU_EV ,Value of MCU_EV event line" "0,1"
|
|
bitfld.long 0x04 13. " ACLK_REF ,Value of ACLK_REF event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 12. " AUXIO15 ,Value of AUXIO15 event line" "0,1"
|
|
bitfld.long 0x04 11. " AUXIO14 ,Value of AUXIO14 event line" "0,1"
|
|
bitfld.long 0x04 10. " AUXIO13 ,Value of AUXIO13 event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " AUXIO12 ,Value of AUXIO12 event line" "0,1"
|
|
bitfld.long 0x04 8. " AUXIO11 ,Value of AUXIO11 event line" "0,1"
|
|
bitfld.long 0x04 7. " AUXIO10 ,Value of AUXIO10 event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " AUXIO9 ,Value of AUXIO9 event line" "0,1"
|
|
bitfld.long 0x04 5. " AUXIO8 ,Value of AUXIO8event line" "0,1"
|
|
bitfld.long 0x04 4. " AUXIO7 ,Value of AUXIO7 event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " AUXIO6 ,Value of AUXIO6 event line" "0,1"
|
|
bitfld.long 0x04 2. " AUXIO5 ,Value of AUXIO5 event line" "0,1"
|
|
bitfld.long 0x04 1. " AUXIO4 ,Value of AUXIO4 event line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AUXIO3 ,Value of AUXIO3 event line" "0,1"
|
|
textline " "
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "EVTOMCUPOL,Event To MCU Domain Polarity Register"
|
|
bitfld.long 0x00 10. " ADC_IRQ ,Event source level" "High,Low"
|
|
bitfld.long 0x00 9. " OBSMUX0 ,Event source level" "High,Low"
|
|
bitfld.long 0x00 8. " ADC_FIFO_ALMOST_FULL ,Event source level" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADC_DONE ,Event source level" "High,Low"
|
|
bitfld.long 0x00 6. " SMPH_AUTOTAKE_DONE ,Event source level" "High,Low"
|
|
bitfld.long 0x00 5. " TIMER1_EV ,Event source level" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMER0_EV ,Event source level" "High,Low"
|
|
bitfld.long 0x00 3. " TDC_DONE ,Event source level" "High,Low"
|
|
bitfld.long 0x00 2. " AUX_COMPB ,Event source level" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUX_COMPA ,Event source level" "High,Low"
|
|
bitfld.long 0x00 0. " AON_WU_EV ,Event source level" "High,Low"
|
|
line.long 0x04 "EVTOMCUFLAGS,Events to MCU Domain Flags Register"
|
|
bitfld.long 0x04 10. " ADC_IRQ ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " OBSMUX0 ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " ADC_FIFO_ALMOST_FULL ,Event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ADC_DONE ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " SMPH_AUTOTAKE_DONE ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " TIMER1_EV ,Event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TIMER0_EV ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " TDC_DONE ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " AUX_COMPB ,Event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " AUX_COMPA ,Event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " AON_WU_EV ,Event flag" "Not occurred,Occurred"
|
|
line.long 0x08 "COMBEVTOMCUMASK,Combined Event To MCU Domain Mask Register"
|
|
bitfld.long 0x08 10. " ADC_IRQ ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " OBSMUX0 ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " ADC_FIFO_ALMOST_FULL ,Event mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ADC_DONE ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " SMPH_AUTOTAKE_DONE ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " TIMER1_EV ,Event mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TIMER0_EV ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " TDC_DONE ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " AUX_COMPB ,Event mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " AUX_COMPA ,Event mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " AON_WU_EV ,Event mask" "Masked,Not masked"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "VECFLAGS,Vector Flags Register"
|
|
bitfld.long 0x00 3. " VEC3 ,Vector 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " VEC2 ,Vector 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VEC1 ,Vector 1 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VEC0 ,Vector 0 Flag" "Not occurred,Occurred"
|
|
wgroup.long 0x38++0x0B
|
|
line.long 0x00 "EVTOMCUFLAGSCLR,Events To MCU Domain Flags Clear Register"
|
|
bitfld.long 0x00 10. " ADC_IRQ ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " OBSMUX0 ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " ADC_FIFO_ALMOST_FULL ,Event Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADC_DONE ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " SMPH_AUTOTAKE_DONE ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TIMER1_EV ,Event Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMER0_EV ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TDC_DONE ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " AUX_COMPB ,Event Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUX_COMPA ,Event Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " AON_WU_EV ,Event Flag Clear" "No effect,Clear"
|
|
line.long 0x04 "EVTOAONFLAGSCLR,Events To AON Domain Clear Register"
|
|
bitfld.long 0x04 8. " TIMER1_EV ,Event AON Domain Clear" "No effect,Clear"
|
|
bitfld.long 0x04 7. " TIMER0_EV ,Event AON Domain Clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " TDC_DONE ,Event AON Domain Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ADC_DONE ,Event AON Domain Clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " AUX_COMPB ,Event AON Domain Clear" "No effect,Clear"
|
|
bitfld.long 0x04 3. " AUX_COMPA ,Event AON Domain Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SWEV2 ,Event AON Domain Clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " SWEV1 ,Event AON Domain Clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " SWEV0 ,Event AON Domain Clear" "No effect,Clear"
|
|
line.long 0x08 "VECFLAGSCLR,Vector Flags Clear Register"
|
|
bitfld.long 0x08 3. " VEC3 ,Vector 3 Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x08 2. " VEC2 ,Vector 2 Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x08 1. " VEC1 ,Vector 1 Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " VEC0 ,Vector 0 Flag Clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WUC (Wake-up Controller)"
|
|
base ad:0x400C6000
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "MODCLKEN0,Module Clock Enable Register"
|
|
bitfld.long 0x00 7. " AUX_ADI4 ,AUX_ADI4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AUX_DDI0_OSC ,AUX_DDI0_OSC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TDC ,AUX_TDC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ANAIF ,AUX_ANAIF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIMER ,AUX_TIMER clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AIODIO1 ,AUX_AIODIO1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AIODIO0 ,AUX_AIODIO0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMPH ,AUX_SMPH clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWROFFREQ,Power Off Request Register"
|
|
bitfld.long 0x04 0. " REQ ,Power off request" "No effect,Requested"
|
|
line.long 0x08 "PWRDWNREQ,Power Down Request Register"
|
|
bitfld.long 0x08 0. " REQ ,Power down request" "Active mode,Power down mode"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PWRDWNACK,Power Down Acknowledgment Register"
|
|
bitfld.long 0x00 0. " ACK ,Power down acknowledgment" "Not acknowledged,Acknowledged"
|
|
if (((d.l(ad:0x400C6000+0x10))&0x01)==0x01)&&(((d.l(ad:0x400C6000+0x14))&0x01)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CLKLFREQ,Low Frequency Clock Request Register"
|
|
bitfld.long 0x00 0. " REQ ,Low frequency clock request" "AON_WUC:AUXCLK,SCLK_LF"
|
|
elif (((d.l(ad:0x400C6000+0x10))&0x01)==0x0)&&(((d.l(ad:0x400C6000+0x14))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CLKLFREQ,Low Frequency Clock Request Register"
|
|
bitfld.long 0x00 0. " REQ ,Low frequency clock request" "AON_WUC:AUXCLK,SCLK_LF"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CLKLFREQ,Low Frequency Clock Request Register"
|
|
bitfld.long 0x00 0. " REQ ,Low frequency clock request" "AON_WUC:AUXCLK,SCLK_LF"
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CLKLFACK,Low Frequency Clock Acknowledgment Register"
|
|
bitfld.long 0x00 0. " ACK ,CLKLFREQ.REQ acknowledgement" "AON_WUC:AUXCLK,SCLK_LF"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "WUEVFLAGS,Wake-up Event Flags Register"
|
|
bitfld.long 0x00 2. " AON_RTC_CH2 ,AON_RTC_CH2 compare event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " AON_SW ,AON_WUC:AUXCTL.SWEV set to '1' event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " AON_PROG_WU ,AON_EVENT:AUXWUSEL.WU0_EV/WU1_EV/WU2_EV sources selected event flag" "Not occurred,Occurred"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WUEVCLR,Wake-up Event Clear Register"
|
|
bitfld.long 0x00 2. " AON_RTC_CH2 ,WUEVFLAGS.AON_RTC_CH wake-up event clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " AON_SW ,WUEVFLAGS.AON_SW wake-up event clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " AON_PROG_WU ,WUEVFLAGS.AON_PROG_WU wake-up event clear" "Not cleared,Cleared"
|
|
if (((d.l(ad:0x400C6000+0x30))&0x03)==0x03)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADCCLKCTL,ADC Clock Control Register"
|
|
rbitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,ADC internal clock enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400C6000+0x30))&0x03)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADCCLKCTL,ADC Clock Control Register"
|
|
rbitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,ADC internal clock enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ADCCLKCTL,ADC Clock Control Register"
|
|
bitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,ADC internal clock enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x400C6000+0x34))&0x03)==0x03)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TDCCLKCTL,TDC Clock Control Register"
|
|
rbitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,TDC counter clock source enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400C6000+0x34))&0x03)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TDCCLKCTL,TDC Clock Control Register"
|
|
rbitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,TDC counter clock source enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TDCCLKCTL,TDC Clock Control Register"
|
|
bitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,TDC counter clock source enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x400C6000+0x38))&0x03)==0x03)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "REFCLKCTL,Reference Clock Control Register"
|
|
rbitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,TDC reference clock source enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x400C6000+0x38))&0x03)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "REFCLKCTL,Reference Clock Control Register"
|
|
rbitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,TDC reference clock source enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "REFCLKCTL,Reference Clock Control Register"
|
|
bitfld.long 0x00 1. " ACK ,REQ last written value acknowledgement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REQ ,TDC reference clock source enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "RTCSUBSECINC0,Real Time Counter Sub Second Increment 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INC15_0 ,Bits 15:0 of the RTC sub-second increment value"
|
|
line.long 0x04 "RTCSUBSECINC1,Real Time Counter Sub Second Increment 1 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " INC23_16 ,Bits 23:16 of the RTC sub-second increment value"
|
|
if (((d.l(ad:0x400C6000+0x44))&0x03)==0x03)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment Control Register"
|
|
rbitfld.long 0x00 1. " UPD_ACK ,UPD_REQ acknowledgement" "Not available,Available"
|
|
bitfld.long 0x00 0. " UPD_REQ ,New real time counter sub second increment value availability" "Not available,Available"
|
|
elif (((d.l(ad:0x400C6000+0x44))&0x03)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment Control Register"
|
|
rbitfld.long 0x00 1. " UPD_ACK ,UPD_REQ acknowledgement" "Not available,Available"
|
|
bitfld.long 0x00 0. " UPD_REQ ,New real time counter sub second increment value availability" "Not available,Available"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment Control Register"
|
|
bitfld.long 0x00 1. " UPD_ACK ,UPD_REQ acknowledgement" "Not available,Available"
|
|
bitfld.long 0x00 0. " UPD_REQ ,New real time counter sub second increment value availability" "Not available,Available"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCUBUSCTL,MCU Bus Control Register"
|
|
bitfld.long 0x00 0. " DISCONNECT_REQ ,AUX domain bus disconnect request" "Not requested,Requested"
|
|
rgroup.long 0x4C++0x07
|
|
line.long 0x00 "MCUBUSSTAT,MCU Bus Status Register"
|
|
bitfld.long 0x00 1. " DISCONNECTED ,AUX domain bus status" "Connected,Disconnected"
|
|
bitfld.long 0x00 0. " DISCONNECT_ACK ,DISCONNECTED acknowledgement" "Connected,Disconnected"
|
|
line.long 0x04 "AONCTLSTAT,AON Domain Control Status Register"
|
|
bitfld.long 0x04 1. " AUX_FORCE_ON ,AON_WUC:AUX_CTL.AUX_FORCE_ON status" "0,1"
|
|
bitfld.long 0x04 0. " SCE_RUN_EN ,AON_WUC:AUX_CTL.SCE_RUN_EN status" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "AUXIOLATCH,AUX Input Output Latch Register"
|
|
bitfld.long 0x00 0. " EN , AUX_AIODIO0/AUX_AIODIO1 signal latching" "Closed,Open"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MODCLKEN1,Module Clock Enable 1 Register"
|
|
bitfld.long 0x00 7. " AUX_ADI4 ,AUX_ADI4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AUX_DDI0_OSC ,AUX_DDI0_OSC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TDC ,AUX_TDC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ANAIF ,AUX_ANAIF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIMER ,AUX_TIMER clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AIODIO1 ,AUX_AIODIO1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AIODIO0 ,AUX_AIODIO0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMPH ,AUX_SMPH clock enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "TIMER (Timer)"
|
|
base ad:0x400C7000
|
|
width 10.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "T0CFG,Timer 0 Configuration Register"
|
|
bitfld.long 0x00 13. " TICK_SRC_POL ,Source count polarity for Timer 0" "Rising,Falling"
|
|
bitfld.long 0x00 8.--12. " TICK_SRC ,Tick source for Timer 0" "RTC_CH2_EV,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,,SMPH_AUTOTAKE_DONE,ADC_DONE,RTC_4KHZ,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PRE ,Prescaler division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
bitfld.long 0x00 1. " MODE ,Timer 0 mode" "2^PRE edges,TICK_SRC edges"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RELOAD ,Timer 0 Reload Settings" "Manually,Automatically"
|
|
line.long 0x04 "T1CFG,Timer 1 Configuration Register"
|
|
bitfld.long 0x04 13. " TICK_SRC_POL ,Source count polarity for Timer 1" "Rising,Falling"
|
|
bitfld.long 0x04 8.--12. " TICK_SRC ,Tick source for Timer 1" "RTC_CH2_EV,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,,SMPH_AUTOTAKE_DONE,ADC_DONE,RTC_4KHZ,OBSMUX0,OBSMUX1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " PRE ,Prescaler division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
bitfld.long 0x04 1. " MODE ,Timer 1 mode" "2^PRE edges,TICK_SRC edges"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RELOAD ,Timer 1 Reload Settings" "Manually,Automatically"
|
|
line.long 0x08 "T0CTL,Timer 0 Control Register"
|
|
bitfld.long 0x08 0. " EN ,Timer 0 enable" "Disabled,Enabled"
|
|
line.long 0x0C "T0TARGET,Timer 0 Target Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Upper limit for Timer 0"
|
|
line.long 0x10 "T1TARGET,Timer 1 Target Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " VALUE ,Upper limit for Timer 1"
|
|
line.long 0x14 "T1CTL,Timer 1 Control Register"
|
|
bitfld.long 0x14 0. " EN ,Timer 1 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMPH (Semaphore)"
|
|
base ad:0x400C8000
|
|
width 10.
|
|
hgroup.long 0x00++0x1F
|
|
hide.long 0x00 "SMPH0,Semaphore 0 Register"
|
|
in
|
|
hide.long 0x04 "SMPH1,Semaphore 1 Register"
|
|
in
|
|
hide.long 0x08 "SMPH2,Semaphore 2 Register"
|
|
in
|
|
hide.long 0x0C "SMPH3,Semaphore 3 Register"
|
|
in
|
|
hide.long 0x10 "SMPH4,Semaphore 4 Register"
|
|
in
|
|
hide.long 0x14 "SMPH5,Semaphore 5 Register"
|
|
in
|
|
hide.long 0x18 "SMPH6,Semaphore 6 Register"
|
|
in
|
|
hide.long 0x1C "SMPH7,Semaphore 7 Register"
|
|
in
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AUTOTAKE,Sticky Request For Single Semaphore Register"
|
|
bitfld.long 0x00 0.--2. " SMPH_ID ,Semaphore ID" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ANAIF (Analog Interface)"
|
|
base ad:0x400C9000
|
|
width 13.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADCCTL,ADC Control Register"
|
|
bitfld.long 0x00 13. " START_POL ,Start polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 8.--12. " START_SRC ,source for ADC conversion start event" "RTC_CH2_EV,AUX_COMPA,AUX_COMPB,TDC_DONE,TIMER0_EV,TIMER1_EV,SMPH_AUTOTAKE_DONE,,,NO_EVENT0,NO_EVENT1,AON_SW,AON_PROG_WU,AUXIO0,AUXIO1,AUXIO2,AUXIO3,AUXIO4,AUXIO5,AUXIO6,AUXIO7,AUXIO8,AUXIO9,AUXIO10,AUXIO11,AUXIO12,AUXIO13,AUXIO14,AUXIO15,ACLK_REF,MCU_EV,ADC_IRQ"
|
|
bitfld.long 0x00 0.--1. " CMD ,ADC interface control command" "Disabled,Enabled,,FIFO flush"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADCFIFOSTAT,ADC FIFO Status Register"
|
|
bitfld.long 0x00 4. " OVERFLOW ,FIFO overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 3. " UNDERFLOW ,FIFO underflow flag" "Not underflowed,Underflowed"
|
|
bitfld.long 0x00 2. " FULL ,FIFO full flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALMOST_FULL ,FIFO almost full flag" "Less than 3 samples,3 Samples"
|
|
bitfld.long 0x00 0. " EMPTY ,FIFO empty flag" "Not empty,Empty"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "ADCFIFO,ADC FIFO Register"
|
|
in
|
|
if (((d.l(ad:0x400C9000+0x10))&0x1F00)==(0x900||0xA00))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ADCTRIG,ADC Trigger Register"
|
|
bitfld.long 0x00 0. " START ,Start trigger" "No effect,Trigger"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "ADCTRIG,ADC Trigger Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ISRCCTL,Current Source Control Register"
|
|
bitfld.long 0x00 0. " RESET_N ,Current source control" "Clamped,Active/Charging"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADI4 (Analog Digital Interface)"
|
|
base ad:0x400CB000
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "MUX0,Multiplexer 0 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.byte 0x00 4.--7. " COMPA_IN ,COMPA_IN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " COMPA_REF ,COMPA_REF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "MUX1,Multiplexer 1 Register(Internal. Only to be used through TI provided API)"
|
|
line.byte 0x02 "MUX2,Multiplexer 2 Register(Internal. Only to be used through TI provided API)"
|
|
bitfld.byte 0x02 3.--7. " ADCCOMPB_IN ,ADCCOMPB_IN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x02 0.--2. " COMPB_REF ,COMPB_REF" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x03 "MUX3,Multiplexer 3 Register (Internal. Only to be used through TI provided API)"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ISRC,Current Source Register"
|
|
bitfld.byte 0x00 2.--7. " TRIM ,Adjust current from current source" "Not connected,0.25 uA,0.5 uA,,1 uA,,,,2 uA,,,,,,,,4.5 uA,,,,,,,,,,,,,,,,11.75 uA,?..."
|
|
bitfld.byte 0x00 0. " EN ,Current source enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x400CB000+0x04))&0x01)==0x01)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "COMP,Comparator Register"
|
|
bitfld.byte 0x00 7. " COMPA_REF_RES_EN ,400kohm resistance from COMPA reference node to ground enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " COMPA_REF_CURR_EN ,2uA IPTAT current from ISRC to COMPA reference enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--5. " COMPB_TRIM ,COMPB voltage reference trim temperature" "No division,Divide by 2,,Divide by 3,,,,Divide by 4"
|
|
bitfld.byte 0x00 2. " COMPB_EN ,Comparator B enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " COMPA_EN ,Comparator A enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "COMP,Comparator Register"
|
|
bitfld.byte 0x00 7. " COMPA_REF_RES_EN ,400kohm resistance from COMPA reference node to ground enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--5. " COMPB_TRIM ,COMPB voltage reference trim temperature" "No division,Divide by 2,,Divide by 3,,,,Divide by 4"
|
|
bitfld.byte 0x00 2. " COMPB_EN ,Comparator B enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " COMPA_EN ,Comparator A enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "MUX4,Multiplexer 4 Register (Internal. Only to be used through TI provided API)"
|
|
if (((d.b(ad:0x400CB000+0x08))&0x80)==0x00)
|
|
group.byte 0x08++0x02
|
|
line.byte 0x00 "ADC0,ADC Control 0 Register"
|
|
bitfld.byte 0x00 7. " SMPL_MODE ,ADC Sampling mode" "Synchronous,Asynchronous"
|
|
bitfld.byte 0x00 3.--6. " SMPL_CYCLE_EXP ,Sampling duration before conversion in ADC synchronous mode" ",,,2.7 us,5.3 us,10.6 us,21.3 us,42.6 us,85.3 us,170 us,341 us,682 us,1.37 ms,2.73 ms,5.46 ms,10.9 ms"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RESET_N ,Reset ADC digital subchip" "Reset,No reset"
|
|
bitfld.byte 0x00 0. " EN ,ADC Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "ADC1,ADC Control 1 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.byte 0x01 0. " SCALE_DIS ,SCALE_DIS (Internal. Only to be used through TI provided API)" "0,1"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "ADCREF0,ADC Reference 0 Register"
|
|
bitfld.byte 0x00 6. " REF_ON_IDLE ,ADC reference power up during IDLE state" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " IOMUX ,Internal. Only to be used through TI provided API" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " EXT ,Internal. Only to be used through TI provided API" "0,1"
|
|
bitfld.byte 0x00 3. " SRC ,ADC reference source" "Fixed 4.3V,Relative VDDS"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " EN ,ADC reference module enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x08++0x02
|
|
line.byte 0x00 "ADC0,ADC Control 0 Register"
|
|
bitfld.byte 0x00 7. " SMPL_MODE ,ADC Sampling mode" "Synchronous,Asynchronous"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RESET_N ,Reset ADC digital subchip" "Reset,No reset"
|
|
bitfld.byte 0x00 0. " EN ,ADC Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "ADC1,ADC Control 1 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.byte 0x01 0. " SCALE_DIS ,SCALE_DIS (Internal. Only to be used through TI provided API)" "0,1"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "ADCREF0,ADC Reference 0 Register"
|
|
bitfld.byte 0x00 5. " IOMUX ,Internal. Only to be used through TI provided API" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " EXT ,Internal. Only to be used through TI provided API" "0,1"
|
|
bitfld.byte 0x00 3. " SRC ,ADC reference source" "Fixed 4.3V,Relative VDDS"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " EN ,ADC reference module enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.b(ad:0x400CB000+0x0A))&0x08)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "ADCREF1,ADC Reference 1 Register"
|
|
bitfld.byte 0x00 0.--5. " VTRIM ,Trim output voltage of ADC fixed reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x0B++0x00
|
|
hide.byte 0x00 "ADCREF1,ADC Reference 1 Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "AON BATMON (Always On Battery and Temperature Monitor)"
|
|
base ad:0x40095000
|
|
width 13.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTL,Control Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x00 1. " CALC_EN ,Calculation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MEAS_EN ,Measurement Enable" "Disabled,Enabled"
|
|
line.long 0x04 "MEASCFG,Measurement Periode Configuration Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x04 0.--1. " PER ,Periode" "0,8,16,32"
|
|
group.long 0x0C++0x1B
|
|
line.long 0x00 "TEMPP0,Temperature Calculation Parameter 0 Register (Internal. Only to be used through TI provided API)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CFG ,Configuration"
|
|
line.long 0x04 "TEMPP1,Temperature Calculation Parameter 1 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x04 0.--5. " CFG ,Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "TEMPP2,Temperature Calculation Parameter 2 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x08 0.--4. " CFG ,Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "BATMONP0,Battery Voltage Calculation Parameter 0 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x0C 0.--5. " CFG ,Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "BATMONP1,Battery Voltage Calculation Parameter 1 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x10 0.--5. " CFG ,Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "IOSTRP0,IO Drive Strength Conversion Parameter 0 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x14 4.--5. " CFG2 ,Configuration 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--3. " CFG1 ,Configuration 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "FLASHPUMPP0,Flash Pump Conversion Parameter 0 Register (Internal. Only to be used through TI provided API)"
|
|
bitfld.long 0x18 8. " FALLB ,FALLB" "0,1"
|
|
bitfld.long 0x18 6.--7. " HIGHLIM ,HIGHLIM" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x18 5. " LOWLIM ,LOWLIM" "0,1"
|
|
bitfld.long 0x18 4. " OVR ,Overflow" "Not overflowed,Overflow"
|
|
textline " "
|
|
bitfld.long 0x18 0.--3. " CFG ,Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l(ad:0x40095000+0x2C))&0x01)==0x01)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "BAT,Last Measured Battery Voltage Register"
|
|
bitfld.long 0x00 8.--10. " INT ,Integer part" "0 V,1 V,2 V,3 V,4 V,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRAC ,Fractional part"
|
|
else
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "BAT,Last Measured Battery Voltage Register"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BATUPD,Battery Update"
|
|
eventfld.long 0x00 0. " STAT ,Status" "Not updated,New battery voltage"
|
|
if (((d.l(ad:0x40095000+0x34))&0x01)==0x01)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEMP,Temperature Register"
|
|
hexmask.long.word 0x00 8.--16. 1. " INT ,Integer part"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TEMP,Temperature Register"
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TEMPUPD,Temperature Update"
|
|
eventfld.long 0x00 0. " STAT ,Status" "Not updated,New temperature"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver and Transmitter)"
|
|
base ad:0x40001000
|
|
width 8.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "DR,Data Register"
|
|
in
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RSR,Status Register"
|
|
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
|
|
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
|
|
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ECR,Error Clear Register"
|
|
bitfld.long 0x00 3. " OE ,Overrun Error" "Clear,Clear"
|
|
bitfld.long 0x00 2. " BE ,Break Error" "Clear,Clear"
|
|
bitfld.long 0x00 1. " PE ,Parity Error" "Clear,Clear"
|
|
bitfld.long 0x00 0. " FE ,Framing Error" "Clear,Clear"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "FR,Flag Register"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY ,Busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTS ,Clear to Send" "High,Low"
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "IBRD,Integer Baud-Rate Divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVINT ,Integer baud rate divisor"
|
|
line.long 0x04 "FBRD,Fractional Baud-Rate Divisor"
|
|
bitfld.long 0x04 0.--5. " DIVFRAC ,Fractional baud rate divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "LCRH,Line Control Register"
|
|
bitfld.long 0x08 7. " SPS ,UART Stick Parity Select" "Disabled,Enabled"
|
|
bitfld.long 0x08 5.--6. " WLEN ,UART Word Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x08 4. " FEN ,UART FIFOs Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " STP2 ,UART Two Stop Bits Select" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EPS ,UART Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x08 1. " PEN ,UART Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " BRK ,UART Send Break" "No break,Break"
|
|
line.long 0x0C "CTL,Control Register"
|
|
bitfld.long 0x0C 15. " CTSEN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " RTSEN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " RTS ,Request to Send" "High,Low"
|
|
bitfld.long 0x0C 9. " RXE ,UART Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " TXE ,UART Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " LBE ,UART Loop Back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x10 "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0x10 3.--5. " RXSEL ,Receive interrupt FIFO level select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
bitfld.long 0x10 0.--2. " TXSEL ,Transmit interrupt FIFO level select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
line.long 0x14 "IMSC,Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x14 10. " OEIM ,Overrun error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x14 9. " BEIM ,Break error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x14 8. " PEIM ,Parity error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x14 7. " FEIM ,Framing error interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x14 6. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x14 5. " TXIM ,Transmit interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x14 4. " RXIM ,Receive interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x14 1. " CTSMIM ,Clear to Send modem interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
rgroup.long 0x3C++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 10. " OERIS ,Overrun error interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " BERIS ,Break error interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " PERIS ,Parity error interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " FERIS ,Framing error interrupt status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTRIS ,Receive timeout interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " RXRIS ,Receive interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CTSRMIS ,Clear to Send interrupt status" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 10. " OEMIS ,Overrun error masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 9. " BEMIS ,Break error masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 8. " PEMIS ,Parity error masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 7. " FEMIS ,Framing error masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RTMIS ,Receive timeout masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 5. " TXMIS ,Transmit masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 4. " RXMIS ,Receive masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 1. " CTSMMIS ,Clear to Send masked interrupt status" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 10. " OEIC ,Overrun error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " BEIC ,Break error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " PEIC ,Parity error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " FEIC ,Framing error interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIC ,Receive timeout interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXIC ,Transmit interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RXIC ,Receive interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTSMIC ,Clear to Send interrupt clear" "No effect,Clear"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACTL,DMA Control Register"
|
|
bitfld.long 0x00 2. " DMAONERR ,DMA on error" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SSI (Synchronous Serial Interface)"
|
|
tree "SSI_0"
|
|
base ad:0x40000000
|
|
width 7.
|
|
if (((d.l(ad:0x40000000))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPH ,CLKOUT phase" "First edge,Second edge"
|
|
bitfld.long 0x00 6. " SPO ,CLKOUT polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "Motorola,TI synchronous,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "Motorola,TI synchronous,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
endif
|
|
if (((d.l(ad:0x40000000+0x04))&0x06)==0x06)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
bitfld.long 0x00 3. " SOD ,Slave-mode output disabled" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
elif (((d.l(ad:0x40000000+0x04))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
bitfld.long 0x00 3. " SOD ,Slave-mode output disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
elif (((d.l(ad:0x40000000+0x04))&0x06)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
endif
|
|
textline ""
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "DR,Data Register"
|
|
in
|
|
textline ""
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Serial interface busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Clock prescale divisor"
|
|
line.long 0x04 "IMSC,Interrupt Mask Set and Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,Transmit FIFO interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " RXIM ,Receive FIFO interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Raw transmit FIFO interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " RXRIS ,Raw interrupt state of receive FIFO interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTRIS ,Raw interrupt state of receive timeout interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " RORRIS ,Raw interrupt state of receive overrun interrupt" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,Masked interrupt state of transmit FIFO interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,Masked interrupt state of receive FIFO interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RTMIS ,Masked interrupt state of receive timeout interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Masked interrupt state of receive overrun interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Clear the receive timeout interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clear the receive overrun interrupt" "No effect,Clear"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSI_1"
|
|
base ad:0x40008000
|
|
width 7.
|
|
if (((d.l(ad:0x40008000))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPH ,CLKOUT phase" "First edge,Second edge"
|
|
bitfld.long 0x00 6. " SPO ,CLKOUT polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "Motorola,TI synchronous,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "Motorola,TI synchronous,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
endif
|
|
if (((d.l(ad:0x40008000+0x04))&0x06)==0x06)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
bitfld.long 0x00 3. " SOD ,Slave-mode output disabled" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
elif (((d.l(ad:0x40008000+0x04))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
bitfld.long 0x00 3. " SOD ,Slave-mode output disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
elif (((d.l(ad:0x40008000+0x04))&0x06)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control 1 Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MS ,Master or slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous serial interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loop back"
|
|
endif
|
|
textline ""
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "DR,Data Register"
|
|
in
|
|
textline ""
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Serial interface busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Clock prescale divisor"
|
|
line.long 0x04 "IMSC,Interrupt Mask Set and Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,Transmit FIFO interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " RXIM ,Receive FIFO interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Raw transmit FIFO interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " RXRIS ,Raw interrupt state of receive FIFO interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTRIS ,Raw interrupt state of receive timeout interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " RORRIS ,Raw interrupt state of receive overrun interrupt" "Not occurred,Occurred"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,Masked interrupt state of transmit FIFO interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,Masked interrupt state of receive FIFO interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RTMIS ,Masked interrupt state of receive timeout interrupt" "No interrupt or disabled,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Masked interrupt state of receive overrun interrupt" "No interrupt or disabled,Interrupt"
|
|
textline " "
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Clear the receive timeout interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clear the receive overrun interrupt" "No effect,Clear"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x40002000
|
|
width 7.
|
|
tree "Slave"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SOAR,Slave Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OAR ,I2C slave own address"
|
|
if (((d.l(ad:0x40002000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SSTAT,Slave Status Register"
|
|
bitfld.long 0x00 2. " FBR ,First byte received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TREQ ,Transmit request" "No request,Request"
|
|
bitfld.long 0x00 0. " RREQ ,Receive request" "No request,Request"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SSTAT,Slave Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TREQ ,Transmit request" "No request,Request"
|
|
bitfld.long 0x00 0. " RREQ ,Receive request" "No request,Request"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "SCTL,Slave Control Register"
|
|
bitfld.long 0x00 0. " DA ,Device active" "Disable,Enable"
|
|
textline ""
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SDR,Slave Data Register"
|
|
in
|
|
textline ""
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIMR,Slave Interrupt Mask Register"
|
|
bitfld.long 0x00 2. " STOPIM ,Stop condition interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " STARTIM ,Start condition interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " DATAIM ,Data interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "SRIS,Slave Raw Interrupt Status Register"
|
|
bitfld.long 0x00 2. " STOPRIS ,Stop condition raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " STARTRIS ,Start condition raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DATARIS ,Data raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "SMIS,Slave Masked Interrupt Status Register"
|
|
bitfld.long 0x04 2. " STOPMIS ,Stop condition masked interrupt status" "No interrupt or masked,Interrupt"
|
|
bitfld.long 0x04 1. " STARTMIS ,Start condition masked interrupt status" "No interrupt or masked,Interrupt"
|
|
bitfld.long 0x04 0. " DATAMIS ,Data masked interrupt status" "No interrupt or masked,Interrupt"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "SICR,Slave Interrupt Clear Register"
|
|
bitfld.long 0x00 2. " STOPIC ,Stop condition interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " STARTIC ,Start condition interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DATAIC ,Data interrupt clear" "No effect,Clear"
|
|
tree.end
|
|
tree "Master"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "MSA,Master Salve Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SA ,I2C master slave address"
|
|
bitfld.long 0x00 0. " RS ,Receive or Send" "Transmit,Receive"
|
|
if (((d.l(ad:0x40002000+0x804))&0x01)==0x00)
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "MSTAT,Master Status Register"
|
|
bitfld.long 0x00 6. " BUSBSY ,Bus busy" "Idle,Busy"
|
|
bitfld.long 0x00 5. " IDLE ,I2C idle" "Not idle,Idle"
|
|
bitfld.long 0x00 4. " ARBLST ,Arbitration lost" "Won,Lost"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATACK_N ,Data Was Not Acknowledged" "Acknowledged,Not acknowledged"
|
|
bitfld.long 0x00 2. " ADRACK_N ,Address Was Not Acknowledged" "Acknowledged,Not acknowledged"
|
|
bitfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUSY ,I2C busy" "Idle,Busy"
|
|
else
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "MSTAT,Master Status Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUSY ,I2C busy" "Idle,Busy"
|
|
endif
|
|
wgroup.long 0x804++0x03
|
|
line.long 0x00 "MCTRL,Master Control Register"
|
|
bitfld.long 0x00 3. " ACK ,Data acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " STOP ,Stop condition" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " START ,Start condition" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,I2C master enable" "Disabled,Enabled"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "MDR,Master Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data for transfer"
|
|
group.long 0x80C++0x07
|
|
line.long 0x00 "MTPR,I2C Master Timer Period Register"
|
|
bitfld.long 0x00 7. " TPR_7 ,SCSCL clock period enable" "Enabled,Disabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TPR ,SCSCL clock period"
|
|
line.long 0x04 "MIMR,Master Interrupt Mask Register"
|
|
bitfld.long 0x04 0. " IM ,Interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
rgroup.long 0x814++0x07
|
|
line.long 0x00 "MRIS,Master Raw Interrupt Status Register"
|
|
bitfld.long 0x00 0. " RIS ,Raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "MMIS,Master Masked Interrupt Status Register"
|
|
bitfld.long 0x04 0. " MIS ,Masked interrupt status" "No interrupt or masked,Interrupt"
|
|
wgroup.long 0x81C++0x03
|
|
line.long 0x00 "MICR,Master Interrupt Clear Register"
|
|
bitfld.long 0x00 0. " IC ,Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "MCR,Master Configuration Register"
|
|
bitfld.long 0x00 5. " SFE ,I2C slave function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MFE ,I2C master function enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LPBK ,I2C loopback" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2S (Integrated Interchip Sound)"
|
|
base ad:0x40021000
|
|
width 15.
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "AIFWCLKSRC,WCLK Source Selection Register"
|
|
bitfld.long 0x00 2. " WCLK_INV ,Inverts WCLK source" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " WCLK_SRC ,WCLK source" "None,External,Internal,None"
|
|
line.long 0x04 "AIFDMACFG,DMA Buffer Size Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " END_FRAME_IDX ,End frame IDX"
|
|
line.long 0x08 "AIFDIRCFG,Pin Direction Register"
|
|
bitfld.long 0x08 8.--9. " AD2 ,Configures the AD2 audio data pin" "Disabled,Input,Output,?..."
|
|
bitfld.long 0x08 4.--5. " AD1 ,Configures the AD1 audio data pin" "Disabled,Input,Output,?..."
|
|
bitfld.long 0x08 0.--1. " AD0 ,Configures the AD0 audio data pin" "Disabled,Input,Output,?..."
|
|
line.long 0x0C "AIFFMTCFG,Serial Interface Format Configuration Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_DELAY ,The number of BCLK periods between a WCLK edge and MSB of the first word in a phase"
|
|
bitfld.long 0x0C 7. " MEM_LEN_24 ,The size of each word stored to or loaded from memory" "16-bits,24-bits"
|
|
bitfld.long 0x0C 6. " SMPL_EDGE ,Sampled/clocked edge" "Negative/positive,Positive/negative"
|
|
bitfld.long 0x0C 5. " DUAL_PHASE ,Dual-phase or single-phase format" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--4. " WORD_LEN ,Number of bits per word" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
textline " "
|
|
line.long 0x10 "AIFWMASK0,Word Selection Bit Mask for Pin 0 Register"
|
|
bitfld.long 0x10 7. " CH7 ,Channel 7 mask" "0,1"
|
|
bitfld.long 0x10 6. " CH6 ,Channel 6 mask" "0,1"
|
|
bitfld.long 0x10 5. " CH5 ,Channel 5 mask" "0,1"
|
|
bitfld.long 0x10 4. " CH4 ,Channel 4 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CH3 ,Channel 3 mask" "0,1"
|
|
bitfld.long 0x10 2. " CH2 ,Channel 2 mask" "0,1"
|
|
bitfld.long 0x10 1. " CH1 ,Channel 1 mask" "0,1"
|
|
bitfld.long 0x10 0. " CH0 ,Channel 0 mask" "0,1"
|
|
line.long 0x14 "AIFWMASK1,Word Selection Bit Mask for Pin 1 Register"
|
|
bitfld.long 0x14 7. " CH7 ,Channel 7 mask" "0,1"
|
|
bitfld.long 0x14 6. " CH6 ,Channel 6 mask" "0,1"
|
|
bitfld.long 0x14 5. " CH5 ,Channel 5 mask" "0,1"
|
|
bitfld.long 0x14 4. " CH4 ,Channel 4 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " CH3 ,Channel 3 mask" "0,1"
|
|
bitfld.long 0x14 2. " CH2 ,Channel 2 mask" "0,1"
|
|
bitfld.long 0x14 1. " CH1 ,Channel 1 mask" "0,1"
|
|
bitfld.long 0x14 0. " CH0 ,Channel 0 mask" "0,1"
|
|
line.long 0x18 "AIFWMASK2,Word Selection Bit Mask for Pin 2 Register"
|
|
bitfld.long 0x18 7. " CH7 ,Channel 7 mask" "0,1"
|
|
bitfld.long 0x18 6. " CH6 ,Channel 6 mask" "0,1"
|
|
bitfld.long 0x18 5. " CH5 ,Channel 5 mask" "0,1"
|
|
bitfld.long 0x18 4. " CH4 ,Channel 4 mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " CH3 ,Channel 3 mask" "0,1"
|
|
bitfld.long 0x18 2. " CH2 ,Channel 2 mask" "0,1"
|
|
bitfld.long 0x18 1. " CH1 ,Channel 1 mask" "0,1"
|
|
bitfld.long 0x18 0. " CH0 ,Channel 0 mask" "0,1"
|
|
textline " "
|
|
line.long 0x1C "AIFPWMVALUE,Audio Interface PWM Debug Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " PULSE_WIDTH ,Width of the active high PWM pulse"
|
|
line.long 0x20 "AIFINPTRNEXT,DMA Input Buffer Next Pointer Register"
|
|
line.long 0x24 "AIFINPTR,DMA Input Buffer Current Pointer Register"
|
|
line.long 0x28 "AIFOUTPTRNEXT,DMA Output Buffer Next Pointer Register"
|
|
line.long 0x2C "AIFOUTPTR,DMA Output Buffer Current Pointer Register"
|
|
textline " "
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "STMPCTL,SampleStaMP Generator Control Register"
|
|
rbitfld.long 0x00 2. " OUT_RDY ,Output ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 1. " IN_RDY ,Input ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " STMP_EN ,Samplestamp generator enable" "Disabled,Enabled"
|
|
rgroup.long 0x38++0x0B
|
|
line.long 0x00 "STMPXCNTCAPT0,Captured XOSC Counter Value, Capture Channel 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPT_VALUE ,The value of the samplestamp XOSC counter"
|
|
line.long 0x04 "STMPXPER,XOSC Period Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,The number of 24 MHz clock cycles in the previous WCLK period"
|
|
line.long 0x08 "STMPWCNTCAPT0,Captured WCLK Counter Value, Capture Channel 0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAPT_VALUE ,The value of the samplestamp WCLK counter"
|
|
group.long 0x44++0x17
|
|
line.long 0x00 "STMPWPER,WCLK Counter Period Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Modulo value for the WCLK counter"
|
|
line.long 0x04 "STMPINTRIG,WCLK Counter Trigger Value for Input Pins Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " IN_START_WCNT ,Compare value used to start the incoming audio streams"
|
|
line.long 0x08 "STMPOUTTRIG,WCLK Counter Trigger Value for Output Pins Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " OUT_START_WCNT ,Compare value used to start the outgoing audio streams"
|
|
line.long 0x0C "STMPWSET,WCLK Counter Set Operation Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Sets the running WCLK counter equal to the written value"
|
|
line.long 0x10 "STMPWADD,WCLK Counter Add Operation Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " VALUE_INC ,Adds the written value to the running WCLK counter"
|
|
line.long 0x14 "STMPXPERMIN,XOSC Minimum Period Value Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " VALUE ,Minimum Value of STMPXPER"
|
|
rgroup.long 0x5C++0x0F
|
|
line.long 0x00 "STMPWCNT,Current Value of WCNT Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_VALUE ,Current value of the WCLK counter"
|
|
line.long 0x04 "STMPXCNT,Current Value of XCNT Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURR_VALUE ,Current value of the XOSC counter"
|
|
line.long 0x08 "STMPXCNTCAPT1,Captured XOSC Counter Value, Capture Channel 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAPT_VALUE ,The value of the samplestamp XOSC counter"
|
|
line.long 0x0C "STMPWCNTCAPT1,Captured WCLK Counter Value, Capture Channel 1 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CAPT_VALUE ,The value of the samplestamp WCLK counter"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "IRQMASK,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 5. " AIF_DMA_IN ,AIF DMA input interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AIF_DMA_OUT ,AIF DMA output interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WCLK_TIMEOUT ,WCLK timeout interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BUS_ERR ,BUS error interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WCLK_ERR ,WCLK error interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTR_ERR ,PTR error interrupt mask" "Disabled,Enabled"
|
|
line.long 0x04 "IRQFLAGS,Raw Interrupt Status Register"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " AIF_DMA_IN ,AIF DMA input interrupt" "Clear,Set"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " AIF_DMA_OUT ,AIF DMA output interrupt" "Clear,Set"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " WCLK_TIMEOUT ,WCLK timeout interrupt" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " BUS_ERR ,BUS error interrupt" "Clear,Set"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " WCLK_ERR ,WCLK error interrupt" "Clear,Set"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " PTR_ERR ,PTR error interrupt" "Clear,Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RFC (RF Core)"
|
|
tree "RF Core Doorbell"
|
|
base ad:0x40041000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CMDR,Doorbell Command Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CMDSTA,Doorbell Command Status Register"
|
|
group.long 0x08++0x1B
|
|
line.long 0x00 "RFHWIFG,RF Hardware Modules Interrupt Flags Register"
|
|
bitfld.long 0x00 19. " RATCH7 ,Radio timer channel 7 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RATCH6 ,Radio timer channel 6 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " RATCH5 ,Radio timer channel 5 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " RATCH4 ,Radio timer channel 4 interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RATCH3 ,Radio timer channel 3 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RATCH2 ,Radio timer channel 2 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " RATCH1 ,Radio timer channel 1 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RATCH0 ,Radio timer channel 0 interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RFESOFT2 ,RF engine software defined interrupt 2 flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RFESOFT1 ,RF engine software defined interrupt 1 flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " RFESOFT0 ,RF engine software defined interrupt 0 flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RFEDONE ,RF engine command done interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRCTK ,Debug tracer system tick interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " MDMSOFT ,Modem synchronization word detection interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " MDMOUT ,Modem FIFO output interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " MDMIN ,Modem FIFO input interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MDMDONE ,Modem command done interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " FSCA ,Frequency synthesizer calibration accelerator interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x04 "RFHWIEN,RF Hardware Modules Interrupt Enable Register"
|
|
bitfld.long 0x04 19. " RATCH7 ,Radio timer channel 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " RATCH6 ,Radio timer channel 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " RATCH5 ,Radio timer channel 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " RATCH4 ,Radio timer channel 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RATCH3 ,Radio timer channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RATCH2 ,Radio timer channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RATCH1 ,Radio timer channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RATCH0 ,Radio timer channel 0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RFESOFT2 ,RF engine software defined interrupt 2 flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RFESOFT1 ,RF engine software defined interrupt 1 flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " RFESOFT0 ,RF engine software defined interrupt 0 flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RFEDONE ,RF engine command done interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TRCTK ,Debug tracer system tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " MDMSOFT ,Modem synchronization word detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " MDMOUT ,Modem FIFO output interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " MDMIN ,Modem FIFO input interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MDMDONE ,Modem command done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " FSCA ,Frequency synthesizer calibration accelerator interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "RFCPEIFG,Command and Packet Engine Generated Interrupts Interrupt Flags Register"
|
|
bitfld.long 0x08 31. " INTERNAL_ERROR ,CPE unexpected error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " BOOT_DONE ,CPE boot finished interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " MODULES_UNLOCKED ,CPE boot process RF core modules and memories unlocked interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " SYNTH_NO_LOCK ,Frequency synthesizer PLL lock lost interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 27. " IRQ27 ,Interrupt flag 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " RX_ABORTED ,Reception aborted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " RX_N_DATA_WRITTEN ,Specified number of bytes written to partial read Rx buffer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " RX_DATA_WRITTEN ,Partial read buffer data written interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 23. " RX_ENTRY_DONE ,Receive queue data entry changing state to finished interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " RX_BUF_FULL ,BLE Receive buffer full interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif !cpuis("CC2620*")&&!cpuis("CC2630*")&&!cpuis("CC1310*")
|
|
bitfld.long 0x08 21. " RX_CTRL_ACK ,BLE LL control packet received acknowledgement interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 20. " RX_CTRL ,BLE LL control packet received interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 19. " RX_EMPTY ,BLE empty packet received interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif cpuis("CC2620*")||cpuis("CC2630*")||cpuis("CC1310*")
|
|
bitfld.long 0x08 18. " RX_IGNORED ,IEEE 802.15.4 frame ignored interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " RX_NOK ,IEEE 802.15.4 frame CRC error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " RX_OK ,IEEE 802.15.4 frame CRC OK interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif cpuis("CC2640*")
|
|
bitfld.long 0x08 18. " RX_IGNORED ,BLE packet ignored interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " RX_NOK ,BLE packet CRC error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " RX_OK ,BLE packet CRC OK interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 18. " RX_IGNORED ,BLE packet/IEEE 802.15.4 frame ignored interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " RX_NOK ,BLE packet/IEEE 802.15.4 frame CRC error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " RX_OK ,BLE packet/IEEE 802.15.4 frame CRC OK interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15. " IRQ15 ,Interrupt flag 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " IRQ14 ,Interrupt flag 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " IRQ13 ,Interrupt flag 13" "No interrupt,Interrupt"
|
|
sif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x08 12. " IRQ12 ,Interrupt flag 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 11. " TX_BUFFER_CHANGED ,BLE buffer change after CMD_BLE_ADV_PAYLOAD completed interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " TX_ENTRY_DONE ,Transmit queue data entry state changed to finished interrupt flag" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x08 12. " IRQ12 ,Interrupt flag 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " TX_ENTRY_DONE ,Transmit queue data entry state changed to finished interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
sif !cpuis("CC2620*")&&!cpuis("CC2630*")&&!cpuis("CC1310*")
|
|
textline " "
|
|
bitfld.long 0x08 9. " TX_RETRANS ,BLE packet retransmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " TX_CTRL_ACK_ACK ,BLE acknowledgement on transmitted LL control packet acknowledgement interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 7. " TX_CTRL_ACK ,BLE transmitted LL control packet acknowledgement interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TX_CTRL ,BLE LL control packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
sif cpuis("CC2620*")||cpuis("CC2630*")||cpuis("CC1310*")
|
|
textline " "
|
|
bitfld.long 0x08 5. " TX_ACK ,IEEE 802.15.4 frame auto ACK transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TX_DONE ,IEEE 802.15.4 frame transmitted interrupt flag" "No interrupt,Interrupt"
|
|
elif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x08 5. " TX_ACK ,BLE transmitted packet ACK receive interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TX_DONE ,BLE packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x08 5. " TX_ACK ,BLE transmitted packet ACK receive/IEEE 802.15.4 frame auto ACK transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TX_DONE ,BLE packet/IEEE 802.15.4 frame transmitted interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
sif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x08 1. " LAST_COMMAND_DONE ,Last radio operation command finished interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " COMMAND_DONE ,Radio operation command finished interrupt flag" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x08 3. " LAST_FG_COMMAND_DONE ,IEEE 802.15.4 last foreground radio operation command finished interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " FG_COMMAND_DONE ,IEEE 802.15.4 foreground radio operation command finished interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " LAST_COMMAND_DONE ,IEEE 802.15.4 last background radio operation command finished interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " COMMAND_DONE ,IEEE 802.15.4 background radio operation command finished interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x0C "RFCPEIEN,Command and Packet Engine Generated Interrupts Interrupt Enable Register"
|
|
bitfld.long 0x0C 31. " INTERNAL_ERROR ,CPE unexpected error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " BOOT_DONE ,CPE boot finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " MODULES_UNLOCKED ,CPE boot process RF core modules and memories unlocked interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " SYNTH_NO_LOCK ,Frequency synthesizer PLL lock lost interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " IRQ27 ,Interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " RX_ABORTED ,Receive aborted interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " RX_N_DATA_WRITTEN ,Specified number of bytes written to partial read Rx buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " RX_DATA_WRITTEN ,Partial read buffer data written interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " RX_ENTRY_DONE ,Receive queue data entry changing state to finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " RX_BUF_FULL ,BLE Receive buffer full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("CC2620*")&&!cpuis("CC2630*")&&!cpuis("CC1310*")
|
|
bitfld.long 0x0C 21. " RX_CTRL_ACK ,BLE LL control packet received acknowledgement interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " RX_CTRL ,BLE LL control packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " RX_EMPTY ,BLE empty packet received interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("CC2620*")||cpuis("CC2630*")||cpuis("CC1310*")
|
|
bitfld.long 0x0C 18. " RX_IGNORED ,IEEE 802.15.4 frame ignored interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " RX_NOK ,IEEE 802.15.4 frame CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " RX_OK ,IEEE 802.15.4 frame CRC OK interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("CC2640*")
|
|
bitfld.long 0x0C 18. " RX_IGNORED ,BLE packet frame ignored interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " RX_NOK ,BLE packet frame CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " RX_OK ,BLE packet frame CRC OK interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 18. " RX_IGNORED ,BLE packet/IEEE 802.15.4 frame ignored interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " RX_NOK ,BLE packet/IEEE 802.15.4 frame CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " RX_OK ,BLE packet/IEEE 802.15.4 frame CRC OK interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 15. " IRQ15 ,Interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " IRQ14 ,Interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " IRQ13 ,Interrupt enable 13" "Disabled,Enabled"
|
|
sif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x0C 12. " IRQ12 ,Interrupt enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " TX_BUFFER_CHANGED ,BLE buffer change after CMD_BLE_ADV_PAYLOAD completed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " TX_ENTRY_DONE ,Transmit queue data entry state changed to finished interrupt enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0C 12. " IRQ12 ,Interrupt enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " TX_ENTRY_DONE ,Transmit queue data entry state changed to finished interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("CC2620*")&&!cpuis("CC2630*")&&!cpuis("CC1310*")
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_RETRANS ,BLE packet retransmitted interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " TX_CTRL_ACK ,BLE acknowledgement on transmitted LL control packet acknowledgement interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " TX_CTRL_ACK ,BLE transmitted LL control packet acknowledgement interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " TX_CTRL ,BLE LL control packet transmitted interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("CC2620*")||cpuis("CC2630*")||cpuis("CC1310*")
|
|
textline " "
|
|
bitfld.long 0x0C 5. " TX_ACK ,IEEE 802.15.4 frame auto ACK transmitted interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TX_DONE ,IEEE 802.15.4 frame transmitted interrupt enable" "Disabled,Enabled"
|
|
elif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x0C 5. " TX_ACK ,BLE transmitted packet ACK receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TX_DONE ,BLE packet transmitted interrupt enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0C 5. " TX_ACK ,BLE transmitted packet ACK receive/IEEE 802.15.4 frame auto ACK transmitted interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TX_DONE ,BLE packet/IEEE 802.15.4 frame transmitted interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LAST_COMMAND_DONE ,Last radio operation command finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " COMMAND_DONE ,Radio operation command finished interrupt enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0C 3. " LAST_FG_COMMAND_DONE ,IEEE 802.15.4 last foreground radio operation command finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " FG_COMMAND_DONE ,IEEE 802.15.4 foreground radio operation command finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LAST_COMMAND_DONE ,IEEE 802.15.4 last background radio operation command finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " COMMAND_DONE ,IEEE 802.15.4 background radio operation command finished interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x10 "RFCPEISL,Command and Packet Engine Generated Interrupts Interrupt Vector Select Register"
|
|
bitfld.long 0x10 31. " INTERNAL_ERROR ,CPE unexpected error interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 30. " BOOT_DONE ,CPE boot finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 29. " MODULES_UNLOCKED ,CPE boot process RF core modules and memories unlocked interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 28. " SYNTH_NO_LOCK ,Frequency synthesizer PLL lock lost interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
bitfld.long 0x10 27. " IRQ27 ,Interrupt vector select 27" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 26. " RX_ABORTED ,Receive aborted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 25. " RX_N_DATA_WRITTEN ,Specified number of bytes written to partial read Rx buffer interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 24. " RX_DATA_WRITTEN ,Partial read buffer data written interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " RX_ENTRY_DONE ,Receive queue data entry changing state to finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 22. " RX_BUF_FULL ,BLE Receive buffer full interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
sif !cpuis("CC2620*")&&!cpuis("CC2630*")&&!cpuis("CC1310*")
|
|
bitfld.long 0x10 21. " RX_CTRL_ACK ,BLE LL control packet received acknowledgement interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 20. " RX_CTRL ,BLE LL control packet received interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 19. " RX_EMPTY ,BLE empty packet received interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
endif
|
|
sif cpuis("CC2620*")||cpuis("CC2630*")||cpuis("CC1310*")
|
|
bitfld.long 0x10 18. " RX_IGNORED ,IEEE 802.15.4 frame ignored interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 17. " RX_NOK ,IEEE 802.15.4 frame CRC error interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 16. " RX_OK ,IEEE 802.15.4 frame CRC OK interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
elif cpuis("CC2640*")
|
|
bitfld.long 0x10 18. " RX_IGNORED ,BLE packet ignored interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 17. " RX_NOK ,BLE packet CRC error interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 16. " RX_OK ,BLE packet CRC OK interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 18. " RX_IGNORED ,BLE packet/IEEE 802.15.4 frame ignored interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 17. " RX_NOK ,BLE packet/IEEE 802.15.4 frame CRC error interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 16. " RX_OK ,BLE packet/IEEE 802.15.4 frame CRC OK interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 15. " IRQ15 ,Interrupt vector select 15" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 14. " IRQ14 ,Interrupt vector select 14" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 13. " IRQ13 ,Interrupt vector select 13" "INT_RF_CPE0,INT_RF_CPE1"
|
|
sif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x10 12. " IRQ12 ,Interrupt 12 vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 11. " TX_BUFFER_CHANGED ,BLE buffer change after CMD_BLE_ADV_PAYLOAD completed interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 10. " TX_ENTRY_DONE ,Transmit queue data entry state changed to finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 12. " IRQ12 ,Interrupt 12 vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 10. " TX_ENTRY_DONE ,Transmit queue data entry state changed to finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
endif
|
|
sif !cpuis("CC2620*")&&!cpuis("CC2630*")&&!cpuis("CC1310*")
|
|
textline " "
|
|
bitfld.long 0x10 9. " TX_RETRANS ,BLE packet retransmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 8. " TX_CTRL_ACK ,BLE acknowledgement on transmitted LL control packet acknowledgement interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 7. " TX_CTRL_ACK ,BLE transmitted LL control packet acknowledgement interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 6. " TX_CTRL ,BLE LL control packet transmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
endif
|
|
sif cpuis("CC2620*")||cpuis("CC2630*")||cpuis("CC1310*")
|
|
textline " "
|
|
bitfld.long 0x10 5. " TX_ACK ,IEEE 802.15.4 frame auto ACK transmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 4. " TX_DONE ,IEEE 802.15.4 frame transmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
elif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x10 5. " TX_ACK ,BLE transmitted packet ACK receive interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 4. " TX_DONE ,BLE packet transmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 5. " TX_ACK ,BLE transmitted packet ACK receive/IEEE 802.15.4 frame auto ACK transmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 4. " TX_DONE ,BLE packet/IEEE 802.15.4 frame transmitted interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
endif
|
|
sif cpuis("CC2640*")
|
|
textline " "
|
|
bitfld.long 0x10 1. " LAST_COMMAND_DONE ,Last radio operation command finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 0. " COMMAND_DONE ,Radio operation command finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x10 3. " LAST_FG_COMMAND_DONE ,IEEE 802.15.4 last foreground radio operation command done interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 2. " FG_COMMAND_DONE ,IEEE 802.15.4 foreground radio operation command done interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 1. " LAST_COMMAND_DONE ,Last (IEEE 802.15.4 background level) radio operation command finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
bitfld.long 0x10 0. " COMMAND_DONE ,(IEEE 802.15.4 background level) radio operation command finished interrupt vector select" "INT_RF_CPE0,INT_RF_CPE1"
|
|
endif
|
|
line.long 0x14 "RFACKIFG,Doorbell Command Acknowledgement Interrupt Flag Register"
|
|
bitfld.long 0x14 0. " ACKFLAG ,Command ACK interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x18 "SYSGPOCTL,RF Core General Purpose Output Control Register"
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|
bitfld.long 0x18 12.--15. " GPOCTL3 ,RF Core GPO line 3 output signal select" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
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|
bitfld.long 0x18 8.--11. " GPOCTL2 ,RF Core GPO line 2 output signal select" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
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|
bitfld.long 0x18 4.--7. " GPOCTL1 ,RF Core GPO line 1 output signal select" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
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|
bitfld.long 0x18 0.--3. " GPOCTL0 ,RF Core GPO line 0 output signal select" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RF Core Power"
|
|
base ad:0x40040000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCLKEN,RF Core Power Management and Clock Enable Register"
|
|
bitfld.long 0x00 10. " RFCTRC ,RF Core Tracer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSCA ,Frequency Synthesizer Calibration Accelerator clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PHA ,Packet Handling Accelerator clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RAT ,Radio Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RFERAM ,RF Engine RAM module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFE ,RF Engine clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MDMRAM ,Modem RAM module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MDM ,Modem module clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPERAM ,Command and Packet Engine RAM module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CPE ,Command and Packet Engine clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " RFC ,RF Core interface essential clocks enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RF Core Radio Timer"
|
|
base ad:0x40043000
|
|
width 12.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RATCNT,Radio Timer Counter Value Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RATCH0VAL,Timer Channel 0 Capture/Compare Register"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RATCH1VAL,Timer Channel 1 Capture/Compare Register"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RATCH2VAL,Timer Channel 2 Capture/Compare Register"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RATCH3VAL,Timer Channel 3 Capture/Compare Register"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RATCH4VAL,Timer Channel 4 Capture/Compare Register"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RATCH5VAL,Timer Channel 5 Capture/Compare Register"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RATCH6VAL,Timer Channel 6 Capture/Compare Register"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "RATCH7VAL,Timer Channel 7 Capture/Compare Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
textline ""
|