4488 lines
314 KiB
Plaintext
4488 lines
314 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: BCM2835 On-Chip Peripherals
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; @Props: Released
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; @Author: JRK
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; @Changelog: 2016-12-07 JRK
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; @Manufacturer: BROADCOM - Broadcom Corporation
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; @Doc: BCM2835-ARM-Peripherals.pdf (2012-02-06)
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; @Chip: BCM2835
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; @Core: ARM1176
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perbcm2835.per 7591 2017-02-18 12:05:10Z askoncej $
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;
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; Know problems:
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; MODULE REGISTER DESCTIPTION
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; Auxiliaries AUX_MU_IER_REG Different address in register map and in register description
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; Auxiliaries AUX_MU_IIR_REG Different address in register map and in register description
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; Auxiliaries AUX_SPI0/1_STAT BIT_COUNT overlaps on some other fields in this register
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; Auxiliaries AUX_SPI0/1_PEEK Different address in register map and in register description
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; Auxiliaries AUX_SPI0/1_IO Different address in register map and in register description
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; Auxiliaries AUXSPI0/1_TXHOLD Lack of this register in the main register map
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; DMA Channel 15 No register description.
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config 16. 8.
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width 0x0B
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tree "Core Registers (ARM1176)"
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width 0x9
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x0100--0x0100
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line.long 0x00 "CTYPE,CTR,Cache Type Register"
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hexmask.long.byte 0x00 25.--28. 1. " Ctype ,Cache Type"
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bitfld.long 0x00 24. " S ,S bit" "Not separated,Separated"
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bitfld.long 0x00 23. " P ,P bit" "Not restricted,Restricted"
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textline " "
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bitfld.long 0x00 18.--21. " Size ,Size" "0.5 KB,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,?..."
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bitfld.long 0x00 15.--17. " Assoc ,Associativity" "Reserved,Reserved,4-way,?..."
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bitfld.long 0x00 14. " M ,M bit" "Data/Instruction,No effect"
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textline " "
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bitfld.long 0x00 12.--13. " Len ,Cache line length" "Reserved,Reserved,8 words,?..."
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bitfld.long 0x00 11. " P ,P bit" "Not restricted,Restricted"
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bitfld.long 0x00 06.--09. " Size ,Size" "0.5 KB,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,?..."
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textline " "
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bitfld.long 0x00 03.--05. " Assoc ,Associativity" "Reserved,Reserved,4-way,?..."
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bitfld.long 0x00 02. " M ,M bit" "Low,High"
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bitfld.long 0x00 00.--01. " Len ,Cache line length" "Reserved,Reserved,8 words,?..."
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width 0x9
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rgroup c15:0x0010--0x0010
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line.long 0x00 "PROCF0,Processor Feature 0 Register"
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hexmask.long.byte 0x00 12.--15. 1. " State3 ,Thumb-2 Execution Environment Support"
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hexmask.long.byte 0x00 08.--11. 1. " State2 ,Java Extension Interface Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " State1 ,Thumb Encoding Type"
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hexmask.long.byte 0x00 00.--03. 1. " State0 ,32-bit ARM Instruction Set Support"
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rgroup c15:0x0110--0x0110
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line.long 0x00 "PROCF1,Processor Feature 1 Register"
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hexmask.long.byte 0x00 08.--11. 1. " MICROPROGMOD ,The ARM Microcontroller Programmer's Model Support"
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hexmask.long.byte 0x00 04.--07. 1. " SECEXTARCH ,Security Extensions Architecture v1 Support"
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textline " "
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hexmask.long.byte 0x00 00.--03. 1. " PROGMODEL ,Standard ARMv4 Programmer's Model Support"
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rgroup c15:0x0210--0x0210
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line.long 0x00 "DEBUGF0,Debug Feature 0 Register"
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hexmask.long.byte 0x00 20.--23. 1. " MEMMAPMICRO ,Memory-Mapped Microcontroller Debug Model Type"
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hexmask.long.byte 0x00 16.--19. 1. " MEMMAPTRACE ,Memory-Mapped Trace Debug Model Type"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " COPRBASEDTRACE ,Coprocessor-Based Trace Debug Model Type"
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hexmask.long.byte 0x00 08.--11. 1. " EMBPROCDEBUG ,Embedded Processor Debug Model Type"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " SECDEBUG ,Secure Debug Model Type"
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hexmask.long.byte 0x00 00.--03. 1. " APPPROCDEBUG ,Applications Processor Debug Model Type"
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rgroup c15:0x0310--0x0310
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line.long 0x00 "AUXF0,Auxiliary Feature 0 Register"
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rgroup c15:0x0410--0x0410
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line.long 0x00 "MMF0,Memory Model Feature 0 Register"
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hexmask.long.byte 0x00 24.--27. 1. " FCSE ,FCSE Support"
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hexmask.long.byte 0x00 20.--23. 1. " AUXCR ,ARMv6 Auxiliary Control Register Support"
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textline " "
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hexmask.long.byte 0x00 16.--19. 1. " TCM/DMA ,TCM and Associated DMA Support"
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hexmask.long.byte 0x00 12.--15. 1. " CACHECOHWDMA ,Cache Coherency With DMA Agent/Shared Memory Support"
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textline " "
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hexmask.long.byte 0x00 08.--11. 1. " CACHECOHWCPU ,Cache Coherency With CPU Agent/Shared Memory Support"
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hexmask.long.byte 0x00 04.--07. 1. " PROTMEMSYSARCH ,Protected Memory System Architecture PMSA Support"
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textline " "
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hexmask.long.byte 0x00 00.--03. 1. " VIRTMEMSYSARCH ,Virtual Memory System Architecture Support"
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rgroup c15:0x0510--0x0510
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line.long 0x00 "MMF1,Memory Model Feature 1 Register"
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hexmask.long.byte 0x00 28.--31. 1. " BRANCHTARGBUFF ,Branch Target Buffer Support"
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hexmask.long.byte 0x00 24.--27. 1. " TESTCLEAN ,Test and Clean Operations on Data Cache Support"
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textline " "
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hexmask.long.byte 0x00 20.--23. 1. " L1CACHEALL_UNIFIED ,Level One Cache Support"
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hexmask.long.byte 0x00 16.--19. 1. " L1CACHEALL_HARVARD ,Level One Cache Support"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " L1CACHELINE_SET/WAY_UNIFIED ,Level One Cache Line Maintenance Operations by Set/Way Support"
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hexmask.long.byte 0x00 08.--11. 1. " L1CACHELINE_SET/WAY_HARVARD ,Level One Cache Line Maintenance Operations by Set/Way Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " L1CACHELINE_MVA_UNIFIED ,Level One Cache Line Maintenance Operations by MVA Support"
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hexmask.long.byte 0x00 00.--03. 1. " L1CACHELINE_MVA_HARVARD ,Level One Cache Line Maintenance Operations by MVA Support"
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rgroup c15:0x0610--0x0610
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line.long 0x00 "MMF2,Memory Model Feature 2 Register"
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hexmask.long.byte 0x00 28.--31. 1. " HARDWAREACCESSFLAG ,Hardware Access Flag Support"
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hexmask.long.byte 0x00 24.--27. 1. " WAITINTSTALL ,Wait for Interrupt Stalling Support"
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textline " "
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hexmask.long.byte 0x00 20.--23. 1. " MEMBARRIER ,Memory Barrier Operations Support"
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hexmask.long.byte 0x00 16.--19. 1. " TLB_UNIFIED ,TLB Maintenance Operations Support"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " TLB_HARVARD ,TLB Maintenance Operations Support"
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hexmask.long.byte 0x00 08.--11. 1. " CACHERANGE ,Cache Maintenance Range Operations Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " BACKGROUNDPREFCACHERANGE ,Background Prefetch Cache Range Operations Support"
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hexmask.long.byte 0x00 00.--03. 1. " FOREGROUNDPREFCACHERANGE ,Foreground Prefetch Cache Range Operations Support"
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rgroup c15:0x0710--0x0710
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line.long 0x00 "MMF3,Memory Model Feature 3 Register"
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hexmask.long.byte 0x00 04.--07. 1. " HIERARCHICALCACHE_MVA ,Hierarchical Cache Maintenance by MVA Support"
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hexmask.long.byte 0x00 00.--03. 1. " HIERARCHICALCACHE_SET/WAY ,Hierarchical Cache Maintenance by Set/Way Support"
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rgroup c15:0x0020--0x0020
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line.long 0x00 "ISFA0,Instruction Set Feature Attribute 0 Register"
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hexmask.long.byte 0x00 24.--27. 1. " DIV_instrs ,Divide Instructions Support"
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hexmask.long.byte 0x00 20.--23. 1. " DEBUG_instrs ,Debug Instructions Support"
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textline " "
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hexmask.long.byte 0x00 16.--19. 1. " COPROCESSOR_instrs ,Coprocessor Instructions Support"
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hexmask.long.byte 0x00 12.--15. 1. " COMBINEDCOMPARE/BRANCH_instrs ,Combined Compare and Branch Instructions Support"
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textline " "
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hexmask.long.byte 0x00 08.--11. 1. " BITFIELD_instrs ,Bitfield Instructions Support"
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hexmask.long.byte 0x00 04.--07. 1. " BITCOUNTING_instrs ,Bit Counting Instructions Support"
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textline " "
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hexmask.long.byte 0x00 00.--03. 1. " ATOMICLOADSTORE_instrs ,Atomic Load and Store Instructions Support"
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rgroup c15:0x0120--0x0120
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line.long 0x00 "ISFA1,Instruction Set Feature Attribute 1 Register"
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hexmask.long.byte 0x00 28.--31. 1. " JAZELLE_instrs ,Jazelle Instructions Support"
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hexmask.long.byte 0x00 24.--27. 1. " INTERWORKING_instrs ,Interworking Instructions Support"
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textline " "
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hexmask.long.byte 0x00 20.--23. 1. " IMMEDIATE_instrs ,Immediate Instructions Support"
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hexmask.long.byte 0x00 16.--19. 1. " FORIFTHEN_instrs ,If Then Instructions Support"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " SIGN/ZEROEXT_instrs ,Sign or Zero Extend Instructions Support"
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hexmask.long.byte 0x00 08.--11. 1. " EXCEPTION2_instrs ,Exception 2 Instructions Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " EXCEPTION1_instrs ,Exception 1 Instructions Support"
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hexmask.long.byte 0x00 00.--03. 1. " ENDIANNESCONTROL_instrs ,Endianness Control Instructions Support"
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rgroup c15:0x0220--0x0220
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line.long 0x00 "ISFA2,Instruction Set Feature Attribute 2 Register"
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hexmask.long.byte 0x00 28.--31. 1. " REVERSAL_instrs ,Reversal instructions Support"
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hexmask.long.byte 0x00 24.--27. 1. " PSR_instrs ,PSR Instructions Support"
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textline " "
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hexmask.long.byte 0x00 20.--23. 1. " ADVANCEDUNSIGNEDMUL_instrs ,Advanced Unsigned Multiply Instructions Support"
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hexmask.long.byte 0x00 16.--19. 1. " ADVANCEDSIGNEDMUL_instrs ,Advanced Signed Multiply Instructions Support"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " MUL_instrs ,Multiply Instructions Support"
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hexmask.long.byte 0x00 08.--11. 1. " MULTIACCESSINT_instrs ,Multi-Access Interruptible Instructions Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " MEMHINT_instrs ,Memory Hint Instructions Support"
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hexmask.long.byte 0x00 00.--03. 1. " LOADSTORE_instrs ,Load and Store Instructions Support"
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rgroup c15:0x0320--0x0320
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line.long 0x00 "ISFA3,Instruction Set Feature Attribute 3 Register"
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hexmask.long.byte 0x00 28.--31. 1. " THUMB-2EXT_instrs ,Thumb-2 Extensions Support"
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hexmask.long.byte 0x00 24.--27. 1. " TRUENOP_instrs ,True NOP Instructions Support"
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textline " "
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hexmask.long.byte 0x00 20.--23. 1. " THUMBCOPY_instrs ,Thumb Copy Instructions Support"
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hexmask.long.byte 0x00 16.--19. 1. " TABLEBRANCH_instrs ,Table Branch Instructions Support"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " SYNCHROPRIMITIVE_instrs ,Synchronization Primitive Instructions Support"
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hexmask.long.byte 0x00 08.--11. 1. " SWI_instrs ,SWI Instructions Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " SIMD_instrs ,Single Instruction Multiple Data Support"
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hexmask.long.byte 0x00 00.--03. 1. " SATURATE_instrs ,Saturate Instructions Support"
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rgroup c15:0x0420--0x0420
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line.long 0x00 "ISFA4,Instruction Set Feature Attribute 4 Register"
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hexmask.long.byte 0x00 20.--23. 1. " PRIM_instrs ,Fractional support for synchronization primitive instructions"
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hexmask.long.byte 0x00 16.--19. 1. " BARRIER_instrs ,Barrier instructions support"
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textline " "
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hexmask.long.byte 0x00 12.--15. 1. " SMC_instrs ,SMC Instructions Support"
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hexmask.long.byte 0x00 08.--11. 1. " WRITEBACK_instrs ,Writeback Instructions Support"
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textline " "
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hexmask.long.byte 0x00 04.--07. 1. " WITHSHIFT_instrs ,With Shift Instructions Support"
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hexmask.long.byte 0x00 00.--03. 1. " UNPRIVILEGED_instrs ,Unprivileged Instructions Support"
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rgroup c15:0x0520--0x0520
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line.long 0x00 "ISFA5,Instruction Set Feature Attribute 5 Register"
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tree.end
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width 8.
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tree "System Control and Configuration"
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
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bitfld.long 0x0 28. " TRE ,TEX Remap Enable" "Disable,Enable"
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bitfld.long 0x0 25. " EE ,Exception Endianess" "Little ,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Fixed,VIC"
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textline " "
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bitfld.long 0x0 23. " XP ,Extended pagetable configuration" "Subpages,ARMv6"
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bitfld.long 0x0 22. " U ,Unaligned Data Access Operations" "Disable,Enable"
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bitfld.long 0x0 21. " FI ,Fast Interrupts" "Disable,Enable"
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textline " "
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bitfld.long 0x00 18. " IT ,Global Enable for Instruction TCM" "Disabled,Enabled"
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bitfld.long 0x00 16. " DT ,Global enable for data TCM" "Disabled,Enabled"
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bitfld.long 0x0 15. " L4 ,Compatible to Software Version 4" "No,Yes"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Base Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Level one Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Program flow prediction" "Disable,Enable"
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bitfld.long 0x0 0x9 " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 0x8 " S ,System Protection" "Disable,Enable"
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textline " "
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bitfld.long 0x0 0x7 " B ,Endianism" "Little,Big"
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bitfld.long 0x0 0x2 " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 0x1 " A ,Alignment Fault Check" "Disable,Enable"
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bitfld.long 0x0 0x0 " M ,MMU" "Disable,Enable"
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group c15:0x0101--0x0101
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line.long 0x00 "ACR,Auxiliary Control Register"
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bitfld.long 0x00 31. " FIO ,Additional Level of Control for Low Interrupt Latency Configuration" "Normal,Low-Lat"
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bitfld.long 0x00 30. " FSD ,Additional Level of Control for Speculative Operations" "Enable,Disable"
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bitfld.long 0x00 29. " BFD ,Branch Folding Disable" "Enable,Disable"
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bitfld.long 0x00 28. " PHD ,Instruction Prefetch Halting on Unconditional Disable" "Enable,Disable"
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textline " "
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bitfld.long 0x00 06. " CZ ,Restriction of Cache Size to 16KB Control" "Normal,Limited"
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bitfld.long 0x00 05. " RV ,Block Transfer Cache Operations Disable" "Enable,Disable"
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bitfld.long 0x00 04. " RA ,Clean Entire Data Cache Disable" "Enable,Disable"
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bitfld.long 0x00 03. " TR ,MicroTLB Random Replacement Enable" "Round robin,Random"
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textline " "
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bitfld.long 0x00 02. " SB ,Static branch prediction enable" "Disable,Enable"
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bitfld.long 0x00 01. " DB ,Dynamic branch prediction enable" "Disable,Enable"
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bitfld.long 0x00 00. " RS ,Return stack enable" "Disable,Enable"
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group c15:0x201--0x201
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group c15:0x0011--0x0011
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
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bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
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textline " "
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bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
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bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
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textline " "
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bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
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bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
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group c15:0x111--0x111
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line.long 0x0 "SDE,Secure Debug Enable register"
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bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
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bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
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group c15:0x0211++0x00
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line.long 0x00 "NACR,Nonsecure Access Control Register"
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bitfld.long 0x00 18. " DMA ,The DMA Channels and Registers for the Secure World Reserve" "Denied,Permitted"
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bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
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textline " "
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bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
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textline " "
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bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
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bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
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textline " "
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bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
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bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
group c15:0x000c++0x00
|
|
line.long 0x00 "SNVBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group c15:0x10c--0x10c
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long.long 0x00 5.--31. 1. " MVBA , Monitor Vector Base Address"
|
|
tree.end
|
|
tree "MMU Control and Configuration"
|
|
width 8.
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX Remap Enable" "Disable,Enable"
|
|
bitfld.long 0x0 25. " EE ,Exception Endianess" "Little ,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Fixed,VIC"
|
|
textline " "
|
|
bitfld.long 0x0 23. " XP ,Extended pagetable configuration" "Subpages,ARMv6"
|
|
bitfld.long 0x0 22. " U ,Unaligned Data Access Operations" "Disable,Enable"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IT ,Global Enable for Instruction TCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DT ,Global enable for data TCM" "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " L4 ,Compatible to Software Version 4" "No,Yes"
|
|
bitfld.long 0x0 14. " RR ,Round Robin Replacement" "Random,Round robin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Vectors" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Level one Instruction Cache" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Program flow prediction" "Disable,Enable"
|
|
bitfld.long 0x0 0x9 " R ,ROM Protection" "Disable,Enable"
|
|
bitfld.long 0x0 0x8 " S ,System Protection" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 0x7 " B ,Endianism" "Little,Big"
|
|
bitfld.long 0x0 0x2 " C ,Data Cache" "Disable,Enable"
|
|
bitfld.long 0x0 0x1 " A ,Alignment Fault Check" "Disable,Enable"
|
|
bitfld.long 0x0 0x0 " M ,MMU" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Copyback/allocated,Writethrough,Copyback/not allocated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " P ,Indicates to the Memory Controller ECC is Enabled" "Disable,Enable"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Copyback/allocated,Writethrough,Copyback/not allocated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " P ,Indicates to the Memory Controller ECC is Enabled" "Disable,Enable"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
if (((data.long(c15:0x0005))&0x0400)==0x00)
|
|
group c15:0x0005--0x0005
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,AXI Decode or Slave Error Caused an Abort Status" "Decode,Slave"
|
|
bitfld.long 0x00 11. " RW ,Read or Write Access Caused an Abort Status" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 10. " S ,Part of the Status Field" "0,1"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs Status" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATUS ,Type of Fault Generated" "No function,Alignment,Instruction debug,Access Bit/Section,Instruction cache,Translation Section,Access Bit/Page,Translation Page,Precise external abort,Domain Section,No function,Domain Page,External abort/first,Permission Section,External abort/second,Permission Page"
|
|
else
|
|
group c15:0x0005--0x0005
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,AXI Decode or Slave Error Caused an Abort Status" "Decode,Slave"
|
|
bitfld.long 0x00 11. " RW ,Read or Write Access Caused an Abort Status" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 10. " S ,Part of the Status Field" "0,1"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs Status" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATUS ,Type of Fault Generated" "No function,No function,No function,No function,No function,No function,Imprecise external abort,No function,No function,No function,No function,No function,No function,No function,No function,No function"
|
|
endif
|
|
group c15:0x0006--0x0006
|
|
line.long 0x00 "FAR,Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " MVA ,Modified Virtual Address"
|
|
group c15:0x0105--0x0105
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,AXI Decode or Slave Error Caused an Abort Status" "Decode,Slave"
|
|
bitfld.long 0x00 0.--3. " STATUS ,Type of Fault Generated" "No function,Alignment fault,Instruction debug event fault,Access Bit fault on Section,No function,Translation Section fault,Access Bit fault on Page,Translation Page fault,Precise external abort,Domain section fault,No function,Domain page fault,External abort/first,Permission section fault,External abort/second,Permission page fault"
|
|
group c15:0x0206--0x0206
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " IFMVA ,Instruction Fault MVA"
|
|
textline " "
|
|
; wgroup c15:0x0008--0x0008
|
|
; line.long 0x00 "TLBOR,TLB Operations Register"
|
|
; hexmask.long.tbyte 0x00 12.--31. 1. " MVA ,Modified virtual address"
|
|
; hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID"
|
|
group c15:0x000A--0x000A
|
|
line.long 0x00 "TLBLR,TLB Lockdown Register"
|
|
bitfld.long 0x00 26.--28. " VICTIM ,Entry in the Lockdown Region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " P ,Subsequent Hardware Page Table Walks Place a TLB Entry" "Set associative,Lockdown TLB"
|
|
textline " "
|
|
group c15:0x002A--0x002A
|
|
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
|
|
bitfld.long 0x00 19. " RSA1N ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " RSA0N ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RSA1D ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " RSA0D ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TEX7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TEX6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TEX5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TEX4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TEX3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TEX2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TEX1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TEX0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group c15:0x012A--0x012A
|
|
line.long 0x00 "NMRRR,Normal Memory Region Remap Register"
|
|
bitfld.long 0x00 30.--31. " OTEX7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OTEX6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OTEX5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OTEX4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OTEX3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OTEX2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OTEX1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OTEX0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " ITEX7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " ITEX6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ITEX5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " ITEX4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ITEX3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " ITEX2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ITEX1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " ITEX0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
group c15:0x042F--0x042F
|
|
line.long 0x00 "PPMRR,Peripheral Port Memory Remap Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address"
|
|
bitfld.long 0x00 0.--4. " SIZE ,Size of the Memory Region That the Peripheral Port is Remapped to" "0KB,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,?..."
|
|
textline " "
|
|
group c15:0x000D--0x000D
|
|
line.long 0x00 "FCSEPID,FCSE PID Register"
|
|
hexmask.long.byte 0x0 25.--31. 0x1 " FCSEPID ,FCSE PID"
|
|
group c15:0x010D--0x010D
|
|
line.long 0x00 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x00 08.--31. 1. " PROCID ,Process ID Value"
|
|
hexmask.long.byte 0x00 00.--07. 1. " ASID , ASID Value"
|
|
group c15:0x020D--0x020D
|
|
line.long 0x00 "URWTPIDR,User Read/Write Thread and Process ID Register"
|
|
group c15:0x030D--0x030D
|
|
line.long 0x00 "UROTPIDR,User Read Only Thread and Process ID Register"
|
|
group c15:0x040D--0x040D
|
|
line.long 0x00 "UPOTPIDR,User Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0x7
|
|
tree "Cache Control and Configuration"
|
|
group c15:0x0009--0x0009
|
|
line.long 0x00 "DCLR,Data Cache Lockdown Register"
|
|
bitfld.long 0x00 07. " L7 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 06. " L6 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 05. " L5 ,Cache Way Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 04. " L4 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 03. " L3 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 02. " L2 ,Cache Way Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 01. " L1 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 00. " L0 ,Cache Way Lock" "Unlocked,Locked"
|
|
group c15:0x0109--0x0109
|
|
line.long 0x00 "ICLR,Instruction Cache Lockdown Register"
|
|
bitfld.long 0x00 07. " L7 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 06. " L6 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 05. " L5 ,Cache Way Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 04. " L4 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 03. " L3 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 02. " L2 ,Cache Way Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 01. " L1 ,Cache Way Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 00. " L0 ,Cache Way Lock" "Unlocked,Locked"
|
|
group c15:0x0089--0x0089
|
|
line.long 0x00 "CBOR,Cache Behavior Override Register"
|
|
bitfld.long 0x00 5. " S_WT ,Write-Through Behavior for Regions Marked as Secure Write-Back" "Not forced,Forced"
|
|
bitfld.long 0x00 4. " S_IL ,Instruction Cache Linefill Behavior for Secure Regions" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " S_DL ,Data Cache Linefill Behavior for Secure Regions" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NS_WT ,Write-Through Behavior for Regions Marked as Non-Secure Write-Back" "Not forced,Forced"
|
|
bitfld.long 0x00 1. " NS_IL ,Instruction Cache Linefill Behavior for Non-Secure Regions" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NS_DL ,Data Cache Linefill Behavior for Non-Secure Regions" "Enabled,Disabled"
|
|
tree.end
|
|
width 0xB
|
|
tree "TCM Control and Configuration"
|
|
rgroup c15:0x0200--0x0200
|
|
line.long 0x00 "TCMS,TCM Status Register"
|
|
bitfld.long 0x00 16.--18. " DTCM ,Number of Data TCM Banks Implemented" "0 Data,1 Data,2 Data,?..."
|
|
bitfld.long 0x00 0.--2. " ITCM ,Number of Instruction TCM Banks Implemented" "0 Instruction,1 Instruction,2 Instruction,?..."
|
|
group c15:0x0019--0x0019
|
|
line.long 0x00 "DTCMR,Data TCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the TCM on Reads" "0KB,Reserved,Reserved,4KB,8KB,16KB,32KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM Enable" "Disabled,Enabled"
|
|
group c15:0x0119--0x0119
|
|
line.long 0x00 "ITCMR,Instruction TCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the TCM on Reads" "0KB,Reserved,Reserved,4KB,8KB,16KB,32KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM Enable" "Disabled,Enabled"
|
|
group c15:0x0219--0x0219
|
|
line.long 0x00 "DTCMNSACR,Data TCM Non-Secure Access Control Register"
|
|
bitfld.long 0x00 0. " NSA ,NS access" "Secure,Secure and Non-Secure"
|
|
group c15:0x0319--0x0319
|
|
line.long 0x00 "ITCMNSACR,Instruction TCM Non-Secure Access Control Register"
|
|
bitfld.long 0x00 0. " NSA ,NS access" "Secure,Secure and Non-Secure"
|
|
group c15:0x0029--0x0029
|
|
line.long 0x00 "TCMSR,TCM Selection Register"
|
|
bitfld.long 0x00 0.--1. " TCMN ,TCM number" "TCM 0,TCM 1,Ignored,Ignored"
|
|
tree.end
|
|
width 0xD
|
|
tree "DMA Control"
|
|
rgroup c15:0x010B--0x010B
|
|
line.long 0x00 "DMAISR1,DMA Identification and Status Register 1"
|
|
bitfld.long 0x00 1. " CH1 ,Information on DMA Channel 1 Functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Information on DMA Channel 0 Functions" "Disabled,Enabled"
|
|
rgroup c15:0x020B--0x020B
|
|
line.long 0x00 "DMAISR2,DMA Identification and Status Register 2"
|
|
bitfld.long 0x00 1. " CH1 ,Information on DMA Channel 1 Functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Information on DMA Channel 0 Functions" "Disabled,Enabled"
|
|
rgroup c15:0x030B--0x030B
|
|
line.long 0x00 "DMAISR3,DMA Identification and Status Register 3"
|
|
bitfld.long 0x00 1. " CH1 ,Information on DMA Channel 1 Functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Information on DMA Channel 0 Functions" "Disabled,Enabled"
|
|
wgroup c15:0x023B--0x023B
|
|
line.long 0x00 "DMAER_Clear,DMA Enable Register Clear"
|
|
group c15:0x002B--0x002B
|
|
line.long 0x00 "DMACNR,DMA Channel Number Register"
|
|
bitfld.long 0x00 0. " CN ,DMA Channel Select" "Channel 0,Channel 1"
|
|
rgroup c15:0x008B--0x008B
|
|
line.long 0x00 "DMACSR,DMA Channel Status Register"
|
|
bitfld.long 0x00 16. " ESX[0] ,Add a SLVERR or DECERR Qualifier to the ES Encoding" "DECERR,SLVERR"
|
|
bitfld.long 0x00 13. " ISX[0] ,Add a SLVERR or DECERR Qualifier to the IS Encoding" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BP ,DMA Parameters Type" "Acceptable,Conditioned inappropriately"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " ES ,Status of the External Address Error" "No error,No error,No error,No error,No error,No error,No error,No error,Reserved,Unshared data error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Access Bit fault on section,Reserved,Translation fault section,Access Bit fault on page,Translation fault page,Reserved,Domain fault section,External Abort can be imprecise,Domain fault page,External Abort on first-level,Permission fault section,External Abort on second-level,Permission fault page"
|
|
textline " "
|
|
bitfld.long 0x00 2.--6. " IS ,Status of the Internal Address Error" "No error,No error,No error,No error,No error,No error,No error,No error,TCM out of range,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Access Bit fault on section,Reserved,Translation fault section,Access Bit fault on page,Translation fault page,Reserved,Domain fault section,Reserved,Domain fault page,External Abort on first-level,Permission fault section,External Abort on second-level,Permission fault page"
|
|
bitfld.long 0x00 0.--1. " STATUS ,Status of the DMA channel" "Idle,Queued,Running,Complete or Error"
|
|
group c15:0x00FB--0x00FB
|
|
line.long 0x00 "DMACIDR,DMA Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extend to Form the Process ID and Identify the Current Process"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process"
|
|
group c15:0x004B--0x004B
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 31. " TR ,Target TCM Select" "Data,Instruction"
|
|
bitfld.long 0x00 30. " DT ,Direction of Transfer Select" "Level 2 memory-TCM,TCM-level 2 memory"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IC ,Interrupt on Completion" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IE ,Interrupt on Error" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FT ,This bit has no effect" "Low,High"
|
|
bitfld.long 0x00 26. " UM ,User Mode Transfer" "Privileged,User"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--19. 1. " ST ,The Increment Value on the External Address"
|
|
bitfld.long 0x00 0.--1. " TS ,Size of DMA Channel Transactions" "Byte,Halfword,Word,Doubleword"
|
|
wgroup c15:0x003B--0x003B
|
|
line.long 0x00 "DMAER_Stop,DMA Enable Register Stop"
|
|
wgroup c15:0x013B--0x013B
|
|
line.long 0x00 "DMAER_Start,DMA Enable Register Start"
|
|
group c15:0x006B--0x006B
|
|
line.long 0x00 "DMAESAR,DMA External Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " ESVA ,External Start VA"
|
|
rgroup c15:0x000B--0x000B
|
|
line.long 0x00 "DMAISR0,DMA Identification and Status Register 0"
|
|
bitfld.long 0x00 1. " CH1 ,Information on DMA Channel 1 Functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Information on DMA Channel 0 Functions" "Disabled,Enabled"
|
|
group c15:0x007B--0x007B
|
|
line.long 0x00 "DMAIEAR,DMA Internal End Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " IEVA ,Internal End VA"
|
|
group c15:0x005B--0x005B
|
|
line.long 0x00 "DMAISAR,DMA Internal Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " ISVA ,Internal Start VA"
|
|
group c15:0x001B--0x001B
|
|
line.long 0x00 "DMAUAR,DMA User Accessibility Register"
|
|
bitfld.long 0x00 1. " U1 ,User Mode Process Access the Registers for Channel 1" "Not accessed,Accessed"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access the Registers for Channel 0" "Not accessed,Accessed"
|
|
tree.end
|
|
width 0x6
|
|
tree "System Performance Monitor"
|
|
group c15:0x00CF--0x00CF
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 20.--27. 1. " EVTCOUNT0 ,Source of Events for Count Register 0"
|
|
hexmask.long.byte 0x00 12.--19. 1. " EVTCOUNT1 ,Source of Events for Count Register 1"
|
|
bitfld.long 0x00 11. " X ,Export of the Events to the Event Bus to an External Monitoring Block Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CCR ,Cycle Counter Register overflow flag" "No overflow,Overflow"
|
|
eventfld.long 0x00 9. " CR1 ,Count Register 1 overflow flag" "No overflow,Overflow"
|
|
eventfld.long 0x00 8. " CR0 ,Count Register 0 overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ECC ,Cycle Counter Interrupt Reporting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EC1 ,Count Register 1 Interrupt Reporting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EC0 ,Count Register 0 Interrupt Reporting Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " D ,Cycle Count Divider" "Every cycle,Every 64th cycle"
|
|
bitfld.long 0x00 2. " C ,Cycle Counter Register Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Count Register 1 and Count Register 0 Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled"
|
|
group c15:0x02CF--0x02CF
|
|
line.long 0x00 "CR0,Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Count value"
|
|
group c15:0x03CF--0x03CF
|
|
line.long 0x00 "CR1,Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Count value"
|
|
group c15:0x01CF--0x01CF
|
|
line.long 0x00 "CCR,Cycle Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Count value"
|
|
tree.end
|
|
width 0xB
|
|
tree "System Validation"
|
|
group c15:0x009F--0x009F
|
|
line.long 0x00 "SUNSAVCR,Secure User and Non-Secure Access Validation Control Register"
|
|
bitfld.long 0x00 0. " V ,Access to System Validation Registers from User and Non-Secure Modes Control" "Secure privileged/privileged,Any"
|
|
group c15:0x04CF--0x04CF
|
|
line.long 0x00 "SVC0_RC,Reset Counter"
|
|
hexmask.long.byte 0x00 0.--5. 1. " CV ,Counter value"
|
|
group c15:0x05CF--0x05CF
|
|
line.long 0x00 "SVC1_IC,Interrupt Counter"
|
|
hexmask.long.byte 0x00 0.--5. 1. " CV ,Counter value"
|
|
group c15:0x06CF--0x06CF
|
|
line.long 0x00 "SVC2_FIC,Fast Interrupt Counter"
|
|
hexmask.long.byte 0x00 0.--5. 1. " CV ,Counter value"
|
|
group c15:0x07CF--0x07CF
|
|
line.long 0x00 "SVC3_EDRC,External Debug Request Counter"
|
|
hexmask.long.byte 0x00 0.--5. 1. " CV ,Counter value"
|
|
group c15:0x00EF--0x00EF
|
|
line.long 0x00 "SVCSM,System Validation Cache Size Mask"
|
|
bitfld.long 0x00 31. " WE ,Write enable" "Not changed,Changed"
|
|
bitfld.long 0x00 12.--14. " DTCM ,Apparent Size of Data TCM and Apparent Number of Data TCM Banks" "Not present,Reserved,Reserved,1 bank 4KB,2 banks 4KB,2 banks 8KB,2 banks 16KB,2 banks 32KB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " ITCM ,Apparent Size of Instruction TCM and Apparent Number of Instruction TCM Banks" "Not present,Reserved,Reserved,1 bank 4KB,2 banks 4KB,2 banks 8KB,2 banks 16KB,2 banks 32KB"
|
|
bitfld.long 0x00 4.--6. " DCACHE ,Apparent Size of Data Cache" "Reserved,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " ICACHE ,Apparent Size of Instruction Cache" "Reserved,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB"
|
|
width 0xC
|
|
tree.open "System Validations"
|
|
tree "System Validation Operations 0-15"
|
|
wgroup c15:0x00DF--0x00DF
|
|
line.long 0x00 "SV0,System Validation Operations 0"
|
|
wgroup c15:0x01DF--0x01DF
|
|
line.long 0x00 "SV1_SRC,Start Reset Counter"
|
|
wgroup c15:0x02DF--0x02DF
|
|
line.long 0x00 "SV2_SIC,Start Interrupt Counter"
|
|
wgroup c15:0x03DF--0x03DF
|
|
line.long 0x00 "SV3_SRIC,Start Reset and Interrupt Counters"
|
|
wgroup c15:0x04DF--0x04DF
|
|
line.long 0x00 "SV4_SFIC,Start Fast Interrupt Counter"
|
|
wgroup c15:0x05DF--0x05DF
|
|
line.long 0x00 "SV5_SRFIC,Start Reset and Fast Interrupt Counters"
|
|
wgroup c15:0x06DF--0x06DF
|
|
line.long 0x00 "SV6_SIFIC,Start Interrupt and Fast Interrupt Counters"
|
|
wgroup c15:0x07DF--0x07DF
|
|
line.long 0x00 "SV7_SRIFIC,Start Reset/Interrupt and Fast Interrupt Counters"
|
|
wgroup c15:0x10DF--0x10DF
|
|
line.long 0x00 "SV8_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x11DF--0x11DF
|
|
line.long 0x00 "SV9_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x12DF--0x12DF
|
|
line.long 0x00 "SV10_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x13DF--0x13DF
|
|
line.long 0x00 "SV11_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x14DF--0x14DF
|
|
line.long 0x00 "SV12_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x15DF--0x15DF
|
|
line.long 0x00 "SV13_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x16DF--0x16DF
|
|
line.long 0x00 "SV14_SEDRC,Start External Debug Request Counter"
|
|
wgroup c15:0x17DF--0x17DF
|
|
line.long 0x00 "SV15_SEDRC,Start External Debug Request Counter"
|
|
tree.end
|
|
width 0xD
|
|
tree "System Validation Operations 16-31"
|
|
wgroup c15:0x20DF--0x20DF
|
|
line.long 0x00 "SV16,System Validation Operations 16"
|
|
wgroup c15:0x21DF--0x21DF
|
|
line.long 0x00 "SV17_SRC,Stop Reset Counter"
|
|
wgroup c15:0x22DF--0x22DF
|
|
line.long 0x00 "SV18_SIC,Stop Interrupt Counter"
|
|
wgroup c15:0x23DF--0x23DF
|
|
line.long 0x00 "SV19_SRIC,Stop Reset and Interrupt Counters"
|
|
wgroup c15:0x24DF--0x24DF
|
|
line.long 0x00 "SV20_SFIC,Stop Fast Interrupt Counter"
|
|
wgroup c15:0x25DF--0x25DF
|
|
line.long 0x00 "SV21_SRFIC,Stop Reset and Fast Interrupt Counters"
|
|
wgroup c15:0x26DF--0x26DF
|
|
line.long 0x00 "SV22_SIFIC,Stop Interrupt and Fast Interrupt Counters"
|
|
wgroup c15:0x27DF--0x27DF
|
|
line.long 0x00 "SV23_SRIFIC,Stop Reset/Interrupt and Fast Interrupt Counters"
|
|
wgroup c15:0x30DF--0x30DF
|
|
line.long 0x00 "SV24_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x31DF--0x31DF
|
|
line.long 0x00 "SV25_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x32DF--0x32DF
|
|
line.long 0x00 "SV26_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x33DF--0x33DF
|
|
line.long 0x00 "SV27_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x34DF--0x34DF
|
|
line.long 0x00 "SV28_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x35DF--0x35DF
|
|
line.long 0x00 "SV29_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x36DF--0x36DF
|
|
line.long 0x00 "SV30_SEDRC,Stop External Debug Request Counter"
|
|
wgroup c15:0x37DF--0x37DF
|
|
line.long 0x00 "SV31_SEDRC,Stop External Debug Request Counter"
|
|
tree.end
|
|
width 0x6
|
|
tree "System Validation Operations 32-47"
|
|
wgroup c15:0x40DF--0x40DF
|
|
line.long 0x00 "SV32,System Validation Operations 32"
|
|
wgroup c15:0x41DF--0x41DF
|
|
line.long 0x00 "SV33,System Validation Operations 33"
|
|
wgroup c15:0x42DF--0x42DF
|
|
line.long 0x00 "SV34,System Validation Operations 34"
|
|
wgroup c15:0x43DF--0x43DF
|
|
line.long 0x00 "SV35,System Validation Operations 35"
|
|
wgroup c15:0x44DF--0x44DF
|
|
line.long 0x00 "SV36,System Validation Operations 36"
|
|
wgroup c15:0x45DF--0x45DF
|
|
line.long 0x00 "SV37,System Validation Operations 37"
|
|
wgroup c15:0x46DF--0x46DF
|
|
line.long 0x00 "SV38,System Validation Operations 38"
|
|
wgroup c15:0x47DF--0x47DF
|
|
line.long 0x00 "SV39,System Validation Operations 39"
|
|
wgroup c15:0x50DF--0x50DF
|
|
line.long 0x00 "SV40,System Validation Operations 40"
|
|
wgroup c15:0x51DF--0x51DF
|
|
line.long 0x00 "SV41,System Validation Operations 41"
|
|
wgroup c15:0x52DF--0x52DF
|
|
line.long 0x00 "SV42,System Validation Operations 42"
|
|
wgroup c15:0x53DF--0x53DF
|
|
line.long 0x00 "SV43,System Validation Operations 43"
|
|
wgroup c15:0x54DF--0x54DF
|
|
line.long 0x00 "SV44,System Validation Operations 44"
|
|
wgroup c15:0x55DF--0x55DF
|
|
line.long 0x00 "SV45,System Validation Operations 45"
|
|
wgroup c15:0x56DF--0x56DF
|
|
line.long 0x00 "SV46,System Validation Operations 46"
|
|
wgroup c15:0x57DF--0x57DF
|
|
line.long 0x00 "SV47,System Validation Operations 47"
|
|
tree.end
|
|
tree "System Validation Operations 48-63"
|
|
wgroup c15:0x60DF--0x60DF
|
|
line.long 0x00 "SV48,System Validation Operations 48"
|
|
wgroup c15:0x61DF--0x61DF
|
|
line.long 0x00 "SV49,System Validation Operations 49"
|
|
wgroup c15:0x62DF--0x62DF
|
|
line.long 0x00 "SV50,System Validation Operations 50"
|
|
wgroup c15:0x63DF--0x63DF
|
|
line.long 0x00 "SV51,System Validation Operations 51"
|
|
wgroup c15:0x64DF--0x64DF
|
|
line.long 0x00 "SV52,System Validation Operations 52"
|
|
wgroup c15:0x65DF--0x65DF
|
|
line.long 0x00 "SV53,System Validation Operations 53"
|
|
wgroup c15:0x66DF--0x66DF
|
|
line.long 0x00 "SV54,System Validation Operations 54"
|
|
wgroup c15:0x67DF--0x67DF
|
|
line.long 0x00 "SV55,System Validation Operations 55"
|
|
wgroup c15:0x70DF--0x70DF
|
|
line.long 0x00 "SV56,System Validation Operations 56"
|
|
wgroup c15:0x71DF--0x71DF
|
|
line.long 0x00 "SV57,System Validation Operations 57"
|
|
wgroup c15:0x72DF--0x72DF
|
|
line.long 0x00 "SV58,System Validation Operations 58"
|
|
wgroup c15:0x73DF--0x73DF
|
|
line.long 0x00 "SV59,System Validation Operations 59"
|
|
wgroup c15:0x74DF--0x74DF
|
|
line.long 0x00 "SV60,System Validation Operations 60"
|
|
wgroup c15:0x75DF--0x75DF
|
|
line.long 0x00 "SV61,System Validation Operations 61"
|
|
wgroup c15:0x76DF--0x76DF
|
|
line.long 0x00 "SV62,System Validation Operations 62"
|
|
wgroup c15:0x77DF--0x77DF
|
|
line.long 0x00 "SV63,System Validation Operations 63"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "Debug Access to Caches and TLB"
|
|
group c15:0x30CF--0x30CF
|
|
line.long 0x00 "DCMVR0,Data Cache Master Valid Register 0"
|
|
group c15:0x31CF--0x31CF
|
|
line.long 0x00 "DCMVR1,Data Cache Master Valid Register 1"
|
|
group c15:0x32CF--0x32CF
|
|
line.long 0x00 "DCMVR2,Data Cache Master Valid Register 2"
|
|
group c15:0x33CF--0x33CF
|
|
line.long 0x00 "DCMVR3,Data Cache Master Valid Register 3"
|
|
group c15:0x34CF--0x34CF
|
|
line.long 0x00 "DCMVR4,Data Cache Master Valid Register 4"
|
|
group c15:0x35CF--0x35CF
|
|
line.long 0x00 "DCMVR5,Data Cache Master Valid Register 5"
|
|
group c15:0x36CF--0x36CF
|
|
line.long 0x00 "DCMVR6,Data Cache Master Valid Register 6"
|
|
group c15:0x37CF--0x37CF
|
|
line.long 0x00 "DCMVR7,Data Cache Master Valid Register 7"
|
|
group c15:0x308F--0x308F
|
|
line.long 0x00 "ICMVR0,Instruction Cache Master Valid Register 0"
|
|
group c15:0x318F--0x318F
|
|
line.long 0x00 "ICMVR1,Instruction Cache Master Valid Register 1"
|
|
group c15:0x328F--0x328F
|
|
line.long 0x00 "ICMVR2,Instruction Cache Master Valid Register 2"
|
|
group c15:0x338F--0x338F
|
|
line.long 0x00 "ICMVR3,Instruction Cache Master Valid Register 3"
|
|
group c15:0x348F--0x348F
|
|
line.long 0x00 "ICMVR4,Instruction Cache Master Valid Register 4"
|
|
group c15:0x358F--0x358F
|
|
line.long 0x00 "ICMVR5,Instruction Cache Master Valid Register 5"
|
|
group c15:0x368F--0x368F
|
|
line.long 0x00 "ICMVR6,Instruction Cache Master Valid Register 6"
|
|
group c15:0x378F--0x378F
|
|
line.long 0x00 "ICMVR7,Instruction Cache Master Valid Register 7"
|
|
group c15:0x527F--0x527F
|
|
line.long 0x00 "TLBLAR,TLB Lockdown Attributes Register"
|
|
bitfld.long 0x00 30.--31. " AP3 ,Sub-page access permissions for the fourth sub-page" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " AP2 ,Sub-page access permissions for the third sub-page" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " AP1 ,Sub-page access permissions for the second sub-page" "0,1,2,3"
|
|
bitfld.long 0x00 25. " SPV ,Page Table Entry Sub-Pages Support" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 7.--10. " DOMAIN ,Domain Number for the Page Table Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " XN ,Execute Never Attribute" "Can,Cannot"
|
|
textline " "
|
|
bitfld.long 0x00 0. " S ,Memory Region Shareable" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x00 1.--5. " TEX_C_B ,TEX[2:0]/C/B Bits" "Strongly ordered,Shared device,Outer/inner Write throught/not allocated,Outer/inner write back/not allocated,Outer/inner noncachable,Reserved,Reserved,Reserved,Non shared device,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Noncachable,Noncachable/write back/allocated,Noncachable/write through/not allocated,Noncachable/write back/not allocated,Write back/allocated/noncachable,Write back/allocated,Write back/through/allocated/not allocated,Write back/allocated/not allocated,Write through/not allocated/noncachable,Write through/back/not allocated/allocated,Write through/not allocated,Write through/back/not allocated,Write back/not allocated/noncachable,Write back/not allocated/allocated,Write back/through/not allocated/,write back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " S ,Memory region shareable" "Not shared,Shared"
|
|
group c15:0x524F--0x524F
|
|
line.long 0x00 "TLBLIR,TLB Lockdown Index Register"
|
|
bitfld.long 0x00 0.--2. " Index ,TLB Lockdown Entrie to Read or Write Select" "0,1,2,3,4,5,6,7"
|
|
group c15:0x526F--0x526F
|
|
line.long 0x00 "TLBLPAR,TLB Lockdown PA Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " PA ,PA of This Page Table Entry"
|
|
bitfld.long 0x00 9. " NSA ,Memory Accesses Types" "Secure,Non-Secure"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NSTID ,Page Table Entry Type" "Secure,Non-Secure"
|
|
bitfld.long 0x00 6.--7. " SIZE ,Size of the Memory Region" "16MB supersection,4KB page,64KB page,1M section"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " APX/AP ,Access permissions extension bit/Access permissions" "No access,Supervisor RW,Supervisor RW/User R,Full access,No access,Supervisor R,Supervisor/User R,Supervisor/User R"
|
|
bitfld.long 0x00 0. " V ,Page Table Entry Valid" "Not valid,Valid"
|
|
group c15:0x525F--0x525F
|
|
line.long 0x00 "TLBLVAR,TLB Lockdown VA Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " VA ,VA of This Page Table Entry"
|
|
bitfld.long 0x00 9. " G ,Page Table Entry Status" "Application-specific,Global"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID for Application-Specific Page Table Entries"
|
|
tree.end
|
|
width 0x7
|
|
tree "Debug"
|
|
rgroup c14:0x0000++0x00
|
|
line.long 0x00 "DIDR,Debug ID Register"
|
|
bitfld.long 0x00 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 20.--23. " CONTEXT ,Number of Breakpoint Register Pairs with context ID comparison capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " VERSION ,Debug architecture version" "Reserved,Reserved,v6.1,?..."
|
|
bitfld.long 0x00 12.--15. " DAR ,Debug architecture revision" "Reserved,TrustZone,?..."
|
|
bitfld.long 0x00 4.--7. " VARIANT ,Implementation-defined variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " REVISION ,Implementation-defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group c14:0x0010++0x00
|
|
line.long 0x00 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x00 30. " RDTRFULL ,The rDTRfull flag" "Empty,Full"
|
|
bitfld.long 0x00 29. " WDTRFULL ,The wDTRfull flag" "Empty,Full"
|
|
bitfld.long 0x00 19. " IDAI ,Imprecise Data Aborts Ignored" "No Debug,DMB operation"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NSWS ,Non-Secure World Status bit" "Secure,Non-Secure"
|
|
bitfld.long 0x00 17. " SPNIDEN ,SPNIDEN Input Pin State" "High,Low"
|
|
bitfld.long 0x00 16. " SPIDEN ,SPNIDEN Input Pin State" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MDME ,The Monitor debug-mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MS ,Mode select bit" "Monitor,Halt"
|
|
bitfld.long 0x00 13. " EARMIE ,Execute ARM instruction enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UMACCC ,User mode access to comms channel control bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " INT ,Interrupts bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,DbgAck bit" "No effect,HIGH"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PD ,Powerdown disable" "LOW,HIGH"
|
|
bitfld.long 0x00 8. " SU ,Sticky Undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " SIDA ,Sticky imprecise Data Aborts bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPDA ,Sticky precise Data Abort bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2.--5. " ME ,Method of entry bits" "Halt DBGTAP,Breakpoint,Watchpoint,BKPT,EDBGRQ,Vector catch,?..."
|
|
bitfld.long 0x00 1. " CR ,Core restarted bit" "Not exited,Exited"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CH ,Core halted bit" "Normal,Debug"
|
|
group c14:0x0070++0x00
|
|
line.long 0x00 "VCR,Vector Catch Register"
|
|
bitfld.long 0x00 31. " FIQ ,Vector Catch Enable - FIQ in Non-Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IRQ ,Vector Catch Enable - IRQ in Non-Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DA ,Vector Catch Enable - Data Abort in Non-Secure world" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PA ,Vector Catch Enable - Prefetch Abort in Non-Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SVC ,Vector Catch Enable - SVC in Non-Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UI ,Vector Catch Enable - Undefined Instruction in Non-Secure world" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FIQ ,Vector Catch Enable - FIQ in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IRQ ,Vector Catch Enable - IRQ in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DA ,Vector Catch Enable - Data Abort in Secure world" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PA ,Vector Catch Enable - Prefetch Abort in Secure World" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SMC ,Vector Catch Enable - SMC in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FIQ ,Vector Catch Enable - FIQ in Secure world" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQ ,Vector Catch Enable - IRQ in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DA ,Vector Catch Enable - Data Abort in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PA ,Vector Catch Enable - Prefetch Abort in Secure world" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SVC ,Vector Catch Enable - SVC in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UI ,Vector Catch Enable - Undefined Instruction in Secure world" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CE ,Vector Catch Enable - Reset" "Disabled,Enabled"
|
|
group c14:0x00a0++0x00
|
|
line.long 0x00 "DSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Write through,No write through"
|
|
bitfld.long 0x00 1. " NIL ,No Instruction Cache Line-Fill" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NDL ,No Data/Unified Cache Line-Fill" "Disabled,Enabled"
|
|
group c14:0x00b0++0x00
|
|
line.long 0x00 "DSMCR,Debug State MMU Control Register"
|
|
bitfld.long 0x00 6. " NDMM ,Data/Unified Main TLB match" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NDML ,Data/Unified Main TLB load" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NIUM ,Instruction Micro TLB match" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NDUM ,Data/Unified Micro TLB match" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NIUL ,Instruction Micro TLB load and flush" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NDUL ,Data/Unified Micro TLB load and flush" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Breakpoints"
|
|
group c14:0x400++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BACID ,Breakpoint address or context ID"
|
|
group c14:0x0500++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 21.--22. " M ,Meaning of BVR" "IMVA Match,Context ID Match,IMVA Mis-match,?..."
|
|
bitfld.long 0x00 20. " E ,Enable linking" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SBM ,Secure breakpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Breakpoint enable" "Disabled,Enabled"
|
|
group c14:0x410++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BACID ,Breakpoint address or context ID"
|
|
group c14:0x0510++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 21.--22. " M ,Meaning of BVR" "IMVA Match,Context ID Match,IMVA Mis-match,?..."
|
|
bitfld.long 0x00 20. " E ,Enable linking" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SBM ,Secure breakpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Breakpoint enable" "Disabled,Enabled"
|
|
group c14:0x420++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BACID ,Breakpoint address or context ID"
|
|
group c14:0x0520++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 21.--22. " M ,Meaning of BVR" "IMVA Match,Context ID Match,IMVA Mis-match,?..."
|
|
bitfld.long 0x00 20. " E ,Enable linking" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SBM ,Secure breakpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Breakpoint enable" "Disabled,Enabled"
|
|
group c14:0x430++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BACID ,Breakpoint address or context ID"
|
|
group c14:0x0530++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 21.--22. " M ,Meaning of BVR" "IMVA Match,Context ID Match,IMVA Mis-match,?..."
|
|
bitfld.long 0x00 20. " E ,Enable linking" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SBM ,Secure breakpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Breakpoint enable" "Disabled,Enabled"
|
|
group c14:0x440++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BACID ,Breakpoint address or context ID"
|
|
group c14:0x0540++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 21.--22. " M ,Meaning of BVR" "IMVA Match,Context ID Match,IMVA Mis-match,?..."
|
|
bitfld.long 0x00 20. " E ,Enable linking" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SBM ,Secure breakpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Breakpoint enable" "Disabled,Enabled"
|
|
group c14:0x450++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BACID ,Breakpoint address or context ID"
|
|
group c14:0x0550++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 21.--22. " M ,Meaning of BVR" "IMVA Match,Context ID Match,IMVA Mis-match,?..."
|
|
bitfld.long 0x00 20. " E ,Enable linking" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SBM ,Secure breakpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Breakpoint enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoints"
|
|
group c14:0x0600++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " WA ,Watchpoint address"
|
|
group c14:0x0700++0x00
|
|
line.long 0x00 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x00 20. " E ,Enable linking bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWM ,Secure watchpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 3.--4. " L/S ,Load/store access" "Reserved,Load,Store,Either"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x0610++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " WA ,Watchpoint address"
|
|
group c14:0x0710++0x00
|
|
line.long 0x00 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x00 20. " E ,Enable linking bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWM ,Secure watchpoint match" "Secure or Non-Secure,Non-Secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " BAS ,Byte address select" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x00 3.--4. " L/S ,Load/store access" "Reserved,Load,Store,Either"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access" "Reserved,Privileged,User,Either"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x0060++0x00
|
|
line.long 0x00 "WFAR,Watchpoint Fault Address Register"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Auxiliaries"
|
|
base ad:0x20215000
|
|
width 8.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "AUXIRQ,Auxiliary Interrupt Status Register"
|
|
bitfld.long 0x00 2. " SPI_2_IRQ ,The SPI 2 module has an interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " SPI_1_IRQ ,The SPI 1 module has an interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " MINI_UART_IRQ ,The mini UART has an interrupt pending" "Not pending,Pending"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AUXENB,Auxiliary Enables Register"
|
|
bitfld.long 0x00 2. " SPI_2_EN ,The SPI 2 module is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SPI_1_EN ,The SPI 1 module is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MINI_UART_EN ,The mini UART is enabled" "Disabled,Enabled"
|
|
width 17.
|
|
tree "Mini UART"
|
|
if (((per.l(ad:0x20215000+0x4C))&0x80)==0x00)
|
|
hgroup.long 0x40++0x07
|
|
hide.long 0x00 "AUX_MU_IO_REG,Mini UART I/O Data Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "AUX_MU_IER_REG,Mini UART Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " EN_RECEIVE_INT ,Enable receive interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_TRANSMIT_INT ,Enable transmit interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "AUX_MU_IO_REG,Mini UART I/O Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LS_8_BITS_BAUDRATE ,Access to the LS 8 bits of the 16-bit baudrate register"
|
|
line.long 0x04 "AUX_MU_IER_REG,Mini UART Interrupt Enable Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MS_8_BITS_BAUDRATE ,Access to the MS 8 bits of the 16-bit baudrate register"
|
|
endif
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "AUX_MU_IIR_REG,Mini UART Interrupt Identify Register"
|
|
rbitfld.long 0x00 7. " FIFO_EN[1] ,Enables FIFO bit 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FIFO_EN[0] ,Enables FIFO bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " INT_ID/FIFO_CLR ,The interrupt Id(Read)/fifo Clear(Write)" "No interrupt/receive FIFO not cleared,Transmit empty/receive FIFO cleared,Receive valid/transmit FIFO not cleared,-/Transmit FIFO cleared"
|
|
rbitfld.long 0x00 0. " INT_PND ,Interrupt pending" "Pending,Not pending"
|
|
line.long 0x04 "AUX_MU_LCR_REG,Mini UART Line Control Register"
|
|
bitfld.long 0x04 7. " DLAB_ACC ,The first to mini UART register give access the baudrate register" "No access,Access"
|
|
bitfld.long 0x04 6. " BREAK ,If held for at least 12 bits times that will indicate a break condition" "No break,Break"
|
|
bitfld.long 0x04 0. " DATA_SIZE ,UART data size mode" "7-bit,8-bit"
|
|
line.long 0x08 "AUX_MU_MCR_REG,Mini UART Modem Control Register"
|
|
bitfld.long 0x08 1. " RTS ,The UART1_RTS line" "High,Low"
|
|
textline " "
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "AUX_MU_LSR_REG,Mini UART Line Status Register"
|
|
in
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "AUX_MU_MSR_REG,Mini UART Modem Status Register"
|
|
bitfld.long 0x00 5. " CTS_STATUS ,The inverse of the UART1_CTS input" "High,Low"
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "AUX_MU_SCRATCH,Mini UART Scratch Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCRATCH ,One whole byte extra on top of the 134217728 provided by the SDC"
|
|
line.long 0x04 "AUX_MU_CNTL_REG,Mini UART Extra Control Register"
|
|
bitfld.long 0x04 7. " CTS_ASSERT_LEVEL ,Allows one to invert the CTS auto flow operation polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x04 6. " RTS_ASSERT_LEVEL ,Allows one to invert the RTS auto flow operation polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x04 4.--5. " RTS_AUTO_FLOW_LEVEL ,Receiver FIFO level the RTS line is de-asserted in auto-flow mode" "3,2,1,4"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CTS_AUTO_FLOW_EN ,Enable transmit auto flow-control using CTS" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RTS_AUTO_FLOW_EN ,Enable transmit auto flow-control using RTS" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TRANSMITTER_EN ,Enable the mini UART transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RECEIVER_EN ,Enable the mini UART receiver" "Disabled,Enabled"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "AUX_MU_STAT_REG,Mini UART Extra Status Register"
|
|
bitfld.long 0x00 24.--27. " TRANSMIT_FIFO_FILL_LVL ,Shows how many symbols are stored in the transmit FIFO" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 16.--19. " RECEIVE_FIFO_FILL_LVL ,Shows how many symbols are stored in the receive FIFO" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 9. " TRANSMITTER_DONE ,The transmitter is idle and the transmit FIFO is Empty(Logic AND of bits 2 and 8)" "Not done,Done"
|
|
bitfld.long 0x00 8. " TRANSMITTER_FIFO_EMPTY ,The transmitter FIFO is empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTS_LINE ,The status of the UART1_CTS line" "Low,High"
|
|
bitfld.long 0x00 6. " RTS_LINE ,The status of the UART1_RTS line" "Low,High"
|
|
bitfld.long 0x00 5. " TRANSMIT_FIFO_FULL ,Transmit FIFO is full" "Not full,Full"
|
|
bitfld.long 0x00 4. " RECEIVER_OVERRUN ,Receiver overrun" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TRANSMITTER_IDLE ,The transmitter is idle" "Busy,Idle"
|
|
bitfld.long 0x00 2. " RECEIVER_IDLE ,The receiver is idle" "Busy,Idle"
|
|
bitfld.long 0x00 1. " SPACE_AVAILABLE ,Space available" "Not available,Available"
|
|
bitfld.long 0x00 0. " SYMBOL_AVAILABLE ,Symbol available" "Not available,Available"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "AUX_MU_BAUD,Mini UART Baudrate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUDRATE ,Mini UART baudrate counter"
|
|
tree.end
|
|
width 17.
|
|
tree "SPI 1"
|
|
if (((per.l(ad:0x20215000+0x80))&0x4000)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "AUX_SPI1_CNTL0,SPI 1 Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " SPEED ,Sets the SPI clock speed"
|
|
bitfld.long 0x00 17.--19. " CHIP_SELECTS ,The pattern output on the CS pins when active" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 16. " POST_INPUT_MODE ,The SPI input works in post input mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VARIABLE_CS ,The SPI takes the CS pattern and the data from the TX fifo or pattern form bits 17-19 (CHIP_SELECTS) of this register" "CHIP_SELECTS,?..."
|
|
bitfld.long 0x00 14. " VARIABLE_WIDTH ,The SPI takes the shift length and the data from the TX fifo or the shift length from bits 0-5 (SHIFT_LENGTH) of this register" "SHIFT_LENGTH,Shift length and data"
|
|
bitfld.long 0x00 12.--13. " DOUT_HOLD_TIME ,Controls the extra DOUT hold time in system clock cycles" "No extra,1 system clock,4 system clocks,7 system clocks"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE ,Enables the SPI interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IN_RISING ,Data is clocked in on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 9. " CLEAR_FIFOS ,The receive and transmit fifo's are held in reset" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OUT_RISING ,Data is clocked out on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 7. " INVERT_SPI_CLK ,Invert SPI CLK" "Not inverted,Inverted"
|
|
bitfld.long 0x00 6. " SHIFT_OUT_MS_BIT_FIRST ,The data is shifted out starting with the MS/LS bit" "LS,MS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SHIFT_LENGTH ,Specifies the number of bits to shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "AUX_SPI1_CNTL0,SPI 1 Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " SPEED ,Sets the SPI clock speed"
|
|
bitfld.long 0x00 17.--19. " CHIP_SELECTS ,The pattern output on the CS pins when active" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 16. " POST_INPUT_MODE ,The SPI input works in post input mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VARIABLE_CS ,The SPI takes the CS pattern and the data from the TX fifo or pattern form bits 17-19(Chip_selects) of this register" "CHIP_SELECTS,Pattern and data"
|
|
bitfld.long 0x00 14. " VARIABLE_WIDTH ,The SPI takes the shift length and the data from the TX fifo or the shift length from bits 0-5(Shift_length) of this register" "SHIFT_LENGTH,Shift length and data"
|
|
bitfld.long 0x00 12.--13. " DOUT_HOLD_TIME ,Controls the extra DOUT hold time in system clock cycles" "No extra,1 system clock,4 system clocks,7 system clocks"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE ,Enables the SPI interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IN_RISING ,Data is clocked in on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 9. " CLEAR_FIFOS ,The receive and transmit fifo's are held in reset" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OUT_RISING ,Data is clocked out on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 7. " INVERT_SPI_CLK ,Invert SPI CLK" "Not inverted,Inverted"
|
|
bitfld.long 0x00 6. " SHIFT_OUT_MS_BIT_FIRST ,The data is shifted out starting with the MS/LS bit" "LS,MS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SHIFT_LENGTH ,Specifies the number of bits to shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "AUX_SPI1_CNTL1,SPI 1 Control Register 1"
|
|
bitfld.long 0x00 8.--10. " CS_HIGH_TIME ,Additional SPI clock cycles where the CS is high" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " TX_EMPTY_IRQ ,Transmit FIFO empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " DONE_IRQ ,Interface idle interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SHIFT_IN_MS_BIT_FIRST ,The data is shifted in starting with the MS/LS bit" "LS,MS"
|
|
bitfld.long 0x00 0. " KEEP_INPUT ,The input shift register is not cleared between transactions" "No,Yes"
|
|
line.long 0x04 "AUX_SPI1_STAT,SPI 1 Status Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TX_FIFO_LEVEL ,The number of data units in the transmit data FIFO"
|
|
hexmask.long.word 0x04 12.--23. 1. " RX_FIFO_LEVEL ,The number of data units in the receive data FIFO"
|
|
bitfld.long 0x04 6. " BUSY ,Indicates the module is busy transferring data" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TX_FULL ,The transmit FIFO is full" "Not full,Full"
|
|
bitfld.long 0x04 3. " TX_EMPTY ,The transmit FIFO is empty" "Not empty,Empty"
|
|
bitfld.long 0x04 2. " RX_EMPTY ,The receiver FIFO is empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " BIT_COUNT ,The number of bits still to be processed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "AUX_SPI1_PEEK,SPI 1 Peek Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Received data of the SPI interfaces"
|
|
hgroup.long (0x80+0x10)++0x03
|
|
hide.long 0x00 "AUX_SPI1_IO,SPI 1 Data Register"
|
|
in
|
|
hgroup.long (0x80+0x30)++0x03
|
|
hide.long 0x00 "AUX_SPI1_TXHOLD,SPI 1 TXHOLD Register"
|
|
in
|
|
tree.end
|
|
tree "SPI 2"
|
|
if (((per.l(ad:0x20215000+0xC0))&0x4000)==0x00)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "AUX_SPI2_CNTL0,SPI 2 Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " SPEED ,Sets the SPI clock speed"
|
|
bitfld.long 0x00 17.--19. " CHIP_SELECTS ,The pattern output on the CS pins when active" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 16. " POST_INPUT_MODE ,The SPI input works in post input mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VARIABLE_CS ,The SPI takes the CS pattern and the data from the TX fifo or pattern form bits 17-19 (CHIP_SELECTS) of this register" "CHIP_SELECTS,?..."
|
|
bitfld.long 0x00 14. " VARIABLE_WIDTH ,The SPI takes the shift length and the data from the TX fifo or the shift length from bits 0-5 (SHIFT_LENGTH) of this register" "SHIFT_LENGTH,Shift length and data"
|
|
bitfld.long 0x00 12.--13. " DOUT_HOLD_TIME ,Controls the extra DOUT hold time in system clock cycles" "No extra,1 system clock,4 system clocks,7 system clocks"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE ,Enables the SPI interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IN_RISING ,Data is clocked in on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 9. " CLEAR_FIFOS ,The receive and transmit fifo's are held in reset" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OUT_RISING ,Data is clocked out on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 7. " INVERT_SPI_CLK ,Invert SPI CLK" "Not inverted,Inverted"
|
|
bitfld.long 0x00 6. " SHIFT_OUT_MS_BIT_FIRST ,The data is shifted out starting with the MS/LS bit" "LS,MS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SHIFT_LENGTH ,Specifies the number of bits to shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "AUX_SPI2_CNTL0,SPI 2 Control Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " SPEED ,Sets the SPI clock speed"
|
|
bitfld.long 0x00 17.--19. " CHIP_SELECTS ,The pattern output on the CS pins when active" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 16. " POST_INPUT_MODE ,The SPI input works in post input mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VARIABLE_CS ,The SPI takes the CS pattern and the data from the TX fifo or pattern form bits 17-19(Chip_selects) of this register" "CHIP_SELECTS,Pattern and data"
|
|
bitfld.long 0x00 14. " VARIABLE_WIDTH ,The SPI takes the shift length and the data from the TX fifo or the shift length from bits 0-5(Shift_length) of this register" "SHIFT_LENGTH,Shift length and data"
|
|
bitfld.long 0x00 12.--13. " DOUT_HOLD_TIME ,Controls the extra DOUT hold time in system clock cycles" "No extra,1 system clock,4 system clocks,7 system clocks"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE ,Enables the SPI interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IN_RISING ,Data is clocked in on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 9. " CLEAR_FIFOS ,The receive and transmit fifo's are held in reset" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OUT_RISING ,Data is clocked out on the rising/falling edge of the SPI clock" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 7. " INVERT_SPI_CLK ,Invert SPI CLK" "Not inverted,Inverted"
|
|
bitfld.long 0x00 6. " SHIFT_OUT_MS_BIT_FIRST ,The data is shifted out starting with the MS/LS bit" "LS,MS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " SHIFT_LENGTH ,Specifies the number of bits to shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long (0xC0+0x04)++0x07
|
|
line.long 0x00 "AUX_SPI2_CNTL1,SPI 2 Control Register 1"
|
|
bitfld.long 0x00 8.--10. " CS_HIGH_TIME ,Additional SPI clock cycles where the CS is high" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " TX_EMPTY_IRQ ,Transmit FIFO empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " DONE_IRQ ,Interface idle interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SHIFT_IN_MS_BIT_FIRST ,The data is shifted in starting with the MS/LS bit" "LS,MS"
|
|
bitfld.long 0x00 0. " KEEP_INPUT ,The input shift register is not cleared between transactions" "No,Yes"
|
|
line.long 0x04 "AUX_SPI2_STAT,SPI 2 Status Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TX_FIFO_LEVEL ,The number of data units in the transmit data FIFO"
|
|
hexmask.long.word 0x04 12.--23. 1. " RX_FIFO_LEVEL ,The number of data units in the receive data FIFO"
|
|
bitfld.long 0x04 6. " BUSY ,Indicates the module is busy transferring data" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TX_FULL ,The transmit FIFO is full" "Not full,Full"
|
|
bitfld.long 0x04 3. " TX_EMPTY ,The transmit FIFO is empty" "Not empty,Empty"
|
|
bitfld.long 0x04 2. " RX_EMPTY ,The receiver FIFO is empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " BIT_COUNT ,The number of bits still to be processed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long (0xC0+0x14)++0x03
|
|
line.long 0x00 "AUX_SPI2_PEEK,SPI 2 Peek Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Received data of the SPI interfaces"
|
|
hgroup.long (0xC0+0x10)++0x03
|
|
hide.long 0x00 "AUX_SPI2_IO,SPI 2 Data Register"
|
|
in
|
|
hgroup.long (0xC0+0x30)++0x03
|
|
hide.long 0x00 "AUX_SPI2_TXHOLD,SPI 2 TXHOLD Register"
|
|
in
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "BSC (Broadcom Serial Controller)"
|
|
tree "BSC0"
|
|
base ad:0x20205000
|
|
width 6.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "C,Control Register"
|
|
bitfld.long 0x00 15. " I2CEN ,I2C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTR ,Interrupt on RX" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTT ,Interrupt on TX" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTD ,Interrupt on DONE" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ST ,Start transfer" "No effect,Start"
|
|
bitfld.long 0x00 4.--5. " CLEAR ,FIFO clear" "No effect,Clear,Clear,Clear"
|
|
bitfld.long 0x00 0. " READ ,Read transfer" "Write,Read"
|
|
line.long 0x04 "S,Status Register"
|
|
eventfld.long 0x04 9. " CLKT ,Clock stretch timeout" "No error,Error"
|
|
eventfld.long 0x04 8. " ERR ,ACK error" "No error,Error"
|
|
rbitfld.long 0x04 7. " RXF ,FIFO full" "Not full,Full"
|
|
rbitfld.long 0x04 6. " TXE ,FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x04 5. " RXD ,FIFO contains data" "No,Yes"
|
|
rbitfld.long 0x04 4. " TXD ,FIFO can accept data" "No,Yes"
|
|
rbitfld.long 0x04 3. " RXR ,FIFO needs reading (Full)" "Not full,Full"
|
|
rbitfld.long 0x04 2. " TXW ,FIFO needs writing (Full)" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x04 1. " DONE ,Transfer done" "Not completed,Completed"
|
|
rbitfld.long 0x04 0. " TA ,Transfer active" "Inactive,Active"
|
|
line.long 0x08 "DLEN,Data Length Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DLEN ,Data length"
|
|
line.long 0x0C "A,Slave Address Register"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " ADDR ,Slave address"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "FIFO,Data FIFO Register"
|
|
in
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "DIV,Clock Divider Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDIV ,Clock divider"
|
|
line.long 0x04 "DEL,Data Delay Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " FEDL ,Falling edge delay"
|
|
hexmask.long.word 0x04 0.--15. 1. " REDL ,Rising edge delay"
|
|
line.long 0x08 "CLKT,Clock Stretch Timeout Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TOUT ,Clock stretch timeout value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BSC1"
|
|
base ad:0x20804000
|
|
width 6.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "C,Control Register"
|
|
bitfld.long 0x00 15. " I2CEN ,I2C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTR ,Interrupt on RX" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTT ,Interrupt on TX" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTD ,Interrupt on DONE" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ST ,Start transfer" "No effect,Start"
|
|
bitfld.long 0x00 4.--5. " CLEAR ,FIFO clear" "No effect,Clear,Clear,Clear"
|
|
bitfld.long 0x00 0. " READ ,Read transfer" "Write,Read"
|
|
line.long 0x04 "S,Status Register"
|
|
eventfld.long 0x04 9. " CLKT ,Clock stretch timeout" "No error,Error"
|
|
eventfld.long 0x04 8. " ERR ,ACK error" "No error,Error"
|
|
rbitfld.long 0x04 7. " RXF ,FIFO full" "Not full,Full"
|
|
rbitfld.long 0x04 6. " TXE ,FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x04 5. " RXD ,FIFO contains data" "No,Yes"
|
|
rbitfld.long 0x04 4. " TXD ,FIFO can accept data" "No,Yes"
|
|
rbitfld.long 0x04 3. " RXR ,FIFO needs reading (Full)" "Not full,Full"
|
|
rbitfld.long 0x04 2. " TXW ,FIFO needs writing (Full)" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x04 1. " DONE ,Transfer done" "Not completed,Completed"
|
|
rbitfld.long 0x04 0. " TA ,Transfer active" "Inactive,Active"
|
|
line.long 0x08 "DLEN,Data Length Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DLEN ,Data length"
|
|
line.long 0x0C "A,Slave Address Register"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " ADDR ,Slave address"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "FIFO,Data FIFO Register"
|
|
in
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "DIV,Clock Divider Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDIV ,Clock divider"
|
|
line.long 0x04 "DEL,Data Delay Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " FEDL ,Falling edge delay"
|
|
hexmask.long.word 0x04 0.--15. 1. " REDL ,Rising edge delay"
|
|
line.long 0x08 "CLKT,Clock Stretch Timeout Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TOUT ,Clock stretch timeout value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
tree "DMA Channel 0"
|
|
base ad:0x20007000
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH0_CS,DMA Channel 0 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH0_CONBLK_AD,DMA Channel 0 Control Block Address Register"
|
|
line.long 0x08 "CH0_TI,DMA Channel 0 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH0_SOURCE_AD,DMA Channel 0 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH0_DEST_AD,DMA Channel 0 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007000+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0_TXFR_LEN,DMA Channel 0 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH0_STRIDE,DMA Channel 0 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH0_TXFR_LEN,DMA Channel 0 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH0_STRIDE,DMA Channel 0 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH0_NEXTCONBK,DMA Channel 0 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH0_DEBUG,DMA Channel 0 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 1"
|
|
base ad:0x20007100
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH1_CS,DMA Channel 1 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH1_CONBLK_AD,DMA Channel 1 Control Block Address Register"
|
|
line.long 0x08 "CH1_TI,DMA Channel 1 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH1_SOURCE_AD,DMA Channel 1 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH1_DEST_AD,DMA Channel 1 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007100+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH1_TXFR_LEN,DMA Channel 1 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH1_STRIDE,DMA Channel 1 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH1_TXFR_LEN,DMA Channel 1 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH1_STRIDE,DMA Channel 1 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH1_NEXTCONBK,DMA Channel 1 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH1_DEBUG,DMA Channel 1 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 2"
|
|
base ad:0x20007200
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH2_CS,DMA Channel 2 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH2_CONBLK_AD,DMA Channel 2 Control Block Address Register"
|
|
line.long 0x08 "CH2_TI,DMA Channel 2 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH2_SOURCE_AD,DMA Channel 2 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH2_DEST_AD,DMA Channel 2 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007200+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH2_TXFR_LEN,DMA Channel 2 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH2_STRIDE,DMA Channel 2 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH2_TXFR_LEN,DMA Channel 2 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH2_STRIDE,DMA Channel 2 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH2_NEXTCONBK,DMA Channel 2 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH2_DEBUG,DMA Channel 2 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 3"
|
|
base ad:0x20007300
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH3_CS,DMA Channel 3 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH3_CONBLK_AD,DMA Channel 3 Control Block Address Register"
|
|
line.long 0x08 "CH3_TI,DMA Channel 3 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH3_SOURCE_AD,DMA Channel 3 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH3_DEST_AD,DMA Channel 3 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007300+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH3_TXFR_LEN,DMA Channel 3 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH3_STRIDE,DMA Channel 3 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH3_TXFR_LEN,DMA Channel 3 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH3_STRIDE,DMA Channel 3 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH3_NEXTCONBK,DMA Channel 3 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH3_DEBUG,DMA Channel 3 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 4"
|
|
base ad:0x20007400
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH4_CS,DMA Channel 4 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH4_CONBLK_AD,DMA Channel 4 Control Block Address Register"
|
|
line.long 0x08 "CH4_TI,DMA Channel 4 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH4_SOURCE_AD,DMA Channel 4 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH4_DEST_AD,DMA Channel 4 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007400+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH4_TXFR_LEN,DMA Channel 4 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH4_STRIDE,DMA Channel 4 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH4_TXFR_LEN,DMA Channel 4 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH4_STRIDE,DMA Channel 4 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH4_NEXTCONBK,DMA Channel 4 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH4_DEBUG,DMA Channel 4 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 5"
|
|
base ad:0x20007500
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH5_CS,DMA Channel 5 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH5_CONBLK_AD,DMA Channel 5 Control Block Address Register"
|
|
line.long 0x08 "CH5_TI,DMA Channel 5 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH5_SOURCE_AD,DMA Channel 5 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH5_DEST_AD,DMA Channel 5 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007500+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH5_TXFR_LEN,DMA Channel 5 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH5_STRIDE,DMA Channel 5 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH5_TXFR_LEN,DMA Channel 5 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH5_STRIDE,DMA Channel 5 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH5_NEXTCONBK,DMA Channel 5 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH5_DEBUG,DMA Channel 5 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 6"
|
|
base ad:0x20007600
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH6_CS,DMA Channel 6 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH6_CONBLK_AD,DMA Channel 6 Control Block Address Register"
|
|
line.long 0x08 "CH6_TI,DMA Channel 6 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH6_SOURCE_AD,DMA Channel 6 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH6_DEST_AD,DMA Channel 6 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20007600+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH6_TXFR_LEN,DMA Channel 6 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH6_STRIDE,DMA Channel 6 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH6_TXFR_LEN,DMA Channel 6 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH6_STRIDE,DMA Channel 6 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH6_NEXTCONBK,DMA Channel 6 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH6_DEBUG,DMA Channel 6 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 7"
|
|
base ad:0x20007700
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH7_CS,DMA Channel 7 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH7_CONBLK_AD,DMA Channel 7 Control Block Address Register"
|
|
line.long 0x08 "CH7_TI,DMA Channel 7 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH7_SOURCE_AD,DMA Channel 7 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH7_DEST_AD,DMA Channel 7 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH7_TXFR_LEN,DMA Channel 7 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH7_STRIDE,DMA Channel 7 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH7_NEXTCONBK,DMA Channel 7 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH7_DEBUG,DMA Channel 7 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 8"
|
|
base ad:0x20007800
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH8_CS,DMA Channel 8 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH8_CONBLK_AD,DMA Channel 8 Control Block Address Register"
|
|
line.long 0x08 "CH8_TI,DMA Channel 8 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH8_SOURCE_AD,DMA Channel 8 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH8_DEST_AD,DMA Channel 8 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH8_TXFR_LEN,DMA Channel 8 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH8_STRIDE,DMA Channel 8 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH8_NEXTCONBK,DMA Channel 8 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH8_DEBUG,DMA Channel 8 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 9"
|
|
base ad:0x20007900
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH9_CS,DMA Channel 9 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH9_CONBLK_AD,DMA Channel 9 Control Block Address Register"
|
|
line.long 0x08 "CH9_TI,DMA Channel 9 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH9_SOURCE_AD,DMA Channel 9 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH9_DEST_AD,DMA Channel 9 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH9_TXFR_LEN,DMA Channel 9 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH9_STRIDE,DMA Channel 9 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH9_NEXTCONBK,DMA Channel 9 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH9_DEBUG,DMA Channel 9 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 10"
|
|
base ad:0x20007A00
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH10_CS,DMA Channel 10 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH10_CONBLK_AD,DMA Channel 10 Control Block Address Register"
|
|
line.long 0x08 "CH10_TI,DMA Channel 10 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH10_SOURCE_AD,DMA Channel 10 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH10_DEST_AD,DMA Channel 10 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH10_TXFR_LEN,DMA Channel 10 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH10_STRIDE,DMA Channel 10 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH10_NEXTCONBK,DMA Channel 10 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH10_DEBUG,DMA Channel 10 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 11"
|
|
base ad:0x20007B00
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH11_CS,DMA Channel 11 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH11_CONBLK_AD,DMA Channel 11 Control Block Address Register"
|
|
line.long 0x08 "CH11_TI,DMA Channel 11 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH11_SOURCE_AD,DMA Channel 11 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH11_DEST_AD,DMA Channel 11 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH11_TXFR_LEN,DMA Channel 11 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH11_STRIDE,DMA Channel 11 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH11_NEXTCONBK,DMA Channel 11 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH11_DEBUG,DMA Channel 11 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 12"
|
|
base ad:0x20007C00
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH12_CS,DMA Channel 12 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH12_CONBLK_AD,DMA Channel 12 Control Block Address Register"
|
|
line.long 0x08 "CH12_TI,DMA Channel 12 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH12_SOURCE_AD,DMA Channel 12 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH12_DEST_AD,DMA Channel 12 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH12_TXFR_LEN,DMA Channel 12 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH12_STRIDE,DMA Channel 12 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH12_NEXTCONBK,DMA Channel 12 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH12_DEBUG,DMA Channel 12 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 13"
|
|
base ad:0x20007D00
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH13_CS,DMA Channel 13 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH13_CONBLK_AD,DMA Channel 13 Control Block Address Register"
|
|
line.long 0x08 "CH13_TI,DMA Channel 13 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH13_SOURCE_AD,DMA Channel 13 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH13_DEST_AD,DMA Channel 13 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH13_TXFR_LEN,DMA Channel 13 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH13_STRIDE,DMA Channel 13 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH13_NEXTCONBK,DMA Channel 13 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH13_DEBUG,DMA Channel 13 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 14"
|
|
base ad:0x20007E00
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH14_CS,DMA Channel 14 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH14_CONBLK_AD,DMA Channel 14 Control Block Address Register"
|
|
line.long 0x08 "CH14_TI,DMA Channel 14 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH14_SOURCE_AD,DMA Channel 14 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH14_DEST_AD,DMA Channel 14 CB Word 2 (Destination Address) Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH14_TXFR_LEN,DMA Channel 14 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH14_STRIDE,DMA Channel 14 CB Word 4 (2d Stride) Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH14_NEXTCONBK,DMA Channel 14 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH14_DEBUG,DMA Channel 14 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Channel 15"
|
|
base ad:0x20E05000
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CH15_CS,DMA Channel 15 Control And Status Register"
|
|
eventfld.long 0x00 31. " RESET ,DMA channel reset" "No effect,Reset"
|
|
eventfld.long 0x00 30. " ABORT ,Abort DMA" "Not aborted,Aborted"
|
|
bitfld.long 0x00 29. " DISDEBUG ,Disable debug pause signal" "No,Yes"
|
|
bitfld.long 0x00 28. " WAIT_FOR_OUTSTANDING_WRITES ,Wait for outstanding writes" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " PANIC_PRIORITY ,AXI panic priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIORITY ,AXI priority level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8. " ERROR ,DMA error" "No error,Error"
|
|
rbitfld.long 0x00 6. " WAITING_FOR_OUTSTANDING_WRITES ,DMA is waiting for the last write to be received" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DREQ_STOPS_DMA ,DMA paused by DREQ state" "Running,Paused"
|
|
rbitfld.long 0x00 4. " PAUSED ,DMA paused state" "Running,Paused"
|
|
rbitfld.long 0x00 3. " DREQ ,Data request state" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT ,Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " END ,DMA end flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ACTIVE ,Activate the DMA" "Disabled,Enabled"
|
|
line.long 0x04 "CH15_CONBLK_AD,DMA Channel 15 Control Block Address Register"
|
|
line.long 0x08 "CH15_TI,DMA Channel 15 CB Word 0 (Transfer Information) Register"
|
|
bitfld.long 0x08 26. " NO_WIDE_BURSTS ,Don't do wide writes as a 2 beat burst" "No,Yes"
|
|
bitfld.long 0x08 21.--25. " WAITS ,Add wait cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " PERMAP ,Peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 12.--15. " BURST_LENGTH ,Burst transfer length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRC_IGNORE ,Ignore reads" "Not ignored,Ignored"
|
|
bitfld.long 0x08 10. " SRC_DREQ ,Control source reads with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 9. " SRC_WIDTH ,Source transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 8. " SRC_INC ,Source address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DEST_IGNORE ,Ignore writes" "Not ignored,Ignored"
|
|
bitfld.long 0x08 6. " DEST_DREQ ,Control destination writes with DREQ" "No effect,Selected"
|
|
bitfld.long 0x08 5. " DEST_WIDTH ,Destination transfer width" "32-bit,128-bit"
|
|
bitfld.long 0x08 4. " DEST_INC ,Destination address increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAIT_RESP ,Wait for a write response" "No,Yes"
|
|
bitfld.long 0x08 1. " TDMODE ,2D mode" "Linear mode,2D mode"
|
|
bitfld.long 0x08 0. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CH15_SOURCE_AD,DMA Channel 15 CB Word 1 (Source Address) Register"
|
|
line.long 0x10 "CH15_DEST_AD,DMA Channel 15 CB Word 2 (Destination Address) Register"
|
|
if (((per.l(ad:0x20E05000+0x08))&0x02)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH15_TXFR_LEN,DMA Channel 15 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long 0x00 0.--29. 1. " XLENGTH ,Transfer length in bytes"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CH15_STRIDE,DMA Channel 15 CB Word 4 (2d Stride) Register"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CH15_TXFR_LEN,DMA Channel 15 CB Word 3 (Transfer Length) Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " YLENGTH ,Y transfer length in bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " XLENGTH ,X transfer length in bytes"
|
|
line.long 0x04 "CH15_STRIDE,DMA Channel 15 CB Word 4 (2d Stride) Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " D_STRIDE ,Destination stride"
|
|
hexmask.long.word 0x04 0.--15. 1. " S_STRIDE ,Source stride"
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CH15_NEXTCONBK,DMA Channel 15 CB Word 5 (Next CB Address) Register"
|
|
line.long 0x04 "CH15_DEBUG,DMA Channel 15 Debug Register"
|
|
rbitfld.long 0x04 28. " LITE ,DMA lite" "Normal,Lite"
|
|
rbitfld.long 0x04 25.--27. " VERSION ,DMA version" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x04 16.--24. 1. " DMA_STATE ,DMA state machine state"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMA_ID ,DMA ID"
|
|
textline " "
|
|
rbitfld.long 0x04 4.--7. " OUTSTANDING_WRITES ,DMA outstanding writes counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x04 2. " READ_ERROR ,Slave read response error" "No error,Error"
|
|
eventfld.long 0x04 1. " FIFO_ERROR ,FIFO error" "No error,Error"
|
|
eventfld.long 0x04 0. " READ_LAST_NOT_SET_ERROR ,Read last not set error" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA Global Registers"
|
|
base ad:0x20007FE0
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_STATUS,Interrupt Status Of Each DMA Channel Register"
|
|
bitfld.long 0x00 15. " INT15 ,Interrupt status of DMA engine 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INT14 ,Interrupt status of DMA engine 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INT13 ,Interrupt status of DMA engine 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INT12 ,Interrupt status of DMA engine 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT11 ,Interrupt status of DMA engine 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INT10 ,Interrupt status of DMA engine 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INT9 ,Interrupt status of DMA engine 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INT8 ,Interrupt status of DMA engine 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INT7 ,Interrupt status of DMA engine 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INT6 ,Interrupt status of DMA engine 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INT5 ,Interrupt status of DMA engine 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INT4 ,Interrupt status of DMA engine 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT3 ,Interrupt status of DMA engine 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INT2 ,Interrupt status of DMA engine 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INT1 ,Interrupt status of DMA engine 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INT0 ,Interrupt status of DMA engine 0" "No interrupt,Interrupt"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ENABLE,Global Enable Bits For Each DMA Channel Register"
|
|
bitfld.long 0x00 14. " EN14 ,Enable DMA engine 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EN13 ,Enable DMA engine 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN12 ,Enable DMA engine 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN11 ,Enable DMA engine 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN10 ,Enable DMA engine 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EN9 ,Enable DMA engine 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EN8 ,Enable DMA engine 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN7 ,Enable DMA engine 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN6 ,Enable DMA engine 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN5 ,Enable DMA engine 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN4 ,Enable DMA engine 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN3 ,Enable DMA engine 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN2 ,Enable DMA engine 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN1 ,Enable DMA engine 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN0 ,Enable DMA engine 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "EMMC (External Mass Media Controller)"
|
|
base ad:0x20300000
|
|
width 16.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "ARG2,ACMD23 Argument Register"
|
|
line.long 0x04 "BLKSIZECNT,Block Size And Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Number of blocks to be transferred"
|
|
hexmask.long.word 0x04 0.--9. 1. " BLKSIZE ,Block size in bytes"
|
|
line.long 0x08 "ARG1,Argument Register"
|
|
line.long 0x0C "CMDTM,Command And Transfer Mode Register"
|
|
bitfld.long 0x0C 24.--29. " CMD_INDEX ,Index of the command to be issued to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 22.--23. " CMD_TYPE ,Type of command to be issued to the card" "NORMAL,SUSPEND,RESUME,ABORT"
|
|
bitfld.long 0x0C 21. " CMD_ISDATA ,Command involves data transfer" "No data present,Data present"
|
|
bitfld.long 0x0C 20. " CMD_IXCHK_EN ,Check that response has same index as command" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CMD_CRCCHK_EN ,Check the responses CRC" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " CMD_RSPNS_TYPE ,Type of expected response from card" "No resp.,136 resp.,48 resp.,48 resp. Busy"
|
|
bitfld.long 0x0C 5. " TM_MULTI_BLOCK ,Type of data transfer" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " TM_DAT_DIR ,Direction of data transfer" "Host to card,Card to host"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " TM_AUTO_CMD_EN ,Select the command to be send after completion of a data transfer" "Disabled,CMD12,CMD23,?..."
|
|
bitfld.long 0x0C 1. " TM_BLKCNT_EN ,Enable the block counter for multiple block transfers" "Disabled,Enabled"
|
|
line.long 0x10 "RESP0,Response Bits 31 : 0 Register"
|
|
line.long 0x14 "RESP1,Response Bits 63 : 32 Register"
|
|
line.long 0x18 "RESP2,Response Bits 95 : 64 Register"
|
|
line.long 0x1C "RESP3,Response Bits 127 : 96 Register"
|
|
line.long 0x20 "DATA,Data Register"
|
|
line.long 0x24 "SATUS,Status Register"
|
|
bitfld.long 0x24 25.--28. " DAT_LEVEL1 ,Value of data lines DAT7 to DAT4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 24. " CMD_LEVEL ,Value of command line CMD" "0,1"
|
|
bitfld.long 0x24 20.--23. " DAT_LEVEL0 ,Value of data lines DAT3 to DAT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 9. " READ_TRANSFER ,New data can be read from EMMC" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x24 8. " WRITE_TRANSFER ,New data can be written from EMMC" "No,Yes"
|
|
bitfld.long 0x24 2. " DAT_ACTIVE ,At least one data line is active" "No,Yes"
|
|
bitfld.long 0x24 1. " DAT_INHIBIT ,Data lines still used by previous data transfer" "No,Yes"
|
|
bitfld.long 0x24 0. " CMD_INHIBIT ,Command line still used by previous command" "No,Yes"
|
|
if (((per.l(ad:0x20300000+0x28))&0x02)==0x02)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CONTROL0,Host Configuration Bits Register 0"
|
|
bitfld.long 0x00 22. " ALT_BOOT_EN ,Enable alternate boot mode access" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOT_EN ,Boot mode access" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SPI_MODE ,SPI mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " GAP_IEN ,Enable SDIO interrupt at block gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " READWAIT_EN ,Use DAT2 read-wait protocol for SDIO cards" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GAP_RESTART ,Restart a transaction which was stopped using the GAP_STOP bit" "Ignore,Restart"
|
|
bitfld.long 0x00 16. " GAP_STOP ,Stop the current transaction at the next block gap" "Ignore,Stop"
|
|
bitfld.long 0x00 5. " HCTL_8BIT ,Use 8 data lines" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HCTL_HS_EN ,Select high speed mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HCTL_DWIDTH ,Use 4 data lines" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CONTROL0,Host Configuration Bits Register 0"
|
|
bitfld.long 0x00 22. " ALT_BOOT_EN ,Enable alternate boot mode access" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BOOT_EN ,Boot mode access" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SPI_MODE ,SPI mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " READWAIT_EN ,Use DAT2 read-wait protocol for SDIO cards" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " GAP_RESTART ,Restart a transaction which was stopped using the GAP_STOP bit" "Ignore,Restart"
|
|
bitfld.long 0x00 16. " GAP_STOP ,Stop the current transaction at the next block gap" "Ignore,Stop"
|
|
bitfld.long 0x00 5. " HCTL_8BIT ,Use 8 data lines" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HCTL_HS_EN ,Select high speed mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HCTL_DWIDTH ,Use 4 data lines" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x2C++0x13
|
|
line.long 0x00 "CONTROL1,Host Configuration Bits Register 1"
|
|
bitfld.long 0x00 26. " SRST_DATA ,Reset the data handling circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SRST_CMD ,Reset the command handling circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SRST_HC ,Reset the complete host circuit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " DATA_TOUNIT ,Data timeout unit exponent" "TMCLK*2^13,TMCLK*2^14,TMCLK*2^15,TMCLK*2^16,TMCLK*2^17,TMCLK*2^18,TMCLK*2^19,TMCLK*2^20,TMCLK*2^21,TMCLK*2^22,TMCLK*2^23,TMCLK*2^24,TMCLK*2^25,TMCLK*2^26,TMCLK*2^27,Disabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLK_FREQ8 ,SD clock base divider LSBs"
|
|
bitfld.long 0x00 6.--7. " CLK_FREQ_MS2 ,SD clock base divider MSBs" "0,1,2,3"
|
|
bitfld.long 0x00 5. " CLK_GENSEL ,Mode of clock generation" "Divided,Programmable"
|
|
bitfld.long 0x00 2. " CLK_EN ,SD clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLK_STABLE ,SD clock stable" "No,Yes"
|
|
bitfld.long 0x00 0. " CLK_INTLEN ,Clock enable for internal EMMC clocks for power saving" "Disabled,Enabled"
|
|
line.long 0x04 "INTERRUPT,Interrupt Flags Register"
|
|
bitfld.long 0x04 24. " ACMD_ERR ,Auto command error" "No error,Error"
|
|
bitfld.long 0x04 22. " DEND_ERR ,End bit on data line not 1" "No error,Error"
|
|
bitfld.long 0x04 21. " DCRC_ERR ,Data CRC error" "No error,Error"
|
|
bitfld.long 0x04 20. " DTO_ERR ,Timeout on data line" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CBAD_ERR ,Incorrect command index in response" "No error,Error"
|
|
bitfld.long 0x04 18. " CEND_ERR ,End bit on command line not 1" "No error,Error"
|
|
bitfld.long 0x04 17. " CCRC_ERR ,Command CRC error" "No error,Error"
|
|
bitfld.long 0x04 16. " CTO_ERR ,Timeout on command line" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x04 15. " ERR ,An error has occurred" "No error,Error"
|
|
bitfld.long 0x04 14. " ENDBOOT ,Boot operation has terminated" "No,Yes"
|
|
bitfld.long 0x04 13. " BOOTACK ,Boot acknowledge has been received" "No,Yes"
|
|
bitfld.long 0x04 12. " RETUNE ,Clock retune request was made" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CARD ,Card made interrupt request" "No,Yes"
|
|
bitfld.long 0x04 5. " READ_RDY ,DATA register contains data to be read" "No,Yes"
|
|
bitfld.long 0x04 4. " WRITE_RDY ,Data can be written to DATA register" "No,Yes"
|
|
bitfld.long 0x04 2. " BLOCK_GAP ,Data transfer has stopped at block gap" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DATA_DONE ,Data transfer has finished" "No,Yes"
|
|
bitfld.long 0x04 0. " CMD_DONE ,Command has finished" "No,Yes"
|
|
line.long 0x08 "IRPT_MASK,Interrupt Flag Enable Register"
|
|
bitfld.long 0x08 24. " ACMD_ERR ,Auto command error mask" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " DEND_ERR ,End bit on data line not 1 mask" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " DCRC_ERR ,Data CRC error mask" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " DTO_ERR ,Timeout on data line mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CBAD_ERR ,Incorrect command index in response mask" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " CEND_ERR ,End bit on command line not 1 mask" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " CCRC_ERR ,Command CRC error mask" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " CTO_ERR ,Timeout on command line mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " ENDBOOT ,Boot operation has terminated interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " BOOTACK ,Boot acknowledge has been received interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " RETUNE ,Clock retune request was made interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CARD ,Card made interrupt request interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " READ_RDY ,DATA register contains data to be read interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " WRITE_RDY ,Data can be written to DATA register interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " BLOCK_GAP ,Data transfer has stopped at block gap interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DATA_DONE ,Data transfer has finished interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " CMD_DONE ,Command has finished interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "IRPT_EN,Interrupt Generation Enable Register"
|
|
bitfld.long 0x0C 24. " ACMD_ERR ,Auto command error interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " DEND_ERR ,End bit on data line not 1 interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " DCRC_ERR ,Data CRC error interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ERR ,Timeout on data line interrupt generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CBAD_ERR ,Incorrect command index in response interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " CEND_ERR ,End bit on command line not 1 interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " CCRC_ERR ,Command CRC error generation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ERR ,Timeout on command line interrupt generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " ENDBOOT ,Boot operation has terminated interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " BOOTACK ,Boot acknowledge has been received interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " RETUNE ,Clock retune request was made interrupt generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CARD ,Card made interrupt request interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " READ_RDY ,DATA register contains data to be read interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " WRITE_RDY ,Data can be written to DATA register interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " BLOCK_GAP ,Data transfer has stopped at block gap interrupt generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DATA_DONE ,Data transfer has finished interrupt generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " CMD_DONE ,Command has finished interrupt generation enable" "Disabled,Enabled"
|
|
line.long 0x10 "CONTROL2,Host Configuration Bits Register 2"
|
|
bitfld.long 0x10 23. " TUNED ,Tuned clock is used for sampling data" "No,Yes"
|
|
bitfld.long 0x10 22. " TUNEON ,Start tuning the SD clock" "Not started or completed,Started"
|
|
bitfld.long 0x10 16.--18. " UHSMODE ,Select the speed mode of the SD card" "SDR12,SDR25,SDR50,SDR104,DDR50,?..."
|
|
rbitfld.long 0x10 7. " NOTC12_ERR ,Error occurred during auto command CMD12 execution" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x10 4. " ACBAD_ERR ,Command index error occurred during auto command execution" "No error,Error"
|
|
rbitfld.long 0x10 3. " ACEND_ERR ,End bit is not 1 during auto command execution" "No error,Error"
|
|
rbitfld.long 0x10 2. " ACCRC_ERR ,Command CRC error occurred during auto command execution" "No error,Error"
|
|
rbitfld.long 0x10 1. " ACTO_ERR ,Timeout occurred during auto command execution" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x10 0. " ACNOX_ERR ,Auto command not executed due to an error" "No,Yes"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FORCE_IRPT,Force Interrupt Event Register"
|
|
bitfld.long 0x00 24. " ACMD_ERR ,Create auto command error" "No,Yes"
|
|
bitfld.long 0x00 22. " DEND_ERR ,Create end bit on data line not 1" "No,Yes"
|
|
bitfld.long 0x00 21. " DCRC_ERR ,Create data CRC error" "No,Yes"
|
|
bitfld.long 0x00 20. " DTO_ERR ,Create timeout on data line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBAD_ERR ,Create incorrect command index in response" "No,Yes"
|
|
bitfld.long 0x00 18. " CEND_ERR ,Create end bit on command line not 1" "No,Yes"
|
|
bitfld.long 0x00 17. " CCRC_ERR ,Create command CRC error" "No,Yes"
|
|
bitfld.long 0x00 16. " CTO_ERR ,Create timeout on command line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ENDBOOT ,Create interrupt boot operation has terminated" "No,Yes"
|
|
bitfld.long 0x00 13. " BOOTACK ,Create interrupt boot acknowledge has been received" "No,Yes"
|
|
bitfld.long 0x00 12. " RETUNE ,Create interrupt clock retune request was made" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CARD ,Create interrupt card made interrupt request" "No,Yes"
|
|
bitfld.long 0x00 5. " READ_RDY ,Create interrupt DATA register contains data to be read" "No,Yes"
|
|
bitfld.long 0x00 4. " WRITE_RDY ,Create interrupt data can be written to DATA register" "No,Yes"
|
|
bitfld.long 0x00 2. " BLOCK_GAP ,Create interrupt data transfer has stopped at block gap" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA_DONE ,Create interrupt data transfer has finished" "No,Yes"
|
|
bitfld.long 0x00 0. " CMD_DONE ,Create interrupt command has finished" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "BOOT_TIMEOUT,Timeout In Boot Mode Register"
|
|
line.long 0x04 "DBG_SEL,Debug Bus Configuration Register"
|
|
bitfld.long 0x04 0. " SELECT ,Submodules accessed by debug bus" "Receiver and fifo_ctrl,Others"
|
|
group.long 0x80++0x13
|
|
line.long 0x00 "EXRDFIFO_CFG,Extension FIFO Configuration Register"
|
|
bitfld.long 0x00 0.--2. " RD_THRSH ,Read threshold in 32 bits words" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "EXRDFIFO_EN,Extension FIFO Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,Enable the extension FIFO" "Disabled,Enabled"
|
|
line.long 0x08 "TUNE_STEP,Delay Per Card Clock Tuning Step Register"
|
|
bitfld.long 0x08 0.--2. " DELAY ,Sampling clock delay per step" "200ps,400ps,400ps,600ps,700ps,900ps,900ps,1100ps"
|
|
line.long 0x0C "TUNE_STEPS_STD,Card Clock Tuning Steps For SDR Register"
|
|
bitfld.long 0x0C 0.--5. " STEPS ,Number of steps" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,?..."
|
|
line.long 0x10 "TUNE_STEPS_DDR,Card Clock Tuning Steps For DDR Register"
|
|
bitfld.long 0x10 0.--5. " STEPS ,Number of steps" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,?..."
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "SPI_INT_SPT,SPI Interrupt Support Register"
|
|
bitfld.long 0x00 7. " SELECT[7] ,Interrupt independent of card select line 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt independent of card select line 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt independent of card select line 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt independent of card select line 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Interrupt independent of card select line 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt independent of card select line 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt independent of card select line 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt independent of card select line 0" "No,Yes"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "SLOTISR_VER,Slot Interrupt Status And Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VENDOR ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SDVERSION ,Host controller specification version"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_STATUS ,Logical OR of interrupt and wakeup signal for each slot"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x20200000
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "GPFSEL0,GPIO Function Select 0 Register"
|
|
bitfld.long 0x00 27.--29. " FSEL9 ,Function select 9" "Input,Output,,,SPI0_MISO,SD1,?..."
|
|
bitfld.long 0x00 24.--26. " FSEL8 ,Function select 8" "Input,Output,,,SPI0_CE0_N,SD0,?..."
|
|
bitfld.long 0x00 21.--23. " FSEL7 ,Function select 7" "Input,Output,,,SPI0_CE1_N,SWE_N/SRW_N,?..."
|
|
bitfld.long 0x00 18.--20. " FSEL6 ,Function select 6" "Input,Output,ARM_RTCK,,GPCLK2,SOE_N/SE,?..."
|
|
bitfld.long 0x00 15.--17. " FSEL5 ,Function select 5" "Input,Output,ARM_TDO,,GPCLK1,SA0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FSEL4 ,Function select 4" "Input,Output,ARM_TDI,,GPCLK0,SA1,?..."
|
|
bitfld.long 0x00 9.--11. " FSEL3 ,Function select 3" "Input,Output,,,SCL1,SA2,?..."
|
|
bitfld.long 0x00 6.--8. " FSEL2 ,Function select 2" "Input,Output,,,SDA1,SA3,?..."
|
|
bitfld.long 0x00 3.--5. " FSEL1 ,Function select 1" "Input,Output,,,SCL0,SA4,?..."
|
|
bitfld.long 0x00 0.--2. " FSEL0 ,Function select 0" "Input,Output,,,SDA0,SA5,?..."
|
|
line.long 0x04 "GPFSEL1,GPIO Function Select 1 Register"
|
|
bitfld.long 0x04 27.--29. " FSEL19 ,Function select 19" "Input,Output,PWM1,SPI1_MISO,PCM_FS,SD11,,BSCSL SCL/SCLK"
|
|
bitfld.long 0x04 24.--26. " FSEL18 ,Function select 18" "Input,Output,PWM0,SPI1_CE0_N,PCM_CLK,SD10,,BSCSL SDA/MOSI"
|
|
bitfld.long 0x04 21.--23. " FSEL17 ,Function select 17" "Input,Output,RTS1,SPI1_CE1_N,,SD9,,RTS0"
|
|
bitfld.long 0x04 18.--20. " FSEL16 ,Function select 16" "Input,Output,CTS1,SPI1_CE2_N,,SD8,,CTS0"
|
|
bitfld.long 0x04 15.--17. " FSEL15 ,Function select 15" "Input,Output,RXD1,,RXD0,SD7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " FSEL14 ,Function select 14" "Input,Output,TXD1,,TXD0,SD6,?..."
|
|
bitfld.long 0x04 9.--11. " FSEL13 ,Function select 13" "Input,Output,ARM_TCK,,PWM1,SD5,?..."
|
|
bitfld.long 0x04 6.--8. " FSEL12 ,Function select 12" "Input,Output,ARM_TMS,,PWM0,SD4,?..."
|
|
bitfld.long 0x04 3.--5. " FSEL11 ,Function select 11" "Input,Output,,,SPI0_SCLK,SD3,?..."
|
|
bitfld.long 0x04 0.--2. " FSEL10 ,Function select 10" "Input,Output,,,SPI0_MOSI,SD2,?..."
|
|
line.long 0x08 "GPFSEL2,GPIO Function Select 2 Register"
|
|
bitfld.long 0x08 27.--29. " FSEL29 ,Function select 29" "Input,Output,,,SCL0,SA4,PCM_FS,?..."
|
|
bitfld.long 0x08 24.--26. " FSEL28 ,Function select 28" "Input,Output,,,SDA0,SA5,PCM_CLK,?..."
|
|
bitfld.long 0x08 21.--23. " FSEL27 ,Function select 27" "Input,Output,,ARM_TMS,,,,SD1_DAT3"
|
|
bitfld.long 0x08 18.--20. " FSEL26 ,Function select 26" "Input,Output,,ARM_TDI,,,,SD1_DAT2"
|
|
bitfld.long 0x08 15.--17. " FSEL25 ,Function select 25" "Input,Output,,ARM_TCK,,SD17,,SD1_DAT1"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FSEL24 ,Function select 24" "Input,Output,,ARM_TDO,,SD16,,SD1_DAT0"
|
|
bitfld.long 0x08 9.--11. " FSEL23 ,Function select 23" "Input,Output,,ARM_RTCK,,SD15,,SD1_CMD"
|
|
bitfld.long 0x08 6.--8. " FSEL22 ,Function select 22" "Input,Output,,ARM_TRST,,SD14,,SD1_CLK"
|
|
bitfld.long 0x08 3.--5. " FSEL21 ,Function select 21" "Input,Output,GPCLK1,SPI1_SCLK,PCM_DOUT,SD13,,BSCSL/CE_N"
|
|
bitfld.long 0x08 0.--2. " FSEL20 ,Function select 20" "Input,Output,GPCLK0,SPI1_MOSI,PCM_DIN,SD12,,BSCSL/MISO"
|
|
line.long 0x0C "GPFSEL3,GPIO Function Select 3 Register"
|
|
bitfld.long 0x0C 27.--29. " FSEL39 ,Function select 39" "Input,Output,,,SPI0_SCLK,SD3,CTS0,?..."
|
|
bitfld.long 0x0C 24.--26. " FSEL38 ,Function select 38" "Input,Output,,,SPI0_MOSI,SD2,RTS0,?..."
|
|
bitfld.long 0x0C 21.--23. " FSEL37 ,Function select 37" "Input,Output,,,SPI0_MISO,SD1,RXD0,?..."
|
|
bitfld.long 0x0C 18.--20. " FSEL36 ,Function select 36" "Input,Output,,,SPI0_CE0_N,SD0,TXD0,?..."
|
|
bitfld.long 0x0C 15.--17. " FSEL35 ,Function select 35" "Input,Output,,,SPI0_CE1_N,SWE_N/SRW_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--14. " FSEL34 ,Function select 34" "Input,Output,,,GPCLK0,SOE_N/SE,?..."
|
|
bitfld.long 0x0C 9.--11. " FSEL33 ,Function select 33" "Input,Output,RXD1,,,SA0,,RXD0"
|
|
bitfld.long 0x0C 6.--8. " FSEL32 ,Function select 32" "Input,Output,TXD1,,GPCLK0,SA1,,TXD0"
|
|
bitfld.long 0x0C 3.--5. " FSEL31 ,Function select 31" "Input,Output,RTS1,,,SA2,PCM_DIN,RTS0"
|
|
bitfld.long 0x0C 0.--2. " FSEL30 ,Function select 30" "Input,Output,CTS1,,,SA3,PCM_DIN,CTS0"
|
|
line.long 0x10 "GPFSEL4,GPIO Function Select 4 Register"
|
|
bitfld.long 0x10 27.--29. " FSEL49 ,Function select 49" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x10 24.--26. " FSEL48 ,Function select 48" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x10 21.--23. " FSEL47 ,Function select 47" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x10 18.--20. " FSEL46 ,Function select 46" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x10 15.--17. " FSEL45 ,Function select 45" "Input,Output,,SPI2_CE2_N,PWM1,SCL0,SCL1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " FSEL44 ,Function select 44" "Input,Output,,SPI2_CE1_N,GPCLK1,SDA0,SDA1,?..."
|
|
bitfld.long 0x10 9.--11. " FSEL43 ,Function select 43" "Input,Output,CTS1,SPI2_CE0_N,GPCLK2,SD7,?..."
|
|
bitfld.long 0x10 6.--8. " FSEL42 ,Function select 42" "Input,Output,RTS1,SPI2_SCLK,GPCLK1,SD6,?..."
|
|
bitfld.long 0x10 3.--5. " FSEL41 ,Function select 41" "Input,Output,RXD1,SPI2_MOSI,PWM1,SD5,?..."
|
|
bitfld.long 0x10 0.--2. " FSEL40 ,Function select 40" "Input,Output,TXD1,SPI2_MISO,PWM0,SD4,?..."
|
|
line.long 0x14 "GPFSEL5,GPIO Function Select 5 Register"
|
|
bitfld.long 0x14 9.--11. " FSEL53 ,Function select 53" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x14 6.--8. " FSEL52 ,Function select 52" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x14 3.--5. " FSEL51 ,Function select 51" "Input,Output,,,Internal,?..."
|
|
bitfld.long 0x14 0.--2. " FSEL50 ,Function select 50" "Input,Output,,,Internal,?..."
|
|
textline " "
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "GPLEV0,GPIO Pin Level 0 Register"
|
|
setclrfld.long 0x00 31. -0x18 31. -0x0C 31. " LVL[31] ,GPIO pin 31 level" "Low,High"
|
|
setclrfld.long 0x00 30. -0x18 30. -0x0C 30. " [30] ,GPIO pin 30 level" "Low,High"
|
|
setclrfld.long 0x00 29. -0x18 29. -0x0C 29. " [29] ,GPIO pin 29 level" "Low,High"
|
|
setclrfld.long 0x00 28. -0x18 28. -0x0C 28. " [28] ,GPIO pin 28 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x18 27. -0x0C 27. " [27] ,GPIO pin 27 level" "Low,High"
|
|
setclrfld.long 0x00 26. -0x18 26. -0x0C 26. " [26] ,GPIO pin 26 level" "Low,High"
|
|
setclrfld.long 0x00 25. -0x18 25. -0x0C 25. " [25] ,GPIO pin 25 level" "Low,High"
|
|
setclrfld.long 0x00 24. -0x18 24. -0x0C 24. " [24] ,GPIO pin 24 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x18 23. -0x0C 23. " [23] ,GPIO pin 23 level" "Low,High"
|
|
setclrfld.long 0x00 22. -0x18 22. -0x0C 22. " [22] ,GPIO pin 22 level" "Low,High"
|
|
setclrfld.long 0x00 21. -0x18 21. -0x0C 21. " [21] ,GPIO pin 21 level" "Low,High"
|
|
setclrfld.long 0x00 20. -0x18 20. -0x0C 20. " [20] ,GPIO pin 20 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x18 19. -0x0C 19. " [19] ,GPIO pin 19 level" "Low,High"
|
|
setclrfld.long 0x00 18. -0x18 18. -0x0C 18. " [18] ,GPIO pin 18 level" "Low,High"
|
|
setclrfld.long 0x00 17. -0x18 17. -0x0C 17. " [17] ,GPIO pin 17 level" "Low,High"
|
|
setclrfld.long 0x00 16. -0x18 16. -0x0C 16. " [16] ,GPIO pin 16 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x18 15. -0x0C 15. " [15] ,GPIO pin 15 level" "Low,High"
|
|
setclrfld.long 0x00 14. -0x18 14. -0x0C 14. " [14] ,GPIO pin 14 level" "Low,High"
|
|
setclrfld.long 0x00 13. -0x18 13. -0x0C 13. " [13] ,GPIO pin 13 level" "Low,High"
|
|
setclrfld.long 0x00 12. -0x18 12. -0x0C 12. " [12] ,GPIO pin 12 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x18 11. -0x0C 11. " [11] ,GPIO pin 11 level" "Low,High"
|
|
setclrfld.long 0x00 10. -0x18 10. -0x0C 10. " [10] ,GPIO pin 10 level" "Low,High"
|
|
setclrfld.long 0x00 9. -0x18 9. -0x0C 9. " [9] ,GPIO pin 9 level" "Low,High"
|
|
setclrfld.long 0x00 8. -0x18 8. -0x0C 8. " [8] ,GPIO pin 8 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x18 7. -0x0C 7. " [7] ,GPIO pin 7 level" "Low,High"
|
|
setclrfld.long 0x00 6. -0x18 6. -0x0C 6. " [6] ,GPIO pin 6 level" "Low,High"
|
|
setclrfld.long 0x00 5. -0x18 5. -0x0C 5. " [5] ,GPIO pin 5 level" "Low,High"
|
|
setclrfld.long 0x00 4. -0x18 4. -0x0C 4. " [4] ,GPIO pin 4 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x18 3. -0x0C 3. " [3] ,GPIO pin 3 level" "Low,High"
|
|
setclrfld.long 0x00 2. -0x18 2. -0x0C 2. " [2] ,GPIO pin 2 level" "Low,High"
|
|
setclrfld.long 0x00 1. -0x18 1. -0x0C 1. " [1] ,GPIO pin 1 level" "Low,High"
|
|
setclrfld.long 0x00 0. -0x18 0. -0x0C 0. " [0] ,GPIO pin 0 level" "Low,High"
|
|
line.long 0x04 "GPLEV1,GPIO Pin Level 1 Register"
|
|
setclrfld.long 0x04 21. -0x14 21. -0x08 21. " LVL[53] ,GPIO pin 53 level" "Low,High"
|
|
setclrfld.long 0x04 20. -0x14 20. -0x08 20. " [52] ,GPIO pin 52 level" "Low,High"
|
|
setclrfld.long 0x04 19. -0x14 19. -0x08 19. " [51] ,GPIO pin 51 level" "Low,High"
|
|
setclrfld.long 0x04 18. -0x14 18. -0x08 18. " [50] ,GPIO pin 50 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x04 17. -0x14 17. -0x08 17. " [49] ,GPIO pin 49 level" "Low,High"
|
|
setclrfld.long 0x04 16. -0x14 16. -0x08 16. " [48] ,GPIO pin 48 level" "Low,High"
|
|
setclrfld.long 0x04 15. -0x14 15. -0x08 15. " [47] ,GPIO pin 47 level" "Low,High"
|
|
setclrfld.long 0x04 14. -0x14 14. -0x08 14. " [46] ,GPIO pin 46 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x04 13. -0x14 13. -0x08 13. " [45] ,GPIO pin 45 level" "Low,High"
|
|
setclrfld.long 0x04 12. -0x14 12. -0x08 12. " [44] ,GPIO pin 44 level" "Low,High"
|
|
setclrfld.long 0x04 11. -0x14 11. -0x08 11. " [43] ,GPIO pin 43 level" "Low,High"
|
|
setclrfld.long 0x04 10. -0x14 10. -0x08 10. " [42] ,GPIO pin 42 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x04 9. -0x14 9. -0x08 9. " [41] ,GPIO pin 41 level" "Low,High"
|
|
setclrfld.long 0x04 8. -0x14 8. -0x08 8. " [40] ,GPIO pin 40 level" "Low,High"
|
|
setclrfld.long 0x04 7. -0x14 7. -0x08 7. " [39] ,GPIO pin 39 level" "Low,High"
|
|
setclrfld.long 0x04 6. -0x14 6. -0x08 6. " [38] ,GPIO pin 38 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x04 5. -0x14 5. -0x08 5. " [37] ,GPIO pin 37 level" "Low,High"
|
|
setclrfld.long 0x04 4. -0x14 4. -0x08 4. " [36] ,GPIO pin 36 level" "Low,High"
|
|
setclrfld.long 0x04 3. -0x14 3. -0x08 3. " [35] ,GPIO pin 35 level" "Low,High"
|
|
setclrfld.long 0x04 2. -0x14 2. -0x08 2. " [34] ,GPIO pin 34 level" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x04 1. -0x14 1. -0x08 1. " [33] ,GPIO pin 33 level" "Low,High"
|
|
setclrfld.long 0x04 0. -0x14 0. -0x08 0. " [32] ,GPIO pin 32 level" "Low,High"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "GPEDS0,GPIO Event Detect Status 0 Register"
|
|
bitfld.long 0x00 31. " EDS[31] ,Event status on GPIO pin 31" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " [30] ,Event status on GPIO pin 30" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " [29] ,Event status on GPIO pin 29" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " [28] ,Event status on GPIO pin 28" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Event status on GPIO pin 27" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " [26] ,Event status on GPIO pin 26" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " [25] ,Event status on GPIO pin 25" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " [24] ,Event status on GPIO pin 24" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Event status on GPIO pin 23" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " [22] ,Event status on GPIO pin 22" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " [21] ,Event status on GPIO pin 21" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " [20] ,Event status on GPIO pin 20" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Event status on GPIO pin 19" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " [18] ,Event status on GPIO pin 18" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " [17] ,Event status on GPIO pin 17" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " [16] ,Event status on GPIO pin 16" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Event status on GPIO pin 15" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " [14] ,Event status on GPIO pin 14" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " [13] ,Event status on GPIO pin 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " [12] ,Event status on GPIO pin 12" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Event status on GPIO pin 11" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " [10] ,Event status on GPIO pin 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " [9] ,Event status on GPIO pin 9" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " [8] ,Event status on GPIO pin 8" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Event status on GPIO pin 7" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " [6] ,Event status on GPIO pin 6" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " [5] ,Event status on GPIO pin 5" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " [4] ,Event status on GPIO pin 4" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Event status on GPIO pin 3" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " [2] ,Event status on GPIO pin 2" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " [1] ,Event status on GPIO pin 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " [0] ,Event status on GPIO pin 0" "Not detected,Detected"
|
|
line.long 0x04 "GPEDS1,GPIO Event Detect Status 1 Register"
|
|
bitfld.long 0x04 21. " EDS[53] ,Event status on GPIO pin 53" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " [52] ,Event status on GPIO pin 52" "Not detected,Detected"
|
|
bitfld.long 0x04 19. " [51] ,Event status on GPIO pin 51" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " [50] ,Event status on GPIO pin 50" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,Event status on GPIO pin 49" "Not detected,Detected"
|
|
bitfld.long 0x04 16. " [48] ,Event status on GPIO pin 48" "Not detected,Detected"
|
|
bitfld.long 0x04 15. " [47] ,Event status on GPIO pin 47" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " [46] ,Event status on GPIO pin 46" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,Event status on GPIO pin 45" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " [44] ,Event status on GPIO pin 44" "Not detected,Detected"
|
|
bitfld.long 0x04 11. " [43] ,Event status on GPIO pin 43" "Not detected,Detected"
|
|
bitfld.long 0x04 10. " [42] ,Event status on GPIO pin 42" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,Event status on GPIO pin 41" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " [40] ,Event status on GPIO pin 40" "Not detected,Detected"
|
|
bitfld.long 0x04 7. " [39] ,Event status on GPIO pin 39" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " [38] ,Event status on GPIO pin 38" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,Event status on GPIO pin 37" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " [36] ,Event status on GPIO pin 36" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " [35] ,Event status on GPIO pin 35" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " [34] ,Event status on GPIO pin 34" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,Event status on GPIO pin 33" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " [32] ,Event status on GPIO pin 32" "Not detected,Detected"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "GPREN0,GPIO Pin Rising Edge Detect Enable 0 Register"
|
|
bitfld.long 0x00 31. " REN[31] ,Rising edge detect enable on GPIO pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Rising edge detect enable on GPIO pin 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Rising edge detect enable on GPIO pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Rising edge detect enable on GPIO pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Rising edge detect enable on GPIO pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Rising edge detect enable on GPIO pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Rising edge detect enable on GPIO pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Rising edge detect enable on GPIO pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Rising edge detect enable on GPIO pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Rising edge detect enable on GPIO pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Rising edge detect enable on GPIO pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Rising edge detect enable on GPIO pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Rising edge detect enable on GPIO pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Rising edge detect enable on GPIO pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Rising edge detect enable on GPIO pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Rising edge detect enable on GPIO pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Rising edge detect enable on GPIO pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Rising edge detect enable on GPIO pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Rising edge detect enable on GPIO pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Rising edge detect enable on GPIO pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Rising edge detect enable on GPIO pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Rising edge detect enable on GPIO pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Rising edge detect enable on GPIO pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Rising edge detect enable on GPIO pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Rising edge detect enable on GPIO pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Rising edge detect enable on GPIO pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Rising edge detect enable on GPIO pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Rising edge detect enable on GPIO pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Rising edge detect enable on GPIO pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Rising edge detect enable on GPIO pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Rising edge detect enable on GPIO pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Rising edge detect enable on GPIO pin 0" "Disabled,Enabled"
|
|
line.long 0x04 "GPREN1,GPIO Pin Rising Edge Detect Enable 1 Register"
|
|
bitfld.long 0x04 21. " REN[53] ,Rising edge detect enable on GPIO pin 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Rising edge detect enable on GPIO pin 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Rising edge detect enable on GPIO pin 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Rising edge detect enable on GPIO pin 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,Rising edge detect enable on GPIO pin 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Rising edge detect enable on GPIO pin 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Rising edge detect enable on GPIO pin 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Rising edge detect enable on GPIO pin 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,Rising edge detect enable on GPIO pin 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Rising edge detect enable on GPIO pin 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,Rising edge detect enable on GPIO pin 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Rising edge detect enable on GPIO pin 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,Rising edge detect enable on GPIO pin 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Rising edge detect enable on GPIO pin 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Rising edge detect enable on GPIO pin 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Rising edge detect enable on GPIO pin 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,Rising edge detect enable on GPIO pin 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Rising edge detect enable on GPIO pin 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Rising edge detect enable on GPIO pin 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Rising edge detect enable on GPIO pin 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,Rising edge detect enable on GPIO pin 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Rising edge detect enable on GPIO pin 32" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "GPFEN0,GPIO Pin Falling Edge Detect Enable 0 Register"
|
|
bitfld.long 0x00 31. " FEN[31] ,Falling edge detect enable on GPIO pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Falling edge detect enable on GPIO pin 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Falling edge detect enable on GPIO pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Falling edge detect enable on GPIO pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Falling edge detect enable on GPIO pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Falling edge detect enable on GPIO pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Falling edge detect enable on GPIO pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Falling edge detect enable on GPIO pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Falling edge detect enable on GPIO pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Falling edge detect enable on GPIO pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Falling edge detect enable on GPIO pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Falling edge detect enable on GPIO pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Falling edge detect enable on GPIO pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Falling edge detect enable on GPIO pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Falling edge detect enable on GPIO pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Falling edge detect enable on GPIO pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Falling edge detect enable on GPIO pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Falling edge detect enable on GPIO pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Falling edge detect enable on GPIO pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Falling edge detect enable on GPIO pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Falling edge detect enable on GPIO pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Falling edge detect enable on GPIO pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Falling edge detect enable on GPIO pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Falling edge detect enable on GPIO pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Falling edge detect enable on GPIO pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Falling edge detect enable on GPIO pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Falling edge detect enable on GPIO pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Falling edge detect enable on GPIO pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Falling edge detect enable on GPIO pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Falling edge detect enable on GPIO pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Falling edge detect enable on GPIO pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Falling edge detect enable on GPIO pin 0" "Disabled,Enabled"
|
|
line.long 0x04 "GPFEN1,GPIO Pin Falling Edge Detect Enable 1 Register"
|
|
bitfld.long 0x04 21. " FEN[53] ,Falling edge detect enable on GPIO pin 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Falling edge detect enable on GPIO pin 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Falling edge detect enable on GPIO pin 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Falling edge detect enable on GPIO pin 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,Falling edge detect enable on GPIO pin 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Falling edge detect enable on GPIO pin 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Falling edge detect enable on GPIO pin 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Falling edge detect enable on GPIO pin 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,Falling edge detect enable on GPIO pin 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Falling edge detect enable on GPIO pin 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,Falling edge detect enable on GPIO pin 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Falling edge detect enable on GPIO pin 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,Falling edge detect enable on GPIO pin 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Falling edge detect enable on GPIO pin 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Falling edge detect enable on GPIO pin 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Falling edge detect enable on GPIO pin 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,Falling edge detect enable on GPIO pin 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Falling edge detect enable on GPIO pin 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Falling edge detect enable on GPIO pin 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Falling edge detect enable on GPIO pin 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,Falling edge detect enable on GPIO pin 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Falling edge detect enable on GPIO pin 32" "Disabled,Enabled"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GPHEN0,GPIO Pin High Detect Enable 0 Register"
|
|
bitfld.long 0x00 31. " HEN[31] ,High detect enable on GPIO pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,High detect enable on GPIO pin 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,High detect enable on GPIO pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,High detect enable on GPIO pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,High detect enable on GPIO pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,High detect enable on GPIO pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,High detect enable on GPIO pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,High detect enable on GPIO pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,High detect enable on GPIO pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,High detect enable on GPIO pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,High detect enable on GPIO pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,High detect enable on GPIO pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,High detect enable on GPIO pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,High detect enable on GPIO pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,High detect enable on GPIO pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,High detect enable on GPIO pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,High detect enable on GPIO pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,High detect enable on GPIO pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,High detect enable on GPIO pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,High detect enable on GPIO pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,High detect enable on GPIO pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,High detect enable on GPIO pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,High detect enable on GPIO pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,High detect enable on GPIO pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,High detect enable on GPIO pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,High detect enable on GPIO pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,High detect enable on GPIO pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,High detect enable on GPIO pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,High detect enable on GPIO pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,High detect enable on GPIO pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,High detect enable on GPIO pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,High detect enable on GPIO pin 0" "Disabled,Enabled"
|
|
line.long 0x04 "GPHEN1,GPIO Pin High Detect Enable 1 Register"
|
|
bitfld.long 0x04 21. " HEN[53] ,High detect enable on GPIO pin 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,High detect enable on GPIO pin 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,High detect enable on GPIO pin 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,High detect enable on GPIO pin 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,High detect enable on GPIO pin 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,High detect enable on GPIO pin 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,High detect enable on GPIO pin 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,High detect enable on GPIO pin 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,High detect enable on GPIO pin 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,High detect enable on GPIO pin 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,High detect enable on GPIO pin 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,High detect enable on GPIO pin 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,High detect enable on GPIO pin 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,High detect enable on GPIO pin 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,High detect enable on GPIO pin 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,High detect enable on GPIO pin 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,High detect enable on GPIO pin 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,High detect enable on GPIO pin 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,High detect enable on GPIO pin 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,High detect enable on GPIO pin 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,High detect enable on GPIO pin 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,High detect enable on GPIO pin 32" "Disabled,Enabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "GPLEN0,GPIO Pin Low Detect Enable 0 Register"
|
|
bitfld.long 0x00 31. " LEN[31] ,Low detect enable on GPIO pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Low detect enable on GPIO pin 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Low detect enable on GPIO pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Low detect enable on GPIO pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Low detect enable on GPIO pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Low detect enable on GPIO pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Low detect enable on GPIO pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Low detect enable on GPIO pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Low detect enable on GPIO pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Low detect enable on GPIO pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Low detect enable on GPIO pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Low detect enable on GPIO pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Low detect enable on GPIO pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Low detect enable on GPIO pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Low detect enable on GPIO pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Low detect enable on GPIO pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Low detect enable on GPIO pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Low detect enable on GPIO pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Low detect enable on GPIO pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Low detect enable on GPIO pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Low detect enable on GPIO pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Low detect enable on GPIO pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Low detect enable on GPIO pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Low detect enable on GPIO pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Low detect enable on GPIO pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Low detect enable on GPIO pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Low detect enable on GPIO pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Low detect enable on GPIO pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Low detect enable on GPIO pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Low detect enable on GPIO pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Low detect enable on GPIO pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Low detect enable on GPIO pin 0" "Disabled,Enabled"
|
|
line.long 0x04 "GPLEN1,GPIO Pin Low Detect Enable 1 Register"
|
|
bitfld.long 0x04 21. " LEN[53] ,Low detect enable on GPIO pin 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Low detect enable on GPIO pin 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Low detect enable on GPIO pin 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Low detect enable on GPIO pin 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,Low detect enable on GPIO pin 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Low detect enable on GPIO pin 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Low detect enable on GPIO pin 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Low detect enable on GPIO pin 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,Low detect enable on GPIO pin 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Low detect enable on GPIO pin 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,Low detect enable on GPIO pin 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Low detect enable on GPIO pin 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,Low detect enable on GPIO pin 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Low detect enable on GPIO pin 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Low detect enable on GPIO pin 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Low detect enable on GPIO pin 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,Low detect enable on GPIO pin 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Low detect enable on GPIO pin 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Low detect enable on GPIO pin 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Low detect enable on GPIO pin 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,Low detect enable on GPIO pin 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Low detect enable on GPIO pin 32" "Disabled,Enabled"
|
|
group.long 0x7C++0x07
|
|
line.long 0x00 "GPAREN0,GPIO Pin Asynchronous Rising Edge Detect Enable 0 Register"
|
|
bitfld.long 0x00 31. " AREN[31] ,Asynchronous rising edge detect enable on GPIO pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Asynchronous rising edge detect enable on GPIO pin 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Asynchronous rising edge detect enable on GPIO pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Asynchronous rising edge detect enable on GPIO pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Asynchronous rising edge detect enable on GPIO pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Asynchronous rising edge detect enable on GPIO pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Asynchronous rising edge detect enable on GPIO pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Asynchronous rising edge detect enable on GPIO pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Asynchronous rising edge detect enable on GPIO pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Asynchronous rising edge detect enable on GPIO pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Asynchronous rising edge detect enable on GPIO pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Asynchronous rising edge detect enable on GPIO pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Asynchronous rising edge detect enable on GPIO pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Asynchronous rising edge detect enable on GPIO pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Asynchronous rising edge detect enable on GPIO pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Asynchronous rising edge detect enable on GPIO pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Asynchronous rising edge detect enable on GPIO pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Asynchronous rising edge detect enable on GPIO pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Asynchronous rising edge detect enable on GPIO pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Asynchronous rising edge detect enable on GPIO pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Asynchronous rising edge detect enable on GPIO pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Asynchronous rising edge detect enable on GPIO pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Asynchronous rising edge detect enable on GPIO pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Asynchronous rising edge detect enable on GPIO pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Asynchronous rising edge detect enable on GPIO pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Asynchronous rising edge detect enable on GPIO pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Asynchronous rising edge detect enable on GPIO pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Asynchronous rising edge detect enable on GPIO pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Asynchronous rising edge detect enable on GPIO pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Asynchronous rising edge detect enable on GPIO pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Asynchronous rising edge detect enable on GPIO pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Asynchronous rising edge detect enable on GPIO pin 0" "Disabled,Enabled"
|
|
line.long 0x04 "GPAREN1,GPIO Pin Asynchronous Rising Edge Detect Enable 1 Register"
|
|
bitfld.long 0x04 21. " AREN[53] ,Asynchronous rising edge detect enable on GPIO pin 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Asynchronous rising edge detect enable on GPIO pin 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Asynchronous rising edge detect enable on GPIO pin 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Asynchronous rising edge detect enable on GPIO pin 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,Asynchronous rising edge detect enable on GPIO pin 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Asynchronous rising edge detect enable on GPIO pin 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Asynchronous rising edge detect enable on GPIO pin 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Asynchronous rising edge detect enable on GPIO pin 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,Asynchronous rising edge detect enable on GPIO pin 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Asynchronous rising edge detect enable on GPIO pin 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,Asynchronous rising edge detect enable on GPIO pin 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Asynchronous rising edge detect enable on GPIO pin 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,Asynchronous rising edge detect enable on GPIO pin 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Asynchronous rising edge detect enable on GPIO pin 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Asynchronous rising edge detect enable on GPIO pin 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Asynchronous rising edge detect enable on GPIO pin 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,Asynchronous rising edge detect enable on GPIO pin 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Asynchronous rising edge detect enable on GPIO pin 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Asynchronous rising edge detect enable on GPIO pin 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Asynchronous rising edge detect enable on GPIO pin 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,Asynchronous rising edge detect enable on GPIO pin 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Asynchronous rising edge detect enable on GPIO pin 32" "Disabled,Enabled"
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "GPAFEN0,GPIO Pin Asynchronous Falling Edge Detect Enable 0 Register"
|
|
bitfld.long 0x00 31. " AFEN[31] ,Asynchronous falling edge detect enable on GPIO pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Asynchronous falling edge detect enable on GPIO pin 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Asynchronous falling edge detect enable on GPIO pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Asynchronous falling edge detect enable on GPIO pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Asynchronous falling edge detect enable on GPIO pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Asynchronous falling edge detect enable on GPIO pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Asynchronous falling edge detect enable on GPIO pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Asynchronous falling edge detect enable on GPIO pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Asynchronous falling edge detect enable on GPIO pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Asynchronous falling edge detect enable on GPIO pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Asynchronous falling edge detect enable on GPIO pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Asynchronous falling edge detect enable on GPIO pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Asynchronous falling edge detect enable on GPIO pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Asynchronous falling edge detect enable on GPIO pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Asynchronous falling edge detect enable on GPIO pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Asynchronous falling edge detect enable on GPIO pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Asynchronous falling edge detect enable on GPIO pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Asynchronous falling edge detect enable on GPIO pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Asynchronous falling edge detect enable on GPIO pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Asynchronous falling edge detect enable on GPIO pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Asynchronous falling edge detect enable on GPIO pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Asynchronous falling edge detect enable on GPIO pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Asynchronous falling edge detect enable on GPIO pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Asynchronous falling edge detect enable on GPIO pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Asynchronous falling edge detect enable on GPIO pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Asynchronous falling edge detect enable on GPIO pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Asynchronous falling edge detect enable on GPIO pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Asynchronous falling edge detect enable on GPIO pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Asynchronous falling edge detect enable on GPIO pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Asynchronous falling edge detect enable on GPIO pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Asynchronous falling edge detect enable on GPIO pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Asynchronous falling edge detect enable on GPIO pin 0" "Disabled,Enabled"
|
|
line.long 0x04 "GPAFEN1,GPIO Pin Asynchronous Falling Edge Detect Enable 1 Register"
|
|
bitfld.long 0x04 21. " AFEN[53] ,Asynchronous falling edge detect enable on GPIO pin 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Asynchronous falling edge detect enable on GPIO pin 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Asynchronous falling edge detect enable on GPIO pin 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Asynchronous falling edge detect enable on GPIO pin 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " [49] ,Asynchronous falling edge detect enable on GPIO pin 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Asynchronous falling edge detect enable on GPIO pin 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Asynchronous falling edge detect enable on GPIO pin 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Asynchronous falling edge detect enable on GPIO pin 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,Asynchronous falling edge detect enable on GPIO pin 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Asynchronous falling edge detect enable on GPIO pin 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,Asynchronous falling edge detect enable on GPIO pin 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Asynchronous falling edge detect enable on GPIO pin 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [41] ,Asynchronous falling edge detect enable on GPIO pin 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Asynchronous falling edge detect enable on GPIO pin 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Asynchronous falling edge detect enable on GPIO pin 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Asynchronous falling edge detect enable on GPIO pin 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [37] ,Asynchronous falling edge detect enable on GPIO pin 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Asynchronous falling edge detect enable on GPIO pin 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Asynchronous falling edge detect enable on GPIO pin 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Asynchronous falling edge detect enable on GPIO pin 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,Asynchronous falling edge detect enable on GPIO pin 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Asynchronous falling edge detect enable on GPIO pin 32" "Disabled,Enabled"
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "GPPUD,GPIO Pin Pull-up/down Enable Register"
|
|
bitfld.long 0x00 0.--1. " PUD ,GPIO pin Pull-up/down" "Disabled,Enabled pull down,Enabled pull up,?..."
|
|
line.long 0x04 "GPPUDCLK0,GPIO Pin Pull-up/down Enable Clock 0 Register"
|
|
bitfld.long 0x04 31. " PUDCLK[31] ,Assert clock on line 31" "No effect,Assert"
|
|
bitfld.long 0x04 30. " [30] ,Assert clock on line 30" "No effect,Assert"
|
|
bitfld.long 0x04 29. " [29] ,Assert clock on line 29" "No effect,Assert"
|
|
bitfld.long 0x04 28. " [28] ,Assert clock on line 28" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [27] ,Assert clock on line 27" "No effect,Assert"
|
|
bitfld.long 0x04 26. " [26] ,Assert clock on line 26" "No effect,Assert"
|
|
bitfld.long 0x04 25. " [25] ,Assert clock on line 25" "No effect,Assert"
|
|
bitfld.long 0x04 24. " [24] ,Assert clock on line 24" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [23] ,Assert clock on line 23" "No effect,Assert"
|
|
bitfld.long 0x04 22. " [22] ,Assert clock on line 22" "No effect,Assert"
|
|
bitfld.long 0x04 21. " [21] ,Assert clock on line 21" "No effect,Assert"
|
|
bitfld.long 0x04 20. " [20] ,Assert clock on line 20" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,Assert clock on line 19" "No effect,Assert"
|
|
bitfld.long 0x04 18. " [18] ,Assert clock on line 18" "No effect,Assert"
|
|
bitfld.long 0x04 17. " [17] ,Assert clock on line 17" "No effect,Assert"
|
|
bitfld.long 0x04 16. " [16] ,Assert clock on line 16" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [15] ,Assert clock on line 15" "No effect,Assert"
|
|
bitfld.long 0x04 14. " [14] ,Assert clock on line 14" "No effect,Assert"
|
|
bitfld.long 0x04 13. " [13] ,Assert clock on line 13" "No effect,Assert"
|
|
bitfld.long 0x04 12. " [12] ,Assert clock on line 12" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,Assert clock on line 11" "No effect,Assert"
|
|
bitfld.long 0x04 10. " [10] ,Assert clock on line 10" "No effect,Assert"
|
|
bitfld.long 0x04 9. " [9] ,Assert clock on line 9" "No effect,Assert"
|
|
bitfld.long 0x04 8. " [8] ,Assert clock on line 8" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Assert clock on line 7" "No effect,Assert"
|
|
bitfld.long 0x04 6. " [6] ,Assert clock on line 6" "No effect,Assert"
|
|
bitfld.long 0x04 5. " [5] ,Assert clock on line 5" "No effect,Assert"
|
|
bitfld.long 0x04 4. " [4] ,Assert clock on line 4" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Assert clock on line 3" "No effect,Assert"
|
|
bitfld.long 0x04 2. " [2] ,Assert clock on line 2" "No effect,Assert"
|
|
bitfld.long 0x04 1. " [1] ,Assert clock on line 1" "No effect,Assert"
|
|
bitfld.long 0x04 0. " [0] ,Assert clock on line 0" "No effect,Assert"
|
|
line.long 0x08 "GPPUDCLK1,GPIO Pin Pull-up/down Enable Clock 1 Register"
|
|
bitfld.long 0x08 21. " PUDCLK[53] ,Assert clock on line 53" "No effect,Assert"
|
|
bitfld.long 0x08 20. " [52] ,Assert clock on line 52" "No effect,Assert"
|
|
bitfld.long 0x08 19. " [51] ,Assert clock on line 51" "No effect,Assert"
|
|
bitfld.long 0x08 18. " [50] ,Assert clock on line 50" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x08 17. " [49] ,Assert clock on line 49" "No effect,Assert"
|
|
bitfld.long 0x08 16. " [48] ,Assert clock on line 48" "No effect,Assert"
|
|
bitfld.long 0x08 15. " [47] ,Assert clock on line 47" "No effect,Assert"
|
|
bitfld.long 0x08 14. " [46] ,Assert clock on line 46" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x08 13. " [45] ,Assert clock on line 45" "No effect,Assert"
|
|
bitfld.long 0x08 12. " [44] ,Assert clock on line 44" "No effect,Assert"
|
|
bitfld.long 0x08 11. " [43] ,Assert clock on line 43" "No effect,Assert"
|
|
bitfld.long 0x08 10. " [42] ,Assert clock on line 42" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x08 9. " [41] ,Assert clock on line 41" "No effect,Assert"
|
|
bitfld.long 0x08 8. " [40] ,Assert clock on line 40" "No effect,Assert"
|
|
bitfld.long 0x08 7. " [39] ,Assert clock on line 39" "No effect,Assert"
|
|
bitfld.long 0x08 6. " [38] ,Assert clock on line 38" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x08 5. " [37] ,Assert clock on line 37" "No effect,Assert"
|
|
bitfld.long 0x08 4. " [36] ,Assert clock on line 36" "No effect,Assert"
|
|
bitfld.long 0x08 3. " [35] ,Assert clock on line 35" "No effect,Assert"
|
|
bitfld.long 0x08 2. " [34] ,Assert clock on line 34" "No effect,Assert"
|
|
textline " "
|
|
bitfld.long 0x08 1. " [33] ,Assert clock on line 33" "No effect,Assert"
|
|
bitfld.long 0x08 0. " [32] ,Assert clock on line 32" "No effect,Assert"
|
|
width 11.
|
|
base ad:0x20101070
|
|
tree "General Purpose GPIO Clocks"
|
|
if (((per.l(ad:0x20101070+0x0))&0x80)==0x00)
|
|
group.long 0x0++0x07
|
|
line.long 0x00 "CM_GP0CTL,Clock Manager General Purpose Clock 0 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PASSWD ,Clock manager password"
|
|
bitfld.long 0x00 9.--10. " MASH ,MASH control" "Integer division,1-stage MASH,2-stage MASH,3-stage MASH"
|
|
bitfld.long 0x00 8. " FLIP ,Invert the clock generator output" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 7. " BUSY ,Clock generator is running" "Idle,Busy"
|
|
bitfld.long 0x00 5. " KILL ,Kill the clock generator" "No effect,Kill"
|
|
bitfld.long 0x00 4. " ENAB ,Enable the clock generator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SRC ,Clock source" "GND,Oscillator,Testdebug0,Testdebug1,PLLA,PLLC,PLLD,HDMI,GND,GND,GND,GND,GND,GND,GND,GND"
|
|
line.long 0x04 "CM_GP0DIV,Clock Manager General Purpose Clock Divisor 0 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " DIVI ,Integer part of divisor"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVF ,Fractional part of divisor"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CM_GP0CTL,Clock Manager General Purpose Clocks Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PASSWD ,Clock manager password"
|
|
rbitfld.long 0x00 9.--10. " MASH ,MASH control" "Integer division,1-stage MASH,2-stage MASH,3-stage MASH"
|
|
rbitfld.long 0x00 8. " FLIP ,Invert the clock generator output" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 7. " BUSY ,Clock generator is running" "Idle,Busy"
|
|
bitfld.long 0x00 5. " KILL ,Kill the clock generator" "No effect,Kill"
|
|
bitfld.long 0x00 4. " ENAB ,Enable the clock generator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SRC ,Clock source" "GND,Oscillator,Testdebug0,Testdebug1,PLLA,PLLC,PLLD,HDMI,GND,GND,GND,GND,GND,GND,GND,GND"
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CM_GP0DIV,Clock Manager General Purpose Clock Divisor 0 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " DIVI ,Integer part of divisor"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIVF ,Fractional part of divisor"
|
|
endif
|
|
if (((per.l(ad:0x20101070+0x8))&0x80)==0x00)
|
|
group.long 0x8++0x07
|
|
line.long 0x00 "CM_GP1CTL,Clock Manager General Purpose Clock 1 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PASSWD ,Clock manager password"
|
|
bitfld.long 0x00 9.--10. " MASH ,MASH control" "Integer division,1-stage MASH,2-stage MASH,3-stage MASH"
|
|
bitfld.long 0x00 8. " FLIP ,Invert the clock generator output" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 7. " BUSY ,Clock generator is running" "Idle,Busy"
|
|
bitfld.long 0x00 5. " KILL ,Kill the clock generator" "No effect,Kill"
|
|
bitfld.long 0x00 4. " ENAB ,Enable the clock generator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SRC ,Clock source" "GND,Oscillator,Testdebug0,Testdebug1,PLLA,PLLC,PLLD,HDMI,GND,GND,GND,GND,GND,GND,GND,GND"
|
|
line.long 0x04 "CM_GP1DIV,Clock Manager General Purpose Clock Divisor 1 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " DIVI ,Integer part of divisor"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVF ,Fractional part of divisor"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CM_GP1CTL,Clock Manager General Purpose Clocks Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PASSWD ,Clock manager password"
|
|
rbitfld.long 0x00 9.--10. " MASH ,MASH control" "Integer division,1-stage MASH,2-stage MASH,3-stage MASH"
|
|
rbitfld.long 0x00 8. " FLIP ,Invert the clock generator output" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 7. " BUSY ,Clock generator is running" "Idle,Busy"
|
|
bitfld.long 0x00 5. " KILL ,Kill the clock generator" "No effect,Kill"
|
|
bitfld.long 0x00 4. " ENAB ,Enable the clock generator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SRC ,Clock source" "GND,Oscillator,Testdebug0,Testdebug1,PLLA,PLLC,PLLD,HDMI,GND,GND,GND,GND,GND,GND,GND,GND"
|
|
rgroup.long (0x8+0x04)++0x03
|
|
line.long 0x00 "CM_GP1DIV,Clock Manager General Purpose Clock Divisor 1 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " DIVI ,Integer part of divisor"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIVF ,Fractional part of divisor"
|
|
endif
|
|
if (((per.l(ad:0x20101070+0x10))&0x80)==0x00)
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CM_GP2CTL,Clock Manager General Purpose Clock 2 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PASSWD ,Clock manager password"
|
|
bitfld.long 0x00 9.--10. " MASH ,MASH control" "Integer division,1-stage MASH,2-stage MASH,3-stage MASH"
|
|
bitfld.long 0x00 8. " FLIP ,Invert the clock generator output" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 7. " BUSY ,Clock generator is running" "Idle,Busy"
|
|
bitfld.long 0x00 5. " KILL ,Kill the clock generator" "No effect,Kill"
|
|
bitfld.long 0x00 4. " ENAB ,Enable the clock generator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SRC ,Clock source" "GND,Oscillator,Testdebug0,Testdebug1,PLLA,PLLC,PLLD,HDMI,GND,GND,GND,GND,GND,GND,GND,GND"
|
|
line.long 0x04 "CM_GP2DIV,Clock Manager General Purpose Clock Divisor 2 Register"
|
|
hexmask.long.word 0x04 12.--23. 1. " DIVI ,Integer part of divisor"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVF ,Fractional part of divisor"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CM_GP2CTL,Clock Manager General Purpose Clocks Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PASSWD ,Clock manager password"
|
|
rbitfld.long 0x00 9.--10. " MASH ,MASH control" "Integer division,1-stage MASH,2-stage MASH,3-stage MASH"
|
|
rbitfld.long 0x00 8. " FLIP ,Invert the clock generator output" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 7. " BUSY ,Clock generator is running" "Idle,Busy"
|
|
bitfld.long 0x00 5. " KILL ,Kill the clock generator" "No effect,Kill"
|
|
bitfld.long 0x00 4. " ENAB ,Enable the clock generator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SRC ,Clock source" "GND,Oscillator,Testdebug0,Testdebug1,PLLA,PLLC,PLLD,HDMI,GND,GND,GND,GND,GND,GND,GND,GND"
|
|
rgroup.long (0x10+0x04)++0x03
|
|
line.long 0x00 "CM_GP2DIV,Clock Manager General Purpose Clock Divisor 2 Register"
|
|
hexmask.long.word 0x00 12.--23. 1. " DIVI ,Integer part of divisor"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIVF ,Fractional part of divisor"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "Interrupts"
|
|
base ad:0x2000B000
|
|
width 14.
|
|
rgroup.long 0x200++0x0B
|
|
line.long 0x00 "IRQ_BP,IRQ Basic Pending Register"
|
|
bitfld.long 0x00 20. " GPU_IRQ_62 ,GPU IRQ 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " GPU_IRQ_57 ,GPU IRQ 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " GPU_IRQ_56 ,GPU IRQ 56" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " GPU_IRQ_55 ,GPU IRQ 55" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPU_IRQ_54 ,GPU IRQ 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " GPU_IRQ_53 ,GPU IRQ 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " GPU_IRQ_19 ,GPU IRQ 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " GPU_IRQ_18 ,GPU IRQ 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " GPU_IRQ_10 ,GPU IRQ 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " GPU_IRQ_9 ,GPU IRQ 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " GPU_IRQ_7 ,GPU IRQ 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQ_R2 ,One or more bits set in pending register 2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IRQ_R1 ,One or more bits set in pending register 1" "No,Yes"
|
|
bitfld.long 0x00 7. " ILL_ACC_T0 ,Illegal access type 0 IRQ pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ILL_ACC_T1 ,Illegal access type 1 IRQ pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " GPU1_HALT ,GPU1 halted IRQ pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPU0_HALT ,GPU0 halted IRQ pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " ARM_DOORBELL_1 ,ARM doorbell 1 IRQ pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ARM_DOORBELL_0 ,ARM doorbell 0 IRQ pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " ARM_MAILBOX ,ARM mailbox IRQ pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ARM_TIMER ,ARM timer IRQ pending" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQ_PEN_1,IRQ Pending 1 Register"
|
|
bitfld.long 0x04 31. " IRQ[31] ,IRQ pending 1 register bit 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " [30] ,IRQ pending 1 register bit 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " [29] ,IRQ pending 1 register bit 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " [28] ,IRQ pending 1 register bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [27] ,IRQ pending 1 register bit 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " [26] ,IRQ pending 1 register bit 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " [25] ,IRQ pending 1 register bit 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " [24] ,IRQ pending 1 register bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [23] ,IRQ pending 1 register bit 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " [22] ,IRQ pending 1 register bit 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " [21] ,IRQ pending 1 register bit 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " [20] ,IRQ pending 1 register bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,IRQ pending 1 register bit 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " [18] ,IRQ pending 1 register bit 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " [17] ,IRQ pending 1 register bit 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " [16] ,IRQ pending 1 register bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [15] ,IRQ pending 1 register bit 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,IRQ pending 1 register bit 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,IRQ pending 1 register bit 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " [12] ,IRQ pending 1 register bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,IRQ pending 1 register bit 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,IRQ pending 1 register bit 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " [9] ,IRQ pending 1 register bit 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,IRQ pending 1 register bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,IRQ pending 1 register bit 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " [6] ,IRQ pending 1 register bit 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,IRQ pending 1 register bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,IRQ pending 1 register bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,IRQ pending 1 register bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,IRQ pending 1 register bit 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,IRQ pending 1 register bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [0] ,IRQ pending 1 register bit 0" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRQ_PEN_2,IRQ Pending 2 Register"
|
|
bitfld.long 0x08 31. " IRQ[63] ,IRQ pending 2 register bit 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " [62] ,IRQ pending 2 register bit 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " [61] ,IRQ pending 2 register bit 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " [60] ,IRQ pending 2 register bit 60" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [59] ,IRQ pending 2 register bit 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " [58] ,IRQ pending 2 register bit 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " [57] ,IRQ pending 2 register bit 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " [56] ,IRQ pending 2 register bit 56" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [55] ,IRQ pending 2 register bit 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " [54] ,IRQ pending 2 register bit 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " [53] ,IRQ pending 2 register bit 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 20. " [52] ,IRQ pending 2 register bit 52" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [51] ,IRQ pending 2 register bit 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " [50] ,IRQ pending 2 register bit 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " [49] ,IRQ pending 2 register bit 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " [48] ,IRQ pending 2 register bit 48" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [47] ,IRQ pending 2 register bit 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " [46] ,IRQ pending 2 register bit 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " [45] ,IRQ pending 2 register bit 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " [44] ,IRQ pending 2 register bit 44" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [43] ,IRQ pending 2 register bit 43" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " [42] ,IRQ pending 2 register bit 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " [41] ,IRQ pending 2 register bit 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " [40] ,IRQ pending 2 register bit 40" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [39] ,IRQ pending 2 register bit 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " [38] ,IRQ pending 2 register bit 38" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " [37] ,IRQ pending 2 register bit 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " [36] ,IRQ pending 2 register bit 36" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [35] ,IRQ pending 2 register bit 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " [34] ,IRQ pending 2 register bit 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " [33] ,IRQ pending 2 register bit 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " [32] ,IRQ pending 2 register bit 32" "No interrupt,Interrupt"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FIQ_CON,FIQ Control Register"
|
|
rbitfld.long 0x00 7. " FIQ_EN ,FIQ enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " FIQ_SOURCE ,Select FIQ source"
|
|
group.long 0x210++0x0B
|
|
line.long 0x00 "IRQ_PEN_1_EN,Enable IRQ Pending 1 Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x0C 31. " IRQ_EN[31] ,Enable IRQ pending 1 bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x0C 30. " [30] ,Enable IRQ pending 1 bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x0C 29. " [29] ,Enable IRQ pending 1 bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x0C 28. " [28] ,Enable IRQ pending 1 bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x0C 27. " [27] ,Enable IRQ pending 1 bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x0C 26. " [26] ,Enable IRQ pending 1 bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x0C 25. " [25] ,Enable IRQ pending 1 bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x0C 24. " [24] ,Enable IRQ pending 1 bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x0C 23. " [23] ,Enable IRQ pending 1 bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x0C 22. " [22] ,Enable IRQ pending 1 bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x0C 21. " [21] ,Enable IRQ pending 1 bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x0C 20. " [20] ,Enable IRQ pending 1 bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x0C 19. " [19] ,Enable IRQ pending 1 bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x0C 18. " [18] ,Enable IRQ pending 1 bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x0C 17. " [17] ,Enable IRQ pending 1 bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x0C 16. " [16] ,Enable IRQ pending 1 bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x0C 15. " [15] ,Enable IRQ pending 1 bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x0C 14. " [14] ,Enable IRQ pending 1 bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x0C 13. " [13] ,Enable IRQ pending 1 bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x0C 12. " [12] ,Enable IRQ pending 1 bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x0C 11. " [11] ,Enable IRQ pending 1 bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x0C 10. " [10] ,Enable IRQ pending 1 bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x0C 9. " [9] ,Enable IRQ pending 1 bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x0C 8. " [8] ,Enable IRQ pending 1 bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x0C 7. " [7] ,Enable IRQ pending 1 bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x0C 6. " [6] ,Enable IRQ pending 1 bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x0C 5. " [5] ,Enable IRQ pending 1 bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x0C 4. " [4] ,Enable IRQ pending 1 bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x0C 3. " [3] ,Enable IRQ pending 1 bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x0C 2. " [2] ,Enable IRQ pending 1 bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x0C 1. " [1] ,Enable IRQ pending 1 bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x0C 0. " [0] ,Enable IRQ pending 1 bit 0" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ_PEN_2_EN,Enable IRQ Pending 2 Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x10 31. " IRQ_EN[63] ,Enable IRQ pending 2 bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x10 30. " [62] ,Enable IRQ pending 2 bit 62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x10 29. " [61] ,Enable IRQ pending 2 bit 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x10 28. " [60] ,Enable IRQ pending 2 bit 60" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x04 27. 0x10 27. " [59] ,Enable IRQ pending 2 bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x10 26. " [58] ,Enable IRQ pending 2 bit 58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x04 25. 0x10 25. " [57] ,Enable IRQ pending 2 bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x10 24. " [56] ,Enable IRQ pending 2 bit 56" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x04 23. 0x10 23. " [55] ,Enable IRQ pending 2 bit 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x10 22. " [54] ,Enable IRQ pending 2 bit 54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x10 21. " [53] ,Enable IRQ pending 2 bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x10 20. " [52] ,Enable IRQ pending 2 bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x10 19. " [51] ,Enable IRQ pending 2 bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x10 18. " [50] ,Enable IRQ pending 2 bit 50" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x10 17. " [49] ,Enable IRQ pending 2 bit 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x10 16. " [48] ,Enable IRQ pending 2 bit 48" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x04 15. 0x10 15. " [47] ,Enable IRQ pending 2 bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x10 14. " [46] ,Enable IRQ pending 2 bit 46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x10 13. " [45] ,Enable IRQ pending 2 bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x10 12. " [44] ,Enable IRQ pending 2 bit 44" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x04 11. 0x10 11. " [43] ,Enable IRQ pending 2 bit 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x10 10. " [42] ,Enable IRQ pending 2 bit 42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x10 9. " [41] ,Enable IRQ pending 2 bit 41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x10 8. " [40] ,Enable IRQ pending 2 bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x10 7. " [39] ,Enable IRQ pending 2 bit 39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x10 6. " [38] ,Enable IRQ pending 2 bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x10 5. " [37] ,Enable IRQ pending 2 bit 37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x10 4. " [36] ,Enable IRQ pending 2 bit 36" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x04 3. 0x10 3. " [35] ,Enable IRQ pending 2 bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x10 2. " [34] ,Enable IRQ pending 2 bit 34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x10 1. " [33] ,Enable IRQ pending 2 bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x10 0. " [32] ,Enable IRQ pending 2 bit 32" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ_BP_EN,IRQ Basic Interrupt Enable Register"
|
|
setclrfld.long 0x08 7. 0x08 7. 0x14 7. " ILL_ACC_T0_EN ,Illegal access type 0 IRQ enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x14 6. " ILL_ACC_T1_EN ,Illegal access type 1 IRQ enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x14 5. " GPU1_HALT_EN ,GPU1 halted IRQ enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x14 4. " GPU0_HALT_EN ,GPU0 halted IRQ enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x08 3. 0x14 3. " ARM_DOORBELL_1_EN ,ARM doorbell 1 IRQ enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x14 2. " ARM_DOORBELL_0_EN ,ARM doorbell 0 IRQ enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 1. 0x08 1. 0x14 1. " ARM_MAILBOX_EN ,ARM mailbox IRQ enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x14 0. " ARM_TIMER_EN ,ARM timer IRQ enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCM / I2S Audio"
|
|
base ad:0x20203000
|
|
width 10.
|
|
if (((per.l(ad:0x20203000))&0x06)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS_A,PCM Control And Status Register"
|
|
bitfld.long 0x00 25. " STBY ,RAM standby" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SYNC ,PCM clock sync helper" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RXSEX ,RX sign extend" "No sign extend,Sign extend"
|
|
bitfld.long 0x00 22. " RXF ,RX FIFO is full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TXE ,TX FIFO is empty" "Not empty,Empty"
|
|
bitfld.long 0x00 20. " RXD ,Indicates that the RX FIFO contains data" "Empty,Contains data"
|
|
bitfld.long 0x00 19. " TXD ,Indicates that the TX FIFO can accept data" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 18. " RXR ,Indicates that the RX FIFO needs reading" "<RXTHR,>=RXTHR"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXW ,Indicates that the TX FIFO needs writing" ">=TXTHR,<TXTHR"
|
|
eventfld.long 0x00 16. " RXERR ,RX FIFO error" "No error,Error"
|
|
eventfld.long 0x00 15. " TXERR ,TX FIFO error" "No error,Error"
|
|
rbitfld.long 0x00 14. " RXSYNC ,RX FIFO sync" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " TXSYNC ,TX FIFO sync" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DMAEN ,DMA DREQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--8. " RXTHR ,Sets the RX FIFO threshold at which point the RXR flag is set" "Single sample,At least full,At least full,Full"
|
|
bitfld.long 0x00 5.--6. " TXTHR ,Sets the TX FIFO threshold at which point the TXW flag is set" "Empty,<full,<full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXCLR ,Clear the RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TXCLR ,Clear the TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TXON ,Enable transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXON ,Enable reception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable the PCM audio interface" "Disabled,Enabled"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "FIFO_A,PCM FIFO Data Register"
|
|
if (((per.l(ad:0x20203000+0x08))&0x200000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MODE_A,PCM Mode Register"
|
|
bitfld.long 0x00 28. " CLK_DIS ,PCM clock disable" "No,Yes"
|
|
bitfld.long 0x00 27. " PDMN ,PDM decimation factor (N)" "16,32"
|
|
bitfld.long 0x00 26. " PDME ,PDM input mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FRXP ,Receive frame packed mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FTXP ,Transmit frame packed mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLKM ,PCM clock mode" "Master mode,Slave mode"
|
|
bitfld.long 0x00 22. " CLKI ,Clock invert this logically inverts the PCM_CLK Signal(Outputs change on edge/input sampled on edge)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 21. " FSM ,Frame sync mode" "Master mode,Slave mode"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FSI ,Frame sync invert this logically inverts the frame sync signal" "Low/high,High/low"
|
|
hexmask.long.word 0x00 10.--19. 1. " FLEN ,Frame length"
|
|
hexmask.long.word 0x00 0.--9. 1. " FSLEN ,Frame sync length"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MODE_A,PCM Mode Register"
|
|
bitfld.long 0x00 28. " CLK_DIS ,PCM clock disable" "No,Yes"
|
|
bitfld.long 0x00 27. " PDMN ,PDM decimation factor (N)" "16,32"
|
|
bitfld.long 0x00 26. " PDME ,PDM input mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FRXP ,Receive frame packed mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FTXP ,Transmit frame packed mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLKM ,PCM clock mode" "Master mode,Slave mode"
|
|
bitfld.long 0x00 22. " CLKI ,Clock invert this logically inverts the PCM_CLK Signal(Outputs change on edge/input sampled on edge)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 21. " FSM ,Frame sync mode" "Master mode,Slave mode"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FSI ,Frame sync invert this logically inverts the frame sync signal" "High/low,Low/high"
|
|
endif
|
|
group.long 0x0C++0x1B
|
|
line.long 0x00 "RXC_A,PCM Receive Configuration Register"
|
|
bitfld.long 0x00 31. " CH1WEX ,Channel 1 width extension bit" "0,1"
|
|
bitfld.long 0x00 30. " CH1EN ,Channel 1 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 20.--29. 1. " CH1POS ,Channel 1 position"
|
|
bitfld.long 0x00 16.--19. " CH1WID ,Channel 1 width" "8-bits,9-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " CH2WEX ,Channel 2 width extension bit" "0,1"
|
|
bitfld.long 0x00 14. " CH2EN ,Channel 2 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 4.--13. 1. " CH2POS ,Channel 2 position"
|
|
bitfld.long 0x00 0.--3. " CH2WID ,Channel 2 width" "8-bits,9-bits,?..."
|
|
line.long 0x04 "TXC_A,PCM Transmit Configuration Register"
|
|
bitfld.long 0x04 31. " CH1WEX ,Channel 1 width extension bit" "0,1"
|
|
bitfld.long 0x04 30. " CH1EN ,Channel 1 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 20.--29. 1. " CH1POS ,Channel 1 position"
|
|
bitfld.long 0x04 16.--19. " CH1WID ,Channel 1 width" "8-bits,9-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " CH2WEX ,Channel 2 width extension bit" "0,1"
|
|
bitfld.long 0x04 14. " CH2EN ,Channel 2 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 4.--13. 1. " CH2POS ,Channel 2 position"
|
|
bitfld.long 0x04 0.--3. " CH2WID ,Channel 2 width" "8-bits,9-bits,?..."
|
|
line.long 0x08 "DREQ_A,PCM DMA Request Level Register"
|
|
hexmask.long.byte 0x08 24.--30. 1. " TX_PANIC ,TX panic level"
|
|
hexmask.long.byte 0x08 16.--22. 1. " RX_PANIC ,RX panic level"
|
|
hexmask.long.byte 0x08 8.--14. 1. " TX ,TX request level"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RX ,RX request level"
|
|
line.long 0x10 "INTEN_A,PCM Interrupt Enables Register"
|
|
bitfld.long 0x10 3. " RXERR ,RX error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TXERR ,TX error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " RXR ,RX read interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TXW ,TX write interrupt enable" "Disabled,Enabled"
|
|
line.long 0x14 "INTSTC_A,PCM Interrupt Status & Clear Register"
|
|
eventfld.long 0x14 3. " RXERR ,RX error interrupt status / clear" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 2. " TXERR ,TX error interrupt status / clear" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 1. " RXR ,RX read interrupt status / clear" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 0. " TXW ,TX write interrupt status / clear" "No interrupt,Interrupt"
|
|
line.long 0x18 "GRAY,PCM Gray Mode Control Register"
|
|
rbitfld.long 0x18 16.--21. " RXFIFOLEVEL ,The current level of the RXFIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x18 10.--15. " FLUSHED ,The number of bits that were flushed into the RXFIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x18 4.--9. " RXLEVEL ,The current fill level of the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x18 2. " FLUSH ,Flush the RX buffer into the RX FIFO" "No flush,Flush"
|
|
bitfld.long 0x18 1. " CLR ,Clear the GRAY mode logic" "No effect,Clear"
|
|
bitfld.long 0x18 0. " EN ,Enable GRAY mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS_A,PCM Control And Status Register"
|
|
rbitfld.long 0x00 25. " STBY ,RAM standby" "Enabled,Disabled"
|
|
rbitfld.long 0x00 24. " SYNC ,PCM clock sync helper" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " RXSEX ,RX sign extend" "No sign extend,Sign extend"
|
|
rbitfld.long 0x00 22. " RXF ,RX FIFO is full" "Not full,Full"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " TXE ,TX FIFO is empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 20. " RXD ,Indicates that the RX FIFO contains data" "Empty,Contains data"
|
|
rbitfld.long 0x00 19. " TXD ,Indicates that the TX FIFO can accept data" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 18. " RXR ,Indicates that the RX FIFO needs reading" "<RXTHR,>=RXTHR"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXW ,Indicates that the TX FIFO needs writing" ">=TXTHR,<TXTHR"
|
|
rbitfld.long 0x00 16. " RXERR ,RX FIFO error" "No error,Error"
|
|
rbitfld.long 0x00 15. " TXERR ,TX FIFO error" "No error,Error"
|
|
rbitfld.long 0x00 14. " RXSYNC ,RX FIFO sync" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " TXSYNC ,TX FIFO sync" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " DMAEN ,DMA DREQ enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7.--8. " RXTHR ,Sets the RX FIFO threshold at which point the RXR flag is set" "Single sample,At least full,At least full,Full"
|
|
rbitfld.long 0x00 5.--6. " TXTHR ,Sets the TX FIFO threshold at which point the TXW flag is set" "Empty,<full,<full,Full"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " RXCLR ,Clear the RX FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 3. " TXCLR ,Clear the TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TXON ,Enable transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXON ,Enable reception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable the PCM audio interface" "Disabled,Enabled"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "FIFO_A,PCM FIFO Data Register"
|
|
if (((per.l(ad:0x20203000+0x08))&0x200000)==0x00)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "MODE_A,PCM Mode Register"
|
|
bitfld.long 0x00 28. " CLK_DIS ,PCM clock disable" "No,Yes"
|
|
bitfld.long 0x00 27. " PDMN ,PDM decimation factor (N)" "16,32"
|
|
bitfld.long 0x00 26. " PDME ,PDM input mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FRXP ,Receive frame packed mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FTXP ,Transmit frame packed mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLKM ,PCM clock mode" "Master mode,Slave mode"
|
|
bitfld.long 0x00 22. " CLKI ,Clock invert this logically inverts the PCM_CLK Signal(Outputs change on edge/input sampled on edge)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 21. " FSM ,Frame sync mode" "Master mode,Slave mode"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FSI ,Frame sync invert this logically inverts the frame sync signal" "Low/high,High/low"
|
|
hexmask.long.word 0x00 10.--19. 1. " FLEN ,Frame length"
|
|
hexmask.long.word 0x00 0.--9. 1. " FSLEN ,Frame sync length"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "MODE_A,PCM Mode Register"
|
|
bitfld.long 0x00 28. " CLK_DIS ,PCM clock disable" "No,Yes"
|
|
bitfld.long 0x00 27. " PDMN ,PDM decimation factor (N)" "16,32"
|
|
bitfld.long 0x00 26. " PDME ,PDM input mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FRXP ,Receive frame packed mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FTXP ,Transmit frame packed mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLKM ,PCM clock mode" "Master mode,Slave mode"
|
|
bitfld.long 0x00 22. " CLKI ,Clock invert this logically inverts the PCM_CLK Signal(Outputs change on edge/input sampled on edge)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 21. " FSM ,Frame sync mode" "Master mode,Slave mode"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FSI ,Frame sync invert this logically inverts the frame sync signal" "High/low,Low/hig"
|
|
endif
|
|
rgroup.long 0x0C++0x1B
|
|
line.long 0x00 "RXC_A,PCM Receive Configuration Register"
|
|
bitfld.long 0x00 31. " CH1WEX ,Channel 1 width extension bit" "0,1"
|
|
bitfld.long 0x00 30. " CH1EN ,Channel 1 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 20.--29. 1. " CH1POS ,Channel 1 position"
|
|
bitfld.long 0x00 16.--19. " CH1WID ,Channel 1 width" "8-bits,9-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " CH2WEX ,Channel 2 width extension bit" "0,1"
|
|
bitfld.long 0x00 14. " CH2EN ,Channel 2 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 4.--13. 1. " CH2POS ,Channel 2 position"
|
|
bitfld.long 0x00 0.--3. " CH2WID ,Channel 2 width" "8-bits,9-bits,?..."
|
|
line.long 0x04 "TXC_A,PCM Transmit Configuration Register"
|
|
bitfld.long 0x04 31. " CH1WEX ,Channel 1 width extension bit" "0,1"
|
|
bitfld.long 0x04 30. " CH1EN ,Channel 1 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 20.--29. 1. " CH1POS ,Channel 1 position"
|
|
bitfld.long 0x04 16.--19. " CH1WID ,Channel 1 width" "8-bits,9-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " CH2WEX ,Channel 2 width extension bit" "0,1"
|
|
bitfld.long 0x04 14. " CH2EN ,Channel 2 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 4.--13. 1. " CH2POS ,Channel 2 position"
|
|
bitfld.long 0x04 0.--3. " CH2WID ,Channel 2 width" "8-bits,9-bits,?..."
|
|
line.long 0x08 "DREQ_A,PCM DMA Request Level Register"
|
|
hexmask.long.byte 0x08 24.--30. 1. " TX_PANIC ,TX panic level"
|
|
hexmask.long.byte 0x08 16.--22. 1. " RX_PANIC ,RX panic level"
|
|
hexmask.long.byte 0x08 8.--14. 1. " TX ,TX request level"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RX ,RX request level"
|
|
line.long 0x10 "INTEN_A,PCM Interrupt Enables Register"
|
|
bitfld.long 0x10 3. " RXERR ,RX error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TXERR ,TX error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " RXR ,RX read interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TXW ,TX write interrupt enable" "Disabled,Enabled"
|
|
line.long 0x14 "INTSTC_A,PCM Interrupt Status & Clear Register"
|
|
bitfld.long 0x14 3. " RXERR ,RX error interrupt status / clear" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " TXERR ,TX error interrupt status / clear" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 1. " RXR ,RX read interrupt status / clear" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " TXW ,TX write interrupt status / clear" "No interrupt,Interrupt"
|
|
line.long 0x18 "GRAY,PCM Gray Mode Control Register"
|
|
bitfld.long 0x18 16.--21. " RXFIFOLEVEL ,The current level of the RXFIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 10.--15. " FLUSHED ,The number of bits that were flushed into the RXFIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 4.--9. " RXLEVEL ,The current fill level of the RX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x18 2. " FLUSH ,Flush the RX buffer into the RX FIFO" "No flush,Flush"
|
|
bitfld.long 0x18 1. " CLR ,Clear the GRAY mode logic" "No effect,Clear"
|
|
bitfld.long 0x18 0. " EN ,Enable GRAY mode" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulator)"
|
|
base ad:0x2020C000
|
|
width 6.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTL,PWM Control Register"
|
|
bitfld.long 0x00 15. " MSEN2 ,Channel 2 M/S enable" "PWM,M/S"
|
|
bitfld.long 0x00 13. " USEF2 ,Channel 2 use FIFO" "Data reg.,FIFO"
|
|
bitfld.long 0x00 12. " POLA2 ,Channel 2 polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 11. " SBIT2 ,Channel 2 silence bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RPTL2 ,Channel 2 repeat last data" "Not repeated,Repeated"
|
|
bitfld.long 0x00 9. " MODE2 ,Channel 2 mode" "PWM,Serialiser"
|
|
bitfld.long 0x00 8. " PWEN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MSEN1 ,Channel 1 M/S enable" "PWM,M/S"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLRF1 ,Clear FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 5. " USEF1 ,Channel 1 use FIFO" "Data reg.,FIFO"
|
|
bitfld.long 0x00 4. " POLA1 ,Channel 1 polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 3. " SBIT1 ,Channel 1 silence bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RPTL1 ,Channel 1 repeat last data" "Not repeated,Repeated"
|
|
bitfld.long 0x00 1. " MODE1 ,Channel 1 mode" "PWM,Serialiser"
|
|
bitfld.long 0x00 0. " PWEN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "STA,PWM Status Register"
|
|
bitfld.long 0x04 12. " STA4 ,Channel 4 state" "Not transmitting,Transmitting"
|
|
bitfld.long 0x04 11. " STA3 ,Channel 3 state" "Not transmitting,Transmitting"
|
|
bitfld.long 0x04 10. " STA2 ,Channel 2 state" "Not transmitting,Transmitting"
|
|
bitfld.long 0x04 9. " STA1 ,Channel 1 state" "Not transmitting,Transmitting"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BERR ,Bus error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 7. " GAPO4 ,Channel 4 gap occurred flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " GAPO3 ,Channel 3 gap occurred flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " GAPO2 ,Channel 2 gap occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 4. " GAPO1 ,Channel 1 gap occurred flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " RERR1 ,FIFO read error flag" "No error,Error"
|
|
eventfld.long 0x04 2. " WERR1 ,FIFO write error flag" "No error,Error"
|
|
bitfld.long 0x04 1. " EMPT1 ,FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FULL1 ,FIFO full flag" "Not full,Full"
|
|
line.long 0x08 "DMAC,PWM DMA Configuration Register"
|
|
bitfld.long 0x08 31. " ENAB ,DMA enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PANIC ,DMA threshold for PANIC signal"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DREQ ,DMA threshold for DREQ signal"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "RNG1,PWM Channel 1 Range Register"
|
|
line.long 0x04 "DAT1,PWM Channel 1 Data Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FIF1,PWM FIFO Input Register"
|
|
in
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "RNG2,PWM Channel 2 Range Register"
|
|
line.long 0x04 "DAT2,PWM Channel 2 Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x20204000
|
|
width 6.
|
|
if (((per.l(ad:0x20204000))&0x1000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,SPI Master Control And Status Register"
|
|
bitfld.long 0x00 25. " LEN_LONG ,Enable long data word" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DMA_LEN ,Enable DMA mode in lossi mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CSPOL2 ,Chip select 2 polarity" "Low,High"
|
|
bitfld.long 0x00 22. " CSPOL1 ,Chip select 1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSPOL1 ,Chip select 0 polarity" "Low,High"
|
|
rbitfld.long 0x00 20. " RXF ,RX FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 19. " RXR ,RX FIFO needs reading" "No,Yes"
|
|
rbitfld.long 0x00 18. " TXD ,TX FIFO can accept data" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " RXD ,RX FIFO contains data" "No,Yes"
|
|
rbitfld.long 0x00 16. " DONE ,Done transfer done" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " LEN ,LEN lossi enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " REN ,Read enable" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADCS ,Automatically deassert chip select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " INTR ,Interrupt on RXR" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTD ,Interrupt on done" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " DMAEN ,DMAEN DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TA ,Transfer active" "Not activated,Activated"
|
|
bitfld.long 0x00 6. " CSPOL ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 5. " CLEAR[1] ,RX FIFO clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLEAR[0] ,TX FIFO clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 2. " CPHA ,Clock phase" "Middle,Begin"
|
|
bitfld.long 0x00 0.--1. " CS ,Chip select" "0,1,2,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,SPI Master Control And Status Register"
|
|
bitfld.long 0x00 24. " DMA_LEN ,Enable DMA mode in lossi mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CSPOL2 ,Chip select 2 polarity" "Low,High"
|
|
bitfld.long 0x00 22. " CSPOL1 ,Chip select 1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSPOL1 ,Chip select 0 polarity" "Low,High"
|
|
rbitfld.long 0x00 20. " RXF ,RX FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 19. " RXR ,RX FIFO needs reading" "No,Yes"
|
|
rbitfld.long 0x00 18. " TXD ,TX FIFO can accept data" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " RXD ,RX FIFO contains data" "No,Yes"
|
|
rbitfld.long 0x00 16. " DONE ,Done transfer done" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " LEN ,LEN lossi enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " REN ,Read enable" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADCS ,Automatically deassert chip select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " INTR ,Interrupt on RXR" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTD ,Interrupt on done" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " DMAEN ,DMAEN DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TA ,Transfer active" "Not activated,Activated"
|
|
bitfld.long 0x00 6. " CSPOL ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 5. " CLEAR[1] ,RX FIFO clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLEAR[0] ,TX FIFO clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 2. " CPHA ,Clock phase" "Middle,Begin"
|
|
bitfld.long 0x00 0.--1. " CS ,Chip select" "0,1,2,?..."
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "FIFO,SPI Master TX And RX Fifos Register"
|
|
in
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLK,SPI Master Clock Divider Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDIV ,Clock divider"
|
|
if (((per.l(ad:0x20204000))&0x100)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DLEN,SPI Master Data Length Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEN ,Data length"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "DLEN,SPI Master Data Length Register"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "LTOH,SPI LOSSI Mode TOH Register"
|
|
bitfld.long 0x00 0.--3. " TOH ,The output hold delay in APB clocks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "DC,SPI DMA DREQ Controls Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RPANIC ,DMA read panic threshold"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RDREQ ,DMA read request threshold"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TPANIC ,DMA write panic threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TDREQ ,DMA write request threshold"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI/BSC SLAVE"
|
|
base ad:0x20214000
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,I2C SPI Data Register"
|
|
rbitfld.long 0x00 27.--31. " RXFLEVEL ,RX FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 22.--26. " TXFLEVEL ,TX FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 21. " RXBUSY ,Receive busy" "Idle,Busy"
|
|
rbitfld.long 0x00 20. " TXFE ,TX FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " RXFF ,RX FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 18. " TXFF ,TX FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 17. " RXFE ,RX FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 16. " TXBUSY ,Transmit busy" "Idle,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " UE ,TX underrun error" "No error,Error"
|
|
rbitfld.long 0x00 8. " OE ,RX overrun error" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Received/transferred data characters"
|
|
line.long 0x04 "RSR,I2C SPI Status And Error Clear Register"
|
|
bitfld.long 0x04 1. " UE ,TX underrun error" "No error,Error"
|
|
bitfld.long 0x04 0. " OE ,RX overrun error" "No error,Error"
|
|
if (((per.l(ad:0x20214000+0x10))&0x04)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SLV,I2C SPI Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ADDR ,SLVADDR I2C slave address"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SLV,I2C SPI Address Register"
|
|
endif
|
|
group.long 0x0C++0x1B
|
|
line.long 0x00 "CR,I2C SPI Control Register"
|
|
bitfld.long 0x00 13. " INV_TXF ,RX inverse TX status flags" "Low,High"
|
|
bitfld.long 0x00 12. " HOSTCTRLEN ,Enable control for host" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TESTFIFO ,TEST FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INV_RXF ,RX inverse RX status flags" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXE ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " BRK ,Break current operation" "No effect,Break"
|
|
rbitfld.long 0x00 6. " ENCTRL ,Enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENSTAT ,Enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPOL ,Clock polarity" ",SPI related"
|
|
bitfld.long 0x00 3. " CPHA ,Clock phase" ",SPI related"
|
|
bitfld.long 0x00 2. " I2C ,I2C mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI ,SPI mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable device" "Disabled,Enabled"
|
|
line.long 0x04 "FR,I2C SPI Flag Register"
|
|
bitfld.long 0x04 11.--15. " RXFLEVEL ,RX FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 6.--10. " TXFLEVEL ,TX FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 5. " RXBUSY ,Receive busy" "Idle,Busy"
|
|
bitfld.long 0x04 4. " TXFE ,TX FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXFF ,RX FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 2. " TXFF ,TX FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 1. " RXFE ,RX FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 0. " TXBUSY ,Transmit busy" "Idle,Busy"
|
|
line.long 0x08 "IFLS,I2C SPI Interrupt FIFO Level Select Register"
|
|
bitfld.long 0x08 3.--5. " RXIFLSEL ,RX interrupt FIFO level select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
bitfld.long 0x08 0.--2. " TXIFLSEL ,TX interrupt FIFO level select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
line.long 0x0C "IMSC,I2C SPI Interrupt Mask Set/clear Register"
|
|
bitfld.long 0x0C 3. " OEIM ,Overrun error interrupt mask" "Clear,Set"
|
|
bitfld.long 0x0C 2. " BEIM ,Break error interrupt mask" "Clear,Set"
|
|
bitfld.long 0x0C 1. " TXIM ,Transmit interrupt mask" "Clear,Set"
|
|
bitfld.long 0x0C 0. " RXIM ,Receive interrupt mask" "Clear,Set"
|
|
line.long 0x10 "RIS,I2C SPI Raw Interrupt Status Register"
|
|
bitfld.long 0x10 3. " OEIM ,Overrun error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " BEIM ,Break error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " TXIM ,Transmit interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " RXIM ,Receive interrupt" "No interrupt,Interrupt"
|
|
line.long 0x14 "MIS,I2C SPI Masked Interrupt Status Register"
|
|
bitfld.long 0x14 3. " OEIM ,Overrun error masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " BEIM ,Break error masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 1. " TXIM ,Transmit masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " RXIM ,Receive masked interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x18 "ICR,I2C SPI Interrupt Clear Register"
|
|
bitfld.long 0x18 3. " OEIM ,Overrun error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x18 2. " BEIM ,Break error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x18 1. " TXIM ,Transmit interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x18 0. " RXIM ,Receive interrupt clear" "No effect,Clear"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "TDR,I2C SPI FIFO Test Data Register"
|
|
in
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "GPUSTAT,I2C SPI GPU Status Register"
|
|
bitfld.long 0x00 0.--3. " DATA ,GPU to host status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HCTRL,I2C SPI Host Control Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA ,SW processing received via I2C bus"
|
|
line.long 0x08 "DEBUG1,I2C Debug Register"
|
|
hexmask.long 0x08 0.--25. 1. " DATA ,Debug data"
|
|
line.long 0x0C "DEBUG2,SPI Debug Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " DATA ,Debug data"
|
|
width 0x0B
|
|
tree.end
|
|
tree "System Timer"
|
|
base ad:0x20003000
|
|
width 5.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,System Timer Control / Status Register"
|
|
bitfld.long 0x00 3. " M3 ,System timer match 3" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " M2 ,System timer match 2" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " M1 ,System timer match 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " M0 ,System timer match 0" "Not detected,Detected"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "CLO,System Timer Counter Lower Register"
|
|
line.long 0x04 "CHI,System Timer Counter Higher Register"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "C0,System Timer Compare Register 0"
|
|
line.long 0x04 "C1,System Timer Compare Register 1"
|
|
line.long 0x08 "C2,System Timer Compare Register 2"
|
|
line.long 0x0C "C3,System Timer Compare Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x20201000
|
|
width 15.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "DR,Data Register"
|
|
in
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RSRECR,Receive Status Register"
|
|
in
|
|
sif (cpuis("BCM89107")||cpuis("BCM89103"))
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "FR,Flag Register"
|
|
bitfld.long 0x00 8. " RI ,Ring indicator modem status input" "High,Low"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 3. " BUSY ,UART busy" "Idle,Busy"
|
|
bitfld.long 0x00 2. " DCD ,Data carrier detect" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " DSR ,Data set ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CTS ,Clear to send" "High,Low"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "ILPR,IrDA Low-power Counter Register"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR,Flag Register"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY ,UART busy" "Idle,Busy"
|
|
bitfld.long 0x00 0. " CTS ,Clear to send" "High,Low"
|
|
endif
|
|
if (((per.l(ad:0x20201000+0x30))&0x01)==0x00)
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "IBRD,Integer Baud Rate Divisor Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IBRD ,The integer baud rate divisor"
|
|
line.long 0x04 "FBRD,Fractional Baud Rate Divisor Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " FBRD ,The fractional baud rate divisor"
|
|
line.long 0x08 "LCRH,Line Control Register"
|
|
rbitfld.long 0x08 7. " SPS ,Stick parity select" "Disabled,Enabled"
|
|
bitfld.long 0x08 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x08 4. " FEN ,Enable fifos" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " STP2 ,Two stop bits select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EPS ,Even parity select" "Odd,Even"
|
|
bitfld.long 0x08 1. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " BRK ,Send break" "No break,Break"
|
|
else
|
|
rgroup.long 0x24++0x0B
|
|
line.long 0x00 "IBRD,Integer Baud Rate Divisor Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IBRD ,The integer baud rate divisor"
|
|
line.long 0x04 "FBRD,Fractional Baud Rate Divisor Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " FBRD ,The fractional baud rate divisor"
|
|
line.long 0x08 "LCRH,Line Control Register"
|
|
bitfld.long 0x08 7. " SPS ,Stick parity select" "Disabled,Enabled"
|
|
bitfld.long 0x08 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x08 4. " FEN ,Enable fifos" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " STP2 ,Two stop bits select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EPS ,Even parity select" "Odd,Even"
|
|
bitfld.long 0x08 1. " PEN ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " BRK ,Send break" "No break,Break"
|
|
endif
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "CR,Control Register"
|
|
sif (cpuis("BCM89107")||cpuis("BCM89103"))
|
|
bitfld.long 0x00 15. " CTSEN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RTSEN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUT2 ,UART modem status output 2" "High,Low"
|
|
bitfld.long 0x00 12. " OUT1 ,UART modem status output 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTS ,Request to send" "High,Low"
|
|
bitfld.long 0x00 10. " DTR ,Data transmit ready" "Not ready,Ready"
|
|
bitfld.long 0x00 9. " RXE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LBE ,Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIRLP ,IrDA SIR low power mode" "Active high pulse,3 times period"
|
|
bitfld.long 0x00 1. " SIREN ,SIR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " CTSEN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RTSEN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RTS ,Request to send" "High,Low"
|
|
bitfld.long 0x00 9. " RXE ,Receive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXE ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LBE ,Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0x04 3.--5. " RXIFLSEL ,Receive interrupt FIFO level select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
bitfld.long 0x04 0.--2. " TXIFLSEL ,Transmit interrupt FIFO level select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
line.long 0x08 "IMSC,Interrupt Mask Set/clear Register"
|
|
sif (cpuis("BCM89107")||cpuis("BCM89103"))
|
|
bitfld.long 0x08 10. " OEIM ,Overrun error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " BEIM ,Break error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " PEIM ,Parity error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " FEIM ,Framing error interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 6. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " TXIM ,Transmit interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " RXIM ,Receive interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " DSRMIM ,Nuartdsr modem interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DCDMIM ,Nuartdcd modem interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CTSMIM ,Nuartcts modem interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " RIMIM ,Nuartri modem interrupt mask" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x08 10. " OEIM ,Overrun error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " BEIM ,Break error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " PEIM ,Parity error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " FEIM ,Framing error interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 6. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " TXIM ,Transmit interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " RXIM ,Receive interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CTSMIM ,Nuartcts modem interrupt mask" "Not masked,Masked"
|
|
endif
|
|
sif (cpuis("BCM89107")||cpuis("BCM89103"))
|
|
rgroup.long 0x3C++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 10. " OERIS ,Overrun error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " BERIS ,Break error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PERIS ,Parity error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " FERIS ,Framing error interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTRIS ,Receive timeout interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXRIS ,Receive interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " DSRRMIS ,Nuartdsr modem interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DCDRMIS ,Nuartdcd modem interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " CTSRMIS ,Nuartcts modem interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RIRMIS ,Nuartri modem modem interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 10. " OEMIS ,Overrun error masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " BEMIS ,Break error masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " PEMIS ,Parity error masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " FEMIS ,Framing error masked interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RTMIS ,Receive timeout masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " TXMIS ,Transmit masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXMIS ,Receive masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " DSRMMIS ,Nuartdsr modem interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DCDMMIS ,Nuartdcd modem interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " CTSMMIS ,Nuartcts modem interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RIMMIS ,Nuartri modem modem interrupt status" "No interrupt,Interrupt"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 10. " OEIC ,Overrun error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " BEIC ,Break error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " PEIC ,Parity error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " FEIC ,Framing error interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIC ,Receive timeout interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXIC ,Transmit interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RXIC ,Receive interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " DSRMIC ,Nuartdsr modem interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DCDMIC ,Nuartdcd modem interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTSMIC ,Nuartcts modem interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RIMIC ,Nuartri modem modem interrupt clear" "No effect,Clear"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "UARTDMACR,DMA Control Register"
|
|
bitfld.word 0x00 2. " DMAONERR ,DMA on error" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
rgroup.byte 0xFE0++0x00
|
|
line.byte 0x00 "UARTPERIPHID0,Peripherial ID 0"
|
|
rgroup.byte 0xFE4++0x00
|
|
line.byte 0x00 "UARTPERIPHID1,Peripherial ID 1"
|
|
rgroup.byte 0xFE8++0x00
|
|
line.byte 0x00 "UARTPERIPHID2,Peripherial ID 2"
|
|
rgroup.byte 0xFEC++0x00
|
|
line.byte 0x00 "UARTPERIPHID3,Peripherial ID 3"
|
|
rgroup.byte 0xFF0++0x00
|
|
line.byte 0x00 "UARTPCELLID0,Peripherial Cell ID 0"
|
|
rgroup.byte 0xFF4++0x00
|
|
line.byte 0x00 "UARTPCELLID1,Peripherial Cell ID 1"
|
|
rgroup.byte 0xFF8++0x00
|
|
line.byte 0x00 "UARTPCELLID2,Peripherial Cell ID 2"
|
|
rgroup.byte 0xFFC++0x00
|
|
line.byte 0x00 "UARTPCELLID3,Peripherial Cell ID 3"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 10. " OERIS ,Overrun error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " BERIS ,Break error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PERIS ,Parity error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " FERIS ,Framing error interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTRIS ,Receive timeout interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXRIS ,Receive interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " CTSRMIS ,UARTCTS modem interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 10. " OERIS ,Overrun error masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " BERIS ,Break error masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " PERIS ,Parity error masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " FERIS ,Framing error masked interrupt status" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTRIS ,Receive timeout masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " RXRIS ,Receive masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " CTSRMIS ,UARTCTS modem masked interrupt status" "Not masked,Masked"
|
|
line.long 0x04 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x04 10. " OERIS ,Overrun error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " BERIS ,Break error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " PERIS ,Parity error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 7. " FERIS ,Framing error interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RTRIS ,Receive timeout interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " TXRIS ,Transmit interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " RXRIS ,Receive interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " CTSRMIS ,UARTCTS modem interrupt clear" "No effect,Clear"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "ITCR,Test Control Register"
|
|
bitfld.long 0x00 1. " ITCR1 ,Test FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ITCR0 ,Integration test enable" "Disabled,Enabled"
|
|
line.long 0x04 "ITIP,Integration Test Input Register"
|
|
bitfld.long 0x04 3. " ITIP3 ,Reads return the value of the nuartcts primary input" "Low,High"
|
|
bitfld.long 0x04 0. " ITIP0 ,Reads return the value of the UARTRXD primary input" "Low,High"
|
|
line.long 0x08 "ITOP,Integration Test Output Register"
|
|
bitfld.long 0x08 11. " ITOP11 ,Intra-chip output. Writes specify the value to be driven on UARTMSINTR" "0,1"
|
|
bitfld.long 0x08 10. " ITOP10 ,Intra-chip output. Writes specify the value to be driven on UARTRXINTR" "0,1"
|
|
bitfld.long 0x08 9. " ITOP9 ,Intra-chip output. Writes specify the value to be driven on UARTTXINTR" "0,1"
|
|
bitfld.long 0x08 8. " ITOP8 ,Intra-chip output. Writes specify the value to be driven on UARTRTINTR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ITOP7 ,Intra-chip output. Writes specify the value to be driven on UARTEINTR" "0,1"
|
|
bitfld.long 0x08 6. " ITOP6 ,Intra-chip output. Writes specify the value to be driven on UARTINTR" "0,1"
|
|
bitfld.long 0x08 3. " ITOP3 ,Intra-chip output. Writes specify the value to be driven on nuartrts." "0,1"
|
|
bitfld.long 0x08 0. " ITOP0 ,Intra-chip output. Writes specify the value to be driven on UARTTXD" "0,1"
|
|
if (((per.l(ad:0x20201000+0x80))&0x02)==0x02)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TDR,Test Data Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " TDR10_0 ,Test data"
|
|
else
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "TDR,Test Data Register"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ARM Timer"
|
|
base ad:0x2000B000
|
|
width 10.
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LOAD,Timer Load Register"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "VALUE,Timer Value Register"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "CONTROL,Timer Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRCP ,Free running counter pre-scaler"
|
|
bitfld.long 0x00 9. " FRC_EN ,Free running counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TIMER_HALT ,Timer halted in debug halted mode" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " TIMER_EN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TIMER_MODE ,Timer mode" "Free running,?..."
|
|
bitfld.long 0x00 5. " INT_ENABLE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " TIMER_PRE ,Pre-scale bits" "/1,/16,/256,/1"
|
|
bitfld.long 0x00 1. " TIMER_SIZE ,Selects 16/32 bit counter operation" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ONE_SHOT ,Selects one-shot or wrapping counter mode" "Wrapping mode,?..."
|
|
wgroup.long 0x40C++0x03
|
|
line.long 0x00 "INT_CLR,Timer IRQ Clear Register"
|
|
rgroup.long 0x410++0x07
|
|
line.long 0x00 "RAW_IRQ,Timer Raw IRQ Register"
|
|
bitfld.long 0x00 0. " RAW_IRQ ,The interrupt pending" "No interrupt,Interrupt"
|
|
line.long 0x04 "MASK_IRQ,Timer Masked IRQ Register"
|
|
bitfld.long 0x04 0. " MASK_IRQ ,The interrupt mask" "Masked,Not masked"
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "RELOAD,Timer Reload Register"
|
|
line.long 0x04 "PRE_DIV,The Timer pre-divider Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " PRE_DIV ,Pre-divider value"
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "FRC,Free Running Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB"
|
|
base ad:0x20980000
|
|
width 15.
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "USB_MDIO_CNTL,USB MDIO Interface Control Register"
|
|
rbitfld.long 0x00 31. " MDIO_BUSY ,MDIO busy" "Idle,Busy"
|
|
bitfld.long 0x00 23. " BB_MDO ,Direct write (Bitbash) MDO output" "0,1"
|
|
bitfld.long 0x00 22. " BB_MDC ,Direct write (Bitbash) MDC output" "0,1"
|
|
bitfld.long 0x00 21. " BB_ENBL ,MDIO bitbash enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FREERUN ,MDC is continuous active or MDC only active during data transfer" "Data transfer,Continuous"
|
|
bitfld.long 0x00 16.--19. " MDC_RATIO ,MDC clock freq is sysclk/mdc_ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MDI ,16-bit read of MDIO input shift register"
|
|
line.long 0x04 "USB_MDIO_DATA,USB Data For MDIO Interface Register"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "USB_VBUS_DRV,USB Vbus And Other Miscellaneous Controls Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
width 0x0B
|
|
textline " "
|