14345 lines
1010 KiB
Plaintext
14345 lines
1010 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AT91SAM9M10/11 On-Chip Peripherals
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; @Props: Released
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; @Author: BUJ, DAN, RAF
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; @Changelog:
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; 2010-03-25
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; 2012-11-06
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: doc6355.pdf (rev. A, 06-Jan-10); doc6437.pdf (2012-03-23)
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; @Core: ARM926EJ-S
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perat91sam9m.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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width 0x0b
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base ad:0x00000000
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0xfffffd00
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "RSTC_CR,Reset Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Reset"
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "RSTC_SR,Reset Controller Status Register"
|
|
in
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RSTC_MR,Reset Controller Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2-cycles,4-cycles,8-cycles,16-cycles,32-cycles,64-cycles,128-cycles,256-cycles,512-cycles,1024-cycles,2048-cycles,4096-cycles,8192-cycles,16384-cycles,32768-cycles,65536-cycles"
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0xfffffdb0
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,Hour Mode Register"
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
if ((data.long(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "0,1,2,3,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
if ((d.l(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CAL_Set/Clr ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIM_Set/Clr ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SEC_Set/Clr ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ALR_Set/Clr ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACK_Set/Clr ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RTC_VER,Valid Entry Register"
|
|
bitfld.long 0x00 3. " NVCAL ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTAL ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NVC ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVT ,Non-Valid Time" "Not detected,Detected"
|
|
width 0xB
|
|
tree.end
|
|
tree "RTT (Real-Time Timer)"
|
|
base ad:0xfffffd20
|
|
width 11.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTT_MR,Real-Time Timer Mode Register"
|
|
bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "No effect,Restarted"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value"
|
|
line.long 0x4 "RTT_AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "RTT_VR,Real-Time Timer Value Register"
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "RTT_SR,Real-time Timer Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PIT (Periodic Interval Timer)"
|
|
base ad:0xfffffd30
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PIT_MR,Periodic Interval Timer Mode Register"
|
|
bitfld.long 0x00 25. " PITIEN ,Periodic Interval Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PITEN ,Period Interval Timer Enabled" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. 1. " PIV ,Periodic Interval Value"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "PIT_SR,Periodic Interval Timer Status Register"
|
|
bitfld.long 0x00 0. " PITS ,Periodic Interval Timer Status" "Not reached,Reached"
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x0 "PIT_PIVR,Periodic Interval Timer Value Register"
|
|
in
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "PIT_PIIR,Periodic Interval Timer Image Register"
|
|
hexmask.long.word 0x0 20.--31. 1. " PICNT ,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. " CPIV ,Current Periodic Interval Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0xfffffd40
|
|
width 8.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "WDT_CR,Watchdog Timer Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restart"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "WDT_MR,Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Running,Stopped"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog Processor Reset" "All,Processor"
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "WDT_SR,Status Register"
|
|
in
|
|
;wgroup 0x0++0x0
|
|
width 0xb
|
|
tree.end
|
|
tree "SHDWC (Shutdown Controller)"
|
|
base ad:0xfffffd10
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "SHDW_CR,Shutdown Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " SHDW ,Shut Down Command" "No effect,Shut down"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SHDW_MR,Shutdown Mode Register"
|
|
bitfld.long 0x00 17. " RTCWKEN ,Real-time Clock Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTTWKEN ,Real-time Timer Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CPTWK0 ,Counter on Wake-Up 0" "1 cycle,17 cycles,33 cycles,49 cycles,65 cycles,81 cycles,97 cycles,113 cycles,129 cycles,145 cycles,161 cycles,177 cycles,193 cycles,209 cycles,225 cycles,241 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WKMODE0 ,Wake-Up Mode 0" "No wake-up,Low/high,High/low,Both"
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "SHDW_SR,Shutdown Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0xfffffd60
|
|
width 11.
|
|
group.long 0x00++0xf
|
|
line.long 0x0 "SYS_GPBR0,General Purpose Backup Register 0"
|
|
line.long 0x4 "SYS_GPBR1,General Purpose Backup Register 1"
|
|
line.long 0x8 "SYS_GPBR2,General Purpose Backup Register 2"
|
|
line.long 0xC "SYS_GPBR3,General Purpose Backup Register 3"
|
|
width 0xb
|
|
tree.end
|
|
tree "MATRIX (Bus Matrix)"
|
|
base ad:0xffffea00
|
|
width 14.
|
|
group.long 0x00++0x2b
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0xC "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x10 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x14 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x18 "MATRIX_MCFG6,Bus Matrix Master Configuration Register 6"
|
|
bitfld.long 0x18 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x1C "MATRIX_MCFG7,Bus Matrix Master Configuration Register 7"
|
|
bitfld.long 0x1C 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x20 "MATRIX_MCFG8,Bus Matrix Master Configuration Register 8"
|
|
bitfld.long 0x20 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x24 "MATRIX_MCFG9,Bus Matrix Master Configuration Register 9"
|
|
bitfld.long 0x24 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x28 "MATRIX_MCFG10,Bus Matrix Master Configuration Register 10"
|
|
bitfld.long 0x28 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MATRIX_MCFG11,Bus Matrix Master Configuration Register 11"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS0,Bus Matrix Priority Register B for Slave 0 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS1,Bus Matrix Priority Register B for Slave 1 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS2,Bus Matrix Priority Register B for Slave 2 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x98++0x7
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS3,Bus Matrix Priority Register B for Slave 3 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xA0++0x7
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS4,Bus Matrix Priority Register B for Slave 4 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xA8++0x7
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A for Slave 5 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS5,Bus Matrix Priority Register B for Slave 5 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xB0++0x7
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register A for Slave 6 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS6,Bus Matrix Priority Register B for Slave 6 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xB8++0x7
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register A for Slave 7 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS7,Bus Matrix Priority Register B for Slave 7 Register"
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MATRIX_MRCR,Master Remap Control Register"
|
|
bitfld.long 0x00 11. " RCB11 ,Remap Command Bit for Master 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RCB10 ,Remap Command Bit for Master 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCB9 ,Remap Command Bit for Master 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RCB8 ,Remap Command Bit for Master 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RCB7 ,Remap Command Bit for Master 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RCB6 ,Remap Command Bit for Master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RCB5 ,Remap Command Bit for Master 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RCB4 ,Remap Command Bit for Master 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RCB3 ,Remap Command Bit for Master 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RCB2 ,Remap Command Bit for Master 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for Master 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for Master 0" "Disabled,Enabled"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "CCFG_TCMR,Bus Matrix TCM Configuration Register"
|
|
bitfld.long 0x00 11. " TCM_NWS ,TCM Wait State" "0 wait state,1 wait state"
|
|
bitfld.long 0x00 4.--7. " DTCM_SIZE ,DTCM Enabled Memory Block Size" "0-KB,Reserved,Reserved,Reserved,Reserved,Reserved,32-KB,64-KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ITCM_SIZE ,ITCM Enabled Memory Block Size" "0-KB,Reserved,Reserved,Reserved,Reserved,Reserved,32-KB,?..."
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "CCFG_VMCR,Bus Matrix Video Mode Configuration Register"
|
|
bitfld.long 0x00 0. " VDEC_SEL ,Video Mode Selection" "OFF,ON"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "EBI1_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x0 18. " DDR_DRIVE ,DDR2 dedicated port I/O slew rate selection" "Low,High"
|
|
bitfld.long 0x0 16.--17. " EBI_DRIVE ,EBI I/O Drive Configuration" "1.8V Low,3.3V Low,1.8V High,3.3V High"
|
|
textline " "
|
|
bitfld.long 0x0 8. " EBI_DBPUC ,EBI Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
bitfld.long 0x0 3. " EBI_CS3A ,EBI1 Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EBI_CS1A ,EBI1 Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree.open "SMC (Static Memory Controller)"
|
|
base ad:0xffffe800
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x60+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x60+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x60+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
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|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
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|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
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|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x70+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x2000)))
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|
group.long (0x70+0xc)++0x3
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|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
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|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
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|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
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|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
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|
textline " "
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|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
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|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
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|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
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|
elif (((d.l(ad:0xffffe800+0x70+0xc))&0x1000000)==0x1000000)
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|
group.long (0x70+0xc)++0x3
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|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
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|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
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|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
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|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
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|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
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|
textline " "
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bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
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|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
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elif ((((d.l(ad:0xffffe800+0x70+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x2000)))
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|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
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|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
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|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
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|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
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|
textline " "
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|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
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|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
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else
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
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|
textline " "
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|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
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|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
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|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "DDRSDRC (DDR/SDR SDRAM Controller)"
|
|
tree "DDRSDRC0"
|
|
base ad:0xffffe600
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DDRSDRC_MR,DDRSDRC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,DDRSDRC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "DDRSDRC_RTR,DDRSDRC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,DDRSDRC Refresh Timer Count"
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x6)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DIC/DS ,Output Driver Impedance Control" "Normal,Weak"
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,Reserved,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x7)==0x3)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x10)==0x10)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "Reserved,9 bits,10 bits,11 bits"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
endif
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x3)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TWTR ,Internal Write to Read Delay" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DDRSDRC_T1PR,Timing 1 Parameter Register"
|
|
bitfld.long 0x00 24.--27. " TXP ,Exit Power-down Delay to First Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXSRD ,Exit Self Refresh Delay to Read Command"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXSNR ,Exit Self Refresh Delay to Non-read Command"
|
|
bitfld.long 0x00 0.--4. " TRFC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x6&&(d.l(ad:0xffffe600+0x08)&0x100000)==0x100000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x7)==0x6&&(d.l(ad:0xffffe600+0x08)&0x100000)==0x0)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x6)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
bitfld.long 0x00 16. " APDE ,Active Power Down Exit Time" "Fast Exit,Slow Exit"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x7)==(0x1||0x3))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
endif
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==(0x0||0x1))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "Reserved,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "32-bit,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DDRSDRC_DLL,DDRSDRC DLL Information Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MDVAL ,DLL Master Delay Value"
|
|
bitfld.long 0x00 2. " MDOVF ,DLL Master Delay Overflow Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDDEC ,DLL Master Delay Decrement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDINC ,DLL Master Delay Increment" "Disabled,Enabled"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
group.long 0x34++0xf
|
|
line.long 0x0 "DDRSDRC_DELAY1,DELAY I/O Register"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDRSDRC_DELAY2,DELAY I/O Register"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "DDRSDRC_DELAY3,DELAY I/O Register"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "DDRSDRC_DELAY4,DELAY I/O Register"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DDRSDRC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "DDRSDRC_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "DDRSDRC1"
|
|
base ad:0xffffe400
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DDRSDRC_MR,DDRSDRC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,DDRSDRC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "DDRSDRC_RTR,DDRSDRC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,DDRSDRC Refresh Timer Count"
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x6)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DIC/DS ,Output Driver Impedance Control" "Normal,Weak"
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,Reserved,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x7)==0x3)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x10)==0x10)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "Reserved,9 bits,10 bits,11 bits"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
endif
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x3)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TWTR ,Internal Write to Read Delay" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DDRSDRC_T1PR,Timing 1 Parameter Register"
|
|
bitfld.long 0x00 24.--27. " TXP ,Exit Power-down Delay to First Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXSRD ,Exit Self Refresh Delay to Read Command"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXSNR ,Exit Self Refresh Delay to Non-read Command"
|
|
bitfld.long 0x00 0.--4. " TRFC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x6&&(d.l(ad:0xffffe400+0x08)&0x100000)==0x100000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x7)==0x6&&(d.l(ad:0xffffe400+0x08)&0x100000)==0x0)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x6)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
bitfld.long 0x00 16. " APDE ,Active Power Down Exit Time" "Fast Exit,Slow Exit"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x7)==(0x1||0x3))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
endif
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==(0x0||0x1))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "Reserved,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "32-bit,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DDRSDRC_DLL,DDRSDRC DLL Information Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MDVAL ,DLL Master Delay Value"
|
|
bitfld.long 0x00 2. " MDOVF ,DLL Master Delay Overflow Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDDEC ,DLL Master Delay Decrement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDINC ,DLL Master Delay Increment" "Disabled,Enabled"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
group.long 0x34++0xf
|
|
line.long 0x0 "DDRSDRC_DELAY1,DELAY I/O Register"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDRSDRC_DELAY2,DELAY I/O Register"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "DDRSDRC_DELAY3,DELAY I/O Register"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "DDRSDRC_DELAY4,DELAY I/O Register"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DDRSDRC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "DDRSDRC_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "ECC (Error Corrected Code)"
|
|
base ad:0xffffe200
|
|
width 0x9
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_CR,ECC Control Register"
|
|
bitfld.long 0x00 1. " SRST ,Soft Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RST ,RESET Parity" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ECC_MR,ECC Mode Register"
|
|
bitfld.long 0x00 4.--5. " TYPECORRECT , Type of Correction" "1 bit for a page,1 bit for 256 bytes,1 bit for 512 bytes,?..."
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page Size" "528 words,1056 words,2112 words,4224 words"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "ECC_SR1,ECC Status Register 1"
|
|
bitfld.long 0x00 30. " MULERR7 ,Multiple Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 29. " ECCERR7 ,ECC Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 28. " RECERR7 ,Recoverable Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MULERR6 ,Multiple Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 25. " ECCERR6 ,ECC Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 24. " RECERR6 ,Recoverable Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MULERR5 ,Multiple Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 21. " ECCERR5 ,ECC Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 20. " RECERR5 ,Recoverable Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MULERR4 ,Multiple Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 17. " ECCERR4 ,ECC Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 16. " RECERR4 ,Recoverable Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MULERR3 ,Multiple Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes" "No error,Error"
|
|
bitfld.long 0x00 13. " ECCERR3 ,ECC Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes" "No error,Error"
|
|
bitfld.long 0x00 12. " RECERR3 ,Recoverable Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MULERR2 ,Multiple Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes" "No error,Error"
|
|
bitfld.long 0x00 9. " ECCERR2 ,ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes" "No error,Error"
|
|
bitfld.long 0x00 8. " RECERR2 ,Recoverable Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MULERR1 ,Multiple Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes" "No error,Error"
|
|
bitfld.long 0x00 5. " ECCERR1 ,ECC Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes" "No error,Error"
|
|
bitfld.long 0x00 4. " RECERR1 ,Recoverable Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MULERR0 ,Multiple Error" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR0 ,ECC Error" "No error,Error"
|
|
bitfld.long 0x00 0. " RECERR0 ,Recoverable Error" "No error,Error"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "ECC_SR2,ECC Status Register 2"
|
|
bitfld.long 0x00 30. " MULERR15 ,Multiple Error in the page between the 3840th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 29. " ECCERR15 ,ECC Error in the page between the 3840th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 28. " RECERR15 ,Recoverable Error in the page between the 3840th and the 4095th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MULERR14 ,Multiple Error in the page between the 3584th and the 3839th bytes" "No error,Error"
|
|
bitfld.long 0x00 25. " ECCERR14 ,ECC Error in the page between the 3584th and the 3839th bytes" "No error,Error"
|
|
bitfld.long 0x00 24. " RECERR14 ,Recoverable Error in the page between the 3584th and the 3839th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MULERR13 ,Multiple Error in the page between the 3328th and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 21. " ECCERR13 ,ECC Error in the page between the 3328th and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 20. " RECERR13 ,Recoverable Error in the page between the 3328th and the 3583rd bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MULERR12 ,Multiple Error in the page between the 3072nd and the 3327th bytes" "No error,Error"
|
|
bitfld.long 0x00 17. " ECCERR12 ,ECC Error in the page between the 3072nd and the 3327th bytes" "No error,Error"
|
|
bitfld.long 0x00 16. " RECERR12 ,Recoverable Error in the page between the 3072nd and the 3327th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MULERR11 ,Multiple Error in the page between the 2816th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 13. " ECCERR11 ,ECC Error in the page between the 2816th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 12. " RECERR11 ,Recoverable Error in the page between the 2816th and the 3071st bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MULERR10 ,Multiple Error in the page between the 2560th and the 2815th bytes" "No error,Error"
|
|
bitfld.long 0x00 9. " ECCERR10 ,ECC Error in the page between the 2560th and the 2815th bytes" "No error,Error"
|
|
bitfld.long 0x00 8. " RECERR10 ,Recoverable Error in the page between the 2560th and the 2815th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MULERR9 ,Multiple Error in the page between the 2304th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 5. " ECCERR9 ,ECC Error in the page between the 2304th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 4. " RECERR9 ,Recoverable Error in the page between the 2304th and the 2559th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MULERR8 ,Multiple Error in the page between the 2048th and the 2303rd bytes" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR8 ,ECC Error in the page between the 2048th and the 2303rd bytes" "No error,Error"
|
|
bitfld.long 0x00 0. " RECERR8 ,Recoverable Error in the page between the 2048th and the 2303rd bytes" "No error,Error"
|
|
if (((d.l(ad:(0xffffe200+0x4)))&0x30)==0x10)
|
|
rgroup.long 0x0c++0x7 "Registers for 1 ECC per 256 bytes for a page"
|
|
line.long 0x0 "ECC_PR0 ,ECC Parity Register 0 "
|
|
hexmask.long.word 0x0 12.--22. 1. " NPARITY0 ,Parity 0 "
|
|
hexmask.long.byte 0x0 3.--10. 8. " WORDADDR0 ,Corrupted Word Address in the page between the 0 byte and the 255th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR0 ,Corrupted Bit Address in the page between the 0 byte and the 255th bytes"
|
|
line.long 0x4 "ECC_PR1 ,ECC Parity Register 1 "
|
|
hexmask.long.word 0x4 12.--22. 1. " NPARITY1 ,Parity 1 "
|
|
hexmask.long.byte 0x4 3.--10. 8. " WORDADDR1 ,Corrupted Word Address in the page between the 256 byte and the 511th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR1 ,Corrupted Bit Address in the page between the 256 byte and the 511th bytes"
|
|
rgroup.long 0x18++0x37
|
|
line.long 0x0 "ECC_PR2 ,ECC Parity Register 2 "
|
|
hexmask.long.word 0x0 12.--22. 1. " NPARITY2 ,Parity 2 "
|
|
hexmask.long.byte 0x0 3.--10. 8. " WORDADDR2 ,Corrupted Word Address in the page between the 512 byte and the 767th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR2 ,Corrupted Bit Address in the page between the 512 byte and the 767th bytes"
|
|
line.long 0x4 "ECC_PR3 ,ECC Parity Register 3 "
|
|
hexmask.long.word 0x4 12.--22. 1. " NPARITY3 ,Parity 3 "
|
|
hexmask.long.byte 0x4 3.--10. 8. " WORDADDR3 ,Corrupted Word Address in the page between the 768 byte and the 1023th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR3 ,Corrupted Bit Address in the page between the 768 byte and the 1023th bytes"
|
|
line.long 0x8 "ECC_PR4 ,ECC Parity Register 4 "
|
|
hexmask.long.word 0x8 12.--22. 1. " NPARITY4 ,Parity 4 "
|
|
hexmask.long.byte 0x8 3.--10. 8. " WORDADDR4 ,Corrupted Word Address in the page between the 1024 byte and the 1279th bytes"
|
|
hexmask.long.byte 0x8 0.--2. 1. " BITADDR4 ,Corrupted Bit Address in the page between the 1024 byte and the 1279th bytes"
|
|
line.long 0xC "ECC_PR5 ,ECC Parity Register 5 "
|
|
hexmask.long.word 0xC 12.--22. 1. " NPARITY5 ,Parity 5 "
|
|
hexmask.long.byte 0xC 3.--10. 8. " WORDADDR5 ,Corrupted Word Address in the page between the 1280 byte and the 1535th bytes"
|
|
hexmask.long.byte 0xC 0.--2. 1. " BITADDR5 ,Corrupted Bit Address in the page between the 1280 byte and the 1535th bytes"
|
|
line.long 0x10 "ECC_PR6 ,ECC Parity Register 6 "
|
|
hexmask.long.word 0x10 12.--22. 1. " NPARITY6 ,Parity 6 "
|
|
hexmask.long.byte 0x10 3.--10. 8. " WORDADDR6 ,Corrupted Word Address in the page between the 1536 byte and the 1791th bytes"
|
|
hexmask.long.byte 0x10 0.--2. 1. " BITADDR6 ,Corrupted Bit Address in the page between the 1536 byte and the 1791th bytes"
|
|
line.long 0x14 "ECC_PR7 ,ECC Parity Register 7 "
|
|
hexmask.long.word 0x14 12.--22. 1. " NPARITY7 ,Parity 7 "
|
|
hexmask.long.byte 0x14 3.--10. 8. " WORDADDR7 ,Corrupted Word Address in the page between the 1792 byte and the 2047th bytes"
|
|
hexmask.long.byte 0x14 0.--2. 1. " BITADDR7 ,Corrupted Bit Address in the page between the 1792 byte and the 2047th bytes"
|
|
line.long 0x18 "ECC_PR8 ,ECC Parity Register 8 "
|
|
hexmask.long.word 0x18 12.--22. 1. " NPARITY8 ,Parity 8 "
|
|
hexmask.long.byte 0x18 3.--10. 8. " WORDADDR8 ,Corrupted Word Address in the page between the 2048 byte and the 2303th bytes"
|
|
hexmask.long.byte 0x18 0.--2. 1. " BITADDR8 ,Corrupted Bit Address in the page between the 2048 byte and the 2303th bytes"
|
|
line.long 0x1C "ECC_PR9 ,ECC Parity Register 9 "
|
|
hexmask.long.word 0x1C 12.--22. 1. " NPARITY9 ,Parity 9 "
|
|
hexmask.long.byte 0x1C 3.--10. 8. " WORDADDR9 ,Corrupted Word Address in the page between the 2304 byte and the 2559th bytes"
|
|
hexmask.long.byte 0x1C 0.--2. 1. " BITADDR9 ,Corrupted Bit Address in the page between the 2304 byte and the 2559th bytes"
|
|
line.long 0x20 "ECC_PR10,ECC Parity Register 10"
|
|
hexmask.long.word 0x20 12.--22. 1. " NPARITY10 ,Parity 10"
|
|
hexmask.long.byte 0x20 3.--10. 8. " WORDADDR10 ,Corrupted Word Address in the page between the 2560 byte and the 2815th bytes"
|
|
hexmask.long.byte 0x20 0.--2. 1. " BITADDR10 ,Corrupted Bit Address in the page between the 2560 byte and the 2815th bytes"
|
|
line.long 0x24 "ECC_PR11,ECC Parity Register 11"
|
|
hexmask.long.word 0x24 12.--22. 1. " NPARITY11 ,Parity 11"
|
|
hexmask.long.byte 0x24 3.--10. 8. " WORDADDR11 ,Corrupted Word Address in the page between the 2816 byte and the 3071th bytes"
|
|
hexmask.long.byte 0x24 0.--2. 1. " BITADDR11 ,Corrupted Bit Address in the page between the 2816 byte and the 3071th bytes"
|
|
line.long 0x28 "ECC_PR12,ECC Parity Register 12"
|
|
hexmask.long.word 0x28 12.--22. 1. " NPARITY12 ,Parity 12"
|
|
hexmask.long.byte 0x28 3.--10. 8. " WORDADDR12 ,Corrupted Word Address in the page between the 3072 byte and the 3327th bytes"
|
|
hexmask.long.byte 0x28 0.--2. 1. " BITADDR12 ,Corrupted Bit Address in the page between the 3072 byte and the 3327th bytes"
|
|
line.long 0x2C "ECC_PR13,ECC Parity Register 13"
|
|
hexmask.long.word 0x2C 12.--22. 1. " NPARITY13 ,Parity 13"
|
|
hexmask.long.byte 0x2C 3.--10. 8. " WORDADDR13 ,Corrupted Word Address in the page between the 3328 byte and the 3583th bytes"
|
|
hexmask.long.byte 0x2C 0.--2. 1. " BITADDR13 ,Corrupted Bit Address in the page between the 3328 byte and the 3583th bytes"
|
|
line.long 0x30 "ECC_PR14,ECC Parity Register 14"
|
|
hexmask.long.word 0x30 12.--22. 1. " NPARITY14 ,Parity 14"
|
|
hexmask.long.byte 0x30 3.--10. 8. " WORDADDR14 ,Corrupted Word Address in the page between the 3584 byte and the 3839th bytes"
|
|
hexmask.long.byte 0x30 0.--2. 1. " BITADDR14 ,Corrupted Bit Address in the page between the 3584 byte and the 3839th bytes"
|
|
line.long 0x34 "ECC_PR15,ECC Parity Register 15"
|
|
hexmask.long.word 0x34 12.--22. 1. " NPARITY15 ,Parity 15"
|
|
hexmask.long.byte 0x34 3.--10. 8. " WORDADDR15 ,Corrupted Word Address in the page between the 3840 byte and the 4095th bytes"
|
|
hexmask.long.byte 0x34 0.--2. 1. " BITADDR15 ,Corrupted Bit Address in the page between the 3840 byte and the 4095th bytes"
|
|
elif (((d.l(ad:(0xffffe200+0x4)))&0x30)==0x20)
|
|
rgroup.long 0x0c++0x7 "Registers for 1 ECC per 512 bytes for a page"
|
|
line.long 0x0 "ECC_PR0 ,ECC Parity Register 0 "
|
|
hexmask.long.word 0x0 12.--23. 1. " NPARITY0 ,Parity 0 "
|
|
hexmask.long.word 0x0 3.--11. 8. " WORDADDR0 ,Corrupted Word Address in the page between the 0 byte and the 511th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR0 ,Corrupted Bit Address in the page between the 0 byte and the 511th bytes"
|
|
line.long 0x4 "ECC_PR1 ,ECC Parity Register 1 "
|
|
hexmask.long.word 0x4 12.--23. 1. " NPARITY1 ,Parity 1 "
|
|
hexmask.long.word 0x4 3.--11. 8. " WORDADDR1 ,Corrupted Word Address in the page between the 512 byte and the 1023th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR1 ,Corrupted Bit Address in the page between the 512 byte and the 1023th bytes"
|
|
rgroup.long 0x18++0x17
|
|
line.long 0x0 "ECC_PR2 ,ECC Parity Register 2 "
|
|
hexmask.long.word 0x0 12.--23. 1. " NPARITY2 ,Parity 2 "
|
|
hexmask.long.word 0x0 3.--11. 8. " WORDADDR2 ,Corrupted Word Address in the page between the 1024 byte and the 1535th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR2 ,Corrupted Bit Address in the page between the 1024 byte and the 1535th bytes"
|
|
line.long 0x4 "ECC_PR3 ,ECC Parity Register 3 "
|
|
hexmask.long.word 0x4 12.--23. 1. " NPARITY3 ,Parity 3 "
|
|
hexmask.long.word 0x4 3.--11. 8. " WORDADDR3 ,Corrupted Word Address in the page between the 1536 byte and the 2047th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR3 ,Corrupted Bit Address in the page between the 1536 byte and the 2047th bytes"
|
|
line.long 0x8 "ECC_PR4 ,ECC Parity Register 4 "
|
|
hexmask.long.word 0x8 12.--23. 1. " NPARITY4 ,Parity 4 "
|
|
hexmask.long.word 0x8 3.--11. 8. " WORDADDR4 ,Corrupted Word Address in the page between the 2048 byte and the 2559th bytes"
|
|
hexmask.long.byte 0x8 0.--2. 1. " BITADDR4 ,Corrupted Bit Address in the page between the 2048 byte and the 2559th bytes"
|
|
line.long 0xC "ECC_PR5 ,ECC Parity Register 5 "
|
|
hexmask.long.word 0xC 12.--23. 1. " NPARITY5 ,Parity 5 "
|
|
hexmask.long.word 0xC 3.--11. 8. " WORDADDR5 ,Corrupted Word Address in the page between the 2560 byte and the 3071th bytes"
|
|
hexmask.long.byte 0xC 0.--2. 1. " BITADDR5 ,Corrupted Bit Address in the page between the 2560 byte and the 3071th bytes"
|
|
line.long 0x10 "ECC_PR6 ,ECC Parity Register 6 "
|
|
hexmask.long.word 0x10 12.--23. 1. " NPARITY6 ,Parity 6 "
|
|
hexmask.long.word 0x10 3.--11. 8. " WORDADDR6 ,Corrupted Word Address in the page between the 3072 byte and the 3583th bytes"
|
|
hexmask.long.byte 0x10 0.--2. 1. " BITADDR6 ,Corrupted Bit Address in the page between the 3072 byte and the 3583th bytes"
|
|
line.long 0x14 "ECC_PR7 ,ECC Parity Register 7 "
|
|
hexmask.long.word 0x14 12.--23. 1. " NPARITY7 ,Parity 7 "
|
|
hexmask.long.word 0x14 3.--11. 8. " WORDADDR7 ,Corrupted Word Address in the page between the 3584 byte and the 4095th bytes"
|
|
hexmask.long.byte 0x14 0.--2. 1. " BITADDR7 ,Corrupted Bit Address in the page between the 3584 byte and the 4095th bytes"
|
|
elif (((d.l(ad:(0xffffe200+0x4)))&0x30)==0x0)
|
|
rgroup.long 0x0C++0x07 "Registers for 1 ECC for a page"
|
|
line.long 0x00 "ECC_PR0,ECC Parity Register 0"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BITADDR ,Corrupted bit offset where an error occurred"
|
|
hexmask.long.word 0x00 4.--15. 10. " WORDADDR ,Word address where an error occurred"
|
|
line.long 0x04 "ECC_PR1,ECC Parity Register 1 "
|
|
hexmask.long.word 0x04 0.--15. 1. " NPARITY ,N PARITY Value"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Clock Generator"
|
|
base ad:0xfffffd50
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCKCR,Slow Clock Configuration Register"
|
|
bitfld.long 0x00 3. " OSCSEL ,Slow Clock Selector" "Internal RC,32768Hz oscillator"
|
|
bitfld.long 0x00 2. " OSC32BYP ,32768Hz Oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OSC32EN ,32768Hz Oscillator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCEN ,Internal RC" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xfffffc00
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PCK7_set/clr ,Programmable Clock 7 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PCK6_set/clr ,Programmable Clock 6 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PCK5_set/clr ,Programmable Clock 5 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PCK4_set/clr ,Programmable Clock 4 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PCK5_set/clr ,Programmable Clock 5 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK4_set/clr ,Programmable Clock 4 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PCK7_set/clr ,Programmable Clock 7 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " DDRCK_set/clr ,DDR Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Status" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Disable" "No effect,Disable"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (IRQ1) (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " VDEC_set/clr ,Video Decoder (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_set/clr ,High Speed Multimedia Card Interface 1 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " UDPHS_set/clr ,USB High Speed Device Port (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_set/clr ,Image Sensor Interface (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " EMAC_set/clr ,Ethernet MAC (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " AC97_set/clr ,AC97 Controller (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDC_set/clr ,LCD Controller (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMA_set/clr ,DMA Controller (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TSADCC_set/clr ,Touch Screen ADC Controller (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PWMC_set/clr ,Pulse Width Modulation Controller (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TC0-5_set/clr ,Timer Counter 0/1/2/3/4/5 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SSC1_set/clr ,Synchronous Serial Controller 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SSC0_set/clr ,Synchronous Serial Controller 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_set/clr ,Serial Peripheral Interface (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI0_set/clr ,Serial Peripheral Interface (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " MCI0_set/clr ,High Speed Multimedia Card Interface 0 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " US3_set/clr ,USART 3 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " US2_set/clr ,USART 2 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " US1_set/clr ,USART 1 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " US0_set/clr ,USART 0 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TRNG_set/clr ,True Random Number Generator (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PIOD/PIOE_set/clr ,Parallel I/O Controller D/E (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 28.--31. " BIASCOUNT , UTMI BIAS Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24. " BIASEN , UTMI BIAS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT , UTMI PLL Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " UPLLEN , UTMI PLL Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MOR,Main Oscillator Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " OSCOUNT ,Main Oscillator Start-up Time"
|
|
bitfld.long 0x04 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range (CPLLA = 0/CPLLA = 1)" "745-800MHz/545-600MHz,695-750 MHz/495-550MHz,645-700 MHz/445-500 MHz,595-650 MHz/400-450 MHz"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB OHCI Clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0. " USBS ,USB OHCI Input clock selection" "PLLA,UPLL"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 12. " PLLADIV2 ,Processor Clock Division" "Clock,Clock/2"
|
|
bitfld.long 0x00 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,Clock/3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 8. " SLCKMCK ,Slow Clock or Master Clock Selection" "Slow,Master"
|
|
bitfld.long 0x0 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLLCK"
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 8. " SLCKMCK ,Slow Clock or Master Clock Selection" "Slow,Master"
|
|
bitfld.long 0x4 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLLCK"
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 11. -0xc 11. -0x8 11. " PCK5 ,Programmable Clock Output 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCK4 ,Programmable Clock Output 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
textline ""
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0xc 6. -0x8 6. " LOCKU_set/clr ,UTMI PLL Lock Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
bitfld.long 0x00 11. " PCK5 ,Programmable Clock Output 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PCK4 ,Programmable Clock Output 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOCKU ,UTMI PLL Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized"
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "PMC_PLLICPR,PLL Charge Pump Current Register"
|
|
bitfld.long 0x00 0. " ICPLLA ,Charge Pump Current" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "AIC (Advanced Interrupt Controller)"
|
|
base ad:0xfffff000
|
|
width 11.
|
|
tree "Source Mode Registers"
|
|
group.long 0x00++0x7f
|
|
line.long 0x0 "AIC_SMR0,AIC Source Mode Register 0"
|
|
bitfld.long 0x0 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
line.long 0x4 "AIC_SMR1,AIC Source Mode Register 1"
|
|
bitfld.long 0x4 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x8 "AIC_SMR2,AIC Source Mode Register 2"
|
|
bitfld.long 0x8 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x8 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0xC "AIC_SMR3,AIC Source Mode Register 3"
|
|
bitfld.long 0xC 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0xC 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x10 "AIC_SMR4,AIC Source Mode Register 4"
|
|
bitfld.long 0x10 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x10 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x14 "AIC_SMR5,AIC Source Mode Register 5"
|
|
bitfld.long 0x14 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x14 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x18 "AIC_SMR6,AIC Source Mode Register 6"
|
|
bitfld.long 0x18 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x18 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x1C "AIC_SMR7,AIC Source Mode Register 7"
|
|
bitfld.long 0x1C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x1C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x20 "AIC_SMR8,AIC Source Mode Register 8"
|
|
bitfld.long 0x20 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x20 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x24 "AIC_SMR9,AIC Source Mode Register 9"
|
|
bitfld.long 0x24 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x24 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x28 "AIC_SMR10,AIC Source Mode Register 10"
|
|
bitfld.long 0x28 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x28 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x2C "AIC_SMR11,AIC Source Mode Register 11"
|
|
bitfld.long 0x2C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x2C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x30 "AIC_SMR12,AIC Source Mode Register 12"
|
|
bitfld.long 0x30 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x30 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x34 "AIC_SMR13,AIC Source Mode Register 13"
|
|
bitfld.long 0x34 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x34 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x38 "AIC_SMR14,AIC Source Mode Register 14"
|
|
bitfld.long 0x38 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x38 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x3C "AIC_SMR15,AIC Source Mode Register 15"
|
|
bitfld.long 0x3C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x3C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x40 "AIC_SMR16,AIC Source Mode Register 16"
|
|
bitfld.long 0x40 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x40 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x44 "AIC_SMR17,AIC Source Mode Register 17"
|
|
bitfld.long 0x44 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x44 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x48 "AIC_SMR18,AIC Source Mode Register 18"
|
|
bitfld.long 0x48 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x48 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x4C "AIC_SMR19,AIC Source Mode Register 19"
|
|
bitfld.long 0x4C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x50 "AIC_SMR20,AIC Source Mode Register 20"
|
|
bitfld.long 0x50 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x50 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x54 "AIC_SMR21,AIC Source Mode Register 21"
|
|
bitfld.long 0x54 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x54 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x58 "AIC_SMR22,AIC Source Mode Register 22"
|
|
bitfld.long 0x58 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x58 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x5C "AIC_SMR23,AIC Source Mode Register 23"
|
|
bitfld.long 0x5C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x5C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x60 "AIC_SMR24,AIC Source Mode Register 24"
|
|
bitfld.long 0x60 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x60 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x64 "AIC_SMR25,AIC Source Mode Register 25"
|
|
bitfld.long 0x64 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x64 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x68 "AIC_SMR26,AIC Source Mode Register 26"
|
|
bitfld.long 0x68 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x68 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x6C "AIC_SMR27,AIC Source Mode Register 27"
|
|
bitfld.long 0x6C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x6C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x70 "AIC_SMR28,AIC Source Mode Register 28"
|
|
bitfld.long 0x70 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x70 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x74 "AIC_SMR29,AIC Source Mode Register 29"
|
|
bitfld.long 0x74 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x74 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x78 "AIC_SMR30,AIC Source Mode Register 30"
|
|
bitfld.long 0x78 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x78 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x7C "AIC_SMR31,AIC Source Mode Register 31"
|
|
bitfld.long 0x7C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x7C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
tree.end
|
|
tree "Source Vector Registers"
|
|
group.long 0x80++0x7f
|
|
textline ""
|
|
line.long 0x0 "AIC_SVR0 ,AIC Source Vector Register 0 "
|
|
textline ""
|
|
line.long 0x4 "AIC_SVR1 ,AIC Source Vector Register 1 "
|
|
textline ""
|
|
line.long 0x8 "AIC_SVR2 ,AIC Source Vector Register 2 "
|
|
textline ""
|
|
line.long 0xC "AIC_SVR3 ,AIC Source Vector Register 3 "
|
|
textline ""
|
|
line.long 0x10 "AIC_SVR4 ,AIC Source Vector Register 4 "
|
|
textline ""
|
|
line.long 0x14 "AIC_SVR5 ,AIC Source Vector Register 5 "
|
|
textline ""
|
|
line.long 0x18 "AIC_SVR6 ,AIC Source Vector Register 6 "
|
|
textline ""
|
|
line.long 0x1C "AIC_SVR7 ,AIC Source Vector Register 7 "
|
|
textline ""
|
|
line.long 0x20 "AIC_SVR8 ,AIC Source Vector Register 8 "
|
|
textline ""
|
|
line.long 0x24 "AIC_SVR9 ,AIC Source Vector Register 9 "
|
|
textline ""
|
|
line.long 0x28 "AIC_SVR10,AIC Source Vector Register 10"
|
|
textline ""
|
|
line.long 0x2C "AIC_SVR11,AIC Source Vector Register 11"
|
|
textline ""
|
|
line.long 0x30 "AIC_SVR12,AIC Source Vector Register 12"
|
|
textline ""
|
|
line.long 0x34 "AIC_SVR13,AIC Source Vector Register 13"
|
|
textline ""
|
|
line.long 0x38 "AIC_SVR14,AIC Source Vector Register 14"
|
|
textline ""
|
|
line.long 0x3C "AIC_SVR15,AIC Source Vector Register 15"
|
|
textline ""
|
|
line.long 0x40 "AIC_SVR16,AIC Source Vector Register 16"
|
|
textline ""
|
|
line.long 0x44 "AIC_SVR17,AIC Source Vector Register 17"
|
|
textline ""
|
|
line.long 0x48 "AIC_SVR18,AIC Source Vector Register 18"
|
|
textline ""
|
|
line.long 0x4C "AIC_SVR19,AIC Source Vector Register 19"
|
|
textline ""
|
|
line.long 0x50 "AIC_SVR20,AIC Source Vector Register 20"
|
|
textline ""
|
|
line.long 0x54 "AIC_SVR21,AIC Source Vector Register 21"
|
|
textline ""
|
|
line.long 0x58 "AIC_SVR22,AIC Source Vector Register 22"
|
|
textline ""
|
|
line.long 0x5C "AIC_SVR23,AIC Source Vector Register 23"
|
|
textline ""
|
|
line.long 0x60 "AIC_SVR24,AIC Source Vector Register 24"
|
|
textline ""
|
|
line.long 0x64 "AIC_SVR25,AIC Source Vector Register 25"
|
|
textline ""
|
|
line.long 0x68 "AIC_SVR26,AIC Source Vector Register 26"
|
|
textline ""
|
|
line.long 0x6C "AIC_SVR27,AIC Source Vector Register 27"
|
|
textline ""
|
|
line.long 0x70 "AIC_SVR28,AIC Source Vector Register 28"
|
|
textline ""
|
|
line.long 0x74 "AIC_SVR29,AIC Source Vector Register 29"
|
|
textline ""
|
|
line.long 0x78 "AIC_SVR30,AIC Source Vector Register 30"
|
|
textline ""
|
|
line.long 0x7C "AIC_SVR31,AIC Source Vector Register 31"
|
|
tree.end
|
|
textline " "
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x00 "AIC_IVR,AIC Interrupt Vector Register"
|
|
line.long 0x04 "AIC_FVR,AIC FIQ Vector Register"
|
|
line.long 0x08 "AIC_ISR,AIC Interrupt Status Register"
|
|
bitfld.long 0x08 0.--4. " IRQID ,Current Interrupt Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x07
|
|
line.long 0x0 "AIC_IPR,AIC Interrupt Pending Register"
|
|
setclrfld.long 0x0 31. 0x20 31. 0x1C 31. " PID31_set/clr ,Interrupt 31 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 30. 0x20 30. 0x1C 30. " PID30_set/clr ,Interrupt 30 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x20 29. 0x1C 29. " PID29_set/clr ,Interrupt 29 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 28. 0x20 28. 0x1C 28. " PID28_set/clr ,Interrupt 28 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x20 27. 0x1C 27. " PID27_set/clr ,Interrupt 27 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 26. 0x20 26. 0x1C 26. " PID26_set/clr ,Interrupt 26 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x20 25. 0x1C 25. " PID25_set/clr ,Interrupt 25 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 24. 0x20 24. 0x1C 24. " PID24_set/clr ,Interrupt 24 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x20 23. 0x1C 23. " PID23_set/clr ,Interrupt 23 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 22. 0x20 22. 0x1C 22. " PID22_set/clr ,Interrupt 22 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x20 21. 0x1C 21. " PID21_set/clr ,Interrupt 21 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 20. 0x20 20. 0x1C 20. " PID20_set/clr ,Interrupt 20 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x20 19. 0x1C 19. " PID19_set/clr ,Interrupt 19 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 18. 0x20 18. 0x1C 18. " PID18_set/clr ,Interrupt 18 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x20 17. 0x1C 17. " PID17_set/clr ,Interrupt 17 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 16. 0x20 16. 0x1C 16. " PID16_set/clr ,Interrupt 16 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x20 15. 0x1C 15. " PID15_set/clr ,Interrupt 15 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 14. 0x20 14. 0x1C 14. " PID14_set/clr ,Interrupt 14 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x20 13. 0x1C 13. " PID13_set/clr ,Interrupt 13 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 12. 0x20 12. 0x1C 12. " PID12_set/clr ,Interrupt 12 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x20 11. 0x1C 11. " PID11_set/clr ,Interrupt 11 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 10. 0x20 10. 0x1C 10. " PID10_set/clr ,Interrupt 10 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x20 9. 0x1C 9. " PID9_set/clr ,Interrupt 9 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 8. 0x20 8. 0x1C 8. " PID8_set/clr ,Interrupt 8 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x20 7. 0x1C 7. " PID7_set/clr ,Interrupt 7 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 6. 0x20 6. 0x1C 6. " PID6_set/clr ,Interrupt 6 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x20 5. 0x1C 5. " PID5_set/clr ,Interrupt 5 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 4. 0x20 4. 0x1C 4. " PID4_set/clr ,Interrupt 4 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x20 3. 0x1C 3. " PID3_set/clr ,Interrupt 3 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 2. 0x20 2. 0x1C 2. " PID2_set/clr ,Interrupt 2 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x20 1. 0x1C 1. " SYS_set/clr ,SYS Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 0. 0x20 0. 0x1C 0. " FIQ_set/clr ,FIQ Interrupt Pending" "Not pending,Pending"
|
|
line.long 0x4 "AIC_IMR,AIC Interrupt Mask Register"
|
|
setclrfld.long 0x4 31. 0x14 31. 0x18 31. " PID31_set/clr ,Interrupt 31 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 30. 0x14 30. 0x18 30. " PID30_set/clr ,Interrupt 30 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 29. 0x14 29. 0x18 29. " PID29_set/clr ,Interrupt 29 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 28. 0x14 28. 0x18 28. " PID28_set/clr ,Interrupt 28 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 27. 0x14 27. 0x18 27. " PID27_set/clr ,Interrupt 27 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 26. 0x14 26. 0x18 26. " PID26_set/clr ,Interrupt 26 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 25. 0x14 25. 0x18 25. " PID25_set/clr ,Interrupt 25 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 24. 0x14 24. 0x18 24. " PID24_set/clr ,Interrupt 24 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 23. 0x14 23. 0x18 23. " PID23_set/clr ,Interrupt 23 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 22. 0x14 22. 0x18 22. " PID22_set/clr ,Interrupt 22 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 21. 0x14 21. 0x18 21. " PID21_set/clr ,Interrupt 21 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 20. 0x14 20. 0x18 20. " PID20_set/clr ,Interrupt 20 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 19. 0x14 19. 0x18 19. " PID19_set/clr ,Interrupt 19 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 18. 0x14 18. 0x18 18. " PID18_set/clr ,Interrupt 18 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 17. 0x14 17. 0x18 17. " PID17_set/clr ,Interrupt 17 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 16. 0x14 16. 0x18 16. " PID16_set/clr ,Interrupt 16 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 15. 0x14 15. 0x18 15. " PID15_set/clr ,Interrupt 15 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 14. 0x14 14. 0x18 14. " PID14_set/clr ,Interrupt 14 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 13. 0x14 13. 0x18 13. " PID13_set/clr ,Interrupt 13 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 12. 0x14 12. 0x18 12. " PID12_set/clr ,Interrupt 12 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 11. 0x14 11. 0x18 11. " PID11_set/clr ,Interrupt 11 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 10. 0x14 10. 0x18 10. " PID10_set/clr ,Interrupt 10 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 9. 0x14 9. 0x18 9. " PID9_set/clr ,Interrupt 9 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 8. 0x14 8. 0x18 8. " PID8_set/clr ,Interrupt 8 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 7. 0x14 7. 0x18 7. " PID7_set/clr ,Interrupt 7 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 6. 0x14 6. 0x18 6. " PID6_set/clr ,Interrupt 6 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 5. 0x14 5. 0x18 5. " PID5_set/clr ,Interrupt 5 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 4. 0x14 4. 0x18 4. " PID4_set/clr ,Interrupt 4 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 3. 0x14 3. 0x18 3. " PID3_set/clr ,Interrupt 3 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 2. 0x14 2. 0x18 2. " PID2_set/clr ,Interrupt 2 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 1. 0x14 1. 0x18 1. " SYS_set/clr ,SYS Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 0. 0x14 0. 0x18 0. " FIQ_set/clr ,FIQ Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x0 "AIC_CISR,AIC Core Interrupt Status Register"
|
|
bitfld.long 0x0 1. " NIRQ ,NIRQ Status" "Deactivated,Activated"
|
|
bitfld.long 0x0 0. " NFIQ ,NFIQ Status" "Deactivated,Activated"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x0 "AIC_EOICR,AIC End of Interrupt Command Register"
|
|
group.long 0x134++0x07
|
|
line.long 0x00 "AIC_SPU,AIC Spurious Interrupt Vector Register"
|
|
line.long 0x04 "AIC_DEBUG,AIC Debug Control Register"
|
|
bitfld.long 0x04 1. " GMSK ,General Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " PROT ,Protection Mode" "Disabled,Enabled"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "AIC_FFSR,Fast Forcing Status Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " PID31_set/clr ,Interrupt 31 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " PID30_set/clr ,Interrupt 30 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " PID29_set/clr ,Interrupt 29 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " PID28_set/clr ,Interrupt 28 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " PID27_set/clr ,Interrupt 27 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " PID26_set/clr ,Interrupt 26 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " PID25_set/clr ,Interrupt 25 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " PID24_set/clr ,Interrupt 24 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " PID23_set/clr ,Interrupt 23 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " PID22_set/clr ,Interrupt 22 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " PID21_set/clr ,Interrupt 21 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " PID20_set/clr ,Interrupt 20 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " PID19_set/clr ,Interrupt 19 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " PID18_set/clr ,Interrupt 18 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " PID17_set/clr ,Interrupt 17 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " PID16_set/clr ,Interrupt 16 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " PID15_set/clr ,Interrupt 15 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " PID14_set/clr ,Interrupt 14 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " PID13_set/clr ,Interrupt 13 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " PID12_set/clr ,Interrupt 12 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " PID11_set/clr ,Interrupt 11 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " PID10_set/clr ,Interrupt 10 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " PID9_set/clr ,Interrupt 9 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " PID8_set/clr ,Interrupt 8 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PID7_set/clr ,Interrupt 7 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " PID6_set/clr ,Interrupt 6 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " PID5_set/clr ,Interrupt 5 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " PID4_set/clr ,Interrupt 4 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " PID3_set/clr ,Interrupt 3 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " PID2_set/clr ,Interrupt 2 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " SYS_set/clr ,SYS Interrupt Fast Forcing Status" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "DBGU (Debug Unit)"
|
|
base ad:0xffffee00
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DBGU_CR,Debug Unit Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBGU_MR,Debug Unit Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,No parity,No parity"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DBGU_IMR,Debug Unit Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " COMMRX_set/clr ,Mask COMMRX Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " COMMTX_set/clr ,Mask COMMTX Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " RXBUFF_set/clr ,Mask RXBUFF Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " TXBUFE_set/clr ,Mask TXBUFE Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " TXEMPTY_set/clr ,Mask TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PARE_set/clr ,Mask Parity Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " FRAME_set/clr ,Mask Framing Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRE_set/clr ,Mask Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " ENDTX_set/clr ,Mask End of Transmit Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " ENDRX_set/clr ,Mask End of Receive Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXRDY_set/clr ,Disable TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RXRDY_set/clr ,Mask RXRDY Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x14--0x17
|
|
line.long 0x0 "DBGU_SR,Debug Unit Status Register"
|
|
bitfld.long 0x0 31. " COMMRX ,Debug Communication Channel Read Status" "Inactive,Active"
|
|
bitfld.long 0x0 30. " COMMTX ,Debug Communication Channel Write Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 12. " RXBUFF ,Receive Buffer Full" "Inactive,Active"
|
|
bitfld.long 0x0 11. " TXBUFE ,Transmission Buffer Empty" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 7. " PARE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x0 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 4. " ENDTX ,End of Transmitter Transfer" "Inactive,Active"
|
|
bitfld.long 0x0 3. " ENDRX ,End of Receiver Transfer" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
hgroup.long 0x18--0x1B
|
|
hide.long 0x0 "DBGU_RHR,Debug Unit Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "DBGU_THR,Debug Unit Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DBGU_BRGR,Debug Unit Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "DBGU_CIDR,Debug Unit Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "Not extended,Extended"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMless/on-chip Flash,Embedded Flash,ROM and Embedded,SRAM em ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier"
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "Reserved,1K bytes,2K bytes,6K bytes,112K bytes,4K bytes,80K bytes,160K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,96K bytes,512K bytes"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "None,8K bytes,16K bytes,32K bytes,Reserved,64K bytes,Reserved,128K bytes,Reserved,256K bytes,512K bytes,Reserved,1024K bytes,Reserved,2048K bytes,?..."
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "None,8K bytes,16K bytes,32K bytes,Reserved,64K bytes,Reserved,128K bytes,Reserved,256K bytes,512K bytes,Reserved,1024K bytes,Reserved,2048K bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" "Reserved,ARM946ES,ARM7TDMI,Reserved,ARM920T,ARM926EJS,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Version of the Device"
|
|
line.long 0x4 "DBGU_EXID,Debug Unit Chip ID Extension Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DBGU_FNR,Debug Unit Force NTRST Register"
|
|
bitfld.long 0x00 0. " FNTRST ,Force NTRST" "Power-on reset,Held low"
|
|
width 0xb
|
|
tree "PDC_DBGU"
|
|
base ad:0xffffee00
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "DBGU_RPR,Debug Unit Receive Pointer Register"
|
|
line.long 0x04 "DBGU_RCR,Debug Unit Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "DBGU_TPR,Debug Unit Transmit Pointer Register"
|
|
line.long 0x0c "DBGU_TCR,Debug Unit Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "DBGU_RNPR,Debug Unit Receive Next Pointer Register"
|
|
line.long 0x14 "DBGU_RNCR,Debug Unit Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "DBGU_TNPR,Debug Unit Transmit Next Pointer Register"
|
|
line.long 0x1c "DBGU_TNCR,Debug Unit Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "DBGU_PTCR,Debug Unit PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DBGU_PTSR,Debug Unit PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output Controller)"
|
|
tree "PIOA"
|
|
base ad:0xfffff200
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,PIO Status MCI1_CK/PCK0" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,PIO Status MCI1_DA7/ECOL" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,PIO Status MCI1_DA6/ECRS" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,PIO Status MCI1_DA5/ERXCK" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,PIO Status MCI1_DA4/ETXER" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,PIO Status MCI1_DA3/TIOB2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,PIO Status MCI1_DA2/PWM3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,PIO Status MCI1_DA1/CTS3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,PIO Status MCI1_DA0/RTS3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,PIO Status MCI1_CDA/SCK3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,PIO Status TWCK0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,PIO Status TWD0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,PIO Status EMDIO0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,PIO Status EMDC/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,PIO Status ETXCK/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,PIO Status ERXER/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,PIO Status ERXDV/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,PIO Status ERXEN/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,PIO Status ERX1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,PIO Status ERX0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,PIO Status ETX1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,PIO Status ETX0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,PIO Status MCI0_DA7/ERX3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,PIO Status MCI0_DA6/ERX2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,PIO Status MCI0_DA5/ETX3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,PIO Status MCI0_DA4/ETX2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,PIO Status MCI0_DA3/TIOB4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,PIO Status MCI0_DA2/TIOA4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,PIO Status MCI0_DA1/TCKL4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,PIO Status MCI0_DA0/TIOB3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,PIO Status MCI0_CDA/TIOA3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,PIO Status MCI0_CK/TCLK3" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,Output Status MCI1_CK/PCK0" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,Output Status MCI1_DA7/ECOL" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,Output Status MCI1_DA6/ECRS" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,Output Status MCI1_DA5/ERXCK" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,Output Status MCI1_DA4/ETXER" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,Output Status MCI1_DA3/TIOB2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,Output Status MCI1_DA2/PWM3" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,Output Status MCI1_DA1/CTS3" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,Output Status MCI1_DA0/RTS3" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,Output Status MCI1_CDA/SCK3" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,Output Status TWCK0/-" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,Output Status TWD0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,Output Status EMDIO0/-" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,Output Status EMDC/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,Output Status ETXCK/-" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,Output Status ERXER/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,Output Status ERXDV/-" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,Output Status ERXEN/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,Output Status ERX1/-" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,Output Status ERX0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,Output Status ETX1/-" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,Output Status ETX0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,Output Status MCI0_DA7/ERX3" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,Output Status MCI0_DA6/ERX2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,Output Status MCI0_DA5/ETX3" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,Output Status MCI0_DA4/ETX2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,Output Status MCI0_DA3/TIOB4" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,Output Status MCI0_DA2/TIOA4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,Output Status MCI0_DA1/TCKL4" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,Output Status MCI0_DA0/TIOB3" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,Output Status MCI0_CDA/TIOA3" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,Output Status MCI0_CK/TCLK3" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,Input Filter Status MCI1_CK/PCK0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,Input Filter Status MCI1_DA7/ECOL" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,Input Filter Status MCI1_DA6/ECRS" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,Input Filter Status MCI1_DA5/ERXCK" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,Input Filter Status MCI1_DA4/ETXER" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,Input Filter Status MCI1_DA3/TIOB2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,Input Filter Status MCI1_DA2/PWM3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,Input Filter Status MCI1_DA1/CTS3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,Input Filter Status MCI1_DA0/RTS3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,Input Filter Status MCI1_CDA/SCK3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,Input Filter Status TWCK0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,Input Filter Status TWD0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,Input Filter Status EMDIO0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,Input Filter Status EMDC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,Input Filter Status ETXCK/-" "Disabled,Enabled"
|
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setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,Input Filter Status ERXER/-" "Disabled,Enabled"
|
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textline " "
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,Input Filter Status ERXDV/-" "Disabled,Enabled"
|
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setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,Input Filter Status ERXEN/-" "Disabled,Enabled"
|
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textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,Input Filter Status ERX1/-" "Disabled,Enabled"
|
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setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,Input Filter Status ERX0/-" "Disabled,Enabled"
|
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textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,Input Filter Status ETX1/-" "Disabled,Enabled"
|
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setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,Input Filter Status ETX0/-" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,Input Filter Status MCI0_DA7/ERX3" "Disabled,Enabled"
|
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setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,Input Filter Status MCI0_DA6/ERX2" "Disabled,Enabled"
|
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textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,Input Filter Status MCI0_DA5/ETX3" "Disabled,Enabled"
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,Input Filter Status MCI0_DA4/ETX2" "Disabled,Enabled"
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textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,Input Filter Status MCI0_DA3/TIOB4" "Disabled,Enabled"
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setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,Input Filter Status MCI0_DA2/TIOA4" "Disabled,Enabled"
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textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,Input Filter Status MCI0_DA1/TCKL4" "Disabled,Enabled"
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,Input Filter Status MCI0_DA0/TIOB3" "Disabled,Enabled"
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textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,Input Filter Status MCI0_CDA/TIOA3" "Disabled,Enabled"
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,Input Filter Status MCI0_CK/TCLK3" "Disabled,Enabled"
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group.long 0x38++0x3
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line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
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setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,Output Data Status MCI1_CK/PCK0" "Low,High"
|
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setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,Output Data Status MCI1_DA7/ECOL" "Low,High"
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textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,Output Data Status MCI1_DA6/ECRS" "Low,High"
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setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,Output Data Status MCI1_DA5/ERXCK" "Low,High"
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textline " "
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setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,Output Data Status MCI1_DA4/ETXER" "Low,High"
|
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setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,Output Data Status MCI1_DA3/TIOB2" "Low,High"
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textline " "
|
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setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,Output Data Status MCI1_DA2/PWM3" "Low,High"
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setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,Output Data Status MCI1_DA1/CTS3" "Low,High"
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textline " "
|
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setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,Output Data Status MCI1_DA0/RTS3" "Low,High"
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setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,Output Data Status MCI1_CDA/SCK3" "Low,High"
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textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,Output Data Status TWCK0/-" "Low,High"
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,Output Data Status TWD0/-" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,Output Data Status EMDIO0/-" "Low,High"
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,Output Data Status EMDC/-" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,Output Data Status ETXCK/-" "Low,High"
|
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setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,Output Data Status ERXER/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,Output Data Status ERXDV/-" "Low,High"
|
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setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,Output Data Status ERXEN/-" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,Output Data Status ERX1/-" "Low,High"
|
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setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,Output Data Status ERX0/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,Output Data Status ETX1/-" "Low,High"
|
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setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,Output Data Status ETX0/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,Output Data Status MCI0_DA7/ERX3" "Low,High"
|
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setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,Output Data Status MCI0_DA6/ERX2" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,Output Data Status MCI0_DA5/ETX3" "Low,High"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,Output Data Status MCI0_DA4/ETX2" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,Output Data Status MCI0_DA3/TIOB4" "Low,High"
|
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setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,Output Data Status MCI0_DA2/TIOA4" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,Output Data Status MCI0_DA1/TCKL4" "Low,High"
|
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,Output Data Status MCI0_DA0/TIOB3" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,Output Data Status MCI0_CDA/TIOA3" "Low,High"
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,Output Data Status MCI0_CK/TCLK3" "Low,High"
|
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rgroup.long 0x3C++0x3
|
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line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
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bitfld.long 0x0 31. " MCI1_CK/PCK0 ,Output Data Status MCI1_CK/PCK0" "Low,High"
|
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bitfld.long 0x0 30. " MCI1_DA7/ECOL ,Output Data Status MCI1_DA7/ECOL" "Low,High"
|
|
bitfld.long 0x0 29. " MCI1_DA6/ECRS ,Output Data Status MCI1_DA6/ECRS" "Low,High"
|
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bitfld.long 0x0 28. " MCI1_DA5/ERXCK ,Output Data Status MCI1_DA5/ERXCK" "Low,High"
|
|
bitfld.long 0x0 27. " MCI1_DA4/ETXER ,Output Data Status MCI1_DA4/ETXER" "Low,High"
|
|
textline " "
|
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bitfld.long 0x0 26. " MCI1_DA3/TIOB2 ,Output Data Status MCI1_DA3/TIOB2" "Low,High"
|
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bitfld.long 0x0 25. " MCI1_DA2/PWM3 ,Output Data Status MCI1_DA2/PWM3" "Low,High"
|
|
bitfld.long 0x0 24. " MCI1_DA1/CTS3 ,Output Data Status MCI1_DA1/CTS3" "Low,High"
|
|
bitfld.long 0x0 23. " MCI1_DA0/RTS3 ,Output Data Status MCI1_DA0/RTS3" "Low,High"
|
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bitfld.long 0x0 22. " MCI1_CDA/SCK3 ,Output Data Status MCI1_CDA/SCK3" "Low,High"
|
|
textline " "
|
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bitfld.long 0x0 21. " TWCK0/- ,Output Data Status TWCK0/-" "Low,High"
|
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bitfld.long 0x0 20. " TWD0/- ,Output Data Status TWD0/-" "Low,High"
|
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bitfld.long 0x0 19. " EMDIO0/- ,Output Data Status EMDIO0/-" "Low,High"
|
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bitfld.long 0x0 18. " EMDC/- ,Output Data Status EMDC/-" "Low,High"
|
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bitfld.long 0x0 17. " ETXCK/- ,Output Data Status ETXCK/-" "Low,High"
|
|
textline " "
|
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bitfld.long 0x0 16. " ERXER/- ,Output Data Status ERXER/-" "Low,High"
|
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bitfld.long 0x0 15. " ERXDV/- ,Output Data Status ERXDV/-" "Low,High"
|
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bitfld.long 0x0 14. " ERXEN/- ,Output Data Status ERXEN/-" "Low,High"
|
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bitfld.long 0x0 13. " ERX1/- ,Output Data Status ERX1/-" "Low,High"
|
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bitfld.long 0x0 12. " ERX0/- ,Output Data Status ERX0/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " ETX1/- ,Output Data Status ETX1/-" "Low,High"
|
|
bitfld.long 0x0 10. " ETX0/- ,Output Data Status ETX0/-" "Low,High"
|
|
bitfld.long 0x0 9. " MCI0_DA7/ERX3 ,Output Data Status MCI0_DA7/ERX3" "Low,High"
|
|
bitfld.long 0x0 8. " MCI0_DA6/ERX2 ,Output Data Status MCI0_DA6/ERX2" "Low,High"
|
|
bitfld.long 0x0 7. " MCI0_DA5/ETX3 ,Output Data Status MCI0_DA5/ETX3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " MCI0_DA4/ETX2 ,Output Data Status MCI0_DA4/ETX2" "Low,High"
|
|
bitfld.long 0x0 5. " MCI0_DA3/TIOB4 ,Output Data Status MCI0_DA3/TIOB4" "Low,High"
|
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bitfld.long 0x0 4. " MCI0_DA2/TIOA4 ,Output Data Status MCI0_DA2/TIOA4" "Low,High"
|
|
bitfld.long 0x0 3. " MCI0_DA1/TCKL4 ,Output Data Status MCI0_DA1/TCKL4" "Low,High"
|
|
bitfld.long 0x0 2. " MCI0_DA0/TIOB3 ,Output Data Status MCI0_DA0/TIOB3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " MCI0_CDA/TIOA3 ,Output Data Status MCI0_CDA/TIOA3" "Low,High"
|
|
bitfld.long 0x0 0. " MCI0_CK/TCLK3 ,Output Data Status MCI0_CK/TCLK3" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,Input Change Interrupt Mask MCI1_CK/PCK0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,Input Change Interrupt Mask MCI1_DA7/ECOL" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,Input Change Interrupt Mask MCI1_DA6/ECRS" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,Input Change Interrupt Mask MCI1_DA5/ERXCK" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,Input Change Interrupt Mask MCI1_DA4/ETXER" "Disabled,Enabled"
|
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setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,Input Change Interrupt Mask MCI1_DA3/TIOB2" "Disabled,Enabled"
|
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textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,Input Change Interrupt Mask MCI1_DA2/PWM3" "Disabled,Enabled"
|
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setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,Input Change Interrupt Mask MCI1_DA1/CTS3" "Disabled,Enabled"
|
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textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,Input Change Interrupt Mask MCI1_DA0/RTS3" "Disabled,Enabled"
|
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setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,Input Change Interrupt Mask MCI1_CDA/SCK3" "Disabled,Enabled"
|
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textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,Input Change Interrupt Mask TWCK0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,Input Change Interrupt Mask TWD0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,Input Change Interrupt Mask EMDIO0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,Input Change Interrupt Mask EMDC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,Input Change Interrupt Mask ETXCK/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,Input Change Interrupt Mask ERXER/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,Input Change Interrupt Mask ERXDV/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,Input Change Interrupt Mask ERXEN/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,Input Change Interrupt Mask ERX1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,Input Change Interrupt Mask ERX0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,Input Change Interrupt Mask ETX1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,Input Change Interrupt Mask ETX0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,Input Change Interrupt Mask MCI0_DA7/ERX3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,Input Change Interrupt Mask MCI0_DA6/ERX2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,Input Change Interrupt Mask MCI0_DA5/ETX3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,Input Change Interrupt Mask MCI0_DA4/ETX2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,Input Change Interrupt Mask MCI0_DA3/TIOB4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,Input Change Interrupt Mask MCI0_DA2/TIOA4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,Input Change Interrupt Mask MCI0_DA1/TCKL4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,Input Change Interrupt Mask MCI0_DA0/TIOB3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,Input Change Interrupt Mask MCI0_CDA/TIOA3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,Input Change Interrupt Mask MCI0_CK/TCLK3" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,Multi Drive Status MCI1_CK/PCK0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,Multi Drive Status MCI1_DA7/ECOL" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,Multi Drive Status MCI1_DA6/ECRS" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,Multi Drive Status MCI1_DA5/ERXCK" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,Multi Drive Status MCI1_DA4/ETXER" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,Multi Drive Status MCI1_DA3/TIOB2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,Multi Drive Status MCI1_DA2/PWM3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,Multi Drive Status MCI1_DA1/CTS3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,Multi Drive Status MCI1_DA0/RTS3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,Multi Drive Status MCI1_CDA/SCK3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,Multi Drive Status TWCK0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,Multi Drive Status TWD0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,Multi Drive Status EMDIO0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,Multi Drive Status EMDC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,Multi Drive Status ETXCK/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,Multi Drive Status ERXER/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,Multi Drive Status ERXDV/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,Multi Drive Status ERXEN/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,Multi Drive Status ERX1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,Multi Drive Status ERX0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,Multi Drive Status ETX1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,Multi Drive Status ETX0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,Multi Drive Status MCI0_DA7/ERX3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,Multi Drive Status MCI0_DA6/ERX2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,Multi Drive Status MCI0_DA5/ETX3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,Multi Drive Status MCI0_DA4/ETX2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,Multi Drive Status MCI0_DA3/TIOB4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,Multi Drive Status MCI0_DA2/TIOA4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,Multi Drive Status MCI0_DA1/TCKL4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,Multi Drive Status MCI0_DA0/TIOB3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,Multi Drive Status MCI0_CDA/TIOA3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,Multi Drive Status MCI0_CK/TCLK3" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " MCI1_CK/PCK0_set/clr ,Pull Up Status MCI1_CK/PCK0" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " MCI1_DA7/ECOL_set/clr ,Pull Up Status MCI1_DA7/ECOL" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " MCI1_DA6/ECRS_set/clr ,Pull Up Status MCI1_DA6/ECRS" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " MCI1_DA5/ERXCK_set/clr ,Pull Up Status MCI1_DA5/ERXCK" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " MCI1_DA4/ETXER_set/clr ,Pull Up Status MCI1_DA4/ETXER" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " MCI1_DA3/TIOB2_set/clr ,Pull Up Status MCI1_DA3/TIOB2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " MCI1_DA2/PWM3_set/clr ,Pull Up Status MCI1_DA2/PWM3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " MCI1_DA1/CTS3_set/clr ,Pull Up Status MCI1_DA1/CTS3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " MCI1_DA0/RTS3_set/clr ,Pull Up Status MCI1_DA0/RTS3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " MCI1_CDA/SCK3_set/clr ,Pull Up Status MCI1_CDA/SCK3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " TWCK0/-_set/clr ,Pull Up Status TWCK0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " TWD0/-_set/clr ,Pull Up Status TWD0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " EMDIO0/-_set/clr ,Pull Up Status EMDIO0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " EMDC/-_set/clr ,Pull Up Status EMDC/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " ETXCK/-_set/clr ,Pull Up Status ETXCK/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " ERXER/-_set/clr ,Pull Up Status ERXER/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " ERXDV/-_set/clr ,Pull Up Status ERXDV/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " ERXEN/-_set/clr ,Pull Up Status ERXEN/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " ERX1/-_set/clr ,Pull Up Status ERX1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " ERX0/-_set/clr ,Pull Up Status ERX0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " ETX1/-_set/clr ,Pull Up Status ETX1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " ETX0/-_set/clr ,Pull Up Status ETX0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " MCI0_DA7/ERX3_set/clr ,Pull Up Status MCI0_DA7/ERX3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " MCI0_DA6/ERX2_set/clr ,Pull Up Status MCI0_DA6/ERX2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " MCI0_DA5/ETX3_set/clr ,Pull Up Status MCI0_DA5/ETX3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " MCI0_DA4/ETX2_set/clr ,Pull Up Status MCI0_DA4/ETX2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " MCI0_DA3/TIOB4_set/clr ,Pull Up Status MCI0_DA3/TIOB4" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " MCI0_DA2/TIOA4_set/clr ,Pull Up Status MCI0_DA2/TIOA4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " MCI0_DA1/TCKL4_set/clr ,Pull Up Status MCI0_DA1/TCKL4" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " MCI0_DA0/TIOB3_set/clr ,Pull Up Status MCI0_DA0/TIOB3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " MCI0_CDA/TIOA3_set/clr ,Pull Up Status MCI0_CDA/TIOA3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " MCI0_CK/TCLK3_set/clr ,Pull Up Status MCI0_CK/TCLK3" "Enabled,Disabled"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " MCI1_CK/PCK0_set/clr ,Peripheral A B Status MCI1_CK/PCK0" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " MCI1_DA7/ECOL_set/clr ,Peripheral A B Status MCI1_DA7/ECOL" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " MCI1_DA6/ECRS_set/clr ,Peripheral A B Status MCI1_DA6/ECRS" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " MCI1_DA5/ERXCK_set/clr ,Peripheral A B Status MCI1_DA5/ERXCK" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " MCI1_DA4/ETXER_set/clr ,Peripheral A B Status MCI1_DA4/ETXER" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " MCI1_DA3/TIOB2_set/clr ,Peripheral A B Status MCI1_DA3/TIOB2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " MCI1_DA2/PWM3_set/clr ,Peripheral A B Status MCI1_DA2/PWM3" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " MCI1_DA1/CTS3_set/clr ,Peripheral A B Status MCI1_DA1/CTS3" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " MCI1_DA0/RTS3_set/clr ,Peripheral A B Status MCI1_DA0/RTS3" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " MCI1_CDA/SCK3_set/clr ,Peripheral A B Status MCI1_CDA/SCK3" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " TWCK0/-_set/clr ,Peripheral A B Status TWCK0/-" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " TWD0/-_set/clr ,Peripheral A B Status TWD0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " EMDIO0/-_set/clr ,Peripheral A B Status EMDIO0/-" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " EMDC/-_set/clr ,Peripheral A B Status EMDC/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " ETXCK/-_set/clr ,Peripheral A B Status ETXCK/-" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " ERXER/-_set/clr ,Peripheral A B Status ERXER/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " ERXDV/-_set/clr ,Peripheral A B Status ERXDV/-" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " ERXEN/-_set/clr ,Peripheral A B Status ERXEN/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " ERX1/-_set/clr ,Peripheral A B Status ERX1/-" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " ERX0/-_set/clr ,Peripheral A B Status ERX0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " ETX1/-_set/clr ,Peripheral A B Status ETX1/-" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " ETX0/-_set/clr ,Peripheral A B Status ETX0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " MCI0_DA7/ERX3_set/clr ,Peripheral A B Status MCI0_DA7/ERX3" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " MCI0_DA6/ERX2_set/clr ,Peripheral A B Status MCI0_DA6/ERX2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " MCI0_DA5/ETX3_set/clr ,Peripheral A B Status MCI0_DA5/ETX3" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " MCI0_DA4/ETX2_set/clr ,Peripheral A B Status MCI0_DA4/ETX2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " MCI0_DA3/TIOB4_set/clr ,Peripheral A B Status MCI0_DA3/TIOB4" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " MCI0_DA2/TIOA4_set/clr ,Peripheral A B Status MCI0_DA2/TIOA4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " MCI0_DA1/TCKL4_set/clr ,Peripheral A B Status MCI0_DA1/TCKL4" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " MCI0_DA0/TIOB3_set/clr ,Peripheral A B Status MCI0_DA0/TIOB3" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " MCI0_CDA/TIOA3_set/clr ,Peripheral A B Status MCI0_CDA/TIOA3" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " MCI0_CK/TCLK3_set/clr ,Peripheral A B Status MCI0_CK/TCLK3" "A,B"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " MCI1_CK/PCK0_set/clr ,Output Write Status MCI1_CK/PCK0" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " MCI1_DA7/ECOL_set/clr ,Output Write Status MCI1_DA7/ECOL" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_DA6/ECRS_set/clr ,Output Write Status MCI1_DA6/ECRS" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " MCI1_DA5/ERXCK_set/clr ,Output Write Status MCI1_DA5/ERXCK" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " MCI1_DA4/ETXER_set/clr ,Output Write Status MCI1_DA4/ETXER" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " MCI1_DA3/TIOB2_set/clr ,Output Write Status MCI1_DA3/TIOB2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " MCI1_DA2/PWM3_set/clr ,Output Write Status MCI1_DA2/PWM3" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MCI1_DA1/CTS3_set/clr ,Output Write Status MCI1_DA1/CTS3" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " MCI1_DA0/RTS3_set/clr ,Output Write Status MCI1_DA0/RTS3" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " MCI1_CDA/SCK3_set/clr ,Output Write Status MCI1_CDA/SCK3" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TWCK0/-_set/clr ,Output Write Status TWCK0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TWD0/-_set/clr ,Output Write Status TWD0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " EMDIO0/-_set/clr ,Output Write Status EMDIO0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " EMDC/-_set/clr ,Output Write Status EMDC/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " ETXCK/-_set/clr ,Output Write Status ETXCK/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " ERXER/-_set/clr ,Output Write Status ERXER/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " ERXDV/-_set/clr ,Output Write Status ERXDV/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " ERXEN/-_set/clr ,Output Write Status ERXEN/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ERX1/-_set/clr ,Output Write Status ERX1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ERX0/-_set/clr ,Output Write Status ERX0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " ETX1/-_set/clr ,Output Write Status ETX1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ETX0/-_set/clr ,Output Write Status ETX0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " MCI0_DA7/ERX3_set/clr ,Output Write Status MCI0_DA7/ERX3" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " MCI0_DA6/ERX2_set/clr ,Output Write Status MCI0_DA6/ERX2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " MCI0_DA5/ETX3_set/clr ,Output Write Status MCI0_DA5/ETX3" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " MCI0_DA4/ETX2_set/clr ,Output Write Status MCI0_DA4/ETX2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " MCI0_DA3/TIOB4_set/clr ,Output Write Status MCI0_DA3/TIOB4" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " MCI0_DA2/TIOA4_set/clr ,Output Write Status MCI0_DA2/TIOA4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " MCI0_DA1/TCKL4_set/clr ,Output Write Status MCI0_DA1/TCKL4" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " MCI0_DA0/TIOB3_set/clr ,Output Write Status MCI0_DA0/TIOB3" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " MCI0_CDA/TIOA3_set/clr ,Output Write Status MCI0_CDA/TIOA3" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " MCI0_CK/TCLK3_set/clr ,Output Write Status MCI0_CK/TCLK3" "Not affected,Affected"
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xfffff400
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,PIO Status ISI_MCK/PCK1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,PIO Status ISI_HSYNC/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,PIO Status ISI_VSYNC/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,PIO Status ISI_PCK/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,PIO Status ISI_D7/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,PIO Status ISI_D6/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,PIO Status ISI_D5/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,PIO Status ISI_D4/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,PIO Status ISI_D3/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,PIO Status ISI_D2/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,PIO Status ISI_D1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,PIO Status ISI_D0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,PIO Status TXD0/SPI0_NPCS2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,PIO Status RXD0/SPI0_NPCS1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,PIO Status SPI1_NPCS0/RTS0" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,PIO Status SPI1_SPCK/SCK0" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,PIO Status SPI1_MOSI/CTS0" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,PIO Status SPI1_MISO/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,PIO Status DTXD/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,PIO Status DRXD/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,PIO Status TWCK1/ISI_D11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,PIO Status TWD1/ISI_D10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,PIO Status RXD3/ISI_D9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,PIO Status TXD3/ISI_D8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,PIO Status RXD2/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,PIO Status TXD2/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,PIO Status RXD1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,PIO Status TXD1/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,PIO Status SPI0_NPCS0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,PIO Status SPI0_SPCK/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,PIO Status SPIO_MOSI/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,PIO Status SPI0_MISO/-" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,Output Status ISI_MCK/PCK1" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,Output Status ISI_HSYNC/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,Output Status ISI_VSYNC/-" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,Output Status ISI_PCK/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,Output Status ISI_D7/-" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,Output Status ISI_D6/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,Output Status ISI_D5/-" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,Output Status ISI_D4/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,Output Status ISI_D3/-" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,Output Status ISI_D2/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,Output Status ISI_D1/-" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,Output Status ISI_D0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,Output Status TXD0/SPI0_NPCS2" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,Output Status RXD0/SPI0_NPCS1" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,Output Status SPI1_NPCS0/RTS0" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,Output Status SPI1_SPCK/SCK0" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,Output Status SPI1_MOSI/CTS0" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,Output Status SPI1_MISO/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,Output Status DTXD/-" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,Output Status DRXD/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,Output Status TWCK1/ISI_D11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,Output Status TWD1/ISI_D10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,Output Status RXD3/ISI_D9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,Output Status TXD3/ISI_D8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,Output Status RXD2/-" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,Output Status TXD2/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,Output Status RXD1/-" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,Output Status TXD1/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,Output Status SPI0_NPCS0/-" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,Output Status SPI0_SPCK/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,Output Status SPIO_MOSI/-" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,Output Status SPI0_MISO/-" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,Input Filter Status ISI_MCK/PCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,Input Filter Status ISI_HSYNC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,Input Filter Status ISI_VSYNC/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,Input Filter Status ISI_PCK/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,Input Filter Status ISI_D7/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,Input Filter Status ISI_D6/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,Input Filter Status ISI_D5/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,Input Filter Status ISI_D4/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,Input Filter Status ISI_D3/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,Input Filter Status ISI_D2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,Input Filter Status ISI_D1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,Input Filter Status ISI_D0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,Input Filter Status TXD0/SPI0_NPCS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,Input Filter Status RXD0/SPI0_NPCS1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,Input Filter Status SPI1_NPCS0/RTS0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,Input Filter Status SPI1_SPCK/SCK0" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,Input Filter Status SPI1_MOSI/CTS0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,Input Filter Status SPI1_MISO/-" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,Input Filter Status DTXD/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,Input Filter Status DRXD/-" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,Input Filter Status TWCK1/ISI_D11" "Disabled,Enabled"
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setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,Input Filter Status TWD1/ISI_D10" "Disabled,Enabled"
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textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,Input Filter Status RXD3/ISI_D9" "Disabled,Enabled"
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setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,Input Filter Status TXD3/ISI_D8" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,Input Filter Status RXD2/-" "Disabled,Enabled"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,Input Filter Status TXD2/-" "Disabled,Enabled"
|
|
textline " "
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,Input Filter Status RXD1/-" "Disabled,Enabled"
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setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,Input Filter Status TXD1/-" "Disabled,Enabled"
|
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textline " "
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,Input Filter Status SPI0_NPCS0/-" "Disabled,Enabled"
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,Input Filter Status SPI0_SPCK/-" "Disabled,Enabled"
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textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,Input Filter Status SPIO_MOSI/-" "Disabled,Enabled"
|
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,Input Filter Status SPI0_MISO/-" "Disabled,Enabled"
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group.long 0x38++0x3
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line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
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setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,Output Data Status ISI_MCK/PCK1" "Low,High"
|
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setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,Output Data Status ISI_HSYNC/-" "Low,High"
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textline " "
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,Output Data Status ISI_VSYNC/-" "Low,High"
|
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setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,Output Data Status ISI_PCK/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,Output Data Status ISI_D7/-" "Low,High"
|
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setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,Output Data Status ISI_D6/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,Output Data Status ISI_D5/-" "Low,High"
|
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setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,Output Data Status ISI_D4/-" "Low,High"
|
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textline " "
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setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,Output Data Status ISI_D3/-" "Low,High"
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setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,Output Data Status ISI_D2/-" "Low,High"
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textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,Output Data Status ISI_D1/-" "Low,High"
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,Output Data Status ISI_D0/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,Output Data Status TXD0/SPI0_NPCS2" "Low,High"
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,Output Data Status RXD0/SPI0_NPCS1" "Low,High"
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textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,Output Data Status SPI1_NPCS0/RTS0" "Low,High"
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setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,Output Data Status SPI1_SPCK/SCK0" "Low,High"
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textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,Output Data Status SPI1_MOSI/CTS0" "Low,High"
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setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,Output Data Status SPI1_MISO/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,Output Data Status DTXD/-" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,Output Data Status DRXD/-" "Low,High"
|
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textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,Output Data Status TWCK1/ISI_D11" "Low,High"
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setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,Output Data Status TWD1/ISI_D10" "Low,High"
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textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,Output Data Status RXD3/ISI_D9" "Low,High"
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setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,Output Data Status TXD3/ISI_D8" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,Output Data Status RXD2/-" "Low,High"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,Output Data Status TXD2/-" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,Output Data Status RXD1/-" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,Output Data Status TXD1/-" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,Output Data Status SPI0_NPCS0/-" "Low,High"
|
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,Output Data Status SPI0_SPCK/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,Output Data Status SPIO_MOSI/-" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,Output Data Status SPI0_MISO/-" "Low,High"
|
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rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " ISI_MCK/PCK1 ,Output Data Status ISI_MCK/PCK1" "Low,High"
|
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bitfld.long 0x0 30. " ISI_HSYNC/- ,Output Data Status ISI_HSYNC/-" "Low,High"
|
|
bitfld.long 0x0 29. " ISI_VSYNC/- ,Output Data Status ISI_VSYNC/-" "Low,High"
|
|
bitfld.long 0x0 28. " ISI_PCK/- ,Output Data Status ISI_PCK/-" "Low,High"
|
|
bitfld.long 0x0 27. " ISI_D7/- ,Output Data Status ISI_D7/-" "Low,High"
|
|
textline " "
|
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bitfld.long 0x0 26. " ISI_D6/- ,Output Data Status ISI_D6/-" "Low,High"
|
|
bitfld.long 0x0 25. " ISI_D5/- ,Output Data Status ISI_D5/-" "Low,High"
|
|
bitfld.long 0x0 24. " ISI_D4/- ,Output Data Status ISI_D4/-" "Low,High"
|
|
bitfld.long 0x0 23. " ISI_D3/- ,Output Data Status ISI_D3/-" "Low,High"
|
|
bitfld.long 0x0 22. " ISI_D2/- ,Output Data Status ISI_D2/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " ISI_D1/- ,Output Data Status ISI_D1/-" "Low,High"
|
|
bitfld.long 0x0 20. " ISI_D0/- ,Output Data Status ISI_D0/-" "Low,High"
|
|
bitfld.long 0x0 19. " TXD0/SPI0_NPCS2 ,Output Data Status TXD0/SPI0_NPCS2" "Low,High"
|
|
bitfld.long 0x0 18. " RXD0/SPI0_NPCS1 ,Output Data Status RXD0/SPI0_NPCS1" "Low,High"
|
|
bitfld.long 0x0 17. " SPI1_NPCS0/RTS0 ,Output Data Status SPI1_NPCS0/RTS0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " SPI1_SPCK/SCK0 ,Output Data Status SPI1_SPCK/SCK0" "Low,High"
|
|
bitfld.long 0x0 15. " SPI1_MOSI/CTS0 ,Output Data Status SPI1_MOSI/CTS0" "Low,High"
|
|
bitfld.long 0x0 14. " SPI1_MISO/- ,Output Data Status SPI1_MISO/-" "Low,High"
|
|
bitfld.long 0x0 13. " DTXD/- ,Output Data Status DTXD/-" "Low,High"
|
|
bitfld.long 0x0 12. " DRXD/- ,Output Data Status DRXD/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " TWCK1/ISI_D11 ,Output Data Status TWCK1/ISI_D11" "Low,High"
|
|
bitfld.long 0x0 10. " TWD1/ISI_D10 ,Output Data Status TWD1/ISI_D10" "Low,High"
|
|
bitfld.long 0x0 9. " RXD3/ISI_D9 ,Output Data Status RXD3/ISI_D9" "Low,High"
|
|
bitfld.long 0x0 8. " TXD3/ISI_D8 ,Output Data Status TXD3/ISI_D8" "Low,High"
|
|
bitfld.long 0x0 7. " RXD2/- ,Output Data Status RXD2/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " TXD2/- ,Output Data Status TXD2/-" "Low,High"
|
|
bitfld.long 0x0 5. " RXD1/- ,Output Data Status RXD1/-" "Low,High"
|
|
bitfld.long 0x0 4. " TXD1/- ,Output Data Status TXD1/-" "Low,High"
|
|
bitfld.long 0x0 3. " SPI0_NPCS0/- ,Output Data Status SPI0_NPCS0/-" "Low,High"
|
|
bitfld.long 0x0 2. " SPI0_SPCK/- ,Output Data Status SPI0_SPCK/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SPIO_MOSI/- ,Output Data Status SPIO_MOSI/-" "Low,High"
|
|
bitfld.long 0x0 0. " SPI0_MISO/- ,Output Data Status SPI0_MISO/-" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,Input Change Interrupt Mask ISI_MCK/PCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,Input Change Interrupt Mask ISI_HSYNC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,Input Change Interrupt Mask ISI_VSYNC/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,Input Change Interrupt Mask ISI_PCK/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,Input Change Interrupt Mask ISI_D7/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,Input Change Interrupt Mask ISI_D6/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,Input Change Interrupt Mask ISI_D5/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,Input Change Interrupt Mask ISI_D4/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,Input Change Interrupt Mask ISI_D3/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,Input Change Interrupt Mask ISI_D2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,Input Change Interrupt Mask ISI_D1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,Input Change Interrupt Mask ISI_D0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,Input Change Interrupt Mask TXD0/SPI0_NPCS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,Input Change Interrupt Mask RXD0/SPI0_NPCS1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,Input Change Interrupt Mask SPI1_NPCS0/RTS0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,Input Change Interrupt Mask SPI1_SPCK/SCK0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,Input Change Interrupt Mask SPI1_MOSI/CTS0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,Input Change Interrupt Mask SPI1_MISO/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,Input Change Interrupt Mask DTXD/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,Input Change Interrupt Mask DRXD/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,Input Change Interrupt Mask TWCK1/ISI_D11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,Input Change Interrupt Mask TWD1/ISI_D10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,Input Change Interrupt Mask RXD3/ISI_D9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,Input Change Interrupt Mask TXD3/ISI_D8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,Input Change Interrupt Mask RXD2/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,Input Change Interrupt Mask TXD2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,Input Change Interrupt Mask RXD1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,Input Change Interrupt Mask TXD1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,Input Change Interrupt Mask SPI0_NPCS0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,Input Change Interrupt Mask SPI0_SPCK/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,Input Change Interrupt Mask SPIO_MOSI/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,Input Change Interrupt Mask SPI0_MISO/-" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,Multi Drive Status ISI_MCK/PCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,Multi Drive Status ISI_HSYNC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,Multi Drive Status ISI_VSYNC/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,Multi Drive Status ISI_PCK/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,Multi Drive Status ISI_D7/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,Multi Drive Status ISI_D6/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,Multi Drive Status ISI_D5/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,Multi Drive Status ISI_D4/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,Multi Drive Status ISI_D3/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,Multi Drive Status ISI_D2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,Multi Drive Status ISI_D1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,Multi Drive Status ISI_D0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,Multi Drive Status TXD0/SPI0_NPCS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,Multi Drive Status RXD0/SPI0_NPCS1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,Multi Drive Status SPI1_NPCS0/RTS0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,Multi Drive Status SPI1_SPCK/SCK0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,Multi Drive Status SPI1_MOSI/CTS0" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,Multi Drive Status SPI1_MISO/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,Multi Drive Status DTXD/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,Multi Drive Status DRXD/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,Multi Drive Status TWCK1/ISI_D11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,Multi Drive Status TWD1/ISI_D10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,Multi Drive Status RXD3/ISI_D9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,Multi Drive Status TXD3/ISI_D8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,Multi Drive Status RXD2/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,Multi Drive Status TXD2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,Multi Drive Status RXD1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,Multi Drive Status TXD1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,Multi Drive Status SPI0_NPCS0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,Multi Drive Status SPI0_SPCK/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,Multi Drive Status SPIO_MOSI/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,Multi Drive Status SPI0_MISO/-" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " ISI_MCK/PCK1_set/clr ,Pull Up Status ISI_MCK/PCK1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " ISI_HSYNC/-_set/clr ,Pull Up Status ISI_HSYNC/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " ISI_VSYNC/-_set/clr ,Pull Up Status ISI_VSYNC/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " ISI_PCK/-_set/clr ,Pull Up Status ISI_PCK/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " ISI_D7/-_set/clr ,Pull Up Status ISI_D7/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " ISI_D6/-_set/clr ,Pull Up Status ISI_D6/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " ISI_D5/-_set/clr ,Pull Up Status ISI_D5/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " ISI_D4/-_set/clr ,Pull Up Status ISI_D4/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " ISI_D3/-_set/clr ,Pull Up Status ISI_D3/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " ISI_D2/-_set/clr ,Pull Up Status ISI_D2/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " ISI_D1/-_set/clr ,Pull Up Status ISI_D1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " ISI_D0/-_set/clr ,Pull Up Status ISI_D0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " TXD0/SPI0_NPCS2_set/clr ,Pull Up Status TXD0/SPI0_NPCS2" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " RXD0/SPI0_NPCS1_set/clr ,Pull Up Status RXD0/SPI0_NPCS1" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " SPI1_NPCS0/RTS0_set/clr ,Pull Up Status SPI1_NPCS0/RTS0" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " SPI1_SPCK/SCK0_set/clr ,Pull Up Status SPI1_SPCK/SCK0" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " SPI1_MOSI/CTS0_set/clr ,Pull Up Status SPI1_MOSI/CTS0" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " SPI1_MISO/-_set/clr ,Pull Up Status SPI1_MISO/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " DTXD/-_set/clr ,Pull Up Status DTXD/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " DRXD/-_set/clr ,Pull Up Status DRXD/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " TWCK1/ISI_D11_set/clr ,Pull Up Status TWCK1/ISI_D11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " TWD1/ISI_D10_set/clr ,Pull Up Status TWD1/ISI_D10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " RXD3/ISI_D9_set/clr ,Pull Up Status RXD3/ISI_D9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " TXD3/ISI_D8_set/clr ,Pull Up Status TXD3/ISI_D8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " RXD2/-_set/clr ,Pull Up Status RXD2/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " TXD2/-_set/clr ,Pull Up Status TXD2/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " RXD1/-_set/clr ,Pull Up Status RXD1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " TXD1/-_set/clr ,Pull Up Status TXD1/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " SPI0_NPCS0/-_set/clr ,Pull Up Status SPI0_NPCS0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " SPI0_SPCK/-_set/clr ,Pull Up Status SPI0_SPCK/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " SPIO_MOSI/-_set/clr ,Pull Up Status SPIO_MOSI/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " SPI0_MISO/-_set/clr ,Pull Up Status SPI0_MISO/-" "Enabled,Disabled"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " ISI_MCK/PCK1_set/clr ,Peripheral A B Status ISI_MCK/PCK1" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " ISI_HSYNC/-_set/clr ,Peripheral A B Status ISI_HSYNC/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " ISI_VSYNC/-_set/clr ,Peripheral A B Status ISI_VSYNC/-" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " ISI_PCK/-_set/clr ,Peripheral A B Status ISI_PCK/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " ISI_D7/-_set/clr ,Peripheral A B Status ISI_D7/-" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " ISI_D6/-_set/clr ,Peripheral A B Status ISI_D6/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " ISI_D5/-_set/clr ,Peripheral A B Status ISI_D5/-" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " ISI_D4/-_set/clr ,Peripheral A B Status ISI_D4/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " ISI_D3/-_set/clr ,Peripheral A B Status ISI_D3/-" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " ISI_D2/-_set/clr ,Peripheral A B Status ISI_D2/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " ISI_D1/-_set/clr ,Peripheral A B Status ISI_D1/-" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " ISI_D0/-_set/clr ,Peripheral A B Status ISI_D0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " TXD0/SPI0_NPCS2_set/clr ,Peripheral A B Status TXD0/SPI0_NPCS2" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " RXD0/SPI0_NPCS1_set/clr ,Peripheral A B Status RXD0/SPI0_NPCS1" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " SPI1_NPCS0/RTS0_set/clr ,Peripheral A B Status SPI1_NPCS0/RTS0" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " SPI1_SPCK/SCK0_set/clr ,Peripheral A B Status SPI1_SPCK/SCK0" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " SPI1_MOSI/CTS0_set/clr ,Peripheral A B Status SPI1_MOSI/CTS0" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " SPI1_MISO/-_set/clr ,Peripheral A B Status SPI1_MISO/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " DTXD/-_set/clr ,Peripheral A B Status DTXD/-" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " DRXD/-_set/clr ,Peripheral A B Status DRXD/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " TWCK1/ISI_D11_set/clr ,Peripheral A B Status TWCK1/ISI_D11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " TWD1/ISI_D10_set/clr ,Peripheral A B Status TWD1/ISI_D10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " RXD3/ISI_D9_set/clr ,Peripheral A B Status RXD3/ISI_D9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " TXD3/ISI_D8_set/clr ,Peripheral A B Status TXD3/ISI_D8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " RXD2/-_set/clr ,Peripheral A B Status RXD2/-" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " TXD2/-_set/clr ,Peripheral A B Status TXD2/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " RXD1/-_set/clr ,Peripheral A B Status RXD1/-" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " TXD1/-_set/clr ,Peripheral A B Status TXD1/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " SPI0_NPCS0/-_set/clr ,Peripheral A B Status SPI0_NPCS0/-" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " SPI0_SPCK/-_set/clr ,Peripheral A B Status SPI0_SPCK/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " SPIO_MOSI/-_set/clr ,Peripheral A B Status SPIO_MOSI/-" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " SPI0_MISO/-_set/clr ,Peripheral A B Status SPI0_MISO/-" "A,B"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " ISI_MCK/PCK1_set/clr ,Output Write Status ISI_MCK/PCK1" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " ISI_HSYNC/-_set/clr ,Output Write Status ISI_HSYNC/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " ISI_VSYNC/-_set/clr ,Output Write Status ISI_VSYNC/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " ISI_PCK/-_set/clr ,Output Write Status ISI_PCK/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ISI_D7/-_set/clr ,Output Write Status ISI_D7/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_D6/-_set/clr ,Output Write Status ISI_D6/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_D5/-_set/clr ,Output Write Status ISI_D5/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " ISI_D4/-_set/clr ,Output Write Status ISI_D4/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " ISI_D3/-_set/clr ,Output Write Status ISI_D3/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " ISI_D2/-_set/clr ,Output Write Status ISI_D2/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " ISI_D1/-_set/clr ,Output Write Status ISI_D1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " ISI_D0/-_set/clr ,Output Write Status ISI_D0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TXD0/SPI0_NPCS2_set/clr ,Output Write Status TXD0/SPI0_NPCS2" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " RXD0/SPI0_NPCS1_set/clr ,Output Write Status RXD0/SPI0_NPCS1" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SPI1_NPCS0/RTS0_set/clr ,Output Write Status SPI1_NPCS0/RTS0" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SPI1_SPCK/SCK0_set/clr ,Output Write Status SPI1_SPCK/SCK0" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_MOSI/CTS0_set/clr ,Output Write Status SPI1_MOSI/CTS0" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_MISO/-_set/clr ,Output Write Status SPI1_MISO/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " DTXD/-_set/clr ,Output Write Status DTXD/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " DRXD/-_set/clr ,Output Write Status DRXD/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWCK1/ISI_D11_set/clr ,Output Write Status TWCK1/ISI_D11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWD1/ISI_D10_set/clr ,Output Write Status TWD1/ISI_D10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RXD3/ISI_D9_set/clr ,Output Write Status RXD3/ISI_D9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TXD3/ISI_D8_set/clr ,Output Write Status TXD3/ISI_D8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RXD2/-_set/clr ,Output Write Status RXD2/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TXD2/-_set/clr ,Output Write Status TXD2/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RXD1/-_set/clr ,Output Write Status RXD1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " TXD1/-_set/clr ,Output Write Status TXD1/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " SPI0_NPCS0/-_set/clr ,Output Write Status SPI0_NPCS0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " SPI0_SPCK/-_set/clr ,Output Write Status SPI0_SPCK/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " SPIO_MOSI/-_set/clr ,Output Write Status SPIO_MOSI/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " SPI0_MISO/-_set/clr ,Output Write Status SPI0_MISO/-" "Not affected,Affected"
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xfffff600
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,PIO Status D31/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,PIO Status D30/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,PIO Status D29/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,PIO Status D28/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,PIO Status D27/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,PIO Status D26/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,PIO Status D25/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,PIO Status D24/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,PIO Status D23/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,PIO Status D22/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,PIO Status D21/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,PIO Status D20/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,PIO Status D19/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,PIO Status D18/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,PIO Status D17/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,PIO Status D16/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,PIO Status NWAIT/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,PIO Status NCS3|NANDCS/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,PIO Status NCS2/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,PIO Status A25|CFRNW/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,PIO Status NCS5|CFCS1/CTS2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,PIO Status NCS4|CFCS0/TCLK2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,PIO Status CFCE2/RTS2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,PIO Status CFCE1/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,PIO Status A24/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,PIO Status A23/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,PIO Status A22|NANDCLE/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,PIO Status A21|NANDALE/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,PIO Status A20/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,PIO Status A19/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,PIO Status DQM3/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,PIO Status DQM2/-" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,Output Status D31/-" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,Output Status D30/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,Output Status D29/-" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,Output Status D28/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,Output Status D27/-" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,Output Status D26/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,Output Status D25/-" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,Output Status D24/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,Output Status D23/-" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,Output Status D22/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,Output Status D21/-" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,Output Status D20/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,Output Status D19/-" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,Output Status D18/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,Output Status D17/-" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,Output Status D16/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,Output Status NWAIT/-" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,Output Status NCS3|NANDCS/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,Output Status NCS2/-" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,Output Status A25|CFRNW/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,Output Status NCS5|CFCS1/CTS2" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,Output Status NCS4|CFCS0/TCLK2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,Output Status CFCE2/RTS2" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,Output Status CFCE1/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,Output Status A24/-" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,Output Status A23/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,Output Status A22|NANDCLE/-" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,Output Status A21|NANDALE/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,Output Status A20/-" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,Output Status A19/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,Output Status DQM3/-" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,Output Status DQM2/-" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,Input Filter Status D31/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,Input Filter Status D30/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,Input Filter Status D29/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,Input Filter Status D28/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,Input Filter Status D27/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,Input Filter Status D26/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,Input Filter Status D25/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,Input Filter Status D24/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,Input Filter Status D23/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,Input Filter Status D22/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,Input Filter Status D21/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,Input Filter Status D20/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,Input Filter Status D19/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,Input Filter Status D18/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,Input Filter Status D17/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,Input Filter Status D16/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,Input Filter Status NWAIT/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,Input Filter Status NCS3|NANDCS/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,Input Filter Status NCS2/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,Input Filter Status A25|CFRNW/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,Input Filter Status NCS5|CFCS1/CTS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,Input Filter Status NCS4|CFCS0/TCLK2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,Input Filter Status CFCE2/RTS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,Input Filter Status CFCE1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,Input Filter Status A24/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,Input Filter Status A23/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,Input Filter Status A22|NANDCLE/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,Input Filter Status A21|NANDALE/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,Input Filter Status A20/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,Input Filter Status A19/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,Input Filter Status DQM3/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,Input Filter Status DQM2/-" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,Output Data Status D31/-" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,Output Data Status D30/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,Output Data Status D29/-" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,Output Data Status D28/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,Output Data Status D27/-" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,Output Data Status D26/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,Output Data Status D25/-" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,Output Data Status D24/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,Output Data Status D23/-" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,Output Data Status D22/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,Output Data Status D21/-" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,Output Data Status D20/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,Output Data Status D19/-" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,Output Data Status D18/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,Output Data Status D17/-" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,Output Data Status D16/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,Output Data Status NWAIT/-" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,Output Data Status NCS3|NANDCS/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,Output Data Status NCS2/-" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,Output Data Status A25|CFRNW/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,Output Data Status NCS5|CFCS1/CTS2" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,Output Data Status NCS4|CFCS0/TCLK2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,Output Data Status CFCE2/RTS2" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,Output Data Status CFCE1/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,Output Data Status A24/-" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,Output Data Status A23/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,Output Data Status A22|NANDCLE/-" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,Output Data Status A21|NANDALE/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,Output Data Status A20/-" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,Output Data Status A19/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,Output Data Status DQM3/-" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,Output Data Status DQM2/-" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " D31/- ,Output Data Status D31/-" "Low,High"
|
|
bitfld.long 0x0 30. " D30/- ,Output Data Status D30/-" "Low,High"
|
|
bitfld.long 0x0 29. " D29/- ,Output Data Status D29/-" "Low,High"
|
|
bitfld.long 0x0 28. " D28/- ,Output Data Status D28/-" "Low,High"
|
|
bitfld.long 0x0 27. " D27/- ,Output Data Status D27/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " D26/- ,Output Data Status D26/-" "Low,High"
|
|
bitfld.long 0x0 25. " D25/- ,Output Data Status D25/-" "Low,High"
|
|
bitfld.long 0x0 24. " D24/- ,Output Data Status D24/-" "Low,High"
|
|
bitfld.long 0x0 23. " D23/- ,Output Data Status D23/-" "Low,High"
|
|
bitfld.long 0x0 22. " D22/- ,Output Data Status D22/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " D21/- ,Output Data Status D21/-" "Low,High"
|
|
bitfld.long 0x0 20. " D20/- ,Output Data Status D20/-" "Low,High"
|
|
bitfld.long 0x0 19. " D19/- ,Output Data Status D19/-" "Low,High"
|
|
bitfld.long 0x0 18. " D18/- ,Output Data Status D18/-" "Low,High"
|
|
bitfld.long 0x0 17. " D17/- ,Output Data Status D17/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " D16/- ,Output Data Status D16/-" "Low,High"
|
|
bitfld.long 0x0 15. " NWAIT/- ,Output Data Status NWAIT/-" "Low,High"
|
|
bitfld.long 0x0 14. " NCS3|NANDCS/- ,Output Data Status NCS3|NANDCS/-" "Low,High"
|
|
bitfld.long 0x0 13. " NCS2/- ,Output Data Status NCS2/-" "Low,High"
|
|
bitfld.long 0x0 12. " A25|CFRNW/- ,Output Data Status A25|CFRNW/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " NCS5|CFCS1/CTS2 ,Output Data Status NCS5|CFCS1/CTS2" "Low,High"
|
|
bitfld.long 0x0 10. " NCS4|CFCS0/TCLK2 ,Output Data Status NCS4|CFCS0/TCLK2" "Low,High"
|
|
bitfld.long 0x0 9. " CFCE2/RTS2 ,Output Data Status CFCE2/RTS2" "Low,High"
|
|
bitfld.long 0x0 8. " CFCE1/- ,Output Data Status CFCE1/-" "Low,High"
|
|
bitfld.long 0x0 7. " A24/- ,Output Data Status A24/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " A23/- ,Output Data Status A23/-" "Low,High"
|
|
bitfld.long 0x0 5. " A22|NANDCLE/- ,Output Data Status A22|NANDCLE/-" "Low,High"
|
|
bitfld.long 0x0 4. " A21|NANDALE/- ,Output Data Status A21|NANDALE/-" "Low,High"
|
|
bitfld.long 0x0 3. " A20/- ,Output Data Status A20/-" "Low,High"
|
|
bitfld.long 0x0 2. " A19/- ,Output Data Status A19/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " DQM3/- ,Output Data Status DQM3/-" "Low,High"
|
|
bitfld.long 0x0 0. " DQM2/- ,Output Data Status DQM2/-" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,Input Change Interrupt Mask D31/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,Input Change Interrupt Mask D30/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,Input Change Interrupt Mask D29/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,Input Change Interrupt Mask D28/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,Input Change Interrupt Mask D27/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,Input Change Interrupt Mask D26/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,Input Change Interrupt Mask D25/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,Input Change Interrupt Mask D24/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,Input Change Interrupt Mask D23/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,Input Change Interrupt Mask D22/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,Input Change Interrupt Mask D21/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,Input Change Interrupt Mask D20/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,Input Change Interrupt Mask D19/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,Input Change Interrupt Mask D18/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,Input Change Interrupt Mask D17/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,Input Change Interrupt Mask D16/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,Input Change Interrupt Mask NWAIT/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,Input Change Interrupt Mask NCS3|NANDCS/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,Input Change Interrupt Mask NCS2/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,Input Change Interrupt Mask A25|CFRNW/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,Input Change Interrupt Mask NCS5|CFCS1/CTS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,Input Change Interrupt Mask NCS4|CFCS0/TCLK2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,Input Change Interrupt Mask CFCE2/RTS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,Input Change Interrupt Mask CFCE1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,Input Change Interrupt Mask A24/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,Input Change Interrupt Mask A23/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,Input Change Interrupt Mask A22|NANDCLE/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,Input Change Interrupt Mask A21|NANDALE/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,Input Change Interrupt Mask A20/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,Input Change Interrupt Mask A19/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,Input Change Interrupt Mask DQM3/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,Input Change Interrupt Mask DQM2/-" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,Multi Drive Status D31/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,Multi Drive Status D30/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,Multi Drive Status D29/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,Multi Drive Status D28/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,Multi Drive Status D27/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,Multi Drive Status D26/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,Multi Drive Status D25/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,Multi Drive Status D24/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,Multi Drive Status D23/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,Multi Drive Status D22/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,Multi Drive Status D21/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,Multi Drive Status D20/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,Multi Drive Status D19/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,Multi Drive Status D18/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,Multi Drive Status D17/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,Multi Drive Status D16/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,Multi Drive Status NWAIT/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,Multi Drive Status NCS3|NANDCS/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,Multi Drive Status NCS2/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,Multi Drive Status A25|CFRNW/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,Multi Drive Status NCS5|CFCS1/CTS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,Multi Drive Status NCS4|CFCS0/TCLK2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,Multi Drive Status CFCE2/RTS2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,Multi Drive Status CFCE1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,Multi Drive Status A24/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,Multi Drive Status A23/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,Multi Drive Status A22|NANDCLE/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,Multi Drive Status A21|NANDALE/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,Multi Drive Status A20/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,Multi Drive Status A19/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,Multi Drive Status DQM3/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,Multi Drive Status DQM2/-" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " D31/-_set/clr ,Pull Up Status D31/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " D30/-_set/clr ,Pull Up Status D30/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " D29/-_set/clr ,Pull Up Status D29/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " D28/-_set/clr ,Pull Up Status D28/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " D27/-_set/clr ,Pull Up Status D27/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " D26/-_set/clr ,Pull Up Status D26/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " D25/-_set/clr ,Pull Up Status D25/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " D24/-_set/clr ,Pull Up Status D24/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " D23/-_set/clr ,Pull Up Status D23/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " D22/-_set/clr ,Pull Up Status D22/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " D21/-_set/clr ,Pull Up Status D21/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " D20/-_set/clr ,Pull Up Status D20/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " D19/-_set/clr ,Pull Up Status D19/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " D18/-_set/clr ,Pull Up Status D18/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " D17/-_set/clr ,Pull Up Status D17/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " D16/-_set/clr ,Pull Up Status D16/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " NWAIT/-_set/clr ,Pull Up Status NWAIT/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " NCS3|NANDCS/-_set/clr ,Pull Up Status NCS3|NANDCS/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " NCS2/-_set/clr ,Pull Up Status NCS2/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " A25|CFRNW/-_set/clr ,Pull Up Status A25|CFRNW/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " NCS5|CFCS1/CTS2_set/clr ,Pull Up Status NCS5|CFCS1/CTS2" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " NCS4|CFCS0/TCLK2_set/clr ,Pull Up Status NCS4|CFCS0/TCLK2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " CFCE2/RTS2_set/clr ,Pull Up Status CFCE2/RTS2" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " CFCE1/-_set/clr ,Pull Up Status CFCE1/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " A24/-_set/clr ,Pull Up Status A24/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " A23/-_set/clr ,Pull Up Status A23/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " A22|NANDCLE/-_set/clr ,Pull Up Status A22|NANDCLE/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " A21|NANDALE/-_set/clr ,Pull Up Status A21|NANDALE/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " A20/-_set/clr ,Pull Up Status A20/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " A19/-_set/clr ,Pull Up Status A19/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " DQM3/-_set/clr ,Pull Up Status DQM3/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " DQM2/-_set/clr ,Pull Up Status DQM2/-" "Enabled,Disabled"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " D31/-_set/clr ,Peripheral A B Status D31/-" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " D30/-_set/clr ,Peripheral A B Status D30/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " D29/-_set/clr ,Peripheral A B Status D29/-" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " D28/-_set/clr ,Peripheral A B Status D28/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " D27/-_set/clr ,Peripheral A B Status D27/-" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " D26/-_set/clr ,Peripheral A B Status D26/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " D25/-_set/clr ,Peripheral A B Status D25/-" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " D24/-_set/clr ,Peripheral A B Status D24/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " D23/-_set/clr ,Peripheral A B Status D23/-" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " D22/-_set/clr ,Peripheral A B Status D22/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " D21/-_set/clr ,Peripheral A B Status D21/-" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " D20/-_set/clr ,Peripheral A B Status D20/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " D19/-_set/clr ,Peripheral A B Status D19/-" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " D18/-_set/clr ,Peripheral A B Status D18/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " D17/-_set/clr ,Peripheral A B Status D17/-" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " D16/-_set/clr ,Peripheral A B Status D16/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " NWAIT/-_set/clr ,Peripheral A B Status NWAIT/-" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " NCS3|NANDCS/-_set/clr ,Peripheral A B Status NCS3|NANDCS/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " NCS2/-_set/clr ,Peripheral A B Status NCS2/-" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " A25|CFRNW/-_set/clr ,Peripheral A B Status A25|CFRNW/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " NCS5|CFCS1/CTS2_set/clr ,Peripheral A B Status NCS5|CFCS1/CTS2" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " NCS4|CFCS0/TCLK2_set/clr ,Peripheral A B Status NCS4|CFCS0/TCLK2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " CFCE2/RTS2_set/clr ,Peripheral A B Status CFCE2/RTS2" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " CFCE1/-_set/clr ,Peripheral A B Status CFCE1/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " A24/-_set/clr ,Peripheral A B Status A24/-" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " A23/-_set/clr ,Peripheral A B Status A23/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " A22|NANDCLE/-_set/clr ,Peripheral A B Status A22|NANDCLE/-" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " A21|NANDALE/-_set/clr ,Peripheral A B Status A21|NANDALE/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " A20/-_set/clr ,Peripheral A B Status A20/-" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " A19/-_set/clr ,Peripheral A B Status A19/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " DQM3/-_set/clr ,Peripheral A B Status DQM3/-" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " DQM2/-_set/clr ,Peripheral A B Status DQM2/-" "A,B"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " D31/-_set/clr ,Output Write Status D31/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " D30/-_set/clr ,Output Write Status D30/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " D29/-_set/clr ,Output Write Status D29/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " D28/-_set/clr ,Output Write Status D28/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " D27/-_set/clr ,Output Write Status D27/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " D26/-_set/clr ,Output Write Status D26/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " D25/-_set/clr ,Output Write Status D25/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " D24/-_set/clr ,Output Write Status D24/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " D23/-_set/clr ,Output Write Status D23/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " D22/-_set/clr ,Output Write Status D22/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " D21/-_set/clr ,Output Write Status D21/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " D20/-_set/clr ,Output Write Status D20/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " D19/-_set/clr ,Output Write Status D19/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " D18/-_set/clr ,Output Write Status D18/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " D17/-_set/clr ,Output Write Status D17/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " D16/-_set/clr ,Output Write Status D16/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " NWAIT/-_set/clr ,Output Write Status NWAIT/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " NCS3|NANDCS/-_set/clr ,Output Write Status NCS3|NANDCS/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NCS2/-_set/clr ,Output Write Status NCS2/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " A25|CFRNW/-_set/clr ,Output Write Status A25|CFRNW/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " NCS5|CFCS1/CTS2_set/clr ,Output Write Status NCS5|CFCS1/CTS2" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " NCS4|CFCS0/TCLK2_set/clr ,Output Write Status NCS4|CFCS0/TCLK2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CFCE2/RTS2_set/clr ,Output Write Status CFCE2/RTS2" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CFCE1/-_set/clr ,Output Write Status CFCE1/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " A24/-_set/clr ,Output Write Status A24/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " A23/-_set/clr ,Output Write Status A23/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " A22|NANDCLE/-_set/clr ,Output Write Status A22|NANDCLE/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " A21|NANDALE/-_set/clr ,Output Write Status A21|NANDALE/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " A20/-_set/clr ,Output Write Status A20/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " A19/-_set/clr ,Output Write Status A19/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " DQM3/-_set/clr ,Output Write Status DQM3/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " DQM2/-_set/clr ,Output Write Status DQM2/-" "Not affected,Affected"
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOD"
|
|
base ad:0xfffff800
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOD_PSR,PIOD Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,PIO Status TIOB1/PWM1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,PIO Status TIOB0/SCK2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,PIO Status TCLK1/SCK1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,PIO Status TSADTRG/SPI1_NPCS1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,PIO Status PCK1/SPI0_NPCS3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,PIO Status PCK0/PWM2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,PIO Status SPI0_NPCS2/PWM1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,PIO Status SPI0_NPCS1/PWM0" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,PIO Status TCLK0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,PIO Status TIOA2/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,PIO Status TIOA1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,PIO Status TIOA0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,PIO Status SPI1_NPCS3/FIQ" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,PIO Status SPI1_NPCS2/IRQ" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,PIO Status CTS1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,PIO Status RTS1/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,PIO Status RF1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,PIO Status TF1/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,PIO Status RK1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,PIO Status TK1/PCK0" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,PIO Status RD1/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,PIO Status TD1/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,PIO Status AC97CK/TCLK5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,PIO Status AC97FS/TIOB5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,PIO Status AC97TX/TIOA5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,PIO Status AC97RX/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,PIO Status RF0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,PIO Status RK0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,PIO Status RD0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,PIO Status TD0/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,PIO Status TF0/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,PIO Status TK0/PWM3" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOD_OSR,PIOD Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,Output Status TIOB1/PWM1" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,Output Status TIOB0/SCK2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,Output Status TCLK1/SCK1" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,Output Status TSADTRG/SPI1_NPCS1" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,Output Status PCK1/SPI0_NPCS3" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,Output Status PCK0/PWM2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,Output Status SPI0_NPCS2/PWM1" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,Output Status SPI0_NPCS1/PWM0" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,Output Status TCLK0/-" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,Output Status TIOA2/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,Output Status TIOA1/-" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,Output Status TIOA0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,Output Status SPI1_NPCS3/FIQ" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,Output Status SPI1_NPCS2/IRQ" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,Output Status CTS1/-" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,Output Status RTS1/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,Output Status RF1/-" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,Output Status TF1/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,Output Status RK1/-" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,Output Status TK1/PCK0" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,Output Status RD1/-" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,Output Status TD1/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,Output Status AC97CK/TCLK5" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,Output Status AC97FS/TIOB5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,Output Status AC97TX/TIOA5" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,Output Status AC97RX/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,Output Status RF0/-" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,Output Status RK0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,Output Status RD0/-" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,Output Status TD0/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,Output Status TF0/-" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,Output Status TK0/PWM3" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOD_IFSR,PIOD Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,Input Filter Status TIOB1/PWM1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,Input Filter Status TIOB0/SCK2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,Input Filter Status TCLK1/SCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,Input Filter Status TSADTRG/SPI1_NPCS1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,Input Filter Status PCK1/SPI0_NPCS3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,Input Filter Status PCK0/PWM2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,Input Filter Status SPI0_NPCS2/PWM1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,Input Filter Status SPI0_NPCS1/PWM0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,Input Filter Status TCLK0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,Input Filter Status TIOA2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,Input Filter Status TIOA1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,Input Filter Status TIOA0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,Input Filter Status SPI1_NPCS3/FIQ" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,Input Filter Status SPI1_NPCS2/IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,Input Filter Status CTS1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,Input Filter Status RTS1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,Input Filter Status RF1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,Input Filter Status TF1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,Input Filter Status RK1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,Input Filter Status TK1/PCK0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,Input Filter Status RD1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,Input Filter Status TD1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,Input Filter Status AC97CK/TCLK5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,Input Filter Status AC97FS/TIOB5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,Input Filter Status AC97TX/TIOA5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,Input Filter Status AC97RX/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,Input Filter Status RF0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,Input Filter Status RK0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,Input Filter Status RD0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,Input Filter Status TD0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,Input Filter Status TF0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,Input Filter Status TK0/PWM3" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOD_ODSR,PIOD Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,Output Data Status TIOB1/PWM1" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,Output Data Status TIOB0/SCK2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,Output Data Status TCLK1/SCK1" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,Output Data Status TSADTRG/SPI1_NPCS1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,Output Data Status PCK1/SPI0_NPCS3" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,Output Data Status PCK0/PWM2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,Output Data Status SPI0_NPCS2/PWM1" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,Output Data Status SPI0_NPCS1/PWM0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,Output Data Status TCLK0/-" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,Output Data Status TIOA2/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,Output Data Status TIOA1/-" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,Output Data Status TIOA0/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,Output Data Status SPI1_NPCS3/FIQ" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,Output Data Status SPI1_NPCS2/IRQ" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,Output Data Status CTS1/-" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,Output Data Status RTS1/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,Output Data Status RF1/-" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,Output Data Status TF1/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,Output Data Status RK1/-" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,Output Data Status TK1/PCK0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,Output Data Status RD1/-" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,Output Data Status TD1/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,Output Data Status AC97CK/TCLK5" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,Output Data Status AC97FS/TIOB5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,Output Data Status AC97TX/TIOA5" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,Output Data Status AC97RX/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,Output Data Status RF0/-" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,Output Data Status RK0/-" "Low,High"
|
|
textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,Output Data Status RD0/-" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,Output Data Status TD0/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,Output Data Status TF0/-" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,Output Data Status TK0/PWM3" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOD_PDSR,PIOD Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " TIOB1/PWM1 ,Output Data Status TIOB1/PWM1" "Low,High"
|
|
bitfld.long 0x0 30. " TIOB0/SCK2 ,Output Data Status TIOB0/SCK2" "Low,High"
|
|
bitfld.long 0x0 29. " TCLK1/SCK1 ,Output Data Status TCLK1/SCK1" "Low,High"
|
|
bitfld.long 0x0 28. " TSADTRG/SPI1_NPCS1 ,Output Data Status TSADTRG/SPI1_NPCS1" "Low,High"
|
|
bitfld.long 0x0 27. " PCK1/SPI0_NPCS3 ,Output Data Status PCK1/SPI0_NPCS3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " PCK0/PWM2 ,Output Data Status PCK0/PWM2" "Low,High"
|
|
bitfld.long 0x0 25. " SPI0_NPCS2/PWM1 ,Output Data Status SPI0_NPCS2/PWM1" "Low,High"
|
|
bitfld.long 0x0 24. " SPI0_NPCS1/PWM0 ,Output Data Status SPI0_NPCS1/PWM0" "Low,High"
|
|
bitfld.long 0x0 23. " TCLK0/- ,Output Data Status TCLK0/-" "Low,High"
|
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bitfld.long 0x0 22. " TIOA2/- ,Output Data Status TIOA2/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " TIOA1/- ,Output Data Status TIOA1/-" "Low,High"
|
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bitfld.long 0x0 20. " TIOA0/- ,Output Data Status TIOA0/-" "Low,High"
|
|
bitfld.long 0x0 19. " SPI1_NPCS3/FIQ ,Output Data Status SPI1_NPCS3/FIQ" "Low,High"
|
|
bitfld.long 0x0 18. " SPI1_NPCS2/IRQ ,Output Data Status SPI1_NPCS2/IRQ" "Low,High"
|
|
bitfld.long 0x0 17. " CTS1/- ,Output Data Status CTS1/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " RTS1/- ,Output Data Status RTS1/-" "Low,High"
|
|
bitfld.long 0x0 15. " RF1/- ,Output Data Status RF1/-" "Low,High"
|
|
bitfld.long 0x0 14. " TF1/- ,Output Data Status TF1/-" "Low,High"
|
|
bitfld.long 0x0 13. " RK1/- ,Output Data Status RK1/-" "Low,High"
|
|
bitfld.long 0x0 12. " TK1/PCK0 ,Output Data Status TK1/PCK0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " RD1/- ,Output Data Status RD1/-" "Low,High"
|
|
bitfld.long 0x0 10. " TD1/- ,Output Data Status TD1/-" "Low,High"
|
|
bitfld.long 0x0 9. " AC97CK/TCLK5 ,Output Data Status AC97CK/TCLK5" "Low,High"
|
|
bitfld.long 0x0 8. " AC97FS/TIOB5 ,Output Data Status AC97FS/TIOB5" "Low,High"
|
|
bitfld.long 0x0 7. " AC97TX/TIOA5 ,Output Data Status AC97TX/TIOA5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " AC97RX/- ,Output Data Status AC97RX/-" "Low,High"
|
|
bitfld.long 0x0 5. " RF0/- ,Output Data Status RF0/-" "Low,High"
|
|
bitfld.long 0x0 4. " RK0/- ,Output Data Status RK0/-" "Low,High"
|
|
bitfld.long 0x0 3. " RD0/- ,Output Data Status RD0/-" "Low,High"
|
|
bitfld.long 0x0 2. " TD0/- ,Output Data Status TD0/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TF0/- ,Output Data Status TF0/-" "Low,High"
|
|
bitfld.long 0x0 0. " TK0/PWM3 ,Output Data Status TK0/PWM3" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOD_IMR,PIOD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,Input Change Interrupt Mask TIOB1/PWM1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,Input Change Interrupt Mask TIOB0/SCK2" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,Input Change Interrupt Mask TCLK1/SCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,Input Change Interrupt Mask TSADTRG/SPI1_NPCS1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,Input Change Interrupt Mask PCK1/SPI0_NPCS3" "Disabled,Enabled"
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|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,Input Change Interrupt Mask PCK0/PWM2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,Input Change Interrupt Mask SPI0_NPCS2/PWM1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,Input Change Interrupt Mask SPI0_NPCS1/PWM0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,Input Change Interrupt Mask TCLK0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,Input Change Interrupt Mask TIOA2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,Input Change Interrupt Mask TIOA1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,Input Change Interrupt Mask TIOA0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,Input Change Interrupt Mask SPI1_NPCS3/FIQ" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,Input Change Interrupt Mask SPI1_NPCS2/IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,Input Change Interrupt Mask CTS1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,Input Change Interrupt Mask RTS1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,Input Change Interrupt Mask RF1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,Input Change Interrupt Mask TF1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,Input Change Interrupt Mask RK1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,Input Change Interrupt Mask TK1/PCK0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,Input Change Interrupt Mask RD1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,Input Change Interrupt Mask TD1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,Input Change Interrupt Mask AC97CK/TCLK5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,Input Change Interrupt Mask AC97FS/TIOB5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,Input Change Interrupt Mask AC97TX/TIOA5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,Input Change Interrupt Mask AC97RX/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,Input Change Interrupt Mask RF0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,Input Change Interrupt Mask RK0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,Input Change Interrupt Mask RD0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,Input Change Interrupt Mask TD0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,Input Change Interrupt Mask TF0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,Input Change Interrupt Mask TK0/PWM3" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOD_ISR,PIOD Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOD_MDSR,PIOD Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,Multi Drive Status TIOB1/PWM1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,Multi Drive Status TIOB0/SCK2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,Multi Drive Status TCLK1/SCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,Multi Drive Status TSADTRG/SPI1_NPCS1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,Multi Drive Status PCK1/SPI0_NPCS3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,Multi Drive Status PCK0/PWM2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,Multi Drive Status SPI0_NPCS2/PWM1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,Multi Drive Status SPI0_NPCS1/PWM0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,Multi Drive Status TCLK0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,Multi Drive Status TIOA2/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,Multi Drive Status TIOA1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,Multi Drive Status TIOA0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,Multi Drive Status SPI1_NPCS3/FIQ" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,Multi Drive Status SPI1_NPCS2/IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,Multi Drive Status CTS1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,Multi Drive Status RTS1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,Multi Drive Status RF1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,Multi Drive Status TF1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,Multi Drive Status RK1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,Multi Drive Status TK1/PCK0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,Multi Drive Status RD1/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,Multi Drive Status TD1/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,Multi Drive Status AC97CK/TCLK5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,Multi Drive Status AC97FS/TIOB5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,Multi Drive Status AC97TX/TIOA5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,Multi Drive Status AC97RX/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,Multi Drive Status RF0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,Multi Drive Status RK0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,Multi Drive Status RD0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,Multi Drive Status TD0/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,Multi Drive Status TF0/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,Multi Drive Status TK0/PWM3" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOD_PUSR,PIOD Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " TIOB1/PWM1_set/clr ,Pull Up Status TIOB1/PWM1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " TIOB0/SCK2_set/clr ,Pull Up Status TIOB0/SCK2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " TCLK1/SCK1_set/clr ,Pull Up Status TCLK1/SCK1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " TSADTRG/SPI1_NPCS1_set/clr ,Pull Up Status TSADTRG/SPI1_NPCS1" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " PCK1/SPI0_NPCS3_set/clr ,Pull Up Status PCK1/SPI0_NPCS3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " PCK0/PWM2_set/clr ,Pull Up Status PCK0/PWM2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " SPI0_NPCS2/PWM1_set/clr ,Pull Up Status SPI0_NPCS2/PWM1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " SPI0_NPCS1/PWM0_set/clr ,Pull Up Status SPI0_NPCS1/PWM0" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " TCLK0/-_set/clr ,Pull Up Status TCLK0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " TIOA2/-_set/clr ,Pull Up Status TIOA2/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " TIOA1/-_set/clr ,Pull Up Status TIOA1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " TIOA0/-_set/clr ,Pull Up Status TIOA0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " SPI1_NPCS3/FIQ_set/clr ,Pull Up Status SPI1_NPCS3/FIQ" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " SPI1_NPCS2/IRQ_set/clr ,Pull Up Status SPI1_NPCS2/IRQ" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " CTS1/-_set/clr ,Pull Up Status CTS1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " RTS1/-_set/clr ,Pull Up Status RTS1/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " RF1/-_set/clr ,Pull Up Status RF1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " TF1/-_set/clr ,Pull Up Status TF1/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " RK1/-_set/clr ,Pull Up Status RK1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " TK1/PCK0_set/clr ,Pull Up Status TK1/PCK0" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " RD1/-_set/clr ,Pull Up Status RD1/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " TD1/-_set/clr ,Pull Up Status TD1/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " AC97CK/TCLK5_set/clr ,Pull Up Status AC97CK/TCLK5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " AC97FS/TIOB5_set/clr ,Pull Up Status AC97FS/TIOB5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " AC97TX/TIOA5_set/clr ,Pull Up Status AC97TX/TIOA5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " AC97RX/-_set/clr ,Pull Up Status AC97RX/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " RF0/-_set/clr ,Pull Up Status RF0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " RK0/-_set/clr ,Pull Up Status RK0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " RD0/-_set/clr ,Pull Up Status RD0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " TD0/-_set/clr ,Pull Up Status TD0/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " TF0/-_set/clr ,Pull Up Status TF0/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " TK0/PWM3_set/clr ,Pull Up Status TK0/PWM3" "Enabled,Disabled"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " TIOB1/PWM1_set/clr ,Peripheral A B Status TIOB1/PWM1" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " TIOB0/SCK2_set/clr ,Peripheral A B Status TIOB0/SCK2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " TCLK1/SCK1_set/clr ,Peripheral A B Status TCLK1/SCK1" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " TSADTRG/SPI1_NPCS1_set/clr ,Peripheral A B Status TSADTRG/SPI1_NPCS1" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " PCK1/SPI0_NPCS3_set/clr ,Peripheral A B Status PCK1/SPI0_NPCS3" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " PCK0/PWM2_set/clr ,Peripheral A B Status PCK0/PWM2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " SPI0_NPCS2/PWM1_set/clr ,Peripheral A B Status SPI0_NPCS2/PWM1" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " SPI0_NPCS1/PWM0_set/clr ,Peripheral A B Status SPI0_NPCS1/PWM0" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " TCLK0/-_set/clr ,Peripheral A B Status TCLK0/-" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " TIOA2/-_set/clr ,Peripheral A B Status TIOA2/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " TIOA1/-_set/clr ,Peripheral A B Status TIOA1/-" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " TIOA0/-_set/clr ,Peripheral A B Status TIOA0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " SPI1_NPCS3/FIQ_set/clr ,Peripheral A B Status SPI1_NPCS3/FIQ" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " SPI1_NPCS2/IRQ_set/clr ,Peripheral A B Status SPI1_NPCS2/IRQ" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " CTS1/-_set/clr ,Peripheral A B Status CTS1/-" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " RTS1/-_set/clr ,Peripheral A B Status RTS1/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " RF1/-_set/clr ,Peripheral A B Status RF1/-" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " TF1/-_set/clr ,Peripheral A B Status TF1/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " RK1/-_set/clr ,Peripheral A B Status RK1/-" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " TK1/PCK0_set/clr ,Peripheral A B Status TK1/PCK0" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " RD1/-_set/clr ,Peripheral A B Status RD1/-" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " TD1/-_set/clr ,Peripheral A B Status TD1/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " AC97CK/TCLK5_set/clr ,Peripheral A B Status AC97CK/TCLK5" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " AC97FS/TIOB5_set/clr ,Peripheral A B Status AC97FS/TIOB5" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " AC97TX/TIOA5_set/clr ,Peripheral A B Status AC97TX/TIOA5" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " AC97RX/-_set/clr ,Peripheral A B Status AC97RX/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " RF0/-_set/clr ,Peripheral A B Status RF0/-" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " RK0/-_set/clr ,Peripheral A B Status RK0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " RD0/-_set/clr ,Peripheral A B Status RD0/-" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " TD0/-_set/clr ,Peripheral A B Status TD0/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " TF0/-_set/clr ,Peripheral A B Status TF0/-" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " TK0/PWM3_set/clr ,Peripheral A B Status TK0/PWM3" "A,B"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOD_OWSR,PIOD Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TIOB1/PWM1_set/clr ,Output Write Status TIOB1/PWM1" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TIOB0/SCK2_set/clr ,Output Write Status TIOB0/SCK2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TCLK1/SCK1_set/clr ,Output Write Status TCLK1/SCK1" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TSADTRG/SPI1_NPCS1_set/clr ,Output Write Status TSADTRG/SPI1_NPCS1" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PCK1/SPI0_NPCS3_set/clr ,Output Write Status PCK1/SPI0_NPCS3" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PCK0/PWM2_set/clr ,Output Write Status PCK0/PWM2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI0_NPCS2/PWM1_set/clr ,Output Write Status SPI0_NPCS2/PWM1" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_NPCS1/PWM0_set/clr ,Output Write Status SPI0_NPCS1/PWM0" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TCLK0/-_set/clr ,Output Write Status TCLK0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TIOA2/-_set/clr ,Output Write Status TIOA2/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TIOA1/-_set/clr ,Output Write Status TIOA1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TIOA0/-_set/clr ,Output Write Status TIOA0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI1_NPCS3/FIQ_set/clr ,Output Write Status SPI1_NPCS3/FIQ" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " SPI1_NPCS2/IRQ_set/clr ,Output Write Status SPI1_NPCS2/IRQ" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " CTS1/-_set/clr ,Output Write Status CTS1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RTS1/-_set/clr ,Output Write Status RTS1/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " RF1/-_set/clr ,Output Write Status RF1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " TF1/-_set/clr ,Output Write Status TF1/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " RK1/-_set/clr ,Output Write Status RK1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TK1/PCK0_set/clr ,Output Write Status TK1/PCK0" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RD1/-_set/clr ,Output Write Status RD1/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TD1/-_set/clr ,Output Write Status TD1/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " AC97CK/TCLK5_set/clr ,Output Write Status AC97CK/TCLK5" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " AC97FS/TIOB5_set/clr ,Output Write Status AC97FS/TIOB5" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " AC97TX/TIOA5_set/clr ,Output Write Status AC97TX/TIOA5" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " AC97RX/-_set/clr ,Output Write Status AC97RX/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RF0/-_set/clr ,Output Write Status RF0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RK0/-_set/clr ,Output Write Status RK0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RD0/-_set/clr ,Output Write Status RD0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TD0/-_set/clr ,Output Write Status TD0/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TF0/-_set/clr ,Output Write Status TF0/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TK0/PWM3_set/clr ,Output Write Status TK0/PWM3" "Not affected,Affected"
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOE"
|
|
base ad:0xfffffa00
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOE_PSR,PIOE Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,PIO Status PWM2/PCK1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,PIO Status LCDD23/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,PIO Status LCDD22/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,PIO Status LCDD21/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,PIO Status LCDD20/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,PIO Status LCDD19/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,PIO Status LCDD18/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,PIO Status LCDD17/LCDD23" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,PIO Status LCDD16/LCDD22" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,PIO Status LCDD15/LCDD21" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,PIO Status LCDD14/LCDD20" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,PIO Status LCDD13/LCDD19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,PIO Status LCDD12/LCDD18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,PIO Status LCDD11/LCDD15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,PIO Status LCDD10/LCDD14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,PIO Status LCDD9/LCDD13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,PIO Status LCDD8/LCDD12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,PIO Status LCDD7/LCDD11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,PIO Status LCDD6/LCDD10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,PIO Status LCDD5/LCDD7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,PIO Status LCDD4/LCDD6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,PIO Status LCDD3/LCDD5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,PIO Status LCDD2/LCDD4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,PIO Status LCDD1/LCDD3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,PIO Status LCDD0/LCDD2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,PIO Status LCDDEN/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,PIO Status LCDDOTCK/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,PIO Status LCDHSYNC/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,PIO Status LCDVSYNC/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,PIO Status LCDCC/-" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,PIO Status LCDMOD/-" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,PIO Status LCDPWR/PCK0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOE_OSR,PIOE Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,Output Status PWM2/PCK1" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,Output Status LCDD23/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,Output Status LCDD22/-" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,Output Status LCDD21/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,Output Status LCDD20/-" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,Output Status LCDD19/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,Output Status LCDD18/-" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,Output Status LCDD17/LCDD23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,Output Status LCDD16/LCDD22" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,Output Status LCDD15/LCDD21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,Output Status LCDD14/LCDD20" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,Output Status LCDD13/LCDD19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,Output Status LCDD12/LCDD18" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,Output Status LCDD11/LCDD15" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,Output Status LCDD10/LCDD14" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,Output Status LCDD9/LCDD13" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,Output Status LCDD8/LCDD12" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,Output Status LCDD7/LCDD11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,Output Status LCDD6/LCDD10" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,Output Status LCDD5/LCDD7" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,Output Status LCDD4/LCDD6" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,Output Status LCDD3/LCDD5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,Output Status LCDD2/LCDD4" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,Output Status LCDD1/LCDD3" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,Output Status LCDD0/LCDD2" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,Output Status LCDDEN/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,Output Status LCDDOTCK/-" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,Output Status LCDHSYNC/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,Output Status LCDVSYNC/-" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,Output Status LCDCC/-" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,Output Status LCDMOD/-" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,Output Status LCDPWR/PCK0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOE_IFSR,PIOE Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,Input Filter Status PWM2/PCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,Input Filter Status LCDD23/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,Input Filter Status LCDD22/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,Input Filter Status LCDD21/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,Input Filter Status LCDD20/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,Input Filter Status LCDD19/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,Input Filter Status LCDD18/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,Input Filter Status LCDD17/LCDD23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,Input Filter Status LCDD16/LCDD22" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,Input Filter Status LCDD15/LCDD21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,Input Filter Status LCDD14/LCDD20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,Input Filter Status LCDD13/LCDD19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,Input Filter Status LCDD12/LCDD18" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,Input Filter Status LCDD11/LCDD15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,Input Filter Status LCDD10/LCDD14" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,Input Filter Status LCDD9/LCDD13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,Input Filter Status LCDD8/LCDD12" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,Input Filter Status LCDD7/LCDD11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,Input Filter Status LCDD6/LCDD10" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,Input Filter Status LCDD5/LCDD7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,Input Filter Status LCDD4/LCDD6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,Input Filter Status LCDD3/LCDD5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,Input Filter Status LCDD2/LCDD4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,Input Filter Status LCDD1/LCDD3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,Input Filter Status LCDD0/LCDD2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,Input Filter Status LCDDEN/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,Input Filter Status LCDDOTCK/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,Input Filter Status LCDHSYNC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,Input Filter Status LCDVSYNC/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,Input Filter Status LCDCC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,Input Filter Status LCDMOD/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,Input Filter Status LCDPWR/PCK0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOE_ODSR,PIOE Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,Output Data Status PWM2/PCK1" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,Output Data Status LCDD23/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,Output Data Status LCDD22/-" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,Output Data Status LCDD21/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,Output Data Status LCDD20/-" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,Output Data Status LCDD19/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,Output Data Status LCDD18/-" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,Output Data Status LCDD17/LCDD23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,Output Data Status LCDD16/LCDD22" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,Output Data Status LCDD15/LCDD21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,Output Data Status LCDD14/LCDD20" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,Output Data Status LCDD13/LCDD19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,Output Data Status LCDD12/LCDD18" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,Output Data Status LCDD11/LCDD15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,Output Data Status LCDD10/LCDD14" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,Output Data Status LCDD9/LCDD13" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,Output Data Status LCDD8/LCDD12" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,Output Data Status LCDD7/LCDD11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,Output Data Status LCDD6/LCDD10" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,Output Data Status LCDD5/LCDD7" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,Output Data Status LCDD4/LCDD6" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,Output Data Status LCDD3/LCDD5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,Output Data Status LCDD2/LCDD4" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,Output Data Status LCDD1/LCDD3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,Output Data Status LCDD0/LCDD2" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,Output Data Status LCDDEN/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,Output Data Status LCDDOTCK/-" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,Output Data Status LCDHSYNC/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,Output Data Status LCDVSYNC/-" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,Output Data Status LCDCC/-" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,Output Data Status LCDMOD/-" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,Output Data Status LCDPWR/PCK0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOE_PDSR,PIOE Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " PWM2/PCK1 ,Output Data Status PWM2/PCK1" "Low,High"
|
|
bitfld.long 0x0 30. " LCDD23/- ,Output Data Status LCDD23/-" "Low,High"
|
|
bitfld.long 0x0 29. " LCDD22/- ,Output Data Status LCDD22/-" "Low,High"
|
|
bitfld.long 0x0 28. " LCDD21/- ,Output Data Status LCDD21/-" "Low,High"
|
|
bitfld.long 0x0 27. " LCDD20/- ,Output Data Status LCDD20/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " LCDD19/- ,Output Data Status LCDD19/-" "Low,High"
|
|
bitfld.long 0x0 25. " LCDD18/- ,Output Data Status LCDD18/-" "Low,High"
|
|
bitfld.long 0x0 24. " LCDD17/LCDD23 ,Output Data Status LCDD17/LCDD23" "Low,High"
|
|
bitfld.long 0x0 23. " LCDD16/LCDD22 ,Output Data Status LCDD16/LCDD22" "Low,High"
|
|
bitfld.long 0x0 22. " LCDD15/LCDD21 ,Output Data Status LCDD15/LCDD21" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " LCDD14/LCDD20 ,Output Data Status LCDD14/LCDD20" "Low,High"
|
|
bitfld.long 0x0 20. " LCDD13/LCDD19 ,Output Data Status LCDD13/LCDD19" "Low,High"
|
|
bitfld.long 0x0 19. " LCDD12/LCDD18 ,Output Data Status LCDD12/LCDD18" "Low,High"
|
|
bitfld.long 0x0 18. " LCDD11/LCDD15 ,Output Data Status LCDD11/LCDD15" "Low,High"
|
|
bitfld.long 0x0 17. " LCDD10/LCDD14 ,Output Data Status LCDD10/LCDD14" "Low,High"
|
|
textline " "
|
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bitfld.long 0x0 16. " LCDD9/LCDD13 ,Output Data Status LCDD9/LCDD13" "Low,High"
|
|
bitfld.long 0x0 15. " LCDD8/LCDD12 ,Output Data Status LCDD8/LCDD12" "Low,High"
|
|
bitfld.long 0x0 14. " LCDD7/LCDD11 ,Output Data Status LCDD7/LCDD11" "Low,High"
|
|
bitfld.long 0x0 13. " LCDD6/LCDD10 ,Output Data Status LCDD6/LCDD10" "Low,High"
|
|
bitfld.long 0x0 12. " LCDD5/LCDD7 ,Output Data Status LCDD5/LCDD7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " LCDD4/LCDD6 ,Output Data Status LCDD4/LCDD6" "Low,High"
|
|
bitfld.long 0x0 10. " LCDD3/LCDD5 ,Output Data Status LCDD3/LCDD5" "Low,High"
|
|
bitfld.long 0x0 9. " LCDD2/LCDD4 ,Output Data Status LCDD2/LCDD4" "Low,High"
|
|
bitfld.long 0x0 8. " LCDD1/LCDD3 ,Output Data Status LCDD1/LCDD3" "Low,High"
|
|
bitfld.long 0x0 7. " LCDD0/LCDD2 ,Output Data Status LCDD0/LCDD2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " LCDDEN/- ,Output Data Status LCDDEN/-" "Low,High"
|
|
bitfld.long 0x0 5. " LCDDOTCK/- ,Output Data Status LCDDOTCK/-" "Low,High"
|
|
bitfld.long 0x0 4. " LCDHSYNC/- ,Output Data Status LCDHSYNC/-" "Low,High"
|
|
bitfld.long 0x0 3. " LCDVSYNC/- ,Output Data Status LCDVSYNC/-" "Low,High"
|
|
bitfld.long 0x0 2. " LCDCC/- ,Output Data Status LCDCC/-" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LCDMOD/- ,Output Data Status LCDMOD/-" "Low,High"
|
|
bitfld.long 0x0 0. " LCDPWR/PCK0 ,Output Data Status LCDPWR/PCK0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOE_IMR,PIOE Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,Input Change Interrupt Mask PWM2/PCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,Input Change Interrupt Mask LCDD23/-" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,Input Change Interrupt Mask LCDD22/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,Input Change Interrupt Mask LCDD21/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,Input Change Interrupt Mask LCDD20/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,Input Change Interrupt Mask LCDD19/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,Input Change Interrupt Mask LCDD18/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,Input Change Interrupt Mask LCDD17/LCDD23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,Input Change Interrupt Mask LCDD16/LCDD22" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,Input Change Interrupt Mask LCDD15/LCDD21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,Input Change Interrupt Mask LCDD14/LCDD20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,Input Change Interrupt Mask LCDD13/LCDD19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,Input Change Interrupt Mask LCDD12/LCDD18" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,Input Change Interrupt Mask LCDD11/LCDD15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,Input Change Interrupt Mask LCDD10/LCDD14" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,Input Change Interrupt Mask LCDD9/LCDD13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,Input Change Interrupt Mask LCDD8/LCDD12" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,Input Change Interrupt Mask LCDD7/LCDD11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,Input Change Interrupt Mask LCDD6/LCDD10" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,Input Change Interrupt Mask LCDD5/LCDD7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,Input Change Interrupt Mask LCDD4/LCDD6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,Input Change Interrupt Mask LCDD3/LCDD5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,Input Change Interrupt Mask LCDD2/LCDD4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,Input Change Interrupt Mask LCDD1/LCDD3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,Input Change Interrupt Mask LCDD0/LCDD2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,Input Change Interrupt Mask LCDDEN/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,Input Change Interrupt Mask LCDDOTCK/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,Input Change Interrupt Mask LCDHSYNC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,Input Change Interrupt Mask LCDVSYNC/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,Input Change Interrupt Mask LCDCC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,Input Change Interrupt Mask LCDMOD/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,Input Change Interrupt Mask LCDPWR/PCK0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOE_ISR,PIOE Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOE_MDSR,PIOE Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,Multi Drive Status PWM2/PCK1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,Multi Drive Status LCDD23/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,Multi Drive Status LCDD22/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,Multi Drive Status LCDD21/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,Multi Drive Status LCDD20/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,Multi Drive Status LCDD19/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,Multi Drive Status LCDD18/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,Multi Drive Status LCDD17/LCDD23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,Multi Drive Status LCDD16/LCDD22" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,Multi Drive Status LCDD15/LCDD21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,Multi Drive Status LCDD14/LCDD20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,Multi Drive Status LCDD13/LCDD19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,Multi Drive Status LCDD12/LCDD18" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,Multi Drive Status LCDD11/LCDD15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,Multi Drive Status LCDD10/LCDD14" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,Multi Drive Status LCDD9/LCDD13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,Multi Drive Status LCDD8/LCDD12" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,Multi Drive Status LCDD7/LCDD11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,Multi Drive Status LCDD6/LCDD10" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,Multi Drive Status LCDD5/LCDD7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,Multi Drive Status LCDD4/LCDD6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,Multi Drive Status LCDD3/LCDD5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,Multi Drive Status LCDD2/LCDD4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,Multi Drive Status LCDD1/LCDD3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,Multi Drive Status LCDD0/LCDD2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,Multi Drive Status LCDDEN/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,Multi Drive Status LCDDOTCK/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,Multi Drive Status LCDHSYNC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,Multi Drive Status LCDVSYNC/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,Multi Drive Status LCDCC/-" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,Multi Drive Status LCDMOD/-" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,Multi Drive Status LCDPWR/PCK0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOE_PUSR,PIOE Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " PWM2/PCK1_set/clr ,Pull Up Status PWM2/PCK1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " LCDD23/-_set/clr ,Pull Up Status LCDD23/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " LCDD22/-_set/clr ,Pull Up Status LCDD22/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " LCDD21/-_set/clr ,Pull Up Status LCDD21/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " LCDD20/-_set/clr ,Pull Up Status LCDD20/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " LCDD19/-_set/clr ,Pull Up Status LCDD19/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " LCDD18/-_set/clr ,Pull Up Status LCDD18/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " LCDD17/LCDD23_set/clr ,Pull Up Status LCDD17/LCDD23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " LCDD16/LCDD22_set/clr ,Pull Up Status LCDD16/LCDD22" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " LCDD15/LCDD21_set/clr ,Pull Up Status LCDD15/LCDD21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " LCDD14/LCDD20_set/clr ,Pull Up Status LCDD14/LCDD20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " LCDD13/LCDD19_set/clr ,Pull Up Status LCDD13/LCDD19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " LCDD12/LCDD18_set/clr ,Pull Up Status LCDD12/LCDD18" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " LCDD11/LCDD15_set/clr ,Pull Up Status LCDD11/LCDD15" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " LCDD10/LCDD14_set/clr ,Pull Up Status LCDD10/LCDD14" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " LCDD9/LCDD13_set/clr ,Pull Up Status LCDD9/LCDD13" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " LCDD8/LCDD12_set/clr ,Pull Up Status LCDD8/LCDD12" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " LCDD7/LCDD11_set/clr ,Pull Up Status LCDD7/LCDD11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " LCDD6/LCDD10_set/clr ,Pull Up Status LCDD6/LCDD10" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " LCDD5/LCDD7_set/clr ,Pull Up Status LCDD5/LCDD7" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " LCDD4/LCDD6_set/clr ,Pull Up Status LCDD4/LCDD6" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " LCDD3/LCDD5_set/clr ,Pull Up Status LCDD3/LCDD5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " LCDD2/LCDD4_set/clr ,Pull Up Status LCDD2/LCDD4" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " LCDD1/LCDD3_set/clr ,Pull Up Status LCDD1/LCDD3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " LCDD0/LCDD2_set/clr ,Pull Up Status LCDD0/LCDD2" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " LCDDEN/-_set/clr ,Pull Up Status LCDDEN/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " LCDDOTCK/-_set/clr ,Pull Up Status LCDDOTCK/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " LCDHSYNC/-_set/clr ,Pull Up Status LCDHSYNC/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " LCDVSYNC/-_set/clr ,Pull Up Status LCDVSYNC/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " LCDCC/-_set/clr ,Pull Up Status LCDCC/-" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " LCDMOD/-_set/clr ,Pull Up Status LCDMOD/-" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " LCDPWR/PCK0_set/clr ,Pull Up Status LCDPWR/PCK0" "Enabled,Disabled"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOE_ABSR,PIOE Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " PWM2/PCK1_set/clr ,Peripheral A B Status PWM2/PCK1" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " LCDD23/-_set/clr ,Peripheral A B Status LCDD23/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " LCDD22/-_set/clr ,Peripheral A B Status LCDD22/-" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " LCDD21/-_set/clr ,Peripheral A B Status LCDD21/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " LCDD20/-_set/clr ,Peripheral A B Status LCDD20/-" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " LCDD19/-_set/clr ,Peripheral A B Status LCDD19/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " LCDD18/-_set/clr ,Peripheral A B Status LCDD18/-" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " LCDD17/LCDD23_set/clr ,Peripheral A B Status LCDD17/LCDD23" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " LCDD16/LCDD22_set/clr ,Peripheral A B Status LCDD16/LCDD22" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " LCDD15/LCDD21_set/clr ,Peripheral A B Status LCDD15/LCDD21" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " LCDD14/LCDD20_set/clr ,Peripheral A B Status LCDD14/LCDD20" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " LCDD13/LCDD19_set/clr ,Peripheral A B Status LCDD13/LCDD19" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " LCDD12/LCDD18_set/clr ,Peripheral A B Status LCDD12/LCDD18" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " LCDD11/LCDD15_set/clr ,Peripheral A B Status LCDD11/LCDD15" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " LCDD10/LCDD14_set/clr ,Peripheral A B Status LCDD10/LCDD14" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " LCDD9/LCDD13_set/clr ,Peripheral A B Status LCDD9/LCDD13" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " LCDD8/LCDD12_set/clr ,Peripheral A B Status LCDD8/LCDD12" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " LCDD7/LCDD11_set/clr ,Peripheral A B Status LCDD7/LCDD11" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " LCDD6/LCDD10_set/clr ,Peripheral A B Status LCDD6/LCDD10" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " LCDD5/LCDD7_set/clr ,Peripheral A B Status LCDD5/LCDD7" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " LCDD4/LCDD6_set/clr ,Peripheral A B Status LCDD4/LCDD6" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " LCDD3/LCDD5_set/clr ,Peripheral A B Status LCDD3/LCDD5" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " LCDD2/LCDD4_set/clr ,Peripheral A B Status LCDD2/LCDD4" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " LCDD1/LCDD3_set/clr ,Peripheral A B Status LCDD1/LCDD3" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " LCDD0/LCDD2_set/clr ,Peripheral A B Status LCDD0/LCDD2" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " LCDDEN/-_set/clr ,Peripheral A B Status LCDDEN/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " LCDDOTCK/-_set/clr ,Peripheral A B Status LCDDOTCK/-" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " LCDHSYNC/-_set/clr ,Peripheral A B Status LCDHSYNC/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " LCDVSYNC/-_set/clr ,Peripheral A B Status LCDVSYNC/-" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " LCDCC/-_set/clr ,Peripheral A B Status LCDCC/-" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " LCDMOD/-_set/clr ,Peripheral A B Status LCDMOD/-" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " LCDPWR/PCK0_set/clr ,Peripheral A B Status LCDPWR/PCK0" "A,B"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOE_OWSR,PIOE Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PWM2/PCK1_set/clr ,Output Write Status PWM2/PCK1" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " LCDD23/-_set/clr ,Output Write Status LCDD23/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LCDD22/-_set/clr ,Output Write Status LCDD22/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LCDD21/-_set/clr ,Output Write Status LCDD21/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LCDD20/-_set/clr ,Output Write Status LCDD20/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LCDD19/-_set/clr ,Output Write Status LCDD19/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDD18/-_set/clr ,Output Write Status LCDD18/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " LCDD17/LCDD23_set/clr ,Output Write Status LCDD17/LCDD23" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDD16/LCDD22_set/clr ,Output Write Status LCDD16/LCDD22" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " LCDD15/LCDD21_set/clr ,Output Write Status LCDD15/LCDD21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " LCDD14/LCDD20_set/clr ,Output Write Status LCDD14/LCDD20" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " LCDD13/LCDD19_set/clr ,Output Write Status LCDD13/LCDD19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " LCDD12/LCDD18_set/clr ,Output Write Status LCDD12/LCDD18" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " LCDD11/LCDD15_set/clr ,Output Write Status LCDD11/LCDD15" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " LCDD10/LCDD14_set/clr ,Output Write Status LCDD10/LCDD14" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " LCDD9/LCDD13_set/clr ,Output Write Status LCDD9/LCDD13" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LCDD8/LCDD12_set/clr ,Output Write Status LCDD8/LCDD12" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LCDD7/LCDD11_set/clr ,Output Write Status LCDD7/LCDD11" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " LCDD6/LCDD10_set/clr ,Output Write Status LCDD6/LCDD10" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " LCDD5/LCDD7_set/clr ,Output Write Status LCDD5/LCDD7" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " LCDD4/LCDD6_set/clr ,Output Write Status LCDD4/LCDD6" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " LCDD3/LCDD5_set/clr ,Output Write Status LCDD3/LCDD5" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " LCDD2/LCDD4_set/clr ,Output Write Status LCDD2/LCDD4" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " LCDD1/LCDD3_set/clr ,Output Write Status LCDD1/LCDD3" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " LCDD0/LCDD2_set/clr ,Output Write Status LCDD0/LCDD2" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " LCDDEN/-_set/clr ,Output Write Status LCDDEN/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " LCDDOTCK/-_set/clr ,Output Write Status LCDDOTCK/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " LCDHSYNC/-_set/clr ,Output Write Status LCDHSYNC/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDVSYNC/-_set/clr ,Output Write Status LCDVSYNC/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " LCDCC/-_set/clr ,Output Write Status LCDCC/-" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " LCDMOD/-_set/clr ,Output Write Status LCDMOD/-" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " LCDPWR/PCK0_set/clr ,Output Write Status LCDPWR/PCK0" "Not affected,Affected"
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0xfffa4000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI0_CR,SPI0 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
in
|
|
if ((((data.long(ad:0xfffa4000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffa4000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI0_SR,SPI0 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI0_IMR,SPI0 Interrupt Mask Register"
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI0 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_SPI0"
|
|
base ad:0xfffa4000
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SPI0_RPR,Serial Peripheral Interface 0 Receive Pointer Register"
|
|
line.long 0x04 "SPI0_RCR,Serial Peripheral Interface 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI0_TPR,Serial Peripheral Interface 0 Transmit Pointer Register"
|
|
line.long 0x0c "SPI0_TCR,Serial Peripheral Interface 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI0_RNPR,Serial Peripheral Interface 0 Receive Next Pointer Register"
|
|
line.long 0x14 "SPI0_RNCR,Serial Peripheral Interface 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI0_TNPR,Serial Peripheral Interface 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI0_TNCR,Serial Peripheral Interface 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI0_PTCR,Serial Peripheral Interface 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI0_PTSR,Serial Peripheral Interface 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0xfffa8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI1_CR,SPI1 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
in
|
|
if ((((data.long(ad:0xfffa8000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffa8000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI1_SR,SPI1 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI1_IMR,SPI1 Interrupt Mask Register"
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI1 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_SPI1"
|
|
base ad:0xfffa8000
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SPI1_RPR,Serial Peripheral Interface 1 Receive Pointer Register"
|
|
line.long 0x04 "SPI1_RCR,Serial Peripheral Interface 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI1_TPR,Serial Peripheral Interface 1 Transmit Pointer Register"
|
|
line.long 0x0c "SPI1_TCR,Serial Peripheral Interface 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI1_RNPR,Serial Peripheral Interface 1 Receive Next Pointer Register"
|
|
line.long 0x14 "SPI1_RNCR,Serial Peripheral Interface 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI1_TNPR,Serial Peripheral Interface 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI1_TNCR,Serial Peripheral Interface 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI1_PTCR,Serial Peripheral Interface 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI1_PTSR,Serial Peripheral Interface 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "TWI (Two-wire Interface)"
|
|
tree "TWI 1"
|
|
base ad:0xfff84000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xfff84000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff84000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff84000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
width 0xb
|
|
tree.end
|
|
tree "TWI 2"
|
|
base ad:0xfff88000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xfff88000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff88000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff88000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0xffffec00
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMAC_GCFG,DMAC Global Configuration Register"
|
|
bitfld.long 0x00 4. " ARB_CFG ,Arbiter configuration" "Fixed,Round robin"
|
|
line.long 0x04 "DMAC_EN,DMAC Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,DMA Controller Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DMAC_SREQ,Software Single Request Register"
|
|
bitfld.long 0x08 15. " DSREQ7 ,Request a destination single transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " SSREQ7 ,Request a source single transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DSREQ6 ,Request a destination single transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " SSREQ6 ,Request a source single transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DSREQ5 ,Request a destination single transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " SSREQ5 ,Request a source single transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DSREQ4 ,Request a destination single transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " SSREQ4 ,Request a source single transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSREQ3 ,Request a destination single transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " SSREQ3 ,Request a source single transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSREQ2 ,Request a destination single transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " SSREQ2 ,Request a source single transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSREQ1 ,Request a destination single transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " SSREQ1 ,Request a source single transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DSREQ0 ,Request a destination single transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " SSREQ0 ,Request a source single transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x0C "DMAC_CREQ,Software Chunk Transfer Request Register"
|
|
bitfld.long 0x0C 15. " DCREQ7 ,Request a destination chunk transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " SCREQ7 ,Request a source chunk transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " DCREQ6 ,Request a destination chunk transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " SCREQ6 ,Request a source chunk transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DCREQ5 ,Request a destination chunk transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " SCREQ5 ,Request a source chunk transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DCREQ4 ,Request a destination chunk transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " SCREQ4 ,Request a source chunk transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DCREQ3 ,Request a destination chunk transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " SCREQ3 ,Request a source chunk transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DCREQ2 ,Request a destination chunk transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " SCREQ2 ,Request a source chunk transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DCREQ1 ,Request a destination chunk transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " SCREQ1 ,Request a source chunk transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DCREQ0 ,Request a destination chunk transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " SCREQ0 ,Request a source chunk transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x10 "DMAC_LAST,Software Last Transfer Flag Register"
|
|
bitfld.long 0x10 15. " DLAST7 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 14. " SLAST7 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DLAST6 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 12. " SLAST6 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DLAST5 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 10. " SLAST5 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DLAST4 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 8. " SLAST4 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DLAST3 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 6. " SLAST3 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DLAST2 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 4. " SLAST2 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DLAST1 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 2. " SLAST1 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DLAST0 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 0. " SLAST0 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMAC_EBCIMR, DMAC Error Buffer Transfer and Chained Buffer Transfer Mask Register"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " ERR7_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " ERR6_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " ERR5_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " ERR4_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " ERR3_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " ERR2_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " ERR1_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " ERR0_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CBTC7_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " CBTC6_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CBTC5_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CBTC4_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CBTC3_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CBTC2_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CBTC1_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CBTC0_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " BTC7_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " BTC6_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " BTC5_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " BTC4_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BTC3_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " BTC2_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " BTC1_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BTC0_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DMAC_EBCISR, DMAC Error Buffer Transfer and Chained Buffer Transfer Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ERR7 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CBTC7 ,Channel 7 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 14. " CBTC6 ,Channel 6 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CBTC5 ,Channel 5 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 12. " CBTC4 ,Channel 4 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CBTC3 ,Channel 3 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 10. " CBTC2 ,Channel 2 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBTC1 ,Channel 1 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 8. " CBTC0 ,Channel 0 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BTC7 ,Channel 7 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 6. " BTC6 ,Channel 6 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTC5 ,Channel 5 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 4. " BTC4 ,Channel 4 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " BTC3 ,Channel 3 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 2. " BTC2 ,Channel 2 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTC1 ,Channel 1 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 0. " BTC0 ,Channel 0 buffer transfer has terminated" "Not terminated,Terminated"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "DMAC_CHER, DMAC Channel Handler Enable Register"
|
|
bitfld.long 0x00 31. " KEEP7 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 30. " KEEP6 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KEEP5 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 28. " KEEP4 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KEEP3 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 26. " KEEP2 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KEEP1 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 24. " KEEP0 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
group.long 0x030++0x3
|
|
line.long 0x00 "DMAC_CHSR, DMAC Channel Handler Status Register"
|
|
bitfld.long 0x00 31. " STAL7 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 30. " STAL6 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " STAL5 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 28. " STAL4 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STAL3 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 26. " STAL2 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " STAL1 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 24. " STAL0 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EMPT7 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 22. " EMPT6 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMPT5 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 20. " EMPT4 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EMPT3 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 18. " EMPT2 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMPT1 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 16. " EMPT0 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " SUSP7_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " SUSP6_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUSP5_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SUSP4_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUSP3_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SUSP2_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUSP1_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SUSP0_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENA7_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENA5_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENA3_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENA2_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENA1_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ENA0_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x1f
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR0 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR0_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP0,DMAC Channel 0 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP0,DMAC Channel 0 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x1f
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR1 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR1_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP1,DMAC Channel 1 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP1,DMAC Channel 1 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x1f
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR2 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR2_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP2,DMAC Channel 2 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP2,DMAC Channel 2 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x1f
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR3 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR3_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP3,DMAC Channel 3 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP3,DMAC Channel 3 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0xDC++0x1f
|
|
line.long 0x00 "DMAC_SADDR4,DMAC Channel 4 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR4, DMAC Channel 4 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR4,DMAC Channel 4 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR4 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR4_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA4,DMAC Channel 4 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB4,DMAC Channel 4 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[4] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG4,DMAC Channel 4 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 4 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 4 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 4 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP4,DMAC Channel 4 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP4,DMAC Channel 4 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x104++0x1f
|
|
line.long 0x00 "DMAC_SADDR5,DMAC Channel 5 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR5, DMAC Channel 5 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR5,DMAC Channel 5 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR5 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR5_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA5,DMAC Channel 5 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB5,DMAC Channel 5 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[5] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG5,DMAC Channel 5 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 5 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 5 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 5 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP5,DMAC Channel 5 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP5,DMAC Channel 5 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x12C++0x1f
|
|
line.long 0x00 "DMAC_SADDR6,DMAC Channel 6 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR6, DMAC Channel 6 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR6,DMAC Channel 6 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR6 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR6_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA6,DMAC Channel 6 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB6,DMAC Channel 6 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[6] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG6,DMAC Channel 6 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 6 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 6 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 6 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP6,DMAC Channel 6 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP6,DMAC Channel 6 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x154++0x1f
|
|
line.long 0x00 "DMAC_SADDR7,DMAC Channel 7 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR7, DMAC Channel 7 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR7,DMAC Channel 7 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR7 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR7_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA7,DMAC Channel 7 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB7,DMAC Channel 7 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[7] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG7,DMAC Channel 7 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 7 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 7 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 7 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP7,DMAC Channel 7 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP7,DMAC Channel 7 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
textline ""
|
|
width 0xb
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
tree "USART0"
|
|
base ad:0xfff8c000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff8c000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l(ad:(0xfff8c000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US0_MAN,USART0xfff8c000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((0==3)&&((d.l(ad:0xfff8c000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((0==3)&&((d.l(ad:0xfff8c000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART0_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0xfff90000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff90000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l(ad:(0xfff90000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US1_MAN,USART0xfff90000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((1==3)&&((d.l(ad:0xfff90000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((1==3)&&((d.l(ad:0xfff90000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART1_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0xfff94000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff94000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l(ad:(0xfff94000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US2_MAN,USART0xfff94000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((2==3)&&((d.l(ad:0xfff94000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((2==3)&&((d.l(ad:0xfff94000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART2"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART2_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Pointer Register"
|
|
line.long 0x04 "USART2_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART2_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Pointer Register"
|
|
line.long 0x0c "USART2_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART2_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Next Pointer Register"
|
|
line.long 0x14 "USART2_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART2_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART2_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART2_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART2_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "UASART3"
|
|
base ad:0xfff98000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff98000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l(ad:(0xfff98000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US3_IMR,USART3 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US3_CSR,USART3 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US3_RHR,USART3 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US3_THR,USART3 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US3_BRGR,USART3 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US3_RTOR,USART3 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US3_TTGR,USART3 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US3_FIDI,USART3 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US3_NER,USART3 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US3_IF,USART3 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US3_MAN,USART0xfff98000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((3==3)&&((d.l(ad:0xfff98000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((3==3)&&((d.l(ad:0xfff98000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART3"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART3_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Pointer Register"
|
|
line.long 0x04 "USART3_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART3_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Pointer Register"
|
|
line.long 0x0c "USART3_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART3_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Next Pointer Register"
|
|
line.long 0x14 "USART3_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART3_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART3_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART3_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART3_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0xfffb8000
|
|
width 0x9
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PWM_MR,PWM Mode Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0xc++3
|
|
line.long 0x0 "PWM_SR,PWM Status Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM Output for Channel 3 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM Output for Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM Output for Channel 1 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM Output for Channel 0 Enable" "Disabled,Enabled"
|
|
group.long 0x18++3
|
|
line.long 0x0 "PWM_IMR,PWM Interrupt Mask Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Enable Interrupt for PWM Channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Enable Interrupt for PWM Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Enable Interrupt for PWM Channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,Enable Interrupt for PWM Channel 0" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PWM_ISR,PWM Interrupt Status Register"
|
|
in
|
|
wgroup 0x0++0x0
|
|
width 0xb
|
|
tree "Channel 0 Registers"
|
|
group.long (0x200+(0*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR0,PWM Channel 0 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD0,PWM Channel 0 Period Register"
|
|
rgroup.long (0x20C+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
wgroup.long (0x210+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD0,PWM Channel 0 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 1 Registers"
|
|
group.long (0x200+(1*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR1,PWM Channel 1 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD1,PWM Channel 1 Period Register"
|
|
rgroup.long (0x20C+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
wgroup.long (0x210+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD1,PWM Channel 1 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 2 Registers"
|
|
group.long (0x200+(2*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR2,PWM Channel 2 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD2,PWM Channel 2 Period Register"
|
|
rgroup.long (0x20C+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
wgroup.long (0x210+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD2,PWM Channel 2 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 3 Registers"
|
|
group.long (0x200+(3*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR3,PWM Channel 3 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD3,PWM Channel 3 Period Register"
|
|
rgroup.long (0x20C+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
wgroup.long (0x210+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD3,PWM Channel 3 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree.end
|
|
tree.open "TC (Timer/Counter)"
|
|
tree "TC Channel 0"
|
|
base ad:0xfff7c000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
base ad:0xfff7c040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
base ad:0xfff7c080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC0/TC1/TC2)"
|
|
base ad:0xfff7c000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 3"
|
|
base ad:0xfffd4000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffd4000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffd4000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
base ad:0xfffd4040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffd4040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffd4040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
base ad:0xfffd4080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffd4080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffd4080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC3/TC4/TC5)"
|
|
base ad:0xfffd4000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "SSC (Synchronous Serial Controller)"
|
|
tree "SSC0"
|
|
base ad:0xfff9c000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC0_CR,SSC0 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC0_CMR,SSC0 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC0_RCMR,SSC0 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC0_RFMR,SSC0 Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC0_TCMR,SSC0 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC0_TFMR,SSC0 Transmit Frame Mode Register"
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC0_THR,SSC0 Transmit Holding Register"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC0_TSHR,SSC0 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC0_RC0R,SSC0 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC0_RC1R,SSC0 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC0_SR,SSC0 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC0_IMR,SSC0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_SSC0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC0_RPR,Synchronous Serial Controller 0 Receive Pointer Register"
|
|
line.long 0x04 "SSC0_RCR,Synchronous Serial Controller 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC0_TPR,Synchronous Serial Controller 0 Transmit Pointer Register"
|
|
line.long 0x0c "SSC0_TCR,Synchronous Serial Controller 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC0_RNPR,Synchronous Serial Controller 0 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC0_RNCR,Synchronous Serial Controller 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC0_TNPR,Synchronous Serial Controller 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC0_TNCR,Synchronous Serial Controller 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC0_PTCR,Synchronous Serial Controller 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC0_PTSR,Synchronous Serial Controller 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SSC1"
|
|
base ad:0xfffa0000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC1_CR,SSC1 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC1_CMR,SSC1 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC1_RCMR,SSC1 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC1_RFMR,SSC1 Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC1_TCMR,SSC1 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC1_TFMR,SSC1 Transmit Frame Mode Register"
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC1_THR,SSC1 Transmit Holding Register"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC1_TSHR,SSC1 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC1_RC0R,SSC1 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC1_RC1R,SSC1 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC1_SR,SSC1 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC1_IMR,SSC1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_SSC1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC1_RPR,Synchronous Serial Controller 1 Receive Pointer Register"
|
|
line.long 0x04 "SSC1_RCR,Synchronous Serial Controller 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC1_TPR,Synchronous Serial Controller 1 Transmit Pointer Register"
|
|
line.long 0x0c "SSC1_TCR,Synchronous Serial Controller 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC1_RNPR,Synchronous Serial Controller 1 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC1_RNCR,Synchronous Serial Controller 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC1_TNPR,Synchronous Serial Controller 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC1_TNCR,Synchronous Serial Controller 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC1_PTCR,Synchronous Serial Controller 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC1_PTSR,Synchronous Serial Controller 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "MCI (MultiMedia Card Interface)"
|
|
tree "MCI 0"
|
|
base ad:0xfff80000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_MCI 0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI0_RPR,MultiMedia Card Interface 0 Receive Pointer Register"
|
|
line.long 0x04 "MCI0_RCR,MultiMedia Card Interface 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI0_TPR,MultiMedia Card Interface 0 Transmit Pointer Register"
|
|
line.long 0x0c "MCI0_TCR,MultiMedia Card Interface 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI0_RNPR,MultiMedia Card Interface 0 Receive Next Pointer Register"
|
|
line.long 0x14 "MCI0_RNCR,MultiMedia Card Interface 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI0_TNPR,MultiMedia Card Interface 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI0_TNCR,MultiMedia Card Interface 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI0_PTCR,MultiMedia Card Interface 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI0_PTSR,MultiMedia Card Interface 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "MCI 1"
|
|
base ad:0xfffd0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_MCI 1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI1_RPR,MultiMedia Card Interface 1 Receive Pointer Register"
|
|
line.long 0x04 "MCI1_RCR,MultiMedia Card Interface 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI1_TPR,MultiMedia Card Interface 1 Transmit Pointer Register"
|
|
line.long 0x0c "MCI1_TCR,MultiMedia Card Interface 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI1_RNPR,MultiMedia Card Interface 1 Receive Next Pointer Register"
|
|
line.long 0x14 "MCI1_RNCR,MultiMedia Card Interface 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI1_TNPR,MultiMedia Card Interface 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI1_TNCR,MultiMedia Card Interface 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI1_PTCR,MultiMedia Card Interface 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI1_PTSR,MultiMedia Card Interface 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "EMAC (Ethernet MAC 10/100)"
|
|
base ad:0xfffbc000
|
|
width 0xC
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EMAC_NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit Halt" "No effect,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Transmission Start" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back Pressure" "No effect,Collisions"
|
|
bitfld.long 0x00 7. " WESTAT ,Statistics Registers Write Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Statistics Registers Increment" "No effect,Incremented"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Statistics Registers Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Loopback Local" "No loopback,Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LB ,Loopback" "No loopback,Loopback"
|
|
line.long 0x04 "EMAC_NCFGR,Network Configuration Register"
|
|
bitfld.long 0x04 19. " IRXFCS ,RX FCS Ignore" "Normal,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Half-Duplex Receive Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DRFCS ,Receive FCS Discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length Field Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " RBOF ,Receive Buffer Offset" "No offset,1-byte,2-byte,3-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry Test" "Normal,Retry"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC Clock Divider" "MCK/8,MCK/16,MCK/32,MCK/64"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BIG ,1536 Bytes Frames Receive" "Not received,Received"
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,All Frames Copy" "Not copied,Copied"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full Duplex Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mb/s,100 Mb/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMAC_NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic IDLE" "Running,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIO ,MDIO Pin Status" "Low,High"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "EMAC_TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No underrun,Underrun"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BEX ,Buffers Mid Frame Exhaust" "Not exhausted,Exhausted"
|
|
bitfld.long 0x00 3. " TGO ,Transmit Go" "Not activated,Activated"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RLE ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
eventfld.long 0x00 1. " COL ,Collision Occurence" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "Not read,Read"
|
|
line.long 0x04 "EMAC_RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 4. " ADDR ,Receive Buffer Queue Pointer Address"
|
|
if (((data.long(ad:(0xfffbc000+0x14)))&0x8)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "EMAC_RSR,Receive Status Register"
|
|
eventfld.long 0x0 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0 1. " REC ,Frame Receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x0 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x0 "EMAC_ISR,Interrupt Status Register"
|
|
in
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EMAC_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " WOL_set/clr , Wake On LAN" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause Time Zero" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PFR_set/clr ,Pause Frame Receive" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " HRESP_set/clr ,Hresp Not OK" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive Overrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 07. -0x8 07. -0x4 7. " TCOMP_set/clr ,Transmit Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 06. -0x8 06. -0x4 6. " TXERR_set/clr ,Transmit Buffers Mid-Frame Exhaust Interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 05. -0x8 05. -0x4 5. " RLE_set/clr ,Retry Limit Exceed" "Enabled,Disabled"
|
|
setclrfld.long 0x0 04. -0x8 04. -0x4 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 03. -0x8 03. -0x4 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Enabled,Disabled"
|
|
setclrfld.long 0x0 02. -0x8 02. -0x4 2. " RXUBR_set/clr ,Receive Used Bit Read" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 01. -0x8 01. -0x4 1. " RCOMP_set/clr ,Receive Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 00. -0x8 00. -0x4 0. " MFD_set/clr ,Management Frame Send" "Enabled,Disabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "EMAC_MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. " SOF ,Frame Start" "Not valid,Valid,Not valid,Not valid"
|
|
bitfld.long 0x0 28.--29. " RW ,Read/Write" "Reserved,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--27. 1. " PHYA ,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. " REGA ,Register Address"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " CODE ,Code" "00,01,10,11"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,PHY Data"
|
|
line.long 0x4 "EMAC_PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "EMAC_HRB,Hash Register Bottom"
|
|
line.long 0x04 "EMAC_HRT,Hash Register Top"
|
|
tree "Specific Address Registers"
|
|
textline " "
|
|
group.long 0x98++0x1F
|
|
line.long 0x0 "EMAC_SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x4 "EMAC_SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x8 "EMAC_SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0xC "EMAC_SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x10 "EMAC_SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x14 "EMAC_SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x18 "EMAC_SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x1C "EMAC_SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "EMAC_TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TID ,Type ID Checking"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "EMAC_USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Transceiver Input Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RMII ,RMII Operation Mode Enable" "MII,RMII"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "EMAC_WOL, Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI , Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 , Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP , ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG , Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " IP , ARP request IP address"
|
|
tree "EMAC Statistic Registers"
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "EMAC_PFR,Pause Frames Received Register"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "EMAC_FTO,Frames Transmitted Ok Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x0 "EMAC_SCF,Single Collision Frames Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "EMAC_MCF,Multicollision Frames Register"
|
|
in
|
|
hgroup.long 0x4c++0x3
|
|
hide.long 0x0 "EMAC_FRO,Frames Received Ok Register"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "EMAC_FCSE,Frames Check Sequence Errors Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x0 "EMAC_ALE,Alignment Errors Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x0 "EMAC_DTF,Deferred Transmission Frames Register"
|
|
in
|
|
hgroup.long 0x5c++0x3
|
|
hide.long 0x0 "EMAC_LCOL,Late Collisions Register"
|
|
in
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_ECOL,Excessive Collisions Register"
|
|
in
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "EMAC_TUND,Transmit Underrun Errors Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "EMAC_CSE,Carrier Sense Errors Register"
|
|
in
|
|
hgroup.long 0x6c++0x3
|
|
hide.long 0x0 "EMAC_RRE,Receive Resource Errors Register"
|
|
in
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROV,Receive Overrun Errors Register"
|
|
in
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x0 "EMAC_RSE,Receive Symbol Errors Register"
|
|
in
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x0 "EMAC_ELE,Excessive Length Errors Register"
|
|
in
|
|
hgroup.long 0x7c++0x3
|
|
hide.long 0x0 "EMAC_RJA,Receive Jabbers Register"
|
|
in
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x0 "EMAC_USF,Undersize Frames Register"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x0 "EMAC_STE,SQE Test Errors Register"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x0 "EMAC_RLE,Received Length Field Mismatch Register"
|
|
in
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
tree.end
|
|
tree.end
|
|
tree.open "UHPHS OHCI (USB High Speed Host Port)"
|
|
base ad:0x00700000
|
|
width 20.
|
|
tree "Control and Status Partition"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IR ,Interrupt Routing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio (Control/Bulk)" "1 : 1,2 : 1,3 : 1,4 : 1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
width 20.
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
eventfld.long 0x00 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "HCINTERRUPTENABLE,HcInterruptEnable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OC ,OC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,RHSC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,FNO Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,UE Interrupt Enable" "Inore,Enabled"
|
|
bitfld.long 0x00 3. " RD ,RD Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 2. " SF ,SF Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,WDH Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 0. " SO ,SO Interrupt Enable" "Ignore,Enabled"
|
|
line.long 0x04 "HCINTERRUPTDISABLE,HcInterruptDisable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 30. " OC ,OC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 6. " RHSC ,RHSC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 5. " FNO ,FNO Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,UE Interrupt Disable" "Inore,Disabled"
|
|
bitfld.long 0x04 3. " RD ,RD Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 2. " SF ,SF Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,WDH Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 0. " SO ,SO Interrupt Disable" "Ignore,Disabled"
|
|
tree.end
|
|
tree "Memory Pointer Partition"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "HCHCCA,Hc HCCA Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
line.long 0x04 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PCED ,Period Current ED"
|
|
line.long 0x08 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " CHED ,Control Head ED"
|
|
line.long 0x0c "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " CCED ,Control Current ED"
|
|
line.long 0x10 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
line.long 0x14 "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x14 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Done Head"
|
|
tree.end
|
|
width 17.
|
|
tree "Frame Counter Partition"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Threshold"
|
|
tree.end
|
|
width 20.
|
|
tree "Root Hub Partition"
|
|
if (((d.l(ad:(0x00700000+0x48)))&0x1100)==0x0)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00700000+0x48)))&0x1100)==0x1000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00700000+0x48)))&0x1100)==0x100)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
endif
|
|
width 20.
|
|
if (((d.l(ad:(0x00700000+0x48)))&0x200)==0x200)
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 31. " PPCM[15] ,Port Power Control Mask[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " PPCM[14] ,Port Power Control Mask[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PPCM[13] ,Port Power Control Mask[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " PPCM[12] ,Port Power Control Mask[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PPCM[11] ,Port Power Control Mask[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " PPCM[10] ,Port Power Control Mask[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPCM[9] ,Port Power Control Mask[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PPCM[8] ,Port Power Control Mask[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PPCM[7] ,Port Power Control Mask[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PPCM[6] ,Port Power Control Mask[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCM[5] ,Port Power Control Mask[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " PPCM[4] ,Port Power Control Mask[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port Power Control Mask[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port Power Control Mask[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port Power Control Mask[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CCIC ,Over Current Indicator Change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local Power Status Change/Set Global Power" "No effect,On all ports"
|
|
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Over Current Indicator" "Low,High"
|
|
bitfld.long 0x00 0. " LPS ,Local Power Status/Clear Global Power" "No effect,Off all ports"
|
|
width 20.
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[0],Hc Rh Port Status [0]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[1],Hc Rh Port Status [1]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[2],Hc Rh Port Status [2]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[3],Hc Rh Port Status [3]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[4],Hc Rh Port Status [4]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[5],Hc Rh Port Status [5]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[6],Hc Rh Port Status [6]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[7],Hc Rh Port Status [7]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[8],Hc Rh Port Status [8]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[9],Hc Rh Port Status [9]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[10],Hc Rh Port Status [10]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[11],Hc Rh Port Status [11]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[12],Hc Rh Port Status [12]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[13],Hc Rh Port Status [13]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[14],Hc Rh Port Status [14]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "UHPHS EHCI (USB High Speed Host Port)"
|
|
base ad:0x00800000
|
|
width 12.
|
|
rgroup.word 0x00++0x01 "Host Controller Capability Registers"
|
|
line.word 0x00 "HCIVERSION,Version Of The EHCI Standard Register"
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "CAPLENGTH,Size Of The Entire Capability Register Area"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "HCSPARAMS,Host Controller Structure Parameters Register"
|
|
bitfld.long 0x00 20.--23. " DPN ,Debug Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " P_INDI ,Port Indicator" "Not supported,Supported"
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " PRR ,Port Routing Rule" "N_PCC,HCSP-PORTROUTE"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,N_PORTS" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HCCPARAMS,Parameters Relating Host Controller Capabilities Register"
|
|
bitfld.long 0x04 19. " FPLC , 32-Frame Periodic List Capability" "Not supported,Supported"
|
|
bitfld.long 0x04 18. " PPCEC , Per-Port Change Event Capability" "Not supported,Supported"
|
|
bitfld.long 0x04 17. " LPMC , Link Power Management Capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 16. " HPC , Hardware Prefetch Capability" "Not supported,Supported"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "Not cached,Reserved,2 microframes,Reserved,Reserved,Reserved,Reserved,Reserved,Entire frame,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2. " ASPC ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
bitfld.long 0x04 1. " PFLF ,Programmable Frame List Flag" "Fixed 1024,Changed 512-256"
|
|
bitfld.long 0x04 0. " 64AC ,64-Bit Addressing Capability" "32-bit,64-bit"
|
|
width 16.
|
|
if (((data.long(ad:0x00800000+0x04))&0x80)==0x80)
|
|
rgroup.long 0x0c++0x07
|
|
line.long 0x00 "HCSP-PORTROUTE0,Companion Host Controller Assign Register"
|
|
line.long 0x04 "HCSP-PORTROUTE1,Companion Host Controller Assign Register"
|
|
else
|
|
hgroup.long 0x0c++0x07
|
|
hide.long 0x00 "HCSP-PORTROUTE0,Companion Host Controller Assign"
|
|
hide.long 0x04 "HCSP-PORTROUTE1,Companion Host Controller Assign"
|
|
endif
|
|
width 12.
|
|
if (((d.l(ad:(0x00800000+0x08)))&0x2)==0x2)
|
|
group.long 0x10++0x3 "Host Controller Operational Registers"
|
|
line.long 0x00 "USBCMD,USBCMD Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host-Initiated Resume Duration" "50,125,200,275,350,425,500,575,650,725,800,875,950,1025,1100,1175"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 15. " PPCEE , Per-Port Change Events Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FSP , Fully Synchronized Prefetch" "Not supported,Supported"
|
|
bitfld.long 0x00 13. " ASPE , Asynchronous Schedule Prefetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PSPE , Periodic Schedule Prefetch Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASPMC ,RO Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "1024,512,256,32"
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
else
|
|
group.long 0x10++0x3 "Host Controller Operational Registers"
|
|
line.long 0x00 "USBCMD,USBCMD Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host-Initiated Resume Duration" "50,125,200,275,350,425,500,575,650,725,800,875,950,1025,1100,1175"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 15. " PPCEE , Per-Port Change Events Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FSP , Fully Synchronized Prefetch" "Not supported,Supported"
|
|
bitfld.long 0x00 13. " ASPE , Asynchronous Schedule Prefetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PSPE , Periodic Schedule Prefetch Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASPMC ,RO Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "1024,512,256,?..."
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
endif
|
|
group.long 0x14++0x017
|
|
line.long 0x00 "USBSTS,Status Information Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PCD , Port-n Change Detect"
|
|
bitfld.long 0x00 15. " ASS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " R ,Reclamation" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Run/Stop==1,Run/Stop==0"
|
|
bitfld.long 0x00 5. " IAA ,Interrupt Async Advance" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HSE ,Host System Error" "No error,Error"
|
|
bitfld.long 0x00 3. " FLR ,Frame List Rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCD ,Port Change Detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEI ,USB Error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "USBINTR,On/off Of Hardware Interrupts Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " PCEE , Port-n Change Event Enable"
|
|
bitfld.long 0x04 5. " IAAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " HSEE ,Host System Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PCDE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " UEIE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " UIE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FRINDEX, Current Frame Number Register"
|
|
hexmask.long.word 0x08 0.--13. 1. " FI ,Frame Index"
|
|
width 18.
|
|
line.long 0x0C "CTRLDSSEGMENT,CTRLDSSEGMENT Register"
|
|
line.long 0x10 "PERIODICLISTBASE,Periodic Framelist Base Address Register"
|
|
hexmask.long 0x10 12.--31. 0x1000 " BA ,Base Address"
|
|
line.long 0x14 "ASYNCLISTADDR,Queue Heads Pointer"
|
|
hexmask.long 0x14 5.--31. 0x20 " LPL ,Link Pointer Low"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CONFIGFLAG,Ownership Specification Register"
|
|
bitfld.long 0x00 0. " CF ,Config Flag" "Each port to cHC,All ports to eHC"
|
|
if ((((data.long(ad:0x00800000+0x04))&0x80000)==0x80000)&&(((data.long(ad:0x00800000+0x54))&0x5)==0x1))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
hexmask.long 0x00 25.--31. 1. " DA , Device Address"
|
|
bitfld.long 0x00 23.--24. " SS , Suspend Status" "Success,Not yet,Not supported,Timeout/Error"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
bitfld.long 0x00 9. " SUL1 , Suspend using L1" "L2,L1"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Detected,Not detected"
|
|
elif ((((data.long(ad:0x00800000+0x04))&0x80000)==0x80000)&&(((data.long(ad:0x00800000+0x54))&0x5)!=0x1))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Detected,Not detected"
|
|
elif ((((data.long(ad:0x00800000+0x04))&0x80000)==0x00)&&(((data.long(ad:0x00800000+0x54))&0x5)==0x1))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Detected,Not detected"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Detected,Not detected"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UDPHS (USB High Speed Device Port)"
|
|
base ad:0xfff78000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UDPHS_CTRL,UDPHS Control Register"
|
|
bitfld.long 0x00 11. " PULLD_DIS , Pull-Down Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " REWAKEUP , Send Remote Wake Up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DETACH , Detach Command" "Attached,Detached"
|
|
bitfld.long 0x00 8. " EN_UDPHS , UDPHS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FADDR_EN , Function Address Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " DEV_ADDR , UDPHS Address"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "UDPHS_FNUM,UDPHS Frame Number Register"
|
|
bitfld.long 0x00 31. " FNUM_ERR , Frame Number CRC Error " "No error,Error"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRAME_NUMBER , Frame Number as defined in the Packet Field Formats"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MICRO_FRAME_NUM , Microframe Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UDPHS_IEN,UDPHS Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SOF , SOF Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro-SOF Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "UDPHS_INTSTA,UDPHS Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPEED , Speed Status" "Full,High"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "UDPHS_CLRINT,UDPHS Clear Interrupt Register"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "UDPHS_EPTRST,UDPHS Endpoints Reset Register"
|
|
bitfld.long 0x04 6. " EPT_6 , Endpoint 6 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " EPT_5 , Endpoint 5 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EPT_4 , Endpoint 4 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 3. " EPT_3 , Endpoint 3 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EPT_2 , Endpoint 2 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 1. " EPT_1 , Endpoint 1 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EPT_0 , Endpoint 0 Reset" "No effect,Reset"
|
|
group.long 0xe0++0x03
|
|
line.long 0x00 "UDPHS_TST,UDPHS Test Register"
|
|
bitfld.long 0x00 5. " OPMODE2 , OpMode2" "No effect,OpMode"
|
|
bitfld.long 0x00 4. " TST_PKT , Test Packet Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TST_K , Test K Mode" "No effect,Test"
|
|
bitfld.long 0x00 2. " TST_J , Test J Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SPEED_CFG , Speed Configuration" "Normal Mode,Reserved,High Speed,Full Speed"
|
|
rgroup.long 0xf0++0xb
|
|
line.long 0x00 "UDPHS_IPNAME1,UDPHS Name1 Register"
|
|
line.long 0x04 "UDPHS_IPNAME2,UDPHS Name2 Register"
|
|
width 18.
|
|
line.long 0x08 "UDPHS_IPFEATURES,UDPHS Features Register"
|
|
bitfld.long 0x08 31. " ISO_EPT_15 ,Endpoint15 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 30. " ISO_EPT_14 ,Endpoint14 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ISO_EPT_13 ,Endpoint13 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 28. " ISO_EPT_12 ,Endpoint12 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ISO_EPT_11 ,Endpoint11 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 26. " ISO_EPT_10 ,Endpoint10 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ISO_EPT_9 ,Endpoint9 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 24. " ISO_EPT_8 ,Endpoint8 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ISO_EPT_7 ,Endpoint7 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 22. " ISO_EPT_6 ,Endpoint6 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ISO_EPT_5 ,Endpoint5 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 20. " ISO_EPT_4 ,Endpoint4 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ISO_EPT_3 ,Endpoint3 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 18. " ISO_EPT_2 ,Endpoint2 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 17. " ISO_EPT_1 ,Endpoint1 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 16. " DATAB16_8 ,UTMI DataBus16_8" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x08 15. " BW_DPRAM ,DPRAM Byte Write Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 12.--14. " FIFO_MAX_SIZE ,DPRAM Size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " DMA_FIFO_DEPTH ,DMA FIFO Depth in Words" "16 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words"
|
|
bitfld.long 0x08 7. " DMA_B_SIZ ,DMA Buffer Size" "16 bits,24 bits"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " DMA_CHANNEL_NBR ,Number of DMA Channels" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--3. " EPT_NBR_MAX ,Max Number of Endpoints" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 19.
|
|
tree "Endpoint 0"
|
|
if ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x0))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x100)))&0x30)==0x20)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x114++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA0,UDPHS Endpoint Set Status Register 0"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA0,UDPHS Endpoint Clear Status Register 0"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x100)))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x100)))&0x8)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x100)))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 1"
|
|
if ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x0))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x120)))&0x30)==0x20)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x134++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA1,UDPHS Endpoint Set Status Register 1"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA1,UDPHS Endpoint Clear Status Register 1"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x120)))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x120)))&0x8)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x120)))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 2"
|
|
if ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x0))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x140)))&0x30)==0x20)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x154++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA2,UDPHS Endpoint Set Status Register 2"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA2,UDPHS Endpoint Clear Status Register 2"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x140)))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x140)))&0x8)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x140)))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 3"
|
|
if ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x0))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x160)))&0x30)==0x20)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x174++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA3,UDPHS Endpoint Set Status Register 3"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA3,UDPHS Endpoint Clear Status Register 3"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x160)))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x160)))&0x8)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x160)))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 4"
|
|
if ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x0))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x180)))&0x30)==0x20)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x194++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA4,UDPHS Endpoint Set Status Register 4"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA4,UDPHS Endpoint Clear Status Register 4"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x180)))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x180)))&0x8)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x180)))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 5"
|
|
if ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x0))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x20)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1B4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA5,UDPHS Endpoint Set Status Register 5"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA5,UDPHS Endpoint Clear Status Register 5"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1A0)))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1A0)))&0x8)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x1A0)))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 6"
|
|
if ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x0))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x20)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1D4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA6,UDPHS Endpoint Set Status Register 6"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA6,UDPHS Endpoint Clear Status Register 6"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1C0)))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1C0)))&0x8)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x1C0)))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "DMA channel 1"
|
|
group.long 0x310++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC1, UDPHS DMA Channel Address Register 1"
|
|
line.long 0x04 "UDPHS_DMAADDRESS1, UDPHS DMA Next Descriptor Address Register 1"
|
|
line.long 0x08 "UDPHS_DMACONTROL1, UDPHS DMA Channel Control Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x310+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS1,UDPHS DMA Channel Status Register 1"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 2"
|
|
group.long 0x320++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC2, UDPHS DMA Channel Address Register 2"
|
|
line.long 0x04 "UDPHS_DMAADDRESS2, UDPHS DMA Next Descriptor Address Register 2"
|
|
line.long 0x08 "UDPHS_DMACONTROL2, UDPHS DMA Channel Control Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x320+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS2,UDPHS DMA Channel Status Register 2"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 3"
|
|
group.long 0x330++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC3, UDPHS DMA Channel Address Register 3"
|
|
line.long 0x04 "UDPHS_DMAADDRESS3, UDPHS DMA Next Descriptor Address Register 3"
|
|
line.long 0x08 "UDPHS_DMACONTROL3, UDPHS DMA Channel Control Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x330+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS3,UDPHS DMA Channel Status Register 3"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 4"
|
|
group.long 0x340++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC4, UDPHS DMA Channel Address Register 4"
|
|
line.long 0x04 "UDPHS_DMAADDRESS4, UDPHS DMA Next Descriptor Address Register 4"
|
|
line.long 0x08 "UDPHS_DMACONTROL4, UDPHS DMA Channel Control Register 4"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x340+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS4,UDPHS DMA Channel Status Register 4"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 5"
|
|
group.long 0x350++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC5, UDPHS DMA Channel Address Register 5"
|
|
line.long 0x04 "UDPHS_DMAADDRESS5, UDPHS DMA Next Descriptor Address Register 5"
|
|
line.long 0x08 "UDPHS_DMACONTROL5, UDPHS DMA Channel Control Register 5"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x350+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS5,UDPHS DMA Channel Status Register 5"
|
|
in
|
|
tree.end
|
|
tree.end
|
|
tree "ISI (Image Sensor Interface)"
|
|
base ad:0xfffb4000
|
|
width 14.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "ISI_CFG1,ISI Configuration 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of Frame Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of Line Delay"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "4 beats,4/8 beats,4/8/16 beats,?..."
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DISCR ,Disable Codec Request" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate captured" "All,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization" "No CRC,CRC"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising,Falling"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
line.long 0x04 "ISI_CFG2,ISI Configuration 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,RGB Pattern" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,YCC Image Data" "Default,Mode1,Mode2,Mode3"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--26. 1. " IM_HSIZE ,Horizontal size of the Image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB Swap" "D7 -> R7,D0 -> R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Gray Scale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8 24 bits,5:6:5 16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,GS Mode" "2 pixels per word,1 pixel per word"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. " IM_VSIZE ,Vertical size of the Image sensor"
|
|
line.long 0x08 "ISI_PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x08 16.--25. 1. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x08 0.--9. 1. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x0c "ISI_PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x10 "ISI_Y2R_SET0,ISI Color Space Conversion YCrCb to RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color Space Conversion Matrix Coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "ISI_Y2R_SET1,ISI Color Space Conversion YCrCb to RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " Cboff ,Color Space Conversion Blue Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " Croff ,Color Space Conversion Red Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 12. " Yoff ,Color Space Conversion Luminance default offset" "No offset,Offset=128"
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
line.long 0x18 "ISI_R2Y_SET0,ISI Color Space Conversion RGB to YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " Roff ,Color Space Conversion Red component offset" "No offset,Offset=16"
|
|
hexmask.long.byte 0x18 16.--23. 1. " C2 ,Color Space Conversion Matrix coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " C1 ,Color Space Conversion Matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " C0 ,Color Space Conversion Matrix coefficient C0"
|
|
line.long 0x1c "ISI_R2Y_SET1,ISI Color Space Conversion RGB to YCrCb Set 1 Register"
|
|
bitfld.long 0x1c 24. " Goff ,Color Space Conversion Green component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " C5 ,Color Space Conversion Matrix coefficient C5"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 8.--15. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " C3 ,Color Space Conversion Matrix coefficient C3"
|
|
line.long 0x20 "ISI_R2Y_SET2,ISI Color Space Conversion RGB to YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " Boff ,Color Space Conversion Blue component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x20 16.--23. 1. " C8 ,Color Space Conversion Matrix coefficient C8"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " C7 ,Color Space Conversion Matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--7. 1. " C6 ,Color Space Conversion Matrix coefficient C6"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "ISI_CTRL,ISI Control Register"
|
|
bitfld.long 0x00 8. " ISI_CDC ,ISI Codec Request" "No effect,Enable"
|
|
bitfld.long 0x00 2. " ISI_SRST ,ISI Software Reset Request" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISI_DIS ,ISI Module Disable Request" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ISI_EN ,ISI Module Enable Request" "No effect,Enable"
|
|
hgroup.long 0x28++0x3
|
|
hide.long 0x00 "ISI_STATUS,ISI Status Register"
|
|
in
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "ISI_IMR,ISI Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " FR_OVR_set/clr ,Frame Rate Overrun Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " CRC_ERR_set/clr ,CRC Synchronization Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " C_OVR_set/clr ,FIFO Codec Overflow Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " P_OVR_set/clr ,FIFO Preview Overflow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " CXFR_DONE_set/clr ,Codec DMA Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " PXFR_DONE_set/clr ,Preview DMA Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " VSYNC_set/clr ,Vertical Synchronization Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " SRST_set/clr ,Software Reset Completed Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIS_DONE_set/clr ,Module Disable Request Termination Interrupt" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DMA_CHSR,DMA Channel Status Register"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " C_CH_S_set/clr ,Preview DMA channel" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " P_CH_S_set/clr ,Codec DMA channel" "Disabled,Enabled"
|
|
group.long 0x44++0x17
|
|
line.long 0x00 "DMA_P_ADDR,DMA Preview Base Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " P_ADDR ,Preview Image Base Address"
|
|
line.long 0x04 "DMA_P_CTRL ,DMA Preview Control Register"
|
|
bitfld.long 0x04 3. " P_DONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " P_IEN ,Transfer Done Flag Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P_WB ,Descriptor Writeback Control Field" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " P_FETCH ,Descriptor Fetch Control Field" "Disabled,Enabled"
|
|
line.long 0x08 "DMA_P_DSCR,DMA Preview Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x4 " P_DSCR ,Preview Descriptor Base Address"
|
|
line.long 0x0c "DMA_C_ADDR,DMA Codec Base Address Register"
|
|
hexmask.long 0x0c 2.--31. 0x4 " C_ADDR ,Preview Image Base Address"
|
|
line.long 0x10 "DMA_C_CTRL ,DMA Codec Control Register"
|
|
bitfld.long 0x10 3. " C_DONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x10 2. " C_IEN ,Transfer Done Flag Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " C_WB ,Descriptor Writeback Control Field" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " C_FETCH ,Descriptor Fetch Control Field" "Disabled,Enabled"
|
|
line.long 0x14 "DMA_C_DSCR,DMA Codec Descriptor Address Register"
|
|
hexmask.long 0x14 2.--31. 0x4 " C_DSCR ,Codec Descriptor Base Address"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "ISI_WPCR,ISI Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x04 "ISI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "TSADCC (Touch Screen ADC Controller)"
|
|
base ad:0xfffb0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TSADCC_CR,TSADCC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TSADCC_MR,TSADCC Mode Register"
|
|
bitfld.long 0x00 28.--31. " PENDBC ,Pen Detect debouncing period" "1/clock,2/clock,4/clock,8/clock,16/clock,32/clock,64/clock,128/clock,256/clock,512/clock,1024/clock,2048/clock,4096/clock,8192/clock,16384/clock,32768/clock"
|
|
bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock,16/clock"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " STARTUP ,Start Up Time"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRES ,Pressure Measurement Selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PENDET , Pen Detect Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDCEN ,PDC transfer in Touchscreen/Interleaved mode or Manual mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TSAMOD , Touch Screen ADC Mode" "ADC,Touch Screen,Interleaved,Manual"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TSADCC_TRGR,TSADCC Trigger Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TRGPER , Trigger Period"
|
|
bitfld.long 0x00 0.--2. " TRGMOD , Trigger Mode " "No trigger,Rising Edge,Falling Edge,Any Edge,Pen Detect,Periodic,Continuous,?..."
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TSADCC_TSR,TSADCC Touch Screen Register"
|
|
bitfld.long 0x00 24.--27. " TSSHTIM , Sample & Hold Time for Touch Screen Channels" "1/clock,1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock"
|
|
bitfld.long 0x00 0.--3. " TSFREQ ,Touch Screen Frequency in Interleaved Mode" "Trigger freq/6,Trigger freq/6,Trigger freq/8,Trigger freq/16,Trigger freq/32,Trigger freq/64,Trigger freq/128,Trigger freq/256,Trigger freq/512,Trigger freq/1024,Trigger freq/2048,Trigger freq/4096,Trigger freq/8192,Trigger freq/16394,Trigger freq/32768,Trigger freq/65536"
|
|
group.long 0x18++0x03
|
|
line.long 0x0 "TSADCC_CHSR,TSADCC Channel Status Register"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_set/clr ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_set/clr ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_set/clr ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_set/clr ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_set/clr ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CH2_set/clr ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "TSADCC_SR, TSADCC Status Register"
|
|
in
|
|
rgroup.long 0x30++0x1f
|
|
line.long 0x0 "TSADCC_CDR0,TSADCC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x4 "TSADCC_CDR1,TSADCC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x8 "TSADCC_CDR2,TSADCC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0xC "TSADCC_CDR3,TSADCC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x10 "TSADCC_CDR4,TSADCC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x14 "TSADCC_CDR5,TSADCC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x18 "TSADCC_CDR6,TSADCC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x1C "TSADCC_CDR7,TSADCC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Channel Data"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "TSADCC_LCDR,TSADCC Last Converted Data Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TSADCC_IMR,TSADCC Interrupt Mask Register"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " OVREZ2_set/clr , Overrun Error Interrupt Enable Z2 Measure" "Disabled,Enabled"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " OVREZ1_set/clr , Overrun Error Interrupt Enable Z1 Measure" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " OVREXP_set/clr , Overrun Error Interrupt Enable X Position" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " EOCZ2_set/clr , End of Conversion Z2 Measure" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " EOCZ1_set/clr , End of Conversion Z1 Measure" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " EOCXP_set/clr , End of Conversion X Position" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " NOCNT_set/clr , No Contact" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " PENCNT_set/clr , Pen Contact" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " ENDRX_set/clr ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " GOVRE_set/clr ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " DRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " OVRE7_set/clr ,Overrun Error Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " OVRE6_set/clr ,Overrun Error Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " OVRE5_set/clr ,Overrun Error Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " OVRE4_set/clr ,Overrun Error Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " OVRE3_set/clr ,Overrun Error Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " OVRE2_set/clr ,Overrun Error Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " OVRE1_set/clr ,Overrun Error Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " OVRE0_set/clr ,Overrun Error Interrupt Mask 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7_set/clr ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6_set/clr ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5_set/clr ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4_set/clr ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3_set/clr ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2_set/clr ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1_set/clr ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0_set/clr ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
group.long 0x50++0xb
|
|
line.long 0x00 "TSADCC_XPDR,TSADCC X Position Data Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA ,X Position Data"
|
|
line.long 0x04 "TSADCC_Z1DR,TSADCC Z1 Data Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " DATA ,Z1 Measurement Data"
|
|
line.long 0x08 "TSADCC_Z2DR,TSADCC Z2 Data Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " DATA , Z2 Measurement Data"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TSADCC_MSCR,TSADCC Manual Switch Command Register"
|
|
bitfld.long 0x00 3. " Y_M ,Switch Command" "Open,Closed"
|
|
bitfld.long 0x00 2. " Y_P ,Switch Command" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " X_M ,Switch Command" "Open,Closed"
|
|
bitfld.long 0x00 0. " X_P ,Switch Command" "Open,Closed"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TSADCC_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " KEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "AC97 (Audio Codec 97)"
|
|
base ad:0xfffac000
|
|
width 13.
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "AC97C_MR,Mode Register"
|
|
bitfld.long 0x00 2. " VRA ,Variable Rate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " WRST ,Warm Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA ,AC97 Controller Global Enable" "No effect,Enabled"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "AC97C_ICA,Input Channel Assignment Register"
|
|
bitfld.long 0x00 27.--29. " CHID12 ,Channel ID for the input slot 12" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 24.--26. " CHID11 ,Channel ID for the input slot 11" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CHID10 ,Channel ID for the input slot 10" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 18.--20. " CHID9 ,Channel ID for the input slot 9" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CHID8 ,Channel ID for the input slot 8" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 12.--14. " CHID7 ,Channel ID for the input slot 7" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CHID6 ,Channel ID for the input slot 6" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 6.--8. " CHID5 ,Channel ID for the input slot 5" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CHID4 ,Channel ID for the input slot 4" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 0.--2. " CHID3 ,Channel ID for the input slot 3" "None,Channel A,Channel B,?..."
|
|
line.long 0x04 "AC97C_OCA,Output Channel Assignment Register"
|
|
bitfld.long 0x04 27.--29. " CHID12 ,Channel ID for the output slot 12" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 24.--26. " CHID11 ,Channel ID for the output slot 11" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " CHID10 ,Channel ID for the output slot 10" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 18.--20. " CHID9 ,Channel ID for the output slot 9" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " CHID8 ,Channel ID for the output slot 8" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 12.--14. " CHID7 ,Channel ID for the output slot 7" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " CHID6 ,Channel ID for the output slot 6" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 6.--8. " CHID5 ,Channel ID for the output slot 5" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " CHID4 ,Channel ID for the output slot 4" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 0.--2. " CHID3 ,Channel ID for the output slot 3" "None,Channel A,Channel B,?..."
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "AC97C_CORHR,Codec Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDATA ,Status Data"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x00 "AC97C_COTHR,Codec Transmit Holding Register"
|
|
bitfld.long 0x00 23. " READ ,Read/Write command" "Write,Read"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CADDR ,CODEC control register index"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CDATA ,Command Data"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "AC97C_CARHR,Channel A Receive Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDATA ,Receive Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "AC97C_CBRHR,Channel B Receive Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDATA ,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "AC97C_CATHR,Channel A Transmit Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TDATA ,Data to Transmit"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "AC97C_CBTHR,Channel B Transmit Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TDATA ,Data to Transmit"
|
|
hgroup.long 0x28++3
|
|
hide.long 0x00 "AC97C_CASR,Channel A Status Register"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "AC97C_CBSR,Channel B Status Register"
|
|
in
|
|
hgroup.long 0x48++3
|
|
hide.long 0x00 "AC97C_COSR,Codec Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "AC97C_CAMR,Channel A Mode Register"
|
|
bitfld.long 0x00 22. " PDCEN ,Peripheral Data Controller Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CEN ,Channel A Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CEM ,Channel A Endian Mode" "Little,Big"
|
|
bitfld.long 0x00 16.--17. " SIZE ,Channel A Data Size" "20 bits,18 bits,16 bits,10 bits"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXBUFF ,Receive Buffer Full for channel A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENDRX ,End of Reception for channel A Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmit Buffer Empty for channel A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENDTX ,End of Transmission for channel A Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x3c++0x3
|
|
line.long 0x00 "AC97C_CBMR,Channel B Mode Register"
|
|
bitfld.long 0x00 22. " PDCEN ,Peripheral Data Controller Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CEN ,Channel B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CEM ,Channel B Endian Mode" "Little,Big"
|
|
bitfld.long 0x00 16.--17. " SIZE ,Channel B Data Size" "20 bits,18 bits,16 bits,10 bits"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXBUFF ,Receive Buffer Full for channel B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENDRX ,End of Reception for channel B Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmit Buffer Empty for channel B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENDTX ,End of Transmission for channel B Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "AC97C_COMR,Codec Mode Register"
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "AC97C_SR,Status Register"
|
|
in
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "AC97C_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CBEVT_set/clr ,Channel B Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CAEVT_set/clr ,Channel A Event" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " COEVT_set/clr ,CODEC Channel Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " WKUP_set/clr ,Wake Up detection" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " SOF_set/clr ,Start Of Frame" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0xFFFC0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "AES_CR,AES Control Register"
|
|
bitfld.long 0x00 16. " LOADSEED ,Random Number Generator Seed Loading" "No effect,Reset"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AES_MR,AES Mode Register"
|
|
bitfld.long 0x00 28. " CMTYP5 ,CounterMeasure Type 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CMTYP4 ,CounterMeasure Type 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CMTYP3 ,CounterMeasure Type 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CMTYP2 ,CounterMeasure Type 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CMTYP1 ,CounterMeasure Type 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " CKEY ,Countermeasure Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. " CFBS ,Cipher Feedback Data Size" "128-bit,64-bit,32-bit,16-bit,8-bit,?..."
|
|
bitfld.long 0x00 15. " LOD ,Last Output Data Mode" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation Mode" "ECB,CBC,OFB,CFB,CTR,?..."
|
|
bitfld.long 0x00 10.--11. " KEYSIZE ,Key Size" "AES128,AES192,AES256,?..."
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start Mode" "MANUAL_START,AUTO_START,IDATAR0_START,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PROCDLY ,Processing Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CIPHER ,Processing Mode" "Decrypts data,Encrypts data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AES_IMR,AES Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr ,Unspecified Register Access Detection Interrupt Mask" "Not enabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "AES_ISR,AES Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x20++0x1F
|
|
line.long 0x0 "AES_KEYWR0,AES Key Word Register 0"
|
|
line.long 0x4 "AES_KEYWR1,AES Key Word Register 1"
|
|
line.long 0x8 "AES_KEYWR2,AES Key Word Register 2"
|
|
line.long 0xC "AES_KEYWR3,AES Key Word Register 3"
|
|
line.long 0x10 "AES_KEYWR4,AES Key Word Register 4"
|
|
line.long 0x14 "AES_KEYWR5,AES Key Word Register 5"
|
|
line.long 0x18 "AES_KEYWR6,AES Key Word Register 6"
|
|
line.long 0x1C "AES_KEYWR7,AES Key Word Register 7"
|
|
wgroup.long 0x40++0xF
|
|
line.long 0x0 "AES_IDATAR0,AES Input Data Register 0"
|
|
line.long 0x4 "AES_IDATAR1,AES Input Data Register 1"
|
|
line.long 0x8 "AES_IDATAR2,AES Input Data Register 2"
|
|
line.long 0xC "AES_IDATAR3,AES Input Data Register 3"
|
|
rgroup.long 0x50++0x0F
|
|
line.long 0x0 "AES_ODATAR0,AES Output Data Register 0"
|
|
line.long 0x4 "AES_ODATAR1,AES Output Data Register 1"
|
|
line.long 0x8 "AES_ODATAR2,AES Output Data Register 2"
|
|
line.long 0xC "AES_ODATAR3,AES Output Data Register 3"
|
|
if ((d.l(ad:(0xFFFC0000+0x04))&0x7000)==0x0)
|
|
hgroup.long 0x60++0x0F
|
|
hide.long 0x0 "AES_IVR0,AES Initialization Vector Register 0"
|
|
hide.long 0x4 "AES_IVR1,AES Initialization Vector Register 1"
|
|
hide.long 0x8 "AES_IVR2,AES Initialization Vector Register 2"
|
|
hide.long 0xC "AES_IVR3,AES Initialization Vector Register 3"
|
|
else
|
|
wgroup.long 0x60++0x0F
|
|
line.long 0x0 "AES_IVR0,AES Initialization Vector Register 0"
|
|
line.long 0x4 "AES_IVR1,AES Initialization Vector Register 1"
|
|
line.long 0x8 "AES_IVR2,AES Initialization Vector Register 2"
|
|
line.long 0xC "AES_IVR3,AES Initialization Vector Register 3"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TDES (Triple Data Encryption Standard)"
|
|
base ad:0xFFFC4000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TDES_CR,AES Control Register"
|
|
bitfld.long 0x00 16. " LOADSEED ,Random Number Generator Seed Loading" "No effect,Reset"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TDES_MR,TDES Mode Register"
|
|
bitfld.long 0x00 28. " CTYPE5 ,Countermeasure type 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CTYPE4 ,Countermeasure type 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CTYPE3 ,Countermeasure type 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CTYPE2 ,Countermeasure type 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CTYPE1 ,Countermeasure type 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CKEY ,Countermeasure Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CFBS ,Cipher Feedback Data Size" "64-bit,32-bit,16-bit,8-bit"
|
|
bitfld.long 0x00 15. " LOD ,Last Output Data Mode" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " OPMOD ,Operation Mode" "ECB,CBC,OFB,CFB"
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start Mode" "Manual Mode,Auto Mode,PDC Mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " KEYMOD ,Key Mode" "Three-key,Two-key"
|
|
bitfld.long 0x00 1.--2. " TDESMOD ,ALGORITHM mode" "Single DES,Triple DES,XTEA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CIPHER ,Processing Mode" "Decrypts data,Encrypts data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TDES_IMR,TDES Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr ,Unspecified Register Access Detection Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "TDES_ISR,TDES Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x20++0x17
|
|
line.long 0x0 "TDES_KEY1W1R,Key 1 Word 1 Register"
|
|
line.long 0x0+0x04 "TDES_KEY1W2R,Key 1 Word 2 Register"
|
|
line.long 0x8 "TDES_KEY2W1R,Key 2 Word 1 Register"
|
|
line.long 0x8+0x04 "TDES_KEY2W2R,Key 2 Word 2 Register"
|
|
line.long 0x10 "TDES_KEY3W1R,Key 3 Word 1 Register"
|
|
line.long 0x10+0x04 "TDES_KEY3W2R,Key 3 Word 2 Register"
|
|
wgroup.long 0x40++0x07
|
|
line.long 0x00 "TDES_IDATA1R,TDES Input Data 1 Register"
|
|
line.long 0x04 "TDES_IDATA2R,TDES Input Data 2 Register"
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "TDES_ODATA1R,TDES Output Data 1 Register"
|
|
line.long 0x04 "TDES_ODATA2R,TDES Output Data 2 Register"
|
|
if ((d.l(ad:(0xFFFC4000+0x04))&0x7000)==0x0)
|
|
hgroup.long 0x60++0x07
|
|
hide.long 0x00 "TDES_IV1R,TDES Initialization Vector 1 Register"
|
|
hide.long 0x04 "TDES_IV2R,TDES Initialization Vector 2 Register"
|
|
else
|
|
wgroup.long 0x60++0x07
|
|
line.long 0x00 "TDES_IV1R,TDES Initialization Vector 1 Register"
|
|
line.long 0x04 "TDES_IV2R,TDES Initialization Vector 2 Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TDES_XTEA_RNDR,TDES XTEA Rounds Register"
|
|
bitfld.long 0x00 0.--5. " XTEA_RNDS ,Number of Rounds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0xFFFC8000
|
|
width 13.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "SHA_CR, SHA Control Register"
|
|
bitfld.long 0x00 8. " SWRST , Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 4. " FIRST , First Block of a Message" "No effect,Next 512-block"
|
|
bitfld.long 0x00 0. " START , Start Processing" "No effect,Start"
|
|
if (((d.l(ad:(0xFFFC8000+0x04)))&0x100)==0x000)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SHA_MR, SHA Mode Register"
|
|
bitfld.long 0x00 8. " ALGO , SHA Algorithm" "SHA1,SHA256"
|
|
bitfld.long 0x00 4. " PROCDLY , Processing Delay" "85,326"
|
|
bitfld.long 0x00 0.--1. " SMOD , Start Mode" "Manual,Auto,PDC,?..."
|
|
elif (((d.l(ad:(0xFFFC8000+0x04)))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SHA_MR, SHA Mode Register"
|
|
bitfld.long 0x00 8. " ALGO , SHA Algorithm" "SHA1,SHA256"
|
|
bitfld.long 0x00 4. " PROCDLY , Processing Delay" "72,265"
|
|
bitfld.long 0x00 0.--1. " SMOD , Start Mode" "Manual,Auto,PDC,?..."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "SHA_IMR, SHA Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr , Unspecified Register Access Detection Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXBUFE_set/clr , Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENDTX_set/clr , End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr , Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x00 "SHA_ISR, SHA Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "SHA_IDATA1R, SHA Input Data 1 Register"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x00 "SHA_IDATA2R, SHA Input Data 2 Register"
|
|
wgroup.long 0x48++0x3
|
|
line.long 0x00 "SHA_IDATA3R, SHA Input Data 3 Register"
|
|
wgroup.long 0x4C++0x3
|
|
line.long 0x00 "SHA_IDATA4R, SHA Input Data 4 Register"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "SHA_IDATA5R, SHA Input Data 5 Register"
|
|
wgroup.long 0x54++0x3
|
|
line.long 0x00 "SHA_IDATA6R, SHA Input Data 6 Register"
|
|
wgroup.long 0x58++0x3
|
|
line.long 0x00 "SHA_IDATA7R, SHA Input Data 7 Register"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x00 "SHA_IDATA8R, SHA Input Data 8 Register"
|
|
wgroup.long 0x60++0x3
|
|
line.long 0x00 "SHA_IDATA9R, SHA Input Data 9 Register"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x00 "SHA_IDATA10R, SHA Input Data 10 Register"
|
|
wgroup.long 0x68++0x3
|
|
line.long 0x00 "SHA_IDATA11R, SHA Input Data 11 Register"
|
|
wgroup.long 0x6C++0x3
|
|
line.long 0x00 "SHA_IDATA12R, SHA Input Data 12 Register"
|
|
wgroup.long 0x70++0x3
|
|
line.long 0x00 "SHA_IDATA13R, SHA Input Data 13 Register"
|
|
wgroup.long 0x74++0x3
|
|
line.long 0x00 "SHA_IDATA14R, SHA Input Data 14 Register"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x00 "SHA_IDATA15R, SHA Input Data 15 Register"
|
|
wgroup.long 0x7C++0x3
|
|
line.long 0x00 "SHA_IDATA16R, SHA Input Data 16 Register"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "SHA_ODATA1R, SHA Output Data 1 Register"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "SHA_ODATA2R, SHA Output Data 2 Register"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x00 "SHA_ODATA3R, SHA Output Data 3 Register"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x00 "SHA_ODATA4R, SHA Output Data 4 Register"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "SHA_ODATA5R, SHA Output Data 5 Register"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "SHA_ODATA6R, SHA Output Data 6 Register"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "SHA_ODATA7R, SHA Output Data 7 Register"
|
|
rgroup.long 0x9C++0x3
|
|
line.long 0x00 "SHA_ODATA8R, SHA Output Data 8 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xfffcc000
|
|
width 0x10
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "TRNG_CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 100. " KEY ,Key"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disables,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TRNG_IMR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "TRNG_ISR,TRNG Interrupt Status Register"
|
|
in
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "TRNG_ODATA ,TRNG Output Data Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "VDEC (Video Decoder)"
|
|
base ad:0x00900000
|
|
width 0xE
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VDEC_IDR,Video Decoder ID Register"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " PROD_ID ,Product ID(0x8170)"
|
|
hexmask.long.byte 0x00 12.--15. 0x01 " MAJOR_VER ,Major Version(0x0)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 0x01 " MINOR_VER ,Minor Version(0x88)"
|
|
hexmask.long.byte 0x00 0.--3. 0x01 " BUILD_VER ,Build Version(0x00)"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "VDEC_DIR,Decoder Interrupt Register"
|
|
bitfld.long 0x00 18. " TO ,Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 17. " JPEGSD ,JPEG Slice Decoded" "No decoding,Decoded"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ISE ,Input Stream Error" "No error,Error"
|
|
bitfld.long 0x00 15. " ASOD ,ASO Detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SBE ,Stream Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 13. " BE ,Bus Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR ,Decoder Ready" "Decoding in progress,Ready"
|
|
bitfld.long 0x00 8. " ISET ,Decoder Interrupt Set" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ID ,Interrupt Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DE ,Decoder Enable" "Enabled,Disabled"
|
|
line.long 0x04 "VDEC_DDCR,Decoder Device Configuration Register"
|
|
bitfld.long 0x04 23. " HTI ,Hardware Timeout Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " DI_LE ,Decoder Input Endian Mode" "Big endian,Little endian"
|
|
textline " "
|
|
bitfld.long 0x04 18. " AHB_BURST ,AHB Precise Burst and Data Discard Enable" "INCR,SINGLE/INCR4/8/16"
|
|
bitfld.long 0x04 17. " DOPF ,Decoder Output Picture Format" "Raster scan,Tiled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 11.--16. 0x01 " LAT_COMP ,Decoder Latency Compensation"
|
|
bitfld.long 0x04 10. " DDCGE ,Decoder Dynamic Clock Gating Enable" "Is running,Is gated"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTCE_LE ,Interface Endian Mode" "Big endian,Little endian"
|
|
bitfld.long 0x04 8. " DO_LE ,Decoder Output Endian Mode" "Big endian,Little endian"
|
|
textline " "
|
|
bitfld.long 0x04 5.--7. " PRIOR ,Decoder Core Internal Bus Service Priority" "Dynamic priority,Post-processor,Input stream read,Reference picture read/post-processor,Reference picture read/decoder output,?..."
|
|
bitfld.long 0x04 0.--4. " MAX_BURST_LEN ,Maximum Burst Length for Decoder Bus Transactions" "INCR always,SINGLE always,Reserved,Reserved,INCR4 INCR SINGLE,Reserved,Reserved,Reserved,INCR8/4 INCR SINGLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,INCR16/8/4 INCR SINGLE(INCR 2-3 b.),INCR16/8/4 INCR SINGLE(INCR 2/3/5-7/9-15 b.),?..."
|
|
line.long 0x08 "VDEC_CTLR0,Decoder Control Register 0 (Decoder Mode and Picture Type)"
|
|
bitfld.long 0x08 28.--31. " DEC_MODE ,Decoding Mode" "H.264,MPEG-4,H.263,JPEG,VC-1,MPEG2,MPEG1,?..."
|
|
bitfld.long 0x08 27. " RLCEN ,RLC Mode Enable" "VLC,RLC"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PICMODE ,Coding mode of Current Picture" "Progressive,Interlaced"
|
|
bitfld.long 0x08 22. " PICSTRUCT ,Structure of the Current Picture" "Frame structure,Field structure"
|
|
textline " "
|
|
bitfld.long 0x08 21. " PICBEN ,B Picture Enable" "I or P,BI (vc1)/D (mpeg1) or B"
|
|
bitfld.long 0x08 20. " PICTYPE ,Picture Type" "Intra type (I),Inter type (P)"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PICFIELD ,Picture Field" "Bottom field,Top field"
|
|
bitfld.long 0x08 18. " FORWMODE ,Coding Mode of Forward Reference Picture" "Progressive,Interlaced"
|
|
textline " "
|
|
bitfld.long 0x08 16. " REFFIELD ,Indicates Which Field Should Be Used As Reference" "Bottom,Top"
|
|
bitfld.long 0x08 15. " OUTDIS ,Disable Decoder Output Picture Writing" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " FILTDIS ,De-block Filtering Disable" "Enabled,Disabled"
|
|
bitfld.long 0x08 13. " QUANT ,Quantization" "Can vary,Fixed(pquant)"
|
|
textline " "
|
|
bitfld.long 0x08 12. " MV ,MPEG-2 Motion Vector Write Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " REFFIRST ,Reference Field First" "Bottom,Top"
|
|
textline " "
|
|
bitfld.long 0x08 8. " HLOCK ,HLOCK Enable" "Disabled,Enabled"
|
|
if ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000)&&(((d.l(a:(0x00900000+0x0C)))&0x8000000)==0x0000000))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "VDEC_CTLR1,Decoder Control Register 1 (Picture Parameters)"
|
|
hexmask.long.word 0x00 23.--31. 0x01 " PIC_WIDTH ,Picture Width"
|
|
textline " "
|
|
bitfld.long 0x00 19.--22. " WIDTH_OFF ,Width Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 11.--18. 0x01 " PIC_HEIGHT ,Picture Height"
|
|
textline " "
|
|
bitfld.long 0x00 7.--10. " HEIGHT_OFF ,Height Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " AVSM ,Alternative Vertical Scan Method" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TOPF ,Top Field" "Low,High"
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " REF_FRAMES ,Number of Reference Frames(H.264)/Semantics(VC-1)"
|
|
line.long 0x04 "VDEC_CTLR2,Decoder Control Register 2(H.264 Stream Decoding Table Selects)"
|
|
hexmask.long.byte 0x04 26.--31. 1. " STREAM_START_BIT ,Stream Start Bit"
|
|
hexmask.long.byte 0x04 19.--23. 1. " QPFILT_CB_OFF ,Chrominance Offset for Cb type"
|
|
textline " "
|
|
hexmask.long.byte 0x04 14.--18. 1. " QPFILT_CR_OFF ,Chrominance Offset for Cr type"
|
|
bitfld.long 0x04 0. " FIELDPIC ,Flag for Stream" "Not Exist,Flag exist"
|
|
line.long 0x08 "VDEC_CTLR3,Decoder Control Register 3 (Stream Buffer Information)"
|
|
bitfld.long 0x08 31. " ST_COD_EN ,Stream Start Code" "Not contains,Contains"
|
|
hexmask.long.byte 0x08 25.--30. 1. " INIT_QP ,Quantization Initialization"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " STREAM_LEN ,Stream Length"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "VDEC_CTLR4,Decoder Control Register 4 (H.264 Control)"
|
|
bitfld.long 0x00 31. " CABAC ,H.264 CABAC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " BW ,Black and White Enable" "4:2:0 sampling format,4:0:0 sampling format"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DIRMV_PRED ,Derive Luma Method" "Low,High"
|
|
bitfld.long 0x00 28. " W_PRED ,Weight Prediction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " W_BIPR ,Weight Prediction for B Slices" "00,01,10,11"
|
|
hexmask.long.byte 0x00 16.--20. 1. " FRAME_NUM_LEN ,Frame Number length"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FRAME_NUM ,Frame Number"
|
|
line.long 0x04 "VDEC_CTLR5,Decoder Control Register 5(H.264 Control)"
|
|
bitfld.long 0x04 31. " CONS_INTRA ,Intra in Prediction" "Only intra macroblocks,Also inter macroblocks"
|
|
bitfld.long 0x04 30. " FILT_CTRL ,Extra Variables Controlling Characteristics of The Deblocking Filter" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RD_PIC ,Redundant Picture Present" "Not present,Present"
|
|
bitfld.long 0x04 28. " T8X8FE ,8x8 Transform Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 17.--27. 1. " REF_PIC_LEN ,Reference Picture Length"
|
|
bitfld.long 0x04 16. " IDREN ,IDR Picture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " IDR_PIC_ID ,IDR Picture"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "VDEC_CTLR6,Decoder Control Register 6 (H.264 VLC Mode)"
|
|
hexmask.long 0x00 2.--31. 2. " MB_CONTROL_BASE ,Macroblock Control Base Address"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000)&&(((d.l(a:(0x00900000+0x0C)))&0x8000000)==0x8000000))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "VDEC_CTLR1,Decoder Control Register 1 (Picture Parameters)"
|
|
hexmask.long.word 0x00 23.--31. 0x01 " PIC_WIDTH ,Picture Width"
|
|
bitfld.long 0x00 19.--22. " WIDTH_OFF ,Width Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 11.--18. 0x01 " PIC_HEIGHT ,Picture Height"
|
|
bitfld.long 0x00 7.--10. " HEIGHT_OFF ,Height Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AVSM ,Alternative Vertical Scan Method" "Low,High"
|
|
bitfld.long 0x00 5. " TOPF ,Top Field" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " REF_FRAMES ,Number of Reference Frames(H.264)/Semantics(VC-1)"
|
|
line.long 0x04 "VDEC_CTLR2,Decoder Control Register 2(H.264 Stream Decoding Table Selects)"
|
|
hexmask.long.byte 0x04 26.--31. 1. " STREAM_START_BIT ,Stream Start Bit"
|
|
hexmask.long.byte 0x04 19.--23. 1. " QPFILT_CB_OFF ,Chrominance Offset for Cb type"
|
|
textline " "
|
|
hexmask.long.byte 0x04 14.--18. 1. " QPFILT_CR_OFF ,Chrominance Offset for Cr type"
|
|
bitfld.long 0x04 0. " FIELDPIC ,Flag for Stream" "Not Exist,Flag exist"
|
|
line.long 0x08 "VDEC_CTLR3,Decoder Control Register 3 (Stream Buffer Information)"
|
|
bitfld.long 0x08 31. " ST_COD_EN ,Stream Start Code" "Doesn't contain,Contains"
|
|
hexmask.long.byte 0x08 25.--30. 1. " INIT_QP ,Quantization Initialization"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " STREAM_LEN ,Stream Length"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "VDEC_CTLR4,Decoder Control Register 4 (H.264 Control)"
|
|
bitfld.long 0x00 31. " CABAC ,H.264 CABAC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " BW ,Black and White Enable" "4:2:0,4:0:0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DIRMV_PRED ,Derive Luma Method" "Low,High"
|
|
bitfld.long 0x00 28. " W_PRED ,Weight Prediction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " W_BIPR ,Weight Prediction for B Slices" "00,01,10,11"
|
|
hexmask.long.byte 0x00 16.--20. 1. " FRAME_NUM_LEN ,Frame Number length"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FRAME_NUM ,Frame Number"
|
|
line.long 0x04 "VDEC_CTLR5,Decoder Control Register 5(H.264 Control)"
|
|
bitfld.long 0x04 31. " CONS_INTRA ,Intra in Prediction" "Also inter macroblocks,Only intra macroblocks"
|
|
bitfld.long 0x04 30. " FILT_CTRL ,Extra Variables Controlling Characteristics of The Deblocking Filter" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RD_PIC ,Redundant Picture Present" "Not present,Present"
|
|
bitfld.long 0x04 28. " T8X8FE ,8x8 Transform Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 17.--27. 1. " REF_PIC_LEN ,Reference Picture Length"
|
|
bitfld.long 0x04 16. " IDREN ,IDR Picture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " IDR_PIC_ID ,IDR Picture"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "VDEC_CTLR6,Decoder Control Register 6 (H.264 RLC Mode)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PPS_ID ,Picture Parameter"
|
|
hexmask.long.byte 0x00 19.--23. 1. " REF_IDX1 ,Maximum Reference Index 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 14.--18. 1. " REF_IDX0 ,Maximum Reference Index 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " POC_LEN ,Picture Order length"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x10000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x20000000))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "VDEC_CTLR1,Decoder Control Register 1 (Picture Parameters)"
|
|
hexmask.long.word 0x00 23.--31. 0x01 " PIC_WIDTH ,Picture Width"
|
|
bitfld.long 0x00 19.--22. " WIDTH_OFF ,Width Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 11.--18. 0x01 " PIC_HEIGHT ,Picture Height"
|
|
bitfld.long 0x00 7.--10. " HEIGHT_OFF ,Height Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AVSM ,Alternative Vertical Scan Method" "Low,High"
|
|
bitfld.long 0x00 5. " TOPF ,Top Field" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " REF_FRAMES ,Number of Reference Frames(H.264)/Semantics(VC-1)"
|
|
line.long 0x04 "VDEC_CTLR2,Decoder Control Register 2(MPEG-4/H.263 Stream Decoding Table Selects)"
|
|
hexmask.long.byte 0x04 26.--31. 1. " STREAM_START_BIT ,Stream Start Bit"
|
|
bitfld.long 0x04 25. " SYNCMAREN ,Synchronization Markers enable" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 24. " QUANTYPE ,Quantization Type" "Type 2,Type 1"
|
|
hexmask.long.byte 0x04 19.--23. 1. " QPFILT_OFF ,Chrominance Offset"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " VLC_THR ,VLC Threshold" "0,1,2,3,4,5,6,7,?..."
|
|
hexmask.long.word 0x04 0.--15. 1. " VOP_TIME_INC ,VOP Time Increment"
|
|
line.long 0x08 "VDEC_CTLR3,Decoder Control Register 3 (Stream Buffer Information)"
|
|
bitfld.long 0x08 31. " ST_COD_EN ,Stream Start Code" "Not contains,Contains"
|
|
hexmask.long.byte 0x08 25.--30. 1. " INIT_QP ,Quantization Initialization"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " STREAM_LEN ,Stream Length"
|
|
hgroup.long 0x1C++0x07
|
|
hide.long 0x00 "VDEC_CTLR4"
|
|
hide.long 0x04 "VDEC_CTLR5"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "VDEC_CTLR6,Decoder Control Register 6 (MPEG-4/H.263 Base Address for MB-control)"
|
|
hexmask.long 0x00 2.--31. 2. " MB_CONTROL_BASE ,Macroblock Control Base Address"
|
|
elif (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x30000000)
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "VDEC_CTLR1,Decoder Control Register 1 (Picture Parameters)"
|
|
hexmask.long.word 0x00 23.--31. 0x01 " PIC_WIDTH ,Picture Width"
|
|
bitfld.long 0x00 19.--22. " WIDTH_OFF ,Width Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 11.--18. 0x01 " PIC_HEIGHT ,Picture Height"
|
|
bitfld.long 0x00 7.--10. " HEIGHT_OFF ,Height Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AVSM ,Alternative Vertical Scan Method" "Low,High"
|
|
bitfld.long 0x00 5. " TOPF ,Top Field" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " REF_FRAMES ,Number of Reference Frames(H.264)/Semantics(VC-1)"
|
|
line.long 0x04 "VDEC_CTLR2,Decoder Control Register 2 (JPEG Stream Decoding Table Selects)"
|
|
hexmask.long.byte 0x04 26.--31. 1. " STREAM_START_BIT ,Stream Start Bit"
|
|
bitfld.long 0x04 11.--12. " QTABLES ,Amount of Quantization Tables in External Memory" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MODE ,JPEG Mode" "Single type/MB 1 bl.,Single type/MB 4 bl.,Three types/MB 6 blocks (4:2:0),Three types/MB 4 blocks (4:2:2),Three types/MB 3 blocks (4:4:4),Three types/MB 4 blocks (4:4:0),?..."
|
|
bitfld.long 0x04 7. " FILL ,JPEG Fill Right" "Multiple of 16,Multiple of 8"
|
|
textline " "
|
|
bitfld.long 0x04 6. " END ,End of JPEG Image in the Stream" "Not in,In"
|
|
bitfld.long 0x04 5. " ACCR ,AC Component of the Cr" "First ,Second"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACCB ,AC Component of the Cb" "First,Second"
|
|
bitfld.long 0x04 3. " DCCR ,DC Component of the Cr" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DCCB ,DC Component of the Cb" "First,Second"
|
|
line.long 0x08 "VDEC_CTLR3,Decoder Control Register 3 (Stream Buffer Information)"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " STREAM_LEN ,Stream Length"
|
|
hgroup.long 0x1C++0x0B
|
|
hide.long 0x00 "VDEC_CTLR4"
|
|
hide.long 0x04 "VDEC_CTLR5"
|
|
hide.long 0x08 "VDEC_CTLR6"
|
|
elif (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x40000000)
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "VDEC_CTLR1,Decoder Control Register 1 (Picture Parameters)"
|
|
hexmask.long.word 0x00 23.--31. 0x01 " PIC_WIDTH ,Picture Width"
|
|
bitfld.long 0x00 19.--22. " WIDTH_OFF ,Width Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 11.--18. 0x01 " PIC_HEIGHT ,Picture Height"
|
|
bitfld.long 0x00 7.--10. " HEIGHT_OFF ,Height Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AVSM ,Alternative Vertical Scan Method" "Low,High"
|
|
bitfld.long 0x00 5. " TOPF ,Top Field" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " REF_FRAMES ,Number of Reference Frames(H.264)/Semantics(VC-1)"
|
|
line.long 0x04 "VDEC_CTLR2,Decoder Control Register 2 (VC-1 Stream Decoding Table Selects)"
|
|
hexmask.long.byte 0x04 26.--31. 1. " STREAM_START_BIT ,Stream Start Bit"
|
|
bitfld.long 0x04 25. " SYNCMAREN ,Synchronization Markers Enable" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 24. " Q_PROFILE ,Quantization Profile" "Picture edges,All macroblocks"
|
|
bitfld.long 0x04 23. " DQBI ,Quantization Step Size" "Any size (STREAMD),Only PQUANT/ALT_PQUANT"
|
|
textline " "
|
|
bitfld.long 0x04 22. " IS_REDU ,Picture Range Reduction" "No,Yes"
|
|
bitfld.long 0x04 20. " FAST_UVMC ,Chroma Interpolation Accuracy" "1/4pel,1/2pel"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TDC_TAB ,Transform DC table" "Low,High"
|
|
bitfld.long 0x04 15.--16. " CAC_TAB ," "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " YAC_TAB ,Luma AC table" "0,1,2,3"
|
|
bitfld.long 0x04 10.--12. " MB_MODE_TAB ,MB Mode Syntax Table Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 7.--9. " MV_TAB ,MV Table Selection (Progressive content/Iinterlaced content)" "0/0,1/1,2/2,3/3,Reserved/4,Reserved/5,Reserved/6,Reserved/7"
|
|
bitfld.long 0x04 4.--6. " MB_TAB ,MB Table Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " 2MV_TAB ,2MV Block Pattern" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " 4MV_TAB ,4MV Block Pattern" "0,1,2,3"
|
|
line.long 0x08 "VDEC_CTLR3,Decoder Control Register 3 (Stream Buffer Information)"
|
|
bitfld.long 0x08 31. " ST_COD_EN ,Stream Start Code" "Doesn't contain,Contains"
|
|
hexmask.long.byte 0x08 25.--30. 1. " INIT_QP ,Quantization Initialization"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " STREAM_LEN ,Stream Length"
|
|
line.long 0x0C "VDEC_CTLR4,Decoder Control Register 4 (VC-1 Control)"
|
|
bitfld.long 0x0C 31. " BIT_PLAN0 ,Bitplane Mode Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " BIT_PLAN1 ,Bitplane Mode Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " BIT_PLAN2 ,Bitplane Mode Enable 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0C 24.--28. 1. " ALT_PQUANT ,Alternative PQUANT"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--23. " DQ_EDGES ,Quantized Edge" "Left,Reserved,Top,Reserved,Right,Reserved,Reserved,Reserved,Bottom,?..."
|
|
bitfld.long 0x0C 19. " TTMBF ,TTMB Flag" "Present,Not present."
|
|
textline " "
|
|
hexmask.long.byte 0x0C 14.--18. 1. " PQ_INDEX ,Pre Quantization index"
|
|
bitfld.long 0x0C 12. " BILIN ,Bilinear Enable" "Bicubic,Bilinear"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " UNIQ ,Uniform Quantization" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " HALFQP ,Inverse Quantization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " TTFRM ,VC-1 Frame Level Transformation Type" "8x8,8x4,4x8,4x4"
|
|
bitfld.long 0x0C 6. " DQUANT ,Data Quantization" "PQUANT used throughout,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " VC1_ADV ,VC-1 Advance Profile" "Disabled,Enabled"
|
|
line.long 0x10 "VDEC_CTLR5,Decoder Control Register 5 (VC-1 Control)"
|
|
hexmask.long.byte 0x10 24.--31. 1. " SCALE_FACTOR ,Scale Factor"
|
|
hexmask.long.byte 0x10 19.--23. 1. " REF_DIST_FWD ,VC-1 Reference Distance for FWD Direction"
|
|
textline " "
|
|
hexmask.long.byte 0x10 14.--18. 1. " REF_DIST_BWD ,VC-1 Reference Distance for BWD Direction"
|
|
line.long 0x14 "VDEC_CTLR6,Decoder Control Register 6 (VC-1 Control)"
|
|
bitfld.long 0x14 24. " ISHIFT0 ,IShift Value" "Disabled,Enabled"
|
|
hexmask.long.byte 0x14 16.--23. 1. " IScale0 ,IScale Value"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--15. 1. " ISHIFT0 ,IShift Value"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x50000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x60000000))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "VDEC_CTLR1,Decoder Control Register 1 (Picture Parameters)"
|
|
hexmask.long.word 0x00 23.--31. 0x01 " PIC_WIDTH ,Picture Width"
|
|
hexmask.long.byte 0x00 11.--18. 0x01 " PIC_HEIGHT ,Picture Height"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AVSM ,Alternative Vertical Scan Method" "Low,High"
|
|
line.long 0x04 "VDEC_CTLR2,Decoder Control Register 2 (MPEG-2/MPEG-1 Stream Decoding Table Selects)"
|
|
hexmask.long.byte 0x04 26.--31. 1. " STREAM_START_BIT ,Stream Start Bit"
|
|
bitfld.long 0x04 24. " Q_SCALE ,Q Scale Type Semantics" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CON_MV ,Concealed Motion in Stream" "Not present,Present"
|
|
bitfld.long 0x04 2.--3. " INTRA_DC ,Intra DC Precision" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 1. " VLC_TAB ,Intra VLC Table Selection" "Low,High"
|
|
bitfld.long 0x04 0. " PRED_DCT ,Frame Prediction Semantics" "Low,High"
|
|
line.long 0x08 "VDEC_CTLR3,Decoder Control Register 3 (Stream Buffer Information)"
|
|
bitfld.long 0x08 31. " ST_COD_EN ,Stream Start Code" "Doesn't contain,Contains"
|
|
hexmask.long.byte 0x08 25.--30. 1. " INIT_QP ,Quantization Initialization"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " STREAM_LEN ,Stream Length"
|
|
hgroup.long 0x1C++0x0B
|
|
hide.long 0x00 "VDEC_CTLR4"
|
|
hide.long 0x04 "VDEC_CTLR5"
|
|
hide.long 0x08 "VDEC_CTLR6"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x10000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x20000000))
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "VDEC_DMVBA,Differential Motion Vector Base Address (H.264, MPEG-4/H.263)"
|
|
hexmask.long 0x00 2.--31. 2. " MV_CONTROL_BASE ,Differential Motion Vector Base Address"
|
|
line.long 0x04 "VDEC_CTLR7,Decoder Control Register 7 (H264, MPEG-4/H.263)"
|
|
hexmask.long 0x04 2.--31. 2. " BA ,Base Address"
|
|
elif (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x40000000)
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "VDEC_DMVBA,Differential Motion Vector Base Address (VC-1 Intensity Control 1)"
|
|
bitfld.long 0x00 24. " ICOMP1 ,Intensity Compensation Value" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IScale1 ,IScale Value"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ISHIFT1 ,IShift Value"
|
|
line.long 0x04 "VDEC_CTLR7,Decoder Control Register 7 (VC-1 Intensity Control 2)"
|
|
bitfld.long 0x04 24. " ICOMP2 ,Intensity Compensation Value" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " IScale2 ,IScale Value"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " ISHIFT2 ,IShift Value"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x50000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x60000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x30000000))
|
|
hgroup.long 0x28++0x07
|
|
hide.long 0x00 "VDEC_DMVBA"
|
|
hide.long 0x04 "VDEC_CTLR7"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "VDEC_RLCVLCBA,RLC/VLC Data Base Address"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x10000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x20000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x40000000))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "VDEC_PICTBA,Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
elif (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x30000000)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "VDEC_PICTBA,Decoded Picture Base Address (JPEG Decoder Output Luma Picture)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x50000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x60000000))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "VDEC_PICTBA,Decoded Picture Base Address (Video)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "VDEC_PIDXBA0,Reference Picture Index 0 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "VDEC_PIDXBA1,Reference Picture Index 1 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "VDEC_PIDXBA2,Reference Picture Index 2 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "VDEC_PIDXBA3,Reference Picture Index 3 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "VDEC_PIDXBA4,Reference Picture Index 4 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "VDEC_PIDXBA5,Reference Picture Index 5 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "VDEC_PIDXBA6,Reference Picture Index 6 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "VDEC_PIDXBA7,Reference Picture Index 7 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "VDEC_PIDXBA8,Reference Picture Index 8 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "VDEC_PIDXBA9,Reference Picture Index 9 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "VDEC_PIDXBA10,Reference Picture Index 10 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "VDEC_PIDXBA11,Reference Picture Index 11 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VDEC_PIDXBA12,Reference Picture Index 12 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "VDEC_PIDXBA13,Reference Picture Index 13 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "VDEC_PIDXBA14,Reference Picture Index 14 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "VDEC_PIDXBA15,Reference Picture Index 15 Base Address (H.264)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x10000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x20000000))
|
|
group.long 0x38++0x1F
|
|
line.long 0x00 "VDEC_PIDXBA0,Reference Picture Index 0 Base Address"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x04 "VDEC_PIDXBA1,Reference Picture Index 1 Base Address (Video)"
|
|
hexmask.long 0x04 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x08 "VDEC_PIDXBA2,Reference Picture Index 2 Base Address (Video)"
|
|
hexmask.long 0x08 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x0C "VDEC_PIDXBA3,Reference Picture Index 3 Base Address (Video)"
|
|
hexmask.long 0x0C 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x10 "VDEC_PIDXBA4,Reference Picture Index 4 Base Address (MPEG-4/H.263 MVD Control)"
|
|
bitfld.long 0x10 19. " SCANF ,Alternate Scan Flag" "Low,High"
|
|
bitfld.long 0x10 15.--18. " FW_BN ,Forward Bit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 7.--10. " BW_BN ,Backward Bit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 2. " ACC_FW ,Forward Motion Vector" "1/2,1/4"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RCB ,Rounding Control Bit" "Rounded,Clipped"
|
|
bitfld.long 0x10 0. " ANC ,Anchor Picture Type" "Intra,Inter"
|
|
line.long 0x14 "VDEC_PIDXBA5,Reference Picture Index 5 Base Address (MPEG-4/H.263 TRB/TRD Delta 0)"
|
|
hexmask.long 0x14 0.--26. 1. " TRB_PER_TRD ,TRB per TRD"
|
|
line.long 0x18 "VDEC_PIDXBA6,Reference Picture Index 6 Base Address (MPEG-4/H.263 TRB/TRD Delta -1)"
|
|
hexmask.long 0x18 0.--26. 1. " TRB_PER_TRD ,TRB per TRD"
|
|
line.long 0x1C "VDEC_PIDXBA7,Reference Picture Index 7 Base Address (MPEG-4/H.263 TRB/TRD Delta 1)"
|
|
hexmask.long 0x1C 0.--26. 1. " TRB_PER_TRD ,TRB per TRD"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA8,Reference Picture Index 8 Base Address"
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA9,Reference Picture Index 9 Base Address"
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA10,Reference Picture Index 10 Base Address"
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA11,Reference Picture Index 11 Base Address"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA12,Reference Picture Index 12 Base Address"
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA13,Reference Picture Index 13 Base Address"
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA14,Reference Picture Index 14 Base Address"
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA15,Reference Picture Index 15 Base Address"
|
|
elif (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x30000000)
|
|
group.long 0x38++0x37
|
|
line.long 0x00 "VDEC_PIDXBA0,Reference Picture Index 0 Base Address (JPEG Decoder Output Chroma Picture)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x04 "VDEC_PIDXBA1,Reference Picture Index 1 Base Address (JPEG Control)"
|
|
hexmask.long.byte 0x04 0.--7. 1. " JPEG_SLICE ,Base Address"
|
|
line.long 0x08 "VDEC_PIDXBA2,Reference Picture Index 2 Base Address (JPEG VLC Code Length First AC Table)"
|
|
hexmask.long.byte 0x08 24.--30. 1. " AC1_CODE6 ,Amount of Code Words of Length 6"
|
|
hexmask.long.byte 0x08 16.--21. 1. " AC1_CODE5 ,Amount of Code Words of Length 5"
|
|
textline " "
|
|
hexmask.long.byte 0x08 11.--15. 1. " AC1_CODE4 ,Amount of Code Words of Length 4"
|
|
bitfld.long 0x08 7.--10. " AC1_CODE3 ,Amount of Code Words of Length 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " AC1_CODE2 ,Amount of Code Words of Length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--1. " AC1_CODE1 ,Amount of Code Words of Length 1" "0,1,2,3"
|
|
line.long 0x0C "VDEC_PIDXBA3,Reference Picture Index 3 Base Address (JPEG VLC Code length First AC Table)"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " AC1_CODE10 ,Amount of Code Words of Length 10"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " AC1_CODE9 ,Amount of Code Words of Length 9"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " AC1_CODE8 ,Amount of Code Words of Length 8"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " AC1_CODE7 ,Amount of Code Words of Length 7"
|
|
line.long 0x10 "VDEC_PIDXBA4,Reference Picture Index 4 Base Address (JPEG VLC Code length First AC Table)"
|
|
hexmask.long.byte 0x10 24.--31. 1. " AC1_CODE14 ,Amount of Code Words of Length 14"
|
|
hexmask.long.byte 0x10 16.--23. 1. " AC1_CODE13 ,Amount of Code Words of Length 13"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " AC1_CODE12 ,Amount of Code Words of Length 12"
|
|
hexmask.long.byte 0x10 0.--7. 1. " AC1_CODE11 ,Amount of Code Words of Length 11"
|
|
line.long 0x14 "VDEC_PIDXBA5,Reference Picture Index 5 Base Address (JPEG VLC Code Length First/Second AC Table)"
|
|
hexmask.long.byte 0x14 27.--31. 1. " AC2_CODE4 ,Amount of Code Words of Length 4(second Table)"
|
|
bitfld.long 0x14 23.--26. " AC2_CODE3 ,Amount of Code Words of Length 3(second Table)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 19.--21. " AC2_CODE2 ,Amount of Code Words of Length 2(second Table)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--17. " AC2_CODE1 ,Amount of Code Words of Length 1(first Table)" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--15. 1. " AC1_CODE16 ,Amount of Code Words of Length 16(first Table)"
|
|
hexmask.long.byte 0x14 0.--7. 1. " AC1_CODE15 ,Amount of Code Words of Length 15(first Table)"
|
|
line.long 0x18 "VDEC_PIDXBA6,Reference Picture Index 6 Base Address (JPEG VLC Code Length Second AC Table)"
|
|
hexmask.long.byte 0x18 24.--31. 1. " AC2_CODE8 ,Amount of Code Words of Length 8"
|
|
hexmask.long.byte 0x18 16.--23. 1. " AC2_CODE7 ,Amount of Code Words of Length 7"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--14. 1. " AC2_CODE ,Amount of Code Words of Length 6"
|
|
hexmask.long.byte 0x18 0.--5. 1. " AC2_CODE5 ,Amount of Code Words of Length 5"
|
|
line.long 0x1C "VDEC_PIDXBA7,Reference Picture Index 7 Base Address (JPEG VLC Code Length Second AC Table)"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " AC2_CODE12 ,Amount of Code Words of Length 12"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " AC2_CODE11 ,Amount of Code Words of Length 11"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " AC2_CODE10 ,Amount of Code Words of Length 10"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " AC2_CODE9 ,Amount of Code Words of Length 9"
|
|
line.long 0x20 "VDEC_PIDXBA8,Reference Picture Index 8 Base Address (JPEG VLC Code Length Second AC Table)"
|
|
hexmask.long.byte 0x20 24.--31. 1. " AC2_CODE16 ,Amount of Code Words of Length 16"
|
|
hexmask.long.byte 0x20 16.--23. 1. " AC2_CODE15 ,Amount of Code Words of Length 15"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " AC2_CODE14 ,Amount of Code Words of Length 14"
|
|
hexmask.long.byte 0x20 0.--7. 1. " AC2_CODE13 ,Amount of Code Words of Length 13"
|
|
line.long 0x24 "VDEC_PIDXBA9,Reference Picture Index 9 Base Address (JPEG VLC Code Length First DC Table)"
|
|
bitfld.long 0x24 28.--31. " DC1_CODE8 ,Amount of Code Words of Length 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 24.--27. " DC1_CODE7 ,Amount of Code Words of Length 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 20.--23. " DC1_CODE6 ,Amount of Code Words of Length 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 16.--19. " DC1_CODE5 ,Amount of Code Words of Length 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 12.--15. " DC1_CODE4 ,Amount of Code Words of Length 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 8.--11. " DC1_CODE3 ,Amount of Code Words of Length 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 4.--6. " DC1_CODE2 ,Amount of Code Words of Length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 0.--1. " DC1_CODE1 ,Amount of Code Words of Length 1" "0,1,2,3"
|
|
line.long 0x28 "VDEC_PIDXBA10,Reference Picture Index 10 Base Address (JPEG VLC Code Length First DC Table)"
|
|
bitfld.long 0x28 28.--31. " DC1_CODE16 ,Amount of Code Words of Length 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 24.--27. " DC1_CODE15 ,Amount of Code Words of Length 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 20.--23. " DC1_CODE14 ,Amount of Code Words of Length 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 16.--19. " DC1_CODE13 ,Amount of Code Words of Length 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 12.--15. " DC1_CODE12 ,Amount of Code Words of Length 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 8.--11. " DC1_CODE11 ,Amount of Code Words of Length 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 4.--7. " DC1_CODE10 ,Amount of Code Words of Length 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 0.--3. " DC1_CODE9 ,Amount of Code Words of Length 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "VDEC_PIDXBA11,Reference Picture Index 11 Base Address (JPEG VLC Code Length Second DC Table)"
|
|
bitfld.long 0x2C 28.--31. " DC2_CODE8 ,Amount of Code Words of Length 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x2C 24.--27. " DC2_CODE7 ,Amount of Code Words of Length 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 20.--23. " DC2_CODE6 ,Amount of Code Words of Length 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x2C 16.--19. " DC2_CODE5 ,Amount of Code Words of Length 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 12.--15. " DC2_CODE4 ,Amount of Code Words of Length 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x2C 8.--11. " DC2_CODE3 ,Amount of Code Words of Length 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 4.--6. " DC2_CODE2 ,Amount of Code Words of Length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 0.--1. " DC2_CODE1 ,Amount of Code Words of Length 1" "0,1,2,3"
|
|
line.long 0x30 "VDEC_PIDXBA12,Reference Picture Index 12 Base Address (JPEG VLC Code Length Second DC Table)"
|
|
bitfld.long 0x30 28.--31. " DC2_CODE16 ,Amount of Code Words of Length 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x30 24.--27. " DC2_CODE15 ,Amount of Code Words of Length 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 20.--23. " DC2_CODE14 ,Amount of Code Words of Length 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x30 16.--19. " DC2_CODE13 ,Amount of Code Words of Length 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 12.--15. " DC2_CODE12 ,Amount of Code Words of Length 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x30 8.--11. " DC2_CODE11 ,Amount of Code Words of Length 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 4.--7. " DC2_CODE10 ,Amount of Code Words of Length 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x30 0.--3. " DC2_CODE9 ,Amount of Code Words of Length 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "VDEC_PIDXBA13,Reference Picture Index 13 Base Address"
|
|
hgroup.long 0x70++0x07
|
|
hide.long 0x00 "VDEC_PIDXBA14,Reference Picture Index 14 Base Address"
|
|
hide.long 0x04 "VDEC_PIDXBA15,Reference Picture Index 15 Base Address"
|
|
elif (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x40000000)
|
|
group.long 0x38++0x1B
|
|
line.long 0x00 "VDEC_PIDXBA0,Reference Picture Index 0 Base Address (Video, JPEG Decoder Output Chroma Picture)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x04 "VDEC_PIDXBA1,Reference Picture Index 1 Base Address (Video)"
|
|
hexmask.long 0x04 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x08 "VDEC_PIDXBA2,Reference Picture Index 2 Base Address (Video)"
|
|
hexmask.long 0x08 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x0C "VDEC_PIDXBA3,Reference Picture Index 3 Base Address (Video)"
|
|
hexmask.long 0x0C 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x10 "VDEC_PIDXBA4,Reference Picture Index 4 Base Address"
|
|
hexmask.long.word 0x10 16.--31. 1. " HEADER_LEN ,Header Length"
|
|
bitfld.long 0x10 13. " PIC_4M ,4M Pictures Allowed" "Only 1 MV/MB,4 MV/MB allowed"
|
|
textline " "
|
|
bitfld.long 0x10 11. " RED_REF_EN ,Range Reduce Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9.--10. " DIFF_MV_RANGE ,Differential Motion Vector Range" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 6.--7. " MV_RANGE ,Motion Vector Range" "[-64 63.f] [-32 31.f],[-128 127.f] [-64 63.f],[-512 511.f] [-128 127.f],[-1024 1023.f] [-256 255.f]"
|
|
bitfld.long 0x10 5. " OVERLAP_EN ,Overlap Smoothing Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3.--4. " OVERLAP_SM ,Overlap Smoothing Method" "Disabled,All macroblocks,Depends on overflagmb syntax element,?..."
|
|
bitfld.long 0x10 2. " ACC_FW ,Forward Motion Vector" "1/2,1/4"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RCB ,Rounding Control Bit" "Rounded,Clipped"
|
|
bitfld.long 0x10 0. " ANC ,Anchor Picture Type" "Intra,Inter"
|
|
line.long 0x14 "VDEC_PIDXBA5,Reference Picture Index 5 Base Address"
|
|
bitfld.long 0x14 24. " ICOMP3 ,Intensity Compensation Value" "Disabled,Enabled"
|
|
hexmask.long.byte 0x14 16.--23. 1. " IScale3 ,IScale Value"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--15. 1. " ISHIFT3 ,IShift Value"
|
|
line.long 0x18 "VDEC_PIDXBA6,Reference Picture Index 6 Base Address"
|
|
bitfld.long 0x18 24. " ICOMP4 ,Intensity Compensation Value" "Disabled,Enabled"
|
|
hexmask.long.byte 0x18 16.--23. 1. " IScale4 ,IScale Value"
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--15. 1. " ISHIFT4 ,IShift Value"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA7,Reference Picture Index 7 Base Address"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA8,Reference Picture Index 8 Base Address"
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA9,Reference Picture Index 9 Base Address"
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA10,Reference Picture Index 10 Base Address"
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA11,Reference Picture Index 11 Base Address"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA12,Reference Picture Index 12 Base Address"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "VDEC_PIDXBA13,Reference Picture Index 13 Base Address (VC-1)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
hgroup.long 0x070++0x07
|
|
hide.long 0x00 "VDEC_PIDXBA14,Reference Picture Index 14 Base Address"
|
|
hide.long 0x04 "VDEC_PIDXBA15,Reference Picture Index 15 Base Address"
|
|
elif ((((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x50000000)||(((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x60000000))
|
|
group.long 0x38++0x13
|
|
line.long 0x00 "VDEC_PIDXBA0,Reference Picture Index 0 Base Address (Video)"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x04 "VDEC_PIDXBA1,Reference Picture Index 1 Base Address (Video)"
|
|
hexmask.long 0x04 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x08 "VDEC_PIDXBA2,Reference Picture Index 2 Base Address (Video)"
|
|
hexmask.long 0x08 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x0C "VDEC_PIDXBA3,Reference Picture Index 3 Base Address (Video)"
|
|
hexmask.long 0x0C 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x10 "VDEC_PIDXBA4,Reference Picture Index 4 Base Address"
|
|
bitfld.long 0x10 19. " SCANF ,Alternate Scan Flag" "Low,High"
|
|
bitfld.long 0x10 15.--18. " FW_HOR_BN ,Forward Horizontal Bit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 11.--14. " FW_VER_BN ,Forward Vertical Bit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 7.--10. " BW_HOR_BN ,Backward Horizontal Bit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 3.--6. " BW_VER_BN ,Backward Vertical Bit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 2. " ACC_FW ,Forward Motion Vector" "1 pel,1/2 pel"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACC_BW ,Forward Motion Vector" "1 pel,1/2 pel"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA5,Reference Picture Index 5 Base Address"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA6,Reference Picture Index 6 Base Address"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA7,Reference Picture Index 7 Base Address"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA8,Reference Picture Index 8 Base Address"
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA9,Reference Picture Index 9 Base Address"
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA10,Reference Picture Index 10 Base Address"
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA11,Reference Picture Index 11 Base Address"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA12,Reference Picture Index 12 Base Address"
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA13,Reference Picture Index 13 Base Address"
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA14,Reference Picture Index 14 Base Address"
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "VDEC_PIDXBA15,Reference Picture Index 15 Base Address"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000)
|
|
group.long 0x78++0x27
|
|
line.long 0x00 "VDEC_PNR0,Reference Picture Number Register 0 (H.264)"
|
|
hexmask.long.word 0x00 16.--31. 1. " REFER1 ,Reference Picture Number for Index 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " REFER0 ,Reference Picture Number for Index 0"
|
|
line.long 0x04 "VDEC_PNR1,Reference Picture Number Register 1 (H.264)"
|
|
hexmask.long.word 0x04 16.--31. 1. " REFER3 ,Reference Picture Number for Index 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " REFER2 ,Reference Picture Number for Index 2"
|
|
line.long 0x08 "VDEC_PNR2,Reference Picture Number Register 2 (H.264)"
|
|
hexmask.long.word 0x08 16.--31. 1. " REFER5 ,Reference Picture Number for Index 5"
|
|
hexmask.long.word 0x08 0.--15. 1. " REFER4 ,Reference Picture Number for Index 4"
|
|
line.long 0x0C "VDEC_PNR3,Reference Picture Number Register 3 (H.264)"
|
|
hexmask.long.word 0x0C 16.--31. 1. " REFER7 ,Reference Picture Number for Index 7"
|
|
hexmask.long.word 0x0C 0.--15. 1. " REFER6 ,Reference Picture Number for Index 6"
|
|
line.long 0x10 "VDEC_PNR4,Reference Picture Number Register 4 (H.264)"
|
|
hexmask.long.word 0x10 16.--31. 1. " REFER9 ,Reference Picture Number for Index 9"
|
|
hexmask.long.word 0x10 0.--15. 1. " REFER8 ,Reference Picture Number for Index 8"
|
|
line.long 0x14 "VDEC_PNR5,Reference Picture Number Register 5 (H.264)"
|
|
hexmask.long.word 0x14 16.--31. 1. " REFER11 ,Reference Picture Number for Index 11"
|
|
hexmask.long.word 0x14 0.--15. 1. " REFER10 ,Reference Picture Number for Index 10"
|
|
line.long 0x18 "VDEC_PNR6,Reference Picture Number Register 6 (H.264)"
|
|
hexmask.long.word 0x18 16.--31. 1. " REFER13 ,Reference Picture Number for Index 13"
|
|
hexmask.long.word 0x18 0.--15. 1. " REFER12 ,Reference Picture Number for Index 12"
|
|
line.long 0x1C "VDEC_PNR7,Reference Picture Number Register 7 (H.264)"
|
|
hexmask.long.word 0x1C 16.--31. 1. " REFER15 ,Reference Picture Number for Index 15"
|
|
hexmask.long.word 0x1C 0.--15. 1. " REFER14 ,Reference Picture Number for Index 14"
|
|
line.long 0x20 "VDEC_PLTFR,Reference Picture Long Term Flag Register (H.264)"
|
|
hexmask.long.word 0x20 0.--31. 1. " LTF ,Long Term Flag"
|
|
line.long 0x24 "VDEC_PVFR,Reference Picture Valid Flag Register (H.264)"
|
|
hexmask.long.word 0x24 0.--31. 1. " VF ,Valid Flag"
|
|
else
|
|
hgroup.long 0x78++0x27
|
|
hide.long 0x00 "VDEC_PNR0,Reference Picture Number Register 0"
|
|
hide.long 0x04 "VDEC_PNR1,Reference Picture Number Register 1"
|
|
hide.long 0x08 "VDEC_PNR2,Reference Picture Number Register 2"
|
|
hide.long 0x0C "VDEC_PNR3,Reference Picture Number Register 3"
|
|
hide.long 0x10 "VDEC_PNR4,Reference Picture Number Register 4"
|
|
hide.long 0x14 "VDEC_PNR5,Reference Picture Number Register 5"
|
|
hide.long 0x18 "VDEC_PNR6,Reference Picture Number Register 6"
|
|
hide.long 0x1C "VDEC_PNR7,Reference Picture Number Register 7"
|
|
hide.long 0x20 "VDEC_PLTFR,Reference Picture Long Term Flag Register"
|
|
hide.long 0x24 "VDEC_PVFR,Reference Picture Valid Flag Register"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)!=0x40000000)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "VDEC_SDTBA,Standard Dependent Tables Base Address"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
else
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "VDEC_SDTBA,Standard Dependent Tables Base Address"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)!=0x30000000)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "VDEC_DMMVBA,Direct Mode Motion Vector Base Address"
|
|
hexmask.long 0x00 2.--31. 2. " BA ,Base Address"
|
|
else
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "VDEC_DMMVBA,Direct Mode Motion Vector Base Address"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)==0x00000000)
|
|
group.long 0xA8++0x17
|
|
line.long 0x00 "VDEC_IRPLR0,H264 Initial Reference Picture List Register 0"
|
|
hexmask.long.byte 0x00 25.--29. 1. " IREFL_BW2 ,Initial Reference Picture List for Backward Picid 2"
|
|
hexmask.long.byte 0x00 20.--24. 1. " IREFL_FW2 ,Initial Reference Picture List for Forward Picid 2"
|
|
hexmask.long.byte 0x00 15.--19. 1. " IREFL_BW1 ,Initial Reference Picture List for Backward Picid 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 10.--14. 1. " IREFL_FW1 ,Initial Reference Picture List for Forward Picid 1"
|
|
hexmask.long.byte 0x00 5.--9. 1. " IREFL_BW0 ,Initial Reference Picture List for Backward Picid 0"
|
|
hexmask.long.byte 0x00 0.--4. 1. " IREFL_FW0 ,Initial Reference Picture List for Forward Picid 0"
|
|
line.long 0x04 "VDEC_IRPLR1,H264 Initial Reference Picture List Register 1"
|
|
hexmask.long.byte 0x04 25.--29. 1. " IREFL_BW5 ,Initial Reference Picture List for Backward Picid 5"
|
|
hexmask.long.byte 0x04 20.--24. 1. " IREFL_FW5 ,Initial Reference Picture List for Forward Picid 5"
|
|
hexmask.long.byte 0x04 15.--19. 1. " IREFL_BW4 ,Initial Reference Picture List for Backward Picid 4"
|
|
textline " "
|
|
hexmask.long.byte 0x04 10.--14. 1. " IREFL_FW4 ,Initial Reference Picture List for Forward Picid 4"
|
|
hexmask.long.byte 0x04 5.--9. 1. " IREFL_BW3 ,Initial Reference Picture List for Backward Picid 3"
|
|
hexmask.long.byte 0x04 0.--4. 1. " IREFL_FW3 ,Initial Reference Picture List for Forward Picid 3"
|
|
line.long 0x08 "VDEC_IRPLR2,H264 Initial Reference Picture List Register 2"
|
|
hexmask.long.byte 0x08 25.--29. 1. " IREFL_BW8 ,Initial Reference Picture List for Backward Picid 8"
|
|
hexmask.long.byte 0x08 20.--24. 1. " IREFL_FW8 ,Initial Reference Picture List for Forward Picid 8"
|
|
hexmask.long.byte 0x08 15.--19. 1. " IREFL_BW7 ,Initial Reference Picture List for Backward Picid 7"
|
|
textline " "
|
|
hexmask.long.byte 0x08 10.--14. 1. " IREFL_FW7 ,Initial Reference Picture List for Forward Picid 7"
|
|
hexmask.long.byte 0x08 5.--9. 1. " IREFL_BW6 ,Initial Reference Picture List for Backward Picid 6"
|
|
hexmask.long.byte 0x08 0.--4. 1. " IREFL_FW6 ,Initial Reference Picture List for Forward Picid 6"
|
|
line.long 0x0C "VDEC_IRPLR3,H264 Initial Reference Picture List Register 3"
|
|
hexmask.long.byte 0x0C 25.--29. 1. " IREFL_BW11 ,Initial Reference Picture List for Backward Picid 11"
|
|
hexmask.long.byte 0x0C 20.--24. 1. " IREFL_FW11 ,Initial Reference Picture List for Forward Picid 11"
|
|
hexmask.long.byte 0x0C 15.--19. 1. " IREFL_BW10 ,Initial Reference Picture List for Backward Picid 10"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " IREFL_FW10 ,Initial Reference Picture List for Forward Picid 10"
|
|
hexmask.long.byte 0x0C 5.--9. 1. " IREFL_BW9 ,Initial Reference Picture List for Backward Picid 9"
|
|
hexmask.long.byte 0x0C 0.--4. 1. " IREFL_FW9 ,Initial Reference Picture List for Forward Picid 9"
|
|
line.long 0x10 "VDEC_IRPLR4,H264 Initial Reference Picture List Register 4"
|
|
hexmask.long.byte 0x10 25.--29. 1. " IREFL_BW14 ,Initial Reference Picture List for Backward Picid 14"
|
|
hexmask.long.byte 0x10 20.--24. 1. " IREFL_FW14 ,Initial Reference Picture List for Forward Picid 14"
|
|
hexmask.long.byte 0x10 15.--19. 1. " IREFL_BW13 ,Initial Reference Picture List for Backward Picid 13"
|
|
textline " "
|
|
hexmask.long.byte 0x10 10.--14. 1. " IREFL_FW13 ,Initial Reference Picture List for Forward Picid 13"
|
|
hexmask.long.byte 0x10 5.--9. 1. " IREFL_BW12 ,Initial Reference Picture List for Backward Picid 12"
|
|
hexmask.long.byte 0x10 0.--4. 1. " IREFL_FW12 ,Initial Reference Picture List for Forward Picid 12"
|
|
line.long 0x14 "VDEC_IRPLR5,H264 Initial Reference Picture List Register 5"
|
|
hexmask.long.byte 0x14 5.--9. 1. " IREFL_BW15 ,Initial Reference Picture List for Backward Picid 15"
|
|
hexmask.long.byte 0x14 0.--4. 1. " IREFL_FW15 ,Initial Reference Picture List for Forward Picid 15"
|
|
else
|
|
group.long 0xA8++0x17
|
|
hide.long 0x00 "VDEC_IRPLR0,H264 Initial Reference Picture List Register 0"
|
|
hide.long 0x04 "VDEC_IRPLR1,H264 Initial Reference Picture List Register 1"
|
|
hide.long 0x08 "VDEC_IRPLR2,H264 Initial Reference Picture List Register 2"
|
|
hide.long 0x0C "VDEC_IRPLR3,H264 Initial Reference Picture List Register 3"
|
|
hide.long 0x10 "VDEC_IRPLR4,H264 Initial Reference Picture List Register 4"
|
|
hide.long 0x14 "VDEC_IRPLR5,H264 Initial Reference Picture List Register 5"
|
|
endif
|
|
if (((d.l(a:(0x00900000+0x0C)))&0xF0000000)!=0x30000000)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "VDEC_ECR,Error Concealment Register"
|
|
hexmask.long.word 0x00 23.--31. 1. " STARTMB_X ,Start MB from SW for X Dimension"
|
|
hexmask.long.byte 0x00 15.--22. 1. " STARTMB_Y ,Start MB from SW for Y Dimension"
|
|
else
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "VDEC_ECR,Error Concealment Register"
|
|
endif
|
|
group.long 0xF0++0x3B
|
|
line.long 0x00 "VDEC_PPIR,Post-Processor Interrupt Register"
|
|
bitfld.long 0x00 13. " BE ,Bus Error" "No error,Error"
|
|
bitfld.long 0x00 12. " PPR ,Post-processor Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ISET ,Post-processor Interrupt Set" "Clear,Set"
|
|
bitfld.long 0x00 4. " ID ,Interrupt Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIPE ,Decoder Post-processing Pipeline Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PPE ,Post-processor Standalone Enable" "Disabled,Enabled"
|
|
line.long 0x04 "VDEC_PPCR,Post Processor Device Configuration Register"
|
|
bitfld.long 0x04 15. " HLOCK ,HLOCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " AHB_BURST ,AHB precise burst and data discard enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PPDCGE ,Post-processor Dynamic Clock Gating Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PPI_LE ,Post-processor Input Endian Mode" "Big,Little"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PPO_LE ,Post-processor Output Endian Mode (for Y Cb Cr)" "Big,Little"
|
|
bitfld.long 0x04 0.--4. " MAX_BURST_LEN ,Maximum burst length for post-processor bus transactions" "INCR,SINGLE ,Reserved,Reserved,INCR4(Also INCR and SINGLE),Reserved,Reserved,Reserved,INCR8(Also INCR and SINGLE),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,INCR16(Also INCR and SINGLE),?..."
|
|
line.long 0x08 "VDEC_PPDCR,Post Processor Deinterlace Control Register"
|
|
bitfld.long 0x08 31. " DEINT_EN ,Deinterlace Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 16.--29. 1. " DEINT_THRD ,Threshold Value Used in Deinterlacing"
|
|
textline " "
|
|
bitfld.long 0x08 15. " BLEND_EN ,Blend Enable for Deinterlacing" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--14. 1. " EDGE_DET_VAL ,Edge Detect Value"
|
|
line.long 0x0C "VDEC_PIYTBA,Post Processor Input Y Top Field Picture Base Address"
|
|
hexmask.long 0x0C 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x10 "VDEC_PICBTBA,Post Processor Input Cb Top Field Picture Base Address"
|
|
hexmask.long 0x10 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x14 "VDEC_PICRBA,Post Processor Input Cr Picture Base Address"
|
|
hexmask.long 0x14 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x18 "VDEC_POYBA,Post Processor Output Y Picture Base Address"
|
|
hexmask.long 0x18 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x1C "VDEC_POCBA,Post Processor Output C Picture Base Address"
|
|
hexmask.long 0x1C 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x20 "VDEC_CAR,Post Processor Contrast Adjustment Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " THRD1 ,Threshold Value 1"
|
|
bitfld.long 0x20 23. " BA , " "Low ,High"
|
|
textline " "
|
|
hexmask.long.word 0x20 10.--19. 1. " OFFSET2 ,Offset Value 2"
|
|
hexmask.long.word 0x20 0.--9. 1. " OFFSET1 ,Offset Value 1"
|
|
line.long 0x24 "VDEC_CACCR,Post Processor Contrast Adjustment and Color Conversion Register"
|
|
hexmask.long.word 0x24 18.--27. 1. " COEFF_A2 ,Coefficient a2"
|
|
hexmask.long.word 0x24 8.--17. 1. " COEFF_A1 ,Coefficient a1"
|
|
textline " "
|
|
hexmask.long.byte 0x24 0.--7. 1. " THRD2 ,Threshold Value 2"
|
|
line.long 0x28 "VDEC_CCR,Post Processor Color Conversion Register"
|
|
hexmask.long.word 0x28 20.--29. 1. " COEFF_D ,Coefficient d"
|
|
hexmask.long.word 0x28 10.--19. 1. " COEFF_C ,Coefficient c"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--9. 1. " COEFF_B ,Coefficient b"
|
|
line.long 0x2C "VDEC_CCRMR,Post Processor Color Conversion and Rotation Mode Register"
|
|
hexmask.long.word 0x2C 21.--29. 1. " CROPSTART_X ,Crop Area X"
|
|
bitfld.long 0x2C 18.--20. " ROT_MODE ,Rotation Mode" "Disabled,+ 90,- 90,Horizontal,Vertical,180,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x2C 10.--17. 1. " COEFF_F ,Coefficient f"
|
|
hexmask.long.word 0x2C 0.--9. 1. " COEFF_E ,Coefficient e"
|
|
line.long 0x30 "VDEC_PISCR,Post Processor Input Picture Size and Cropping Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " CROPSTART_Y ,Crop Area Y"
|
|
hexmask.long.byte 0x30 18.--22. 1. " RANGEMAP_COEFF ,Range Map Value"
|
|
textline " "
|
|
hexmask.long.byte 0x30 8.--15. 1. " IN_PICT_H ,Input Picture Height"
|
|
hexmask.long.byte 0x30 0.--7. 1. " IN_PICT_W ,Input Picture Width"
|
|
line.long 0x34 "VDEC_PIYBBA,Post Processor Input Y Bottom Field Picture Base Address"
|
|
hexmask.long 0x34 2.--31. 2. " BA ,Base Address"
|
|
line.long 0x38 "VDEC_PICBBBA,Post Processor Input Cb Bottom Field Picture Base Address"
|
|
hexmask.long 0x38 2.--31. 2. " BA ,Base Address"
|
|
group.long 0x13C++0x3F
|
|
line.long 0x00 "VDEC_RGPSRR0,Post Processor R and G Padding and Scaling Ratio Register 0"
|
|
bitfld.long 0x00 31. " MAP_Y_EN ,Range map enable for luminance component" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAP_C_EN ,Range map enable for chrominance component" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " YCBCR_RAN ,Defines the YCbCr Range in RGB Conversion" "16..235/240,0...255"
|
|
bitfld.long 0x00 28. " RGBBY32 ,RGB Pixel Amount/32-bit Word" "1,2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 23.--27. 1. " RGB_R_PADD ,Padding for R-component"
|
|
hexmask.long.byte 0x00 18.--22. 1. " RGB_G_PADD ,Padding for G-component"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " SCALE_W_RATIO ,Scaling Ratio for Width"
|
|
line.long 0x04 "VDEC_BPSRR1,Post Processor B Padding and Scaling Ratio Register 1"
|
|
bitfld.long 0x04 27.--29. " PP_IN_STRUCT ,PP Input Data Picture Structure" "Top field/progressive frame,Bottom field,Interlaced field,Interlaced frame,Ripped top field,Ripped bottom,?..."
|
|
bitfld.long 0x04 25.--26. " H_SCAL_MOD ,Horizontal Scaling Mode" "Off,Up,Down,?..."
|
|
textline " "
|
|
bitfld.long 0x04 23.--24. " V_SCAL_MOD ,Vertical Scaling Mode" "Off,Up,Down,?..."
|
|
hexmask.long.byte 0x04 18.--22. 1. " RGB_B_PADD ,Padding for B-component"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " SCALE_H_RATIO ,Scaling Ratio for Height"
|
|
line.long 0x08 "VDEC_SRR2,Post Processor Scaling Ratio Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " W_SCALE_INV ,Inverse Scaling for Width"
|
|
hexmask.long.word 0x08 0.--15. 1. " H_SCALE_INV ,Inverse Scaling for Height"
|
|
line.long 0x0C "VDEC_REDMR,Post Processor Red Channel Mask Register"
|
|
bitfld.long 0x0C 31. " MASK[31:0] ,Bit 31 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 30. ",Bit 30 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 29. ",Bit 29 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 28. ",Bit 28 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 27. ",Bit 27 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 26. ",Bit 26 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 25. ",Bit 25 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 24. ",Bit 24 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 23. ",Bit 23 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 22. ",Bit 22 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 21. ",Bit 21 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 20. ",Bit 20 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 19. ",Bit 19 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 18. ",Bit 18 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 17. ",Bit 17 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 16. ",Bit 16 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 15. ",Bit 15 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 14. ",Bit 14 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 13. ",Bit 13 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 12. ",Bit 12 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 11. ",Bit 11 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 10. ",Bit 10 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 9. ",Bit 9 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 8. ",Bit 8 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 7. ",Bit 7 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 6. ",Bit 6 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 5. ",Bit 5 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 4. ",Bit 4 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 3. ",Bit 3 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 2. ",Bit 2 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 1. ",Bit 1 Mask for R Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x0C 0. ",Bit 0 Mask for R Component (and Alpha Channel)" "0,1"
|
|
line.long 0x10 "VDEC_GREMR,Post Processor Green Channel Mask Register"
|
|
bitfld.long 0x10 31. " MASK[31:0] ,Bit 31 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 30. ",Bit 30 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 29. ",Bit 29 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 28. ",Bit 28 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 27. ",Bit 27 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 26. ",Bit 26 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 25. ",Bit 25 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 24. ",Bit 24 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 23. ",Bit 23 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 22. ",Bit 22 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 21. ",Bit 21 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 20. ",Bit 20 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 19. ",Bit 19 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 18. ",Bit 18 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 17. ",Bit 17 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 16. ",Bit 16 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 15. ",Bit 15 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 14. ",Bit 14 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 13. ",Bit 13 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 12. ",Bit 12 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 11. ",Bit 11 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 10. ",Bit 10 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 9. ",Bit 9 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 8. ",Bit 8 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 7. ",Bit 7 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 6. ",Bit 6 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 5. ",Bit 5 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 4. ",Bit 4 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 3. ",Bit 3 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 2. ",Bit 2 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 1. ",Bit 1 Mask for G Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x10 0. ",Bit 0 Mask for G Component (and Alpha Channel)" "0,1"
|
|
line.long 0x14 "VDEC_BLUMR,Post Processor Blue Channel Mask Register"
|
|
bitfld.long 0x14 31. " MASK[31:0] ,Bit 31 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 30. ",Bit 30 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 29. ",Bit 29 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 28. ",Bit 28 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 27. ",Bit 27 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 26. ",Bit 26 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 25. ",Bit 25 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 24. ",Bit 24 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 23. ",Bit 23 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 22. ",Bit 22 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 21. ",Bit 21 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 20. ",Bit 20 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 19. ",Bit 19 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 18. ",Bit 18 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 17. ",Bit 17 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 16. ",Bit 16 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 15. ",Bit 15 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 14. ",Bit 14 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 13. ",Bit 13 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 12. ",Bit 12 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 11. ",Bit 11 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 10. ",Bit 10 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 9. ",Bit 9 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 8. ",Bit 8 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 7. ",Bit 7 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 6. ",Bit 6 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 5. ",Bit 5 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 4. ",Bit 4 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 3. ",Bit 3 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 2. ",Bit 2 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 1. ",Bit 1 Mask for B Component (and Alpha Channel)" "0,1"
|
|
bitfld.long 0x14 0. ",Bit 0 Mask for B Component (and Alpha Channel)" "0,1"
|
|
line.long 0x18 "VDEC_CTLR,Post Processor Control Register"
|
|
bitfld.long 0x18 29.--31. " IN_FORMAT ,PP Input Picture Data Format" "YUYV 4:2:2,4:2:0 Semi-p,4:2:0 p,4:0:0,4:2:2 Semi-p ,4:2:0 Semi-p in tiled format,4:4:0,?..."
|
|
bitfld.long 0x18 26.--28. " OUT_FORMAT ,Output Picture Data Format" "RGB,4:2:0 p,4:2:2 p,YUYV 4:2:2,4:4:4 p,YCh 4:2:0,YCh 4:2:2,YCh 4:4:4"
|
|
textline " "
|
|
hexmask.long.word 0x18 15.--25. 1. " OUT_H ,Scaled Picture Height in Pixels"
|
|
hexmask.long.word 0x18 4.--14. 1. " OUT_W ,Scaled Picture Width in Pixels"
|
|
textline " "
|
|
bitfld.long 0x18 1. " CROP8_R_EN ,Crop 8 Right Pixel" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " CROP8_D_EN ,Crop 8 Down Pixel" "Disabled,Enabled"
|
|
line.long 0x1C "VDEC_M1STR,Post Processor Mask 1 Start Coordinate Register"
|
|
bitfld.long 0x1C 24.--27. " RMV ,Range Map Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 23. " MAP_COEFF ," "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 22. " M1_AB_EN ,Mask 1 Alpha Blending Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x1C 11.--21. 1. " M1_START_Y ,Mask 1 Y start"
|
|
textline " "
|
|
hexmask.long.word 0x1C 0.--10. 1. " M1_START_X ,Mask 1 X Start"
|
|
line.long 0x20 "VDEC_M2STR,Post Processor Mask 2 Start Coordinate Register"
|
|
bitfld.long 0x20 22. " M2_AB_EN ,Mask 2 Alpha Blending Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x20 11.--21. 1. " M2_START_Y ,Mask 2 Y start"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--10. 1. " M2_START_X ,Mask 2 X Start"
|
|
line.long 0x24 "VDEC_M1SZOWR,Post Processor Mask 1 Size and PP Original Width Register"
|
|
hexmask.long.word 0x24 23.--31. 1. " P_ORIG_W ,PP Input Picture Original Width"
|
|
bitfld.long 0x24 22. " M1_EN ,Mask 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x24 11.--21. 1. " M1_END_Y ,Mask 1 Y End"
|
|
hexmask.long.word 0x24 0.--10. 1. " M1_END_X ,Mask 1 X End"
|
|
line.long 0x28 "VDEC_M2SZR,Post Processor Mask 2 Size Register"
|
|
bitfld.long 0x28 22. " M2_EN ,Mask 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x28 11.--21. 1. " M2_END_Y ,Mask 2 Y End"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--10. 1. " M2_END_X ,Mask 2 X End"
|
|
line.long 0x2C "VDEC_PIPR0,Post Processor Picture-in-Picture Register 0"
|
|
bitfld.long 0x2C 29. " RIGHT_EN ,Right side overcross enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 28. " LEFT_EN ,Left side overcross enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 27. " UP_EN ,Upward overcross enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 26. " DOWN_EN ,Downward overcross enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x2C 15.--25. 1. " UP_CROSS ,Up Cross"
|
|
hexmask.long.word 0x2C 0.--10. 1. " DOWN_CROSS ,Down Cross"
|
|
line.long 0x30 "VDEC_DPIPR1,Post Processor Dithering and Picture-in-Picture Register 1"
|
|
bitfld.long 0x30 30.--31. " DITH_SEL_R ,Dithering Control for RChannel" "Disabled,4 b matrix,5 b matrix,6 b matrix"
|
|
bitfld.long 0x30 28.--29. " DITH_SEL_G ,Dithering Control for GChannel" "Disabled,4 b matrix,5 b matrix,6 b matrix"
|
|
textline " "
|
|
bitfld.long 0x30 26.--27. " DITH_SEL_B ,Dithering Control for BChannel" "Disabled,4 b matrix,5 b matrix,6 b matrix"
|
|
hexmask.long.word 0x30 11.--21. 1. " RIGHT_CROSS ,Right Cross"
|
|
textline " "
|
|
hexmask.long.word 0x30 0.--10. 1. " LEFT_CROSS ,Left Cross"
|
|
line.long 0x34 "VDEC_DWR,Post Processor Display Width Register"
|
|
hexmask.long.word 0x34 0.--11. 1. " DISP_WIDTH ,Display Width"
|
|
line.long 0x38 "VDEC_ABGUI1BA,Post Processor Alpha Blending GUI 1 Component Base Address"
|
|
hexmask.long 0x38 2.--31. 2. " AB_GUI1_BA ,Alpha Blending GUI 1 Base Address"
|
|
line.long 0x3C "VDEC_ABGUI2BA,Post Processor Alpha Blending GUI 2 Component Base Address"
|
|
hexmask.long 0x3C 2.--31. 2. " AB_GUI2_BA ,Alpha Blending GUI 2 Base Address"
|
|
width 0xb
|
|
tree.end
|
|
tree "LCDC (LCD Controller)"
|
|
base ad:0x00500000
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
hexmask.long 0x00 2.--31. 0x4 " BADDR-U ,Base Address for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
line.long 0x04 "DMABADDR2,DMA Base Address Register 2"
|
|
rgroup.long 0x08++0xf
|
|
line.long 0x00 "DMAFRMPT1,DMA Frame Pointer Register 1"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMPT-U ,Current value of frame pointer for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
line.long 0x04 "DMAFRMPT2,DMA Frame Pointer Register 2"
|
|
hexmask.long.tbyte 0x04 0.--22. 1. " FRMPT-L ,Current value of frame pointer for the Lower panel in dual scan mode"
|
|
line.long 0x8 "DMAFRMADD1,DMA Frame Address Register 1"
|
|
line.long 0xC "DMAFRMADD2,DMA Frame Address Register 2"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DMAFRMCFG,DMA Frame Configuration Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BRSTLN ,Burst Length"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMSIZE ,Frame Size"
|
|
line.long 0x4 "DMACON,DMA Control Register"
|
|
bitfld.long 0x4 4. " DMA2DEN ,DMA 2D Adressing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " DMAUPDT ,DMA Configuration Update" "No effect,Updated"
|
|
textline " "
|
|
bitfld.long 0x4 2. " DMABUSY ,DMA Busy" "Idle,Busy"
|
|
bitfld.long 0x4 1. " DMARST ,DMA Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x0 "DMA2DCFG,DMA 2D Adressing Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " PIXELOFF ,DAM2D Addressing Pixel Offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRINC ,DMA 2D Addressing Address increment"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "LCDCON1,LCD Control Register 1"
|
|
hexmask.long.word 0x00 21.--31. 1. " LINECNT ,Line Counter"
|
|
hexmask.long.word 0x00 12.--20. 1. " CLKVAL ,Clock Divider"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass lcd_pclk Divider" "Not bypassed,Bypassed"
|
|
if ((d.l(ad:0x00500000+0x804)&0x3)==0x2)
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,24 bpp/unpacked,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00500000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00500000+0x804)&0x4)==(0x4)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "Reserved,8-bit,16-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00500000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00500000+0x804)&0x4)==(0x0)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "4-bit,8-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
else
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
endif
|
|
group.long 0x808++0xf
|
|
line.long 0x0 "LCDTIM1,LCD Timing Configuration Register 1"
|
|
bitfld.long 0x0 24.--27. " VHDLY ,Vertical to horizontal delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
hexmask.long.byte 0x0 16.--21. 1. 1. " VPW ,Vertical Synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.byte 0x0 0.--7. 1. " VFP ,Vertical Front Porch"
|
|
line.long 0x4 "LCDTIM2,LCD Timing Configuration Register 2"
|
|
hexmask.long.word 0x4 21.--31. 1. 1. " HFP ,Horizontal Front Porch"
|
|
hexmask.long.byte 0x4 8.--13. 1. 1. " HPW ,Horizontal synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. 1. " HBP ,Horizontal Back Porch"
|
|
line.long 0x8 "LCDFRMCFG,LCD Frame Configuration Register"
|
|
hexmask.long.word 0x8 21.--31. 1. " LINESIZE ,Horizontal size of LCD module"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--10. 1. " LINEVAL ,Vertical size of LCD module"
|
|
line.long 0xC "LCDFIFO,LCD FIFO Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " FIFOTH ,FIFO Threshold"
|
|
group.long 0x818++0x3
|
|
line.long 0x0 "LCDMVAL,LCD_MODE Toggle Rate Value Register"
|
|
bitfld.long 0x0 31. " MMODE ,LCD_MODE toggle rate select" "Each frame,MVAL"
|
|
hexmask.long.byte 0x0 0.--7. 1. 1. " MVAL ,LCD_MODE toggle rate value"
|
|
group.long 0x81c--0x847
|
|
line.long 0x00 "DP1_2,Dithering Pattern DP1_2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DP1_2 ,Pattern value for 1/2 duty cycle"
|
|
line.long 0x04 "DP4_7,Dithering Pattern DP4_7 Register"
|
|
hexmask.long 0x04 0.--27. 1. " DP4_7 ,Pattern value for 4/7 duty cycle"
|
|
line.long 0x8 "DP3_5,Dithering Pattern DP3_5 Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. " DP3_5 ,Pattern value for 3/5 duty cycle"
|
|
line.long 0xc "DP2_3,Dithering Pattern DP2_3 Register"
|
|
hexmask.long.word 0xc 0.--11. 1. " DP2_3 ,Pattern value for 2/3 duty cycle"
|
|
line.long 0x10 "DP5_7,Dithering Pattern DP5_7 Register"
|
|
hexmask.long 0x10 0.--27. 1. " DP5_7 ,Pattern value for 5/7 duty cycle"
|
|
line.long 0x14 "DP3_4,Dithering Pattern DP3_4 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DP3_4 ,Pattern value for 3/4 duty cycle"
|
|
line.long 0x18 "DP4_5,Dithering Pattern DP4_5 Register"
|
|
hexmask.long.tbyte 0x18 0.--19. 1. " DP4_5 ,Pattern value for 4/5 duty cycle"
|
|
line.long 0x1c "DP6_7,Dithering Pattern DP6_7 Register"
|
|
hexmask.long 0x1c 0.--27. 1. " DP6_7 ,Pattern value for 6/7 duty cycle"
|
|
line.long 0x20 "PWRCON,Power Control Register"
|
|
bitfld.long 0x20 31. " LCD_BUSY ,LCD Busy" "Idle,Busy"
|
|
hexmask.long.byte 0x20 1.--7. 1. " GUARD_TIME ,Guard Time"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LCD_PWR ,LCD module power control" "Low,High"
|
|
line.long 0x24 "CONTRAST_CTR,Contrast Control Register"
|
|
bitfld.long 0x24 3. " ENA ,PWM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " POL ,Output polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " PS ,Prescaler" "fLCDC_CLOCK,fLCDC_CLOCK/2,fLCDC_CLOCK/4,fLCDC_CLOCK/8"
|
|
line.long 0x28 "CONTRAST_VAL,Contrast Value Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " CVAL ,PWM compare value"
|
|
group.long 0x850++0x3
|
|
line.long 0x0 "LCD_IMR,LCD Interrupt Mask Register"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " MERIM_set/clr ,DMA Memory error Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OWRIM_set/clr ,FIFO overwrite Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " UFLWIM_set/clr ,FIFO underflow Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EOFIM_set/clr ,DMA End of frame Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " LSTLNIM_set/clr ,Last line Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " LNIM_set/clr ,Line Interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x3
|
|
line.long 0x0 "LCD_ISR,LCD Interrupt Status Register"
|
|
bitfld.long 0x0 6. " MERIS ,DMA Memory error Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 5. " OWRIS ,FIFO overwrite Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UFLWIS ,FIFO underflow Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 2. " EOFIS ,DMA End of frame Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LSTLNIS ,Last line Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 0. " LNIS ,Line Interrupt status" "Not active,Active"
|
|
wgroup.long 0x858++0x3
|
|
line.long 0x00 "LCD_ICR,LCD Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " MERIC ,DMA Memory error Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " OWRIC ,FIFO overwrite Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIC ,FIFO underflow Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " EOFIC ,DMA End of frame Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIC ,Last line Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " LNIC ,Line Interrupt clear" "No effect,Clear"
|
|
wgroup.long 0x860++03
|
|
line.long 0x00 "LCD_ITR,LCD Interrupt Test Register"
|
|
bitfld.long 0x00 6. " MERIT ,DMA Memory error interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 5. " OWRIT ,FIFO overwrite interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIT ,FIFO underflow interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 2. " EOFIT ,DMA End of frame interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIT ,Last line interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 0. " LNIT ,Line interrupt test" "No effect,Set"
|
|
rgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "LCD_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "LCD_WPSR,LCD Write Protect Status Register"
|
|
in
|
|
tree "Palette Entry Registers"
|
|
tree "0-63"
|
|
group.long 0xc00++0xff
|
|
line.long 0x0 "LUT_ENTRY_0 ,Palette Entry 0 "
|
|
line.long 0x4 "LUT_ENTRY_1 ,Palette Entry 1 "
|
|
line.long 0x8 "LUT_ENTRY_2 ,Palette Entry 2 "
|
|
line.long 0xC "LUT_ENTRY_3 ,Palette Entry 3 "
|
|
line.long 0x10 "LUT_ENTRY_4 ,Palette Entry 4 "
|
|
line.long 0x14 "LUT_ENTRY_5 ,Palette Entry 5 "
|
|
line.long 0x18 "LUT_ENTRY_6 ,Palette Entry 6 "
|
|
line.long 0x1C "LUT_ENTRY_7 ,Palette Entry 7 "
|
|
line.long 0x20 "LUT_ENTRY_8 ,Palette Entry 8 "
|
|
line.long 0x24 "LUT_ENTRY_9 ,Palette Entry 9 "
|
|
line.long 0x28 "LUT_ENTRY_10 ,Palette Entry 10 "
|
|
line.long 0x2C "LUT_ENTRY_11 ,Palette Entry 11 "
|
|
line.long 0x30 "LUT_ENTRY_12 ,Palette Entry 12 "
|
|
line.long 0x34 "LUT_ENTRY_13 ,Palette Entry 13 "
|
|
line.long 0x38 "LUT_ENTRY_14 ,Palette Entry 14 "
|
|
line.long 0x3C "LUT_ENTRY_15 ,Palette Entry 15 "
|
|
line.long 0x40 "LUT_ENTRY_16 ,Palette Entry 16 "
|
|
line.long 0x44 "LUT_ENTRY_17 ,Palette Entry 17 "
|
|
line.long 0x48 "LUT_ENTRY_18 ,Palette Entry 18 "
|
|
line.long 0x4C "LUT_ENTRY_19 ,Palette Entry 19 "
|
|
line.long 0x50 "LUT_ENTRY_20 ,Palette Entry 20 "
|
|
line.long 0x54 "LUT_ENTRY_21 ,Palette Entry 21 "
|
|
line.long 0x58 "LUT_ENTRY_22 ,Palette Entry 22 "
|
|
line.long 0x5C "LUT_ENTRY_23 ,Palette Entry 23 "
|
|
line.long 0x60 "LUT_ENTRY_24 ,Palette Entry 24 "
|
|
line.long 0x64 "LUT_ENTRY_25 ,Palette Entry 25 "
|
|
line.long 0x68 "LUT_ENTRY_26 ,Palette Entry 26 "
|
|
line.long 0x6C "LUT_ENTRY_27 ,Palette Entry 27 "
|
|
line.long 0x70 "LUT_ENTRY_28 ,Palette Entry 28 "
|
|
line.long 0x74 "LUT_ENTRY_29 ,Palette Entry 29 "
|
|
line.long 0x78 "LUT_ENTRY_30 ,Palette Entry 30 "
|
|
line.long 0x7C "LUT_ENTRY_31 ,Palette Entry 31 "
|
|
line.long 0x80 "LUT_ENTRY_32 ,Palette Entry 32 "
|
|
line.long 0x84 "LUT_ENTRY_33 ,Palette Entry 33 "
|
|
line.long 0x88 "LUT_ENTRY_34 ,Palette Entry 34 "
|
|
line.long 0x8C "LUT_ENTRY_35 ,Palette Entry 35 "
|
|
line.long 0x90 "LUT_ENTRY_36 ,Palette Entry 36 "
|
|
line.long 0x94 "LUT_ENTRY_37 ,Palette Entry 37 "
|
|
line.long 0x98 "LUT_ENTRY_38 ,Palette Entry 38 "
|
|
line.long 0x9C "LUT_ENTRY_39 ,Palette Entry 39 "
|
|
line.long 0xA0 "LUT_ENTRY_40 ,Palette Entry 40 "
|
|
line.long 0xA4 "LUT_ENTRY_41 ,Palette Entry 41 "
|
|
line.long 0xA8 "LUT_ENTRY_42 ,Palette Entry 42 "
|
|
line.long 0xAC "LUT_ENTRY_43 ,Palette Entry 43 "
|
|
line.long 0xB0 "LUT_ENTRY_44 ,Palette Entry 44 "
|
|
line.long 0xB4 "LUT_ENTRY_45 ,Palette Entry 45 "
|
|
line.long 0xB8 "LUT_ENTRY_46 ,Palette Entry 46 "
|
|
line.long 0xBC "LUT_ENTRY_47 ,Palette Entry 47 "
|
|
line.long 0xC0 "LUT_ENTRY_48 ,Palette Entry 48 "
|
|
line.long 0xC4 "LUT_ENTRY_49 ,Palette Entry 49 "
|
|
line.long 0xC8 "LUT_ENTRY_50 ,Palette Entry 50 "
|
|
line.long 0xCC "LUT_ENTRY_51 ,Palette Entry 51 "
|
|
line.long 0xD0 "LUT_ENTRY_52 ,Palette Entry 52 "
|
|
line.long 0xD4 "LUT_ENTRY_53 ,Palette Entry 53 "
|
|
line.long 0xD8 "LUT_ENTRY_54 ,Palette Entry 54 "
|
|
line.long 0xDC "LUT_ENTRY_55 ,Palette Entry 55 "
|
|
line.long 0xE0 "LUT_ENTRY_56 ,Palette Entry 56 "
|
|
line.long 0xE4 "LUT_ENTRY_57 ,Palette Entry 57 "
|
|
line.long 0xE8 "LUT_ENTRY_58 ,Palette Entry 58 "
|
|
line.long 0xEC "LUT_ENTRY_59 ,Palette Entry 59 "
|
|
line.long 0xF0 "LUT_ENTRY_60 ,Palette Entry 60 "
|
|
line.long 0xF4 "LUT_ENTRY_61 ,Palette Entry 61 "
|
|
line.long 0xF8 "LUT_ENTRY_62 ,Palette Entry 62 "
|
|
line.long 0xFC "LUT_ENTRY_63 ,Palette Entry 63 "
|
|
tree.end
|
|
tree "64-127"
|
|
group.long 0xd00++0xff
|
|
line.long 0x0 "LUT_ENTRY_64 ,Palette Entry 64 "
|
|
line.long 0x4 "LUT_ENTRY_65 ,Palette Entry 65 "
|
|
line.long 0x8 "LUT_ENTRY_66 ,Palette Entry 66 "
|
|
line.long 0xC "LUT_ENTRY_67 ,Palette Entry 67 "
|
|
line.long 0x10 "LUT_ENTRY_68 ,Palette Entry 68 "
|
|
line.long 0x14 "LUT_ENTRY_69 ,Palette Entry 69 "
|
|
line.long 0x18 "LUT_ENTRY_70 ,Palette Entry 70 "
|
|
line.long 0x1C "LUT_ENTRY_71 ,Palette Entry 71 "
|
|
line.long 0x20 "LUT_ENTRY_72 ,Palette Entry 72 "
|
|
line.long 0x24 "LUT_ENTRY_73 ,Palette Entry 73 "
|
|
line.long 0x28 "LUT_ENTRY_74 ,Palette Entry 74 "
|
|
line.long 0x2C "LUT_ENTRY_75 ,Palette Entry 75 "
|
|
line.long 0x30 "LUT_ENTRY_76 ,Palette Entry 76 "
|
|
line.long 0x34 "LUT_ENTRY_77 ,Palette Entry 77 "
|
|
line.long 0x38 "LUT_ENTRY_78 ,Palette Entry 78 "
|
|
line.long 0x3C "LUT_ENTRY_79 ,Palette Entry 79 "
|
|
line.long 0x40 "LUT_ENTRY_80 ,Palette Entry 80 "
|
|
line.long 0x44 "LUT_ENTRY_81 ,Palette Entry 81 "
|
|
line.long 0x48 "LUT_ENTRY_82 ,Palette Entry 82 "
|
|
line.long 0x4C "LUT_ENTRY_83 ,Palette Entry 83 "
|
|
line.long 0x50 "LUT_ENTRY_84 ,Palette Entry 84 "
|
|
line.long 0x54 "LUT_ENTRY_85 ,Palette Entry 85 "
|
|
line.long 0x58 "LUT_ENTRY_86 ,Palette Entry 86 "
|
|
line.long 0x5C "LUT_ENTRY_87 ,Palette Entry 87 "
|
|
line.long 0x60 "LUT_ENTRY_88 ,Palette Entry 88 "
|
|
line.long 0x64 "LUT_ENTRY_89 ,Palette Entry 89 "
|
|
line.long 0x68 "LUT_ENTRY_90 ,Palette Entry 90 "
|
|
line.long 0x6C "LUT_ENTRY_91 ,Palette Entry 91 "
|
|
line.long 0x70 "LUT_ENTRY_92 ,Palette Entry 92 "
|
|
line.long 0x74 "LUT_ENTRY_93 ,Palette Entry 93 "
|
|
line.long 0x78 "LUT_ENTRY_94 ,Palette Entry 94 "
|
|
line.long 0x7C "LUT_ENTRY_95 ,Palette Entry 95 "
|
|
line.long 0x80 "LUT_ENTRY_96 ,Palette Entry 96 "
|
|
line.long 0x84 "LUT_ENTRY_97 ,Palette Entry 97 "
|
|
line.long 0x88 "LUT_ENTRY_98 ,Palette Entry 98 "
|
|
line.long 0x8C "LUT_ENTRY_99 ,Palette Entry 99 "
|
|
line.long 0x90 "LUT_ENTRY_100,Palette Entry 100"
|
|
line.long 0x94 "LUT_ENTRY_101,Palette Entry 101"
|
|
line.long 0x98 "LUT_ENTRY_102,Palette Entry 102"
|
|
line.long 0x9C "LUT_ENTRY_103,Palette Entry 103"
|
|
line.long 0xA0 "LUT_ENTRY_104,Palette Entry 104"
|
|
line.long 0xA4 "LUT_ENTRY_105,Palette Entry 105"
|
|
line.long 0xA8 "LUT_ENTRY_106,Palette Entry 106"
|
|
line.long 0xAC "LUT_ENTRY_107,Palette Entry 107"
|
|
line.long 0xB0 "LUT_ENTRY_108,Palette Entry 108"
|
|
line.long 0xB4 "LUT_ENTRY_109,Palette Entry 109"
|
|
line.long 0xB8 "LUT_ENTRY_110,Palette Entry 110"
|
|
line.long 0xBC "LUT_ENTRY_111,Palette Entry 111"
|
|
line.long 0xC0 "LUT_ENTRY_112,Palette Entry 112"
|
|
line.long 0xC4 "LUT_ENTRY_113,Palette Entry 113"
|
|
line.long 0xC8 "LUT_ENTRY_114,Palette Entry 114"
|
|
line.long 0xCC "LUT_ENTRY_115,Palette Entry 115"
|
|
line.long 0xD0 "LUT_ENTRY_116,Palette Entry 116"
|
|
line.long 0xD4 "LUT_ENTRY_117,Palette Entry 117"
|
|
line.long 0xD8 "LUT_ENTRY_118,Palette Entry 118"
|
|
line.long 0xDC "LUT_ENTRY_119,Palette Entry 119"
|
|
line.long 0xE0 "LUT_ENTRY_120,Palette Entry 120"
|
|
line.long 0xE4 "LUT_ENTRY_121,Palette Entry 121"
|
|
line.long 0xE8 "LUT_ENTRY_122,Palette Entry 122"
|
|
line.long 0xEC "LUT_ENTRY_123,Palette Entry 123"
|
|
line.long 0xF0 "LUT_ENTRY_124,Palette Entry 124"
|
|
line.long 0xF4 "LUT_ENTRY_125,Palette Entry 125"
|
|
line.long 0xF8 "LUT_ENTRY_126,Palette Entry 126"
|
|
line.long 0xFC "LUT_ENTRY_127,Palette Entry 127"
|
|
tree.end
|
|
tree "128-191"
|
|
group.long 0xe00++0xff
|
|
line.long 0x0 "LUT_ENTRY_128,Palette Entry 128"
|
|
line.long 0x4 "LUT_ENTRY_129,Palette Entry 129"
|
|
line.long 0x8 "LUT_ENTRY_130,Palette Entry 130"
|
|
line.long 0xC "LUT_ENTRY_131,Palette Entry 131"
|
|
line.long 0x10 "LUT_ENTRY_132,Palette Entry 132"
|
|
line.long 0x14 "LUT_ENTRY_133,Palette Entry 133"
|
|
line.long 0x18 "LUT_ENTRY_134,Palette Entry 134"
|
|
line.long 0x1C "LUT_ENTRY_135,Palette Entry 135"
|
|
line.long 0x20 "LUT_ENTRY_136,Palette Entry 136"
|
|
line.long 0x24 "LUT_ENTRY_137,Palette Entry 137"
|
|
line.long 0x28 "LUT_ENTRY_138,Palette Entry 138"
|
|
line.long 0x2C "LUT_ENTRY_139,Palette Entry 139"
|
|
line.long 0x30 "LUT_ENTRY_140,Palette Entry 140"
|
|
line.long 0x34 "LUT_ENTRY_141,Palette Entry 141"
|
|
line.long 0x38 "LUT_ENTRY_142,Palette Entry 142"
|
|
line.long 0x3C "LUT_ENTRY_143,Palette Entry 143"
|
|
line.long 0x40 "LUT_ENTRY_144,Palette Entry 144"
|
|
line.long 0x44 "LUT_ENTRY_145,Palette Entry 145"
|
|
line.long 0x48 "LUT_ENTRY_146,Palette Entry 146"
|
|
line.long 0x4C "LUT_ENTRY_147,Palette Entry 147"
|
|
line.long 0x50 "LUT_ENTRY_148,Palette Entry 148"
|
|
line.long 0x54 "LUT_ENTRY_149,Palette Entry 149"
|
|
line.long 0x58 "LUT_ENTRY_150,Palette Entry 150"
|
|
line.long 0x5C "LUT_ENTRY_151,Palette Entry 151"
|
|
line.long 0x60 "LUT_ENTRY_152,Palette Entry 152"
|
|
line.long 0x64 "LUT_ENTRY_153,Palette Entry 153"
|
|
line.long 0x68 "LUT_ENTRY_154,Palette Entry 154"
|
|
line.long 0x6C "LUT_ENTRY_155,Palette Entry 155"
|
|
line.long 0x70 "LUT_ENTRY_156,Palette Entry 156"
|
|
line.long 0x74 "LUT_ENTRY_157,Palette Entry 157"
|
|
line.long 0x78 "LUT_ENTRY_158,Palette Entry 158"
|
|
line.long 0x7C "LUT_ENTRY_159,Palette Entry 159"
|
|
line.long 0x80 "LUT_ENTRY_160,Palette Entry 160"
|
|
line.long 0x84 "LUT_ENTRY_161,Palette Entry 161"
|
|
line.long 0x88 "LUT_ENTRY_162,Palette Entry 162"
|
|
line.long 0x8C "LUT_ENTRY_163,Palette Entry 163"
|
|
line.long 0x90 "LUT_ENTRY_164,Palette Entry 164"
|
|
line.long 0x94 "LUT_ENTRY_165,Palette Entry 165"
|
|
line.long 0x98 "LUT_ENTRY_166,Palette Entry 166"
|
|
line.long 0x9C "LUT_ENTRY_167,Palette Entry 167"
|
|
line.long 0xA0 "LUT_ENTRY_168,Palette Entry 168"
|
|
line.long 0xA4 "LUT_ENTRY_169,Palette Entry 169"
|
|
line.long 0xA8 "LUT_ENTRY_170,Palette Entry 170"
|
|
line.long 0xAC "LUT_ENTRY_171,Palette Entry 171"
|
|
line.long 0xB0 "LUT_ENTRY_172,Palette Entry 172"
|
|
line.long 0xB4 "LUT_ENTRY_173,Palette Entry 173"
|
|
line.long 0xB8 "LUT_ENTRY_174,Palette Entry 174"
|
|
line.long 0xBC "LUT_ENTRY_175,Palette Entry 175"
|
|
line.long 0xC0 "LUT_ENTRY_176,Palette Entry 176"
|
|
line.long 0xC4 "LUT_ENTRY_177,Palette Entry 177"
|
|
line.long 0xC8 "LUT_ENTRY_178,Palette Entry 178"
|
|
line.long 0xCC "LUT_ENTRY_179,Palette Entry 179"
|
|
line.long 0xD0 "LUT_ENTRY_180,Palette Entry 180"
|
|
line.long 0xD4 "LUT_ENTRY_181,Palette Entry 181"
|
|
line.long 0xD8 "LUT_ENTRY_182,Palette Entry 182"
|
|
line.long 0xDC "LUT_ENTRY_183,Palette Entry 183"
|
|
line.long 0xE0 "LUT_ENTRY_184,Palette Entry 184"
|
|
line.long 0xE4 "LUT_ENTRY_185,Palette Entry 185"
|
|
line.long 0xE8 "LUT_ENTRY_186,Palette Entry 186"
|
|
line.long 0xEC "LUT_ENTRY_187,Palette Entry 187"
|
|
line.long 0xF0 "LUT_ENTRY_188,Palette Entry 188"
|
|
line.long 0xF4 "LUT_ENTRY_189,Palette Entry 189"
|
|
line.long 0xF8 "LUT_ENTRY_190,Palette Entry 190"
|
|
line.long 0xFC "LUT_ENTRY_191,Palette Entry 191"
|
|
tree.end
|
|
tree "192-255"
|
|
group.long 0xf00++0xff
|
|
line.long 0x0 "LUT_ENTRY_192,Palette Entry 192"
|
|
line.long 0x4 "LUT_ENTRY_193,Palette Entry 193"
|
|
line.long 0x8 "LUT_ENTRY_194,Palette Entry 194"
|
|
line.long 0xC "LUT_ENTRY_195,Palette Entry 195"
|
|
line.long 0x10 "LUT_ENTRY_196,Palette Entry 196"
|
|
line.long 0x14 "LUT_ENTRY_197,Palette Entry 197"
|
|
line.long 0x18 "LUT_ENTRY_198,Palette Entry 198"
|
|
line.long 0x1C "LUT_ENTRY_199,Palette Entry 199"
|
|
line.long 0x20 "LUT_ENTRY_200,Palette Entry 200"
|
|
line.long 0x24 "LUT_ENTRY_201,Palette Entry 201"
|
|
line.long 0x28 "LUT_ENTRY_202,Palette Entry 202"
|
|
line.long 0x2C "LUT_ENTRY_203,Palette Entry 203"
|
|
line.long 0x30 "LUT_ENTRY_204,Palette Entry 204"
|
|
line.long 0x34 "LUT_ENTRY_205,Palette Entry 205"
|
|
line.long 0x38 "LUT_ENTRY_206,Palette Entry 206"
|
|
line.long 0x3C "LUT_ENTRY_207,Palette Entry 207"
|
|
line.long 0x40 "LUT_ENTRY_208,Palette Entry 208"
|
|
line.long 0x44 "LUT_ENTRY_209,Palette Entry 209"
|
|
line.long 0x48 "LUT_ENTRY_210,Palette Entry 210"
|
|
line.long 0x4C "LUT_ENTRY_211,Palette Entry 211"
|
|
line.long 0x50 "LUT_ENTRY_212,Palette Entry 212"
|
|
line.long 0x54 "LUT_ENTRY_213,Palette Entry 213"
|
|
line.long 0x58 "LUT_ENTRY_214,Palette Entry 214"
|
|
line.long 0x5C "LUT_ENTRY_215,Palette Entry 215"
|
|
line.long 0x60 "LUT_ENTRY_216,Palette Entry 216"
|
|
line.long 0x64 "LUT_ENTRY_217,Palette Entry 217"
|
|
line.long 0x68 "LUT_ENTRY_218,Palette Entry 218"
|
|
line.long 0x6C "LUT_ENTRY_219,Palette Entry 219"
|
|
line.long 0x70 "LUT_ENTRY_220,Palette Entry 220"
|
|
line.long 0x74 "LUT_ENTRY_221,Palette Entry 221"
|
|
line.long 0x78 "LUT_ENTRY_222,Palette Entry 222"
|
|
line.long 0x7C "LUT_ENTRY_223,Palette Entry 223"
|
|
line.long 0x80 "LUT_ENTRY_224,Palette Entry 224"
|
|
line.long 0x84 "LUT_ENTRY_225,Palette Entry 225"
|
|
line.long 0x88 "LUT_ENTRY_226,Palette Entry 226"
|
|
line.long 0x8C "LUT_ENTRY_227,Palette Entry 227"
|
|
line.long 0x90 "LUT_ENTRY_228,Palette Entry 228"
|
|
line.long 0x94 "LUT_ENTRY_229,Palette Entry 229"
|
|
line.long 0x98 "LUT_ENTRY_230,Palette Entry 230"
|
|
line.long 0x9C "LUT_ENTRY_231,Palette Entry 231"
|
|
line.long 0xA0 "LUT_ENTRY_232,Palette Entry 232"
|
|
line.long 0xA4 "LUT_ENTRY_233,Palette Entry 233"
|
|
line.long 0xA8 "LUT_ENTRY_234,Palette Entry 234"
|
|
line.long 0xAC "LUT_ENTRY_235,Palette Entry 235"
|
|
line.long 0xB0 "LUT_ENTRY_236,Palette Entry 236"
|
|
line.long 0xB4 "LUT_ENTRY_237,Palette Entry 237"
|
|
line.long 0xB8 "LUT_ENTRY_238,Palette Entry 238"
|
|
line.long 0xBC "LUT_ENTRY_239,Palette Entry 239"
|
|
line.long 0xC0 "LUT_ENTRY_240,Palette Entry 240"
|
|
line.long 0xC4 "LUT_ENTRY_241,Palette Entry 241"
|
|
line.long 0xC8 "LUT_ENTRY_242,Palette Entry 242"
|
|
line.long 0xCC "LUT_ENTRY_243,Palette Entry 243"
|
|
line.long 0xD0 "LUT_ENTRY_244,Palette Entry 244"
|
|
line.long 0xD4 "LUT_ENTRY_245,Palette Entry 245"
|
|
line.long 0xD8 "LUT_ENTRY_246,Palette Entry 246"
|
|
line.long 0xDC "LUT_ENTRY_247,Palette Entry 247"
|
|
line.long 0xE0 "LUT_ENTRY_248,Palette Entry 248"
|
|
line.long 0xE4 "LUT_ENTRY_249,Palette Entry 249"
|
|
line.long 0xE8 "LUT_ENTRY_250,Palette Entry 250"
|
|
line.long 0xEC "LUT_ENTRY_251,Palette Entry 251"
|
|
line.long 0xF0 "LUT_ENTRY_252,Palette Entry 252"
|
|
line.long 0xF4 "LUT_ENTRY_253,Palette Entry 253"
|
|
line.long 0xF8 "LUT_ENTRY_254,Palette Entry 254"
|
|
line.long 0xFC "LUT_ENTRY_255,Palette Entry 255"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
textline ""
|